Method, system and device for atomicity guarantee of array table access instruction

Abstract

This invention discloses a method, system, and apparatus for ensuring the atomicity of array table access instructions. The array table system running on a DPU includes an atomicity processing module, an instruction processing module, an instruction dispatch module, a memory unit, an instruction return processing module, and a status monitoring module. The status monitoring module monitors and counts the number of instructions processed by the atomicity processing module, instruction processing module, instruction dispatch module, and instruction return processing module in real time, providing a reference for mitigating instruction conflicts and ensuring that each read or write operation is performed smoothly.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and specifically to a method, system, and apparatus for ensuring the atomicity of array table access instructions. Background Technology

[0002] In modern computing, large amounts of data need to be processed. Array tables face write instructions, read instructions, and read-after-write instructions. If a read-after-write instruction is not completed, a subsequent read instruction may read old data, causing data corruption. In other words, when software performs CRUD operations on array tables, there may be situations where read-after-write operations are performed on the same table entry. Without atomic processing of instructions, subsequent instructions may read old data. However, traditional atomic processing relies on the CPU to complete instruction atomicity, which incurs a significant time overhead. Summary of the Invention

[0003] In view of this, the present invention provides a method, system and apparatus for ensuring the atomicity of array table access instructions, which can guarantee the atomicity of instructions and ensure that the operation of each instruction execution is correct and that the data is not corrupted.

[0004] Firstly, a method for ensuring the atomicity of array table access instructions involves atomically processing read-then-write instructions accessing the array table system on a Data Processing Unit (DPU) before outputting them to the array table system. The DPU is equipped with an instruction cache, an atomic add-in cache, and a read-clear cache. The atomic processing includes:

[0005] Determine the type of the read-then-write instruction currently stored at the beginning of the instruction cache. If the type is an atomic add instruction, output the read-then-write instruction to the atomic add cache. If the type is a read clear instruction, output the read-then-write instruction to the read clear cache.

[0006] Determine if a read-before-write instruction exists in the current instruction cache at the same address as the read-before-write instruction currently stored in the atomic add-in cache or read clear cache. If yes, output the read-before-write instruction to the array table system. After the read-before-write instruction is executed, read the next read-before-write instruction in the instruction cache for type determination. If no, output the read-before-write instruction to the memory unit of the array table system and simultaneously read the next read-before-write instruction in the instruction cache for type determination.

[0007] Furthermore, the array table system running on the DPU includes an atomic processing module, an instruction processing module, an instruction dispatch module, a memory unit, and an instruction return processing module, and the instruction cache, atomic add cache, and read clear cache are set in the atomic processing module;

[0008] The atomicity processing module is used to determine the type of the current instruction accessing the array table system. If the type is a read-then-write instruction, the current instruction accessing the array table system is atomically processed before being output to the instruction processing module. If the type is a write instruction or a read instruction, the current instruction accessing the array table system is directly output to the instruction processing module. At the same time, the atomicity processing module is also used to receive the completion instruction output by the instruction return processing module, which indicates that the previous read-then-write instruction has been completed, and to determine whether to read the next read-then-write instruction in the instruction cache for type determination based on the completion instruction.

[0009] The instruction processing module is used to parse the received instruction and send the parsed instruction part and the write data part to the instruction distribution module. The instruction part is a write instruction, a read instruction, or a read-after-write instruction. At the same time, the instruction processing module is also used to send the parsed instruction part to the instruction return processing module.

[0010] The instruction dispatch module is used to determine whether to execute the currently received instruction part based on whether it has received the completion instruction output by the instruction return processing module, which indicates that the previous read-write instruction has been executed. If it has, and the received instruction part is a write instruction or a read instruction, the write instruction is converted into a write address or the read instruction is converted into a read address, and the write address channel of the memory unit storing the data to be accessed is accessed according to the write address or the read address channel of the memory unit is accessed according to the read address. At the same time, the write data channel of the memory unit is also accessed according to the write data part.

[0011] The instruction return processing module is used to determine the type of the received instruction. When the type is determined to be a read-then-write instruction, the instruction return processing module is also used to access the read data channel of the memory unit according to the currently received read-then-write instruction, process the read data, and output the completion instruction to the atomicity processing module and the instruction dispatch module after the read data processing is completed. The completion instruction has a higher priority than the write instruction, so the completion instruction is executed first and then the write instruction is executed.

[0012] Furthermore, a method for ensuring the atomicity of array table access instructions also includes splitting the read-then-write instruction into an instruction and write data before outputting them to the array table system, wherein the instruction is either an atomic addition instruction or a read-clear instruction.

[0013] Furthermore, the array table system also includes a status monitoring module;

[0014] The status monitoring module is used to receive status information that represents its own status from the atomicity processing module, instruction processing module, instruction distribution module, and instruction return processing module, respectively. At the same time, it counts the number of instructions processed by the atomicity processing module, instruction processing module, instruction distribution module, and instruction return processing module based on the status information, and reports the statistical results to the monitoring software.

[0015] Furthermore, if the read-after-write instruction is an atomic addition instruction, then after the read data processing is completed, the completion instruction output by the instruction return processing module to the atomicity processing module and the instruction dispatch module is an atomic addition completion instruction;

[0016] If the read-after-write instruction is a read-clear-complete instruction, then after the read data processing is completed, the completion instruction output by the instruction return processing module to the atomicity processing module and the instruction dispatch module is a read-clear-complete instruction.

[0017] Furthermore, the DPU has a clock frequency of 200MHz.

[0018] Secondly, a system for guaranteeing the atomicity of array table access instructions, wherein read-then-write instructions for accessing the array table system are atomically processed on a DPU before being output to the array table system, and the DPU is equipped with instruction buffers, atomic add-in buffers, and read-clear buffers, and the system for guaranteeing the atomicity of array table access instructions includes:

[0019] The first judgment module is used to determine the type of the read-then-write instruction currently stored at the beginning of the instruction cache. If the type is an atomic add instruction, the read-then-write instruction is output to the atomic add cache; if the type is a read clear instruction, the read-then-write instruction is output to the read clear cache.

[0020] The second judgment module is used to determine whether there is a read-after-write instruction in the current instruction cache with the same address as the read-after-write instruction currently stored in the atomic add cache or read clear cache. If yes, the read-after-write instruction is output to the array table system and after the read-after-write instruction is executed, the next read-after-write instruction in the instruction cache is read for type judgment. If no, the read-after-write instruction is output to the memory unit of the array table system and the next read-after-write instruction in the instruction cache is read for type judgment.

[0021] Furthermore, the array table system running on the DPU includes an atomic processing module, an instruction processing module, an instruction dispatch module, a memory unit, and an instruction return processing module, and the instruction cache, atomic add cache, and read clear cache are set in the atomic processing module;

[0022] The atomicity processing module is used to determine the type of the current instruction accessing the array table system. If the type is a read-then-write instruction, the current instruction accessing the array table system is atomically processed before being output to the instruction processing module. If the type is a write instruction or a read instruction, the current instruction accessing the array table system is directly output to the instruction processing module. At the same time, the atomicity processing module is also used to receive the completion instruction output by the instruction return processing module, which indicates that the previous read-then-write instruction has been completed, and to determine whether to read the next read-then-write instruction in the instruction cache for type determination based on the completion instruction.

[0023] The instruction processing module is used to parse the received instruction and send the parsed instruction part and the write data part to the instruction distribution module. The instruction part is a write instruction, a read instruction, or a read-after-write instruction. At the same time, the instruction processing module is also used to send the parsed instruction part to the instruction return processing module.

[0024] The instruction dispatch module is used to determine whether to execute the currently received instruction part based on whether it has received the completion instruction output by the instruction return processing module, which indicates that the previous read-write instruction has been executed. If it has, and the received instruction part is a write instruction or a read instruction, the write instruction is converted into a write address or the read instruction is converted into a read address, and the write address channel of the memory unit storing the data to be accessed is accessed according to the write address or the read address channel of the memory unit is accessed according to the read address. At the same time, the write data channel of the memory unit is also accessed according to the write data part.

[0025] The instruction return processing module is used to determine the type of the received instruction. When the type is determined to be a read-then-write instruction, the instruction return processing module is also used to access the read data channel of the memory unit according to the currently received read-then-write instruction, process the read data, and output the completion instruction to the atomicity processing module and the instruction dispatch module after the read data processing is completed. The completion instruction has a higher priority than the write instruction, so the completion instruction is executed first and then the write instruction is executed.

[0026] Thirdly, an apparatus for ensuring the atomicity of array table access instructions, the apparatus comprising: a host computer and a memory for storing a computer program executable on the host computer; wherein, when the host computer runs the computer program, it performs the steps of any of the methods described in the first aspect.

[0027] Fourthly, a computer-readable storage medium having a computer program stored thereon, characterized in that, when the computer program is executed by a host computer, it implements the steps of any of the methods described in the first aspect.

[0028] Beneficial effects:

[0029] 1. A method for ensuring the atomicity of array table access instructions, which determines whether an instruction conflict has occurred by checking whether there is a read-then-write instruction in the current instruction cache with the same address as the read-then-write instruction currently stored in the atomic add-cache or read-clear cache. This ensures that the next instruction will not be executed until the previous read-then-write instruction is completed, thus ensuring that the data content is not corrupted and that each read or write operation contains correct data.

[0030] 2. A method for ensuring the atomicity of array table access instructions, wherein the array table system running on the DPU includes an atomicity processing module, an instruction processing module, an instruction dispatch module, a memory unit, an instruction return processing module, and a status monitoring module; the status monitoring module monitors and counts the number of instructions processed by the atomicity processing module, the instruction processing module, the instruction dispatch module, and the instruction return processing module in real time, providing a reference for mitigating instruction conflicts, so as to ensure that each read or write operation is performed smoothly.

[0031] 3. A method for ensuring the atomicity of array table access instructions. Compared with traditional central processing units (CPUs) and graphics processing units (GPUs), DPUs have high data parallelism and optimization capabilities. At a clock speed of 200MHz, the atomicity of instructions can be completed in 175 nanoseconds, which is relatively low in time overhead and can more effectively process and accelerate various data-intensive tasks.

[0032] 4. A system that guarantees the atomicity of array table access instructions determines whether an instruction conflict has occurred by checking whether there is a read-then-write instruction in the current instruction cache with the same address as the read-then-write instruction currently stored in the atomic add-cache or read-clear cache. This ensures that the next instruction will only be executed after the previous read-then-write instruction is completed, thus preventing data corruption and ensuring that each read or write operation produces correct data.

[0033] 5. A device for ensuring the atomicity of array table access instructions, which determines whether an instruction conflict has occurred by determining whether there is a read-after-write instruction in the current instruction cache with the same address as the read-after-write instruction currently stored in the atomic add-cache or read-clear cache. This ensures that the next instruction will not be executed until the previous read-after-write instruction is completed, thus ensuring that the data content is not corrupted and that each read or write operation contains correct data.

[0034] 6. A storage medium that guarantees the atomicity of array table access instructions. It determines whether an instruction conflict has occurred by checking whether there is a read-after-write instruction with the same address as the read-after-write instruction currently stored in the atomic add-cache or read-clear cache. This ensures that the next instruction will only be executed after the previous read-after-write instruction is completed, thus preventing data corruption and ensuring that each read or write operation contains correct data. Attached Figure Description

[0035] Figure 1 The flowchart illustrates a method for ensuring the atomicity of array table access instructions provided by this invention.

[0036] Figure 2 The schematic diagram of the array table system provided by the present invention. Detailed Implementation

[0037] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0038] like Figure 1 As shown, this invention provides a method for ensuring the atomicity of array table access instructions. The method involves atomically processing read-then-write instructions accessing the array table system on the DPU before outputting them to the array table system. The DPU is equipped with an instruction cache, an atomic add-in cache, and a read-clear cache. The atomic processing includes:

[0039] Determine the type of the read-then-write instruction currently stored at the beginning of the instruction cache. If the type is an atomic add instruction, output the read-then-write instruction to the atomic add cache. If the type is a read clear instruction, output the read-then-write instruction to the read clear cache.

[0040] Determine if a read-before-write instruction exists in the current instruction cache at the same address as the read-before-write instruction currently stored in the atomic add cache or read clear cache. If yes, split the read-before-write instruction into instructions and write data, and output them to the array table system. After the read-before-write instruction is executed, read the next read-before-write instruction in the instruction cache for type determination, where the instruction is either an atomic add instruction or a read clear instruction. If no, split the read-before-write instruction into instructions and write data, output them to the memory unit of the array table system, and simultaneously read the next read-before-write instruction in the instruction cache for type determination, where the instruction is either an atomic add instruction or a read clear instruction.

[0041] In other words, when an atomic addition instruction is cached in the atomic addition cache, it is checked whether the address of the atomic addition instruction in the atomic addition cache is the same as the address of the atomic addition instruction or read clear instruction currently stored in the instruction cache. If they are the same, reading from the instruction cache is stopped, and the instruction cache is released after the conflicting instruction is completed. The atomic addition instruction is then split into instruction part and write data part and output. If they are different, the atomic addition instruction currently cached in the atomic addition cache is split into instruction part and write data part and output from the instruction cache. Similarly, when a read clear instruction is cached in the read clear cache, it is checked whether the address of the read clear instruction in the read clear cache is the same as the address of the atomic addition instruction or read clear instruction currently stored in the instruction cache. If they are the same, reading from the instruction cache is stopped, and the instruction cache is released after the conflicting instruction is completed. The read clear instruction is then split into instruction part and write data part and output. If they are different, the read clear addition instruction currently cached in the read clear addition cache is split into instruction part and write data part and output from the instruction cache.

[0042] It should be noted that atomic cache addition and read-clear cache are only used for judgment, and instruction output needs to be performed from the instruction cache; at the same time, DPU (Data Processing Unit) is a processor unit specifically designed to process data. As shown in Table 1, when the DPU operates at a clock frequency of 200MHz (one CLK cycle is 5ns), it can complete the atomic processing of instructions in 175 nanoseconds. That is, the higher the clock frequency, the smaller the latency.

[0043] Table 1

[0044]

[0045]

[0046] Furthermore, such as Figure 2 As shown, the array table system running on the DPU includes an atomic processing module, an instruction processing module, an instruction dispatch module, a memory unit, an instruction return processing module, and a status monitoring module. The instruction cache, atomic add cache, and read clear cache are set in the atomic processing module.

[0047] The atomicity processing module is used to determine the type of the instruction currently accessing the array table system. If the type is a read-then-write instruction, the instruction is atomically processed before being output to the instruction processing module. If the type is a write instruction or a read instruction, the instruction is directly output to the instruction processing module. At the same time, the atomicity processing module is also used to receive the completion instruction output by the instruction return processing module, which indicates that the previous read-then-write instruction has been completed, and to determine whether to read the next read-then-write instruction in the instruction cache for type determination based on the completion instruction.

[0048] The instruction processing module is used to parse the received instruction and send the parsed instruction part and the write data part to the instruction distribution module. The instruction part is a write instruction, a read instruction, or a read-after-write instruction. At the same time, the instruction processing module is also used to send the parsed instruction part to the instruction return processing module.

[0049] The instruction dispatch module is used to determine whether it should execute the currently received instruction portion based on whether it has received a completion instruction output by the instruction return processing module, which indicates that the previous read-write instruction has been executed. If it has, and the received instruction portion is a write instruction or a read instruction, the module converts the write instruction into a write address or the read instruction into a read address, and accesses the write address channel of the memory unit storing the data to be accessed based on the write address or accesses the read address channel of the memory unit based on the read address. At the same time, it also accesses the write data channel of the memory unit based on the write data portion.

[0050] The instruction return processing module is used to determine the type of the received instruction. When the determined type is a read-then-write instruction, the instruction return processing module is also used to access the read data channel of the memory unit according to the currently received read-then-write instruction, process the read data, and output the completion instruction to the atomicity processing module and the instruction distribution module after the read data processing is completed. If the read-then-write instruction is an atomic addition instruction, then after the read data processing is completed, the completion instruction output by the instruction return processing module to the atomicity processing module and the instruction distribution module is an atomic addition completion instruction. If the read-then-write instruction is a read-clear completion instruction, then after the read data processing is completed, the completion instruction output by the instruction return processing module to the atomicity processing module and the instruction distribution module is a read-clear completion instruction. The completion instruction has a higher priority than the write instruction, so the completion instruction is executed first and then the write instruction is executed.

[0051] The status monitoring module is used to receive status information that represents its own status from the atomicity processing module, instruction processing module, instruction distribution module, and instruction return processing module, respectively. At the same time, it counts the number of instructions processed by the atomicity processing module, instruction processing module, instruction distribution module, and instruction return processing module based on the status information, and reports the statistical results to the monitoring software.

[0052] As another implementation, the present invention also provides a system for guaranteeing the atomicity of array table access instructions. This system performs atomic processing on the DPU before outputting read-write instructions to the array table system, and the DPU is equipped with instruction buffers, atomic add-in buffers, and read-clear buffers. The system for guaranteeing the atomicity of array table access instructions includes:

[0053] The first judgment module is used to determine the type of the read-then-write instruction currently stored at the beginning of the instruction cache. If the type is an atomic add instruction, the read-then-write instruction is output to the atomic add cache; if the type is a read clear instruction, the read-then-write instruction is output to the read clear cache.

[0054] The second judgment module is used to determine whether there is a read-after-write instruction in the current instruction cache with the same address as the read-after-write instruction currently stored in the atomic add cache or read clear cache. If yes, the read-after-write instruction is output to the array table system and after the read-after-write instruction is executed, the next read-after-write instruction in the instruction cache is read for type judgment. If no, the read-after-write instruction is output to the memory unit of the array table system and the next read-after-write instruction in the instruction cache is read for type judgment.

[0055] As another implementation, the present invention also provides an apparatus for ensuring the atomicity of array table access instructions, the apparatus comprising: a host computer and a memory for storing a computer program that can run on the host computer; wherein, when the host computer runs the computer program, it executes each step of the method for ensuring the atomicity of array table access instructions as described above.

[0056] As another implementation, the present invention also provides a computer-readable storage medium storing a computer program. When the computer program is run by a host computer, it executes the various steps of the method for ensuring the atomicity of array table access instructions as described above, which will not be elaborated here. This storage medium can be a physical storage medium, such as an optical disc, USB flash drive, floppy disk, or hard disk.

[0057] Of course, the present invention may have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. A method for ensuring the atomicity of array table access instructions, characterized in that, The read-then-write instructions for accessing the array table system are atomically processed on the DPU before being output to the array table system. The DPU is equipped with instruction buffers, atomic add-to-buffer, and read-clear-to-buffer. The atomic processing includes: Determine the type of the read-then-write instruction currently stored at the beginning of the instruction cache. If the type is an atomic add instruction, output the read-then-write instruction to the atomic add cache. If the type is a read clear instruction, output the read-then-write instruction to the read clear cache. Determine if a read-before-write instruction exists in the current instruction cache at the same address as the read-before-write instruction currently stored in the atomic add-in cache or read clear cache. If yes, output the read-before-write instruction to the array table system. After the read-before-write instruction is executed, read the next read-before-write instruction in the instruction cache for type determination. If no, output the read-before-write instruction to the memory unit of the array table system and simultaneously read the next read-before-write instruction in the instruction cache for type determination.

2. The method for ensuring the atomicity of array table access instructions as described in claim 1, characterized in that, The array table system running on the DPU includes an atomic processing module, an instruction processing module, an instruction dispatch module, a memory unit, and an instruction return processing module, and the instruction cache, atomic add cache, and read clear cache are set in the atomic processing module; The atomicity processing module is used to determine the type of the current instruction accessing the array table system. If the type is a read-then-write instruction, the current instruction accessing the array table system is atomically processed before being output to the instruction processing module. If the type is a write instruction or a read instruction, the current instruction accessing the array table system is directly output to the instruction processing module. At the same time, the atomicity processing module is also used to receive the completion instruction output by the instruction return processing module, which indicates that the previous read-then-write instruction has been completed, and to determine whether to read the next read-then-write instruction in the instruction cache for type determination based on the completion instruction. The instruction processing module is used to parse the received instruction and send the parsed instruction part and the write data part to the instruction distribution module. The instruction part is a write instruction, a read instruction, or a read-after-write instruction. At the same time, the instruction processing module is also used to send the parsed instruction part to the instruction return processing module. The instruction dispatch module is used to determine whether to execute the currently received instruction part based on whether it has received the completion instruction output by the instruction return processing module, which indicates that the previous read-write instruction has been executed. If it has, and the received instruction part is a write instruction or a read instruction, the write instruction is converted into a write address or the read instruction is converted into a read address, and the write address channel of the memory unit storing the data to be accessed is accessed according to the write address or the read address channel of the memory unit is accessed according to the read address. At the same time, the write data channel of the memory unit is also accessed according to the write data part. The instruction return processing module is used to determine the type of the received instruction. When the type is determined to be a read-then-write instruction, the instruction return processing module is also used to access the read data channel of the memory unit according to the currently received read-then-write instruction, process the read data, and output the completion instruction to the atomicity processing module and the instruction dispatch module after the read data processing is completed. The completion instruction has a higher priority than the write instruction, so the completion instruction is executed first and then the write instruction is executed.

3. The method for ensuring the atomicity of array table access instructions as described in claim 2, characterized in that, It also includes splitting the read-then-write instruction into instructions and write data before outputting them to the array table system, and the instructions are either atomic addition instructions or read-clear instructions.

4. The method for ensuring the atomicity of array table access instructions as described in claim 3, characterized in that, The array table system also includes a status monitoring module; The status monitoring module is used to receive status information that represents its own status from the atomicity processing module, instruction processing module, instruction distribution module, and instruction return processing module, respectively. At the same time, it counts the number of instructions processed by the atomicity processing module, instruction processing module, instruction distribution module, and instruction return processing module based on the status information, and reports the statistical results to the monitoring software.

5. The method for ensuring the atomicity of array table access instructions as described in claim 3, characterized in that, If the read-after-write instruction is an atomic addition instruction, then after the read data processing is completed, the completion instruction output by the instruction return processing module to the atomicity processing module and the instruction dispatch module is an atomic addition completion instruction; If the read-after-write instruction is a read-clear-complete instruction, then after the read data processing is completed, the completion instruction output by the instruction return processing module to the atomicity processing module and the instruction dispatch module is a read-clear-complete instruction.

6. A method for ensuring the atomicity of array table access instructions as described in any one of claims 1 to 5, characterized in that, The DPU has a main frequency of 200MHz.

7. A system for guaranteeing the atomicity of array table access instructions, characterized in that, The read-then-write instructions for accessing the array table system are atomically processed on the DPU before being output to the array table system. The DPU is equipped with instruction buffers, atomic add-in buffers, and read-clear buffers. The system ensuring the atomicity of the array table access instructions includes: The first judgment module is used to determine the type of the read-then-write instruction currently stored at the beginning of the instruction cache. If the type is an atomic add instruction, the read-then-write instruction is output to the atomic add cache; if the type is a read clear instruction, the read-then-write instruction is output to the read clear cache. The second judgment module is used to determine whether there is a read-after-write instruction in the current instruction cache with the same address as the read-after-write instruction currently stored in the atomic add cache or read clear cache. If yes, the read-after-write instruction is output to the array table system and after the read-after-write instruction is executed, the next read-after-write instruction in the instruction cache is read for type judgment. If no, the read-after-write instruction is output to the memory unit of the array table system and the next read-after-write instruction in the instruction cache is read for type judgment.

8. The system for guaranteeing the atomicity of array table access instructions as described in claim 7, characterized in that, The array table system running on the DPU includes an atomic processing module, an instruction processing module, an instruction dispatch module, a memory unit, and an instruction return processing module, and the instruction cache, atomic add cache, and read clear cache are set in the atomic processing module; The atomicity processing module is used to determine the type of the current instruction accessing the array table system. If the type is a read-then-write instruction, the current instruction accessing the array table system is atomically processed before being output to the instruction processing module. If the type is a write instruction or a read instruction, the current instruction accessing the array table system is directly output to the instruction processing module. At the same time, the atomicity processing module is also used to receive the completion instruction output by the instruction return processing module, which indicates that the previous read-then-write instruction has been completed, and to determine whether to read the next read-then-write instruction in the instruction cache for type determination based on the completion instruction. The instruction processing module is used to parse the received instruction and send the parsed instruction part and the write data part to the instruction distribution module. The instruction part is a write instruction, a read instruction, or a read-after-write instruction. At the same time, the instruction processing module is also used to send the parsed instruction part to the instruction return processing module. The instruction dispatch module is used to determine whether to execute the currently received instruction part based on whether it has received the completion instruction output by the instruction return processing module, which indicates that the previous read-write instruction has been executed. If it has, and the received instruction part is a write instruction or a read instruction, the write instruction is converted into a write address or the read instruction is converted into a read address, and the write address channel of the memory unit storing the data to be accessed is accessed according to the write address or the read address channel of the memory unit is accessed according to the read address. At the same time, the write data channel of the memory unit is also accessed according to the write data part. The instruction return processing module is used to determine the type of the received instruction. When the type is determined to be a read-then-write instruction, the instruction return processing module is also used to access the read data channel of the memory unit according to the currently received read-then-write instruction, process the read data, and output the completion instruction to the atomicity processing module and the instruction dispatch module after the read data processing is completed. The completion instruction has a higher priority than the write instruction, so the completion instruction is executed first and then the write instruction is executed.

9. A device for guaranteeing the atomicity of array table access instructions, characterized in that, The apparatus includes: a host computer and a memory for storing a computer program that can run on the host computer; wherein, when the host computer runs the computer program, it performs the steps of the method according to any one of claims 1 to 6.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the host computer, it implements the steps of the method according to any one of claims 1 to 6.

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