Display device

Abstract

The present application provides a display device capable of improving the inhibitory effect of burn-in caused by the residual voltage of the pixel electrode after the power is turned off. The display device comprises: a first switch circuit (45) controlled to be turned on at a first time (t1) of a power-off procedure, and supplies a first power voltage signal (PSIG1) to a scan line (SCL); a second switch circuit (46) controlled to be turned on at the first time (t1), and supplies a GND potential to a signal line (DTL); and a reset circuit (47) which, after controlling the first switch circuit (45) and the second switch circuit (46) to be turned on at the first time (t1), maintains the on state of the first switch circuit (45) and the second switch circuit (46) after the control of the gate driver and the signal line selection circuit is stopped at a second time (t2) after the first time (t1).

Description

Technical Field

[0001] This invention relates to display devices. Background Technology

[0002] Conventionally, a liquid crystal display device has been disclosed that, when the power is off, short-circuit the common electrode and the source line to turn on the pixel transistor, thereby writing the ground potential of the source line to the pixel. By setting the potential of the pixel electrode to the ground potential, afterimages can be quickly eliminated, and screen burn-in caused by residual voltage can be prevented (for example, see Patent Document 1). Another liquid crystal display device has been disclosed that, when transitioning from an operating state to a non-operating state, turns on the gates of all TFTs and sets the liquid crystal driving power supply to the ground potential, discharging the liquid crystal driving voltage stored in the liquid crystal and the holding capacitor (for example, see Patent Document 2).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2008-299253

[0004] Patent Document 2: Japanese Patent Application Publication No. 2001-22326

[0005] In the aforementioned prior art, the potential of the pixel electrode does not take into account the fact that after the pixel electrode potential is set to ground, when the gate signal potential becomes the cutoff potential, the potential of the pixel electrode changes through the drain-gate capacitance of the pixel transistor, which can generate residual voltage in the pixel electrode. Therefore, it is sometimes impossible to fully achieve the effect of suppressing screen burn-in caused by residual voltage in the pixel electrode. Summary of the Invention

[0006] The object of the present invention is to provide a display device capable of suppressing residual voltage on pixel electrodes after power disconnection, which occurs during the power disconnection sequence.

[0007] A display device according to one aspect of this disclosure includes: a pixel having a pixel transistor and a pixel electrode connected to the drain (first electrode) of the pixel transistor; a scan line connected to the gate of the pixel transistor; a signal line connected to the source (second electrode) of the pixel transistor; and a driving circuit that is supplied with a positive first power supply voltage signal and a negative second power supply voltage signal to drive the pixel transistor, the driving circuit including: a gate driver that supplies a scan signal to the scan line; a signal line selection circuit that supplies a pixel signal to the signal line; and a display control circuit that controls the gate driver and the signal line selection circuit to, during display operation, drive the pixel transistor. A holding capacitor is provided between the base electrode and a common electrode with a supply potential lower than GND. The driving circuit includes: a first switching circuit that is turned on at a first moment of a power-off procedure to supply the first power supply voltage signal to the scan line; a second switching circuit that is turned on at the first moment to supply GND potential to the signal line; and a reset circuit that, after turning on the first switching circuit and the second switching circuit at the first moment, maintains the on-state of the first switching circuit and the second switching circuit after the control of the gate driver and the signal line selection circuit stops at a second moment after the first moment. Attached Figure Description

[0008] Figure 1 This is a diagram illustrating an example of the general configuration of a display device according to an embodiment.

[0009] Figure 2 This is a diagram showing an example of the pixel arrangement in a display area.

[0010] Figure 3 It is a cross-sectional view showing the general cross-sectional structure of the display device.

[0011] Figure 4 This is a top view showing an example of pixel composition.

[0012] Figure 5A It shows along Figure 4 The first example of the cross section of line A1-A2.

[0013] Figure 5B It shows along Figure 4 The second example of the cross section of line A1-A2.

[0014] Figure 6 This is a diagram illustrating an example of the drive circuit configuration of the display device involved in the comparative example.

[0015] Figure 7 This is a timing diagram illustrating an example of the power disconnection procedure involved in the comparative example.

[0016] Figure 8 Based on Figure 7 The image shows an enlarged view of the potential changes of the pixel electrode after the power disconnection procedure has been reset.

[0017] Figure 9 This is a diagram illustrating an example of the drive circuit configuration of the display device according to the embodiment.

[0018] Figure 10 This is a timing diagram illustrating an example of a power disconnection procedure involved in an implementation.

[0019] Figure 11 Based on Figure 10 The image shows an enlarged view of the potential changes of the pixel electrode after the power disconnection procedure has been reset.

[0020] Figure 12A This is a diagram showing the circuit configuration of the first inverter circuit.

[0021] Figure 12B This is a diagram showing the input and output potentials of the first inverter circuit. Detailed Implementation

[0022] The embodiments for carrying out the invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the contents described in the following embodiments. Furthermore, the constituent elements described below include elements readily conceived by those skilled in the art, as well as substantially the same elements. Moreover, the constituent elements described below can be appropriately combined. It should be noted that the disclosure is merely an example, and appropriate modifications that maintain the spirit of the invention and are readily conceived by those skilled in the art are naturally included within the scope of the present invention. In addition, to make the description clearer, the width, thickness, shape, etc., of various parts in the drawings are sometimes schematically shown compared to the actual form; ultimately, this is only an example and does not limit the interpretation of the present invention. Furthermore, in this specification and the various drawings, the same reference numerals are used for elements that are the same as those described in the previously shown drawings, and detailed descriptions are sometimes appropriately omitted.

[0023] Figure 1 This is a diagram illustrating an example of the general configuration of a display device according to an embodiment. Figure 2 This is a diagram showing an example of the pixel arrangement in a display area.

[0024] The display device 1 described in this embodiment is, for example, a liquid crystal display device that uses a liquid crystal display element as the display element. Furthermore, in this disclosure, the display device 1 can employ, for example, a column inversion driving method or a frame inversion driving method as the driving method. However, the driving method in the display device 1 is not limited to the column inversion driving method or the frame inversion driving method.

[0025] The display device 1 has a display area AA on the display panel 11, and a drive circuit 40 is provided in the surrounding area of ​​the display area AA. The display device 1 is supplied with power from the power supply device 12.

[0026] The driving circuit 40 includes a gate driver 42, a signal line selection circuit 43, and a display control circuit 44. The gate driver 42 and the signal line selection circuit 43 are thin-film transistor (TFT) circuits formed in the peripheral area of ​​the display area AA. The display control circuit 44 is included in a driver IC (Integrated Circuit) 4 mounted in the peripheral area of ​​the display area AA. The driver IC 4 is connected to the control device 13, for example, via a relay substrate made of a flexible printed circuit (FPC).

[0027] The control device 13 controls the power supply from the power supply device 12 to the display device 1. Additionally, the control device 13 controls the power on and off of the display device 1. The power supply device 12 and the control device 13 are, for example, mounted on a device (not shown) mounted on the display device 1.

[0028] The display area AA includes a plurality of pixels Pix arranged in the Dx direction (first direction) and the Dy direction (second direction). Additionally, the display area AA includes a scan line (gate line) SCL that supplies scan signals (gate signals) GATE to the pixels Pix, and a signal line DTL that supplies pixel signals SIG to the pixels Pix. In this embodiment, the scan line SCL extends in the Dx direction. Furthermore, in this embodiment, the signal line DTL extends in the Dy direction.

[0029] like Figure 2 As shown, each pixel Pix has a pixel transistor Tr and a pixel electrode PX. The pixel transistor Tr is composed of a thin-film transistor (TFT), such as an n-channel MOS (Metal Oxide Semiconductor) type TFT (hereinafter also referred to as "n-type TFT"). The source (second electrode) of the pixel transistor Tr is connected to the signal line DTL, the gate is connected to the scan line (gate line) SCL, and the drain (first electrode) is connected to the pixel electrode PX. A holding capacitor CS is formed between the pixel electrode PX and the common electrode COML.

[0030] Scan signals (gate signals) GATE (1, 2, ..., m, ..., M) are supplied to the gates of pixel transistors Tr of pixels Pix arranged in the row direction (Dx direction) via scan lines (gate lines) SCL, and pixel signals SIG (1, 2, ..., n, ..., N) are supplied to the sources of pixel transistors Tr of pixels Pix arranged in the column direction (Dy direction) via signal lines DTL. Figure 2 The example shown depicts M pixels (Pix) arranged in the column direction (Dy direction) and N pixels (Pix) arranged in the row direction (Dx direction), but it is not a limitation. Hereinafter, rows where pixels (Pix) are arranged in the row direction (Dx direction) will be referred to as pixel rows. Similarly, columns where pixels (Pix) are arranged in the column direction (Dy direction) will be referred to as pixel columns.

[0031] In this disclosure, a pixel Pix includes, for example, a red pixel for displaying red (R), a green pixel for displaying green (G), and a blue pixel for displaying blue (B). As a pixel arrangement, an example is a strip arrangement of RGB pixels in the row direction (Dx direction), but the pixel arrangement is not limited to an RGB strip arrangement. Specifically, for example, a white pixel for displaying white (W) can be configured as a pixel Pix, or it can be formed as an obliquely upward strip arrangement with a predetermined angle relative to the row direction (Dx direction) and the column direction (Dy direction), or an arrangement of multiple groups of pixels displaying different colors periodically configured in both the row direction (Dx direction) and the column direction (Dy direction).

[0032] The power supply device 12 generates a positive first power supply voltage signal PSIG1 and a negative second power supply voltage signal PSIG2 to supply to the display device 1. The first power supply voltage signal PSIG1 is controlled to a first potential (VGH) when the display device 1 is operating. The second power supply voltage signal PSIG2 is controlled to a second potential (VGL) when the display device 1 is operating. The first potential (VGH) is, for example, set to 7 [V]. The second potential (VGL) is, for example, set to -7 [V]. The first potential (VGH) supplied when the display device 1 is operating is not limited to 7 [V]. Similarly, the second potential (VGL) supplied when the display device 1 is operating is not limited to -7 [V].

[0033] The control device 13 sends the original signal of the image displayed on the display device 1, i.e., the image signal Source, to the display device 1. Additionally, the control device 13 sends a first power control signal PCTRL1 to the display device 1 for controlling the power on and off of the display device 1. Furthermore, the control device 13 sends a second power control signal PCTRL2 to the power supply device 12 for controlling the power supply from the power supply device 12 to the display device 1.

[0034] The control device 13 includes, for example, a CPU (Central Processing Unit) and a storage device such as a memory. By using these hardware resources, such as the CPU and storage device, the control device 13 executes a program to realize the display function of the display device 1. Based on the execution result of the program, the control device 13 controls the driver IC4 to process the image displayed on the display device 1 as image input grayscale information.

[0035] The display control circuit 44 controls the display operation in the display area AA by controlling the gate driver 42 and the signal line selection circuit 43. The display control circuit 44 receives various control signals from the control device 13, such as the image signal Source and the first power control signal PCTRL1. Furthermore, the display control circuit 44 converts the image signal Source from the control device 13 into an image signal Vsig and outputs it. The image signal Vsig is, for example, a signal obtained by time-division multiplexing the pixel signal Sig corresponding to the RGB pixel arrangement. Additionally, the display control circuit 44 supplies a common potential VCOM to the common electrode COML.

[0036] Furthermore, the display control circuit 44 serves as an interface (I / F) between the signal line selection circuit 43 and the control device 13, as well as a timing generator. It should be noted that the driver IC4, which includes the display control circuit 44, may not be mounted on the display panel 11, but rather on a relay substrate connected to the display panel 11. Additionally, the gate driver 42 and the signal line selection circuit 43 may also be included in the driver IC4.

[0037] Next, refer to Figures 3 to 5B The general structure of the display device 1 according to the embodiment will be described. Figure 3 This is a cross-sectional view showing the general cross-sectional structure of the display device. Figure 4 This is a top view showing an example of pixel composition. Figure 5A It shows along Figure 4 The first example of a cross-section along line A1-A2. In Figure 5A The first example shown illustrates an instance where a bottom-gate transistor is used as a pixel transistor Tr. Figure 5B It shows along Figure 4 The second example of a cross-section along line A1-A2. Figure 5B The second example shown illustrates an instance where a top-gate transistor is used as the pixel transistor Tr.

[0038] The array substrate 2 includes a first substrate 21 made of glass or transparent resin, a plurality of pixel electrodes PX, a common electrode COML, and an insulating layer 24 insulating the pixel electrodes PX from the common electrode COML. The plurality of pixel electrodes PX are arranged, for example, in a row and column (matrix) arrangement above the first substrate 21. The common electrode COML is disposed between the first substrate 21 and the pixel electrodes PX.

[0039] Pixel electrodes PX are provided corresponding to each pixel Pix. The pixel signal SIG used for display operation is supplied to the pixel electrode PX from the signal line selection circuit 43 via the signal line DTL and the pixel transistor Tr. Additionally, during display operation, a common potential VCOM for display is supplied as a voltage signal from the driver IC4 to the common electrode COML. The common potential VCOM is preferably a different potential from ground (GND), for example, set to approximately -0.7V. The setting value of the common potential VCOM is set to an optimal value that does not produce flicker in drive modes such as column inversion drive mode and frame inversion drive mode. Furthermore, the common potential VCOM is preferably a fixed potential, but it can also have a waveform composed of an AC rectangular wave.

[0040] The pixel electrode PX and the common electrode COML are made of a transparent conductive material such as ITO (Indium Tin Oxide). A polarizing plate 35B is provided on the underside of the first substrate 21, separated by an adhesive layer (not shown).

[0041] The opposing substrate 3 includes a second substrate 31 made of glass or transparent resin, and a color filter 32 and a light-shielding layer (not shown) formed on one side of the second substrate 31. In addition, a polarizing plate 35A is provided on the upper side of the second substrate 31 through an adhesive layer (not shown).

[0042] The array substrate 2 and the opposing substrate 3 are arranged opposite each other with a predetermined interval (cell gap). A liquid crystal layer 6, serving as a display functional layer, is disposed in the space between the first substrate 21 and the second substrate 31. The liquid crystal layer 6 modulates the light passing through it by changing the orientation state of the liquid crystal molecules according to the electric field state between each pixel electrode PX and the common electrode COML, thereby altering the orientation state of the liquid crystal molecules at each pixel Pix. In this embodiment, for example, a liquid crystal suitable for lateral electric field modes such as IPS (in-plane switching) including FFS (edge ​​field switching) is used.

[0043] The array substrate 2 includes pixel transistors Tr for each pixel Pix, signal lines DTL supplying pixel signals SIG to each pixel electrode PX, and scan lines (gate lines) SCL supplying gate signals GATE to drive each pixel transistor Tr. The signal lines DTL and scan lines (gate lines) SCL extend on a plane parallel to the surface of the first substrate 21.

[0044] like Figure 4 As shown, the area surrounded by the scan line (gate line) SCL and the signal line DTL is the pixel Pix. The pixel electrode PX has multiple strip electrodes 22a and connecting portions 22b.

[0045] like Figure 4 As shown, the pixel transistor Tr includes a semiconductor 61, a source electrode 62, a drain electrode 63, and a gate electrode 64.

[0046] like Figure 5A As shown, in the configuration where a bottom-gate transistor is used as a pixel transistor Tr, a gate line layer 51 is provided on the first substrate 21. A gate electrode 64 (scan line (gate line) SCL) is provided on the gate line layer 51. An insulating layer 58a (second insulating layer) is provided on the first substrate 21, covering the gate electrode 64. A semiconductor layer 52 is provided on the insulating layer 58a. A semiconductor 61 is provided on the semiconductor layer 52. A signal line layer 53 is provided on the upper side of the semiconductor layer 52, separated by an insulating layer 58c (first insulating layer).

[0047] like Figure 5B As shown, in the configuration where a top-gate transistor is used as a pixel transistor Tr, a write shielding layer LS is provided on the first substrate 21. A semiconductor layer 52 is provided on the write shielding layer LS, separated by an insulating layer 58f. A semiconductor 61 is provided on the semiconductor layer 52. A gate line layer 51 is provided on the upper side of the semiconductor layer 52, separated by an insulating layer 58c. A gate electrode 64 is provided on the gate line layer 51. An insulating layer 58a is provided on the insulating layer 58c, covering the gate electrode 64. A signal line layer 53 is provided on the upper side of the gate line layer 51, separated by an insulating layer 58a.

[0048] A drain electrode 63 and a source electrode 62 (signal line DTL) are provided on the signal line layer 53. An auxiliary wiring layer 54 is provided above the drain electrode 63 and the source electrode 62 (signal line DTL) and separated by an insulating layer 58d (third insulating layer). A common electrode layer 55 is provided above the auxiliary wiring layer 54 and separated by an insulating layer 58e. A common electrode COML is provided on the common electrode layer 55. It should be noted that a configuration in which the auxiliary wiring layer and the common electrode layer overlap without being separated by an insulating layer can also be adopted. A pixel electrode PX is provided above the common electrode layer 55 and separated by an insulating layer 24.

[0049] like Figure 4 as well as Figure 5A (or Figure 5BAs shown, the pixel electrode PX is connected to the drain electrode 63 of the pixel transistor Tr via contact hole H11. The drain electrode 63 is connected to the semiconductor 61 via contact hole H12. The semiconductor 61 intersects with the gate electrode 64 when viewed from above. The gate electrode 64 is connected to the scan line (gate line) SCL and protrudes from one side of the scan line (gate line) SCL. The semiconductor 61 extends to a position overlapping with the source electrode 62 and is electrically connected to the source electrode 62 via contact hole H13. The source electrode 62 is connected to the signal line DTL and protrudes from one side of the signal line DTL.

[0050] As the material for semiconductor 61, known materials such as polycrystalline silicon and oxide semiconductors can be used. For example, since TAOS (Transparent Amorphous Oxide Semiconductor) is used, the ability to maintain the voltage used for image display for a long time (holding rate) is good, which can improve display quality. In addition, oxide semiconductors containing TAOS have low leakage current when the pixel transistor Tr is turned off.

[0051] The gate electrode 64 (scan line (gate line) SCL) is made of, for example, aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), or alloys thereof. The drain electrode 63 and the source electrode 62 (signal line DTL) are made of, for example, an alloy of titanium and aluminum, namely titanium-aluminum (TiAl).

[0052] Known insulating materials can be used as the materials for insulating layers 24, 58a, 58c, 58d, 58e, and 58f. Alternatively, for example, silicon oxide (SiO2) can be used as the material for insulating layer 58c. An organic insulating film such as acrylic acid can be used as the material for insulating layer 58d. This achieves planarization of the surface on which the common electrode COML is disposed.

[0053] The material of the auxiliary wiring layer 54, like that of the gate electrode 64 (scan line (gate line) SCL), is, for example, made of aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), or alloys thereof.

[0054] In the display device 1 with the above-described schematic structure, in addition to the holding capacitance CS formed between the pixel electrode PX and the common electrode COML, a parasitic capacitance is also generated between the pixel electrode PX and other conductive components.

[0055] In liquid crystal display devices, since the output of the drive circuit becomes high impedance when the power is off, it is necessary to reset (discharge) the potential held at the pixel electrode when the power is off. The control process (sequence) of resetting the potential held at the pixel electrode when the power is off is also called the "power off sequence".

[0056] The specific configuration of the drive circuit 40 of the display device 1 according to the embodiment and the power disconnection procedure will be described below.

[0057] First, the display device 10 involved in the comparative example and the power disconnection procedure will be explained. Figure 6 This is a diagram illustrating an example of the drive circuit configuration of the display device involved in the comparative example. Figure 6 The diagram shows an example of the circuit configuration corresponding to a single pixel Pix(m, n). Figure 2 In the pixel arrangement shown, pixel Pix(m, n) represents the nth pixel from the left in the row direction (Dx direction) and the mth pixel from the top in the column direction (Dy direction). Additionally, in Figure 6 In the diagram, the parasitic capacitance CP generated between the pixel electrode PX and the scan line (gate line) SCL is shown by dashed lines.

[0058] Each circuit element constituting the drive circuit 40 operates by being supplied with a first power supply voltage signal PSIG1 and a second power supply voltage signal PSIG2 from the power supply device 12. When the display device 1 is operating, the potential (first potential VGH) of the first power supply voltage signal PSIG1 supplied from the power supply device 12 is set to a high potential of the scan signal (gate signal) GATE(m) supplied to the gate of the pixel transistor Tr. Conversely, when the display device 1 is operating, the potential (second potential VGL) of the second power supply voltage signal PSIG2 supplied from the power supply device 12 is set to a low potential of the scan signal GATE(m) supplied to the gate of the pixel transistor Tr.

[0059] The display control circuit 44 (driver IC4) controls the gate driver 42 and the signal line selection circuit 43. Specifically, the display control circuit 44 supplies the gate driver 42 with a start pulse STV, a shift clock CKV, and other synchronization signals, as well as a scan line drive signal ENB. In addition, the display control circuit 44 supplies the signal line selection control signals ASW(n) and XASW(n) to the signal line selection circuit 43.

[0060] Furthermore, in this disclosure, the display control circuit 44 supplies a reset signal XReset to the gate driver 42 during the power-off procedure. This reset signal is used to control the conduction of the pixel transistors Tr of all pixels Pix within the display area AA, thereby resetting the potential of the pixel electrodes PX. The reset signal XReset is a signal that is set to a high potential (first potential VGH) during display operation and a low potential (second potential VGL) during the power-off procedure.

[0061] The gate driver 42 includes a shift register circuit 421 and a scan line drive circuit 422 as the main circuit elements for performing display operations. In addition, in this disclosure, the gate driver 42 includes an AND circuit that outputs a low potential (second potential VGL) to the scan line drive circuit 422 at least when the reset signal XReset is low (second potential VGL).

[0062] The shift register circuit 421 is a circuit that generates a high potential (first potential VGH) signal based on the synchronization signals such as the start pulse STV and shift clock CKV output from the display control circuit 44 when the pixel row of the m-th column is selected.

[0063] Specifically, the shift register circuit 421, for example, when the shift clock CKV is high, takes in the output of the previous stage shift register S / R (or the start pulse STV), and when the shift clock CKV is low, it cuts off the path to take in the output of the previous stage shift register S / R (or the start pulse STV), while maintaining the value through the latching operation in the shift register S / R.

[0064] The output signal of the shift register circuit 421 is logically inverted by the inverter circuit 423. When the display is active, i.e. the reset signal XReset is at a high potential (first potential VGH), the output signal of the inverter circuit 423 is input to the scan line drive circuit 422 via the AND circuit 424.

[0065] The scan line drive circuit 422 is a circuit that generates a scan signal GATE(m) supplied to the gate of the pixel transistor Tr based on the signal output from the AND circuit 424 and the scan line drive signal ENB output from the display control circuit 44. The high potential of the scan line drive signal ENB is set to the first potential VGH.

[0066] Specifically, during display operation, when the signal output from the AND circuit 424 is at a high potential (first potential VGH), the first transistor Tr1, composed of a p-channel MOS-type TFT (hereinafter also referred to as "p-type TFT"), and the second transistor Tr2, composed of an n-type TFT, are turned off, while the third transistor Tr3, composed of an n-type TFT, is turned on. Therefore, the output potential of the scan line driving circuit 422 becomes the second potential VGL, and the pixel transistor Tr of pixel Pix(m,n) is turned off.

[0067] Furthermore, during display operation, when the signal output from the AND circuit 424 is at a low potential (second potential VGL), the first transistor Tr1 and the second transistor Tr2 are turned on, while the third transistor Tr3 is turned off. Therefore, the output potential of the scan line driving circuit 422 becomes the high potential of the scan line driving signal ENB, i.e., the first potential VGH, and the pixel transistor Tr of pixel Pix(m,n) is turned on.

[0068] The signal line selection circuit 43 is a switching circuit that selectively outputs the image signal Vsig from the display control circuit 44 as a pixel signal SIG when selecting the pixel column of the nth row. Specifically, the signal line selection circuit 43 includes a switching transistor ASWTr composed of an n-type TFT and a switching transistor XASWTr composed of a p-type TFT.

[0069] When the signal line selection control signal ASW(n) output from the display control circuit 44 is at a high level and the signal line selection control signal XASW(n) is at a low level, the signal line selection circuit 43 controls the switching transistors ASWTr and XASWTr to be turned on. Conversely, when the signal line selection control signal ASW(n) output from the display control circuit 44 is at a low level and the signal line selection control signal XASW(n) is at a high level, the signal line selection circuit 43 controls the switching transistors ASWTr and XASWTr to be turned off.

[0070] The signal line selection control signal ASW(n) and the signal line selection control signal XASW(n) are complementary signals with inverted logic. The signal line selection control signal XASW(n) can also be generated by logically inverting the signal line selection control signal ASW(n). Furthermore, the signal line selection control signal ASW(n) can also be generated by logically inverting the signal line selection control signal XASW(n). Moreover, the signal line selection circuit 43 can also be constructed solely using a switching transistor composed of an n-type TFT or a p-type TFT. When the switching transistor is composed of an n-type TFT, the signal line selection control signal XASW is not required. Similarly, when the switching transistor is composed of a p-type TFT, the signal line selection control signal ASW is not required.

[0071] By operating the various circuit elements of the driving circuit 40 described above, when selecting a pixel Pix(m,n) during a display operation, the pixel transistor Tr of pixel Pix(m,n) is turned on, and the pixel signal SIG is written to the pixel electrode PX of pixel Pix(m,n). Afterwards, until the pixel transistor Tr of pixel Pix(m,n) is turned off and pixel Pix(m,n) is turned on again in the next frame, the potential of the pixel signal SIG is maintained at the holding capacitor CS. By performing the above control on all pixels Pix within the display area AA in a selection order corresponding to a predetermined driving mode (e.g., column inversion driving mode, frame inversion mode), a display operation in the display area AA can be performed.

[0072] In the power-off procedure of the display device 10 described in the comparative example above, the display control circuit 44 sets the reset signal XReset to a low potential (second potential VGL). As a result, the scan line drive circuit 422 is supplied with a low potential (second potential VGL), the potential of all scan lines (gate lines) SCL becomes low (second potential VGL), the pixel transistors Tr of all pixels Pix within the display area AA are turned on, and the potential of the pixel electrode PX is reset. This suppresses screen burn-in of the liquid crystal caused by the residual voltage of the pixel electrode PX.

[0073] Figure 7 This is a timing diagram illustrating an example of the power-off procedure involved in the comparative example. In this disclosure, the display control circuit 44 executes the power-off procedure of the display device 1 based on the first power control signal PCTRL1 output from the control device 13. Figure 7 The example shown illustrates a power-off procedure that begins at time t0. Before time t0, it is assumed that the usual display actions described above are performed.

[0074] When the power-off procedure begins at time t0, the display device 1 displays a black screen. Specifically, the display control circuit 44 sets the grayscale of the image signal Vsig corresponding to all pixels Pix within the display area AA to "0" to perform the display operation. This ensures that the potential held at the pixel electrode PX is at its minimum. Hereinafter, the period of black screen display will be referred to as the "black insertion period." It should be noted that a black insertion period may not necessarily be set.

[0075] When the black insertion period ends at time t1, the display control circuit 44 supplies the GND potential as the potential supplied to the signal line DTL. At this time, the display control circuit 44 sets the signal line selection control signal ASW corresponding to all signal lines DTL to a high potential and sets the signal line selection control signal XASW corresponding to all signal lines DTL to a low potential. As a result, the switching transistors ASWTr and XASWTr are turned on and supplied the GND potential to the signal line DTL, and the potential of the signal line DTL is set to the GND potential.

[0076] Additionally, at time t1, the display control circuit 44 stops supplying the common potential VCOM to the common electrode COML. As a result, the potential of the common electrode COML converges to the GND potential before time t4. Also, at time t1, the display control circuit 44 sets all scan line drive signals ENB to a high potential (first potential VGH). Furthermore, the display control circuit 44 sets the reset signal XReset to a low potential (second potential VGL). As a result, the potential of the output signal of the AND circuit 424 becomes low (second potential VGL). Consequently, the first transistor Tr1 and the second transistor Tr2 of the scan line drive circuit 422 are turned on, the third transistor Tr3 is turned off, the potential of all scan lines SCL becomes the first potential VGH supplied as the high potential of the scan line drive signal ENB, and the pixel transistor Tr of all pixels Pix is ​​turned on. Therefore, the pixel electrode PX of all pixels Pix is ​​electrically connected to the signal line DTL at the GND potential via the turned-on pixel transistor Tr, and the potential of the pixel electrode PX of all pixels Pix is ​​reset to the GND potential.

[0077] At time t2, after resetting the potential of the pixel electrodes PX of all pixels Pix, the power supply device 12 stops supplying the first power supply voltage signal PSIG1 and the second power supply voltage signal PSIG2 to the display device 1 based on the second power control signal PCTRL2 output from the control device 13. As a result, the driver IC4 stops control, and the potentials of the synchronization signals such as the start pulse STV, the shift clock CKV, all scan line drive signals ENB, the reset signal XReset, and the signal line selection control signals ASW and XASW corresponding to all signal lines DTL become the GND potential.

[0078] It should be noted that the potentials of the first power supply voltage signal PSIG1 and the second power supply voltage signal PSIG2 gradually decrease due to the power smoothing capacitor (not shown) provided in the power supply device 12. Therefore, the potentials of the first power supply voltage signal PSIG1 and the second power supply voltage signal PSIG2 converge to the GND potential after each control signal becomes GND. In other words, the potentials of each control signal output from the driver IC shift to the GND potential more abruptly than the first power supply voltage signal PSIG1 and the second power supply voltage signal PSIG2.

[0079] At this time, a sharp potential change occurs on the scan line SCL, from the high potential (first potential VGH) of the scan line drive signal ENB of the scan signal GATE to the GND potential. As described above, a parasitic capacitance CP is formed between the drain and gate of the pixel transistor Tr. The sudden voltage change of the scan line SCL acts on this parasitic capacitance CP, causing the potential of the pixel electrode PX to drop from its original reset potential (GND potential).

[0080] Here, we will explain in more detail the principle of the potential drop of the pixel electrode PX. Figure 8 Based on Figure 7 The image shows an enlarged view of the potential changes of the pixel electrode after the power disconnection procedure has been reset. Figure 8 The solid line shown indicates the potential of the pixel electrode PX. Figure 8 The dashed line shown indicates the potential of the scan line SCL. It should be noted that in this comparative example, at time t2, the common electrode COML converges to the GND potential. In addition, after the potential of the signal line DTL also converges to the GND potential, it becomes a high-impedance state (floating state).

[0081] like Figure 8 As shown, when the gate potential of the pixel transistor Tr connected to the scan line SCL changes from the first potential VGH to the GND potential, the parasitic capacitance CP discharges accordingly. During the period when the pixel transistor Tr remains in the on-state before its potential falls below the threshold voltage Vth, the parasitic capacitance CP is recharged from the signal line DTL via the pixel transistor Tr. However, when the gate potential of the pixel transistor Tr changes drastically, the discharge rate of the parasitic capacitance CP exceeds its recharge rate. This results in a drop in the potential of the pixel electrode PX.

[0082] Furthermore, as described above, during the brief period when the pixel transistor Tr remains in the on state, the signal line DTL, which can serve as the charge supply source for recharging the pixel electrode PX, is in a high-impedance state (floating state) due to the signal line selection control signals ASW and XASW becoming GND. Therefore, due to the charge supply for recharging the pixel electrode PX, the potential of the signal line DTL drops from the GND potential. Consequently, the potential drop of the pixel electrode PX recharged from the signal line DTL becomes more significant. Thus, when the potential of the pixel transistor Tr falls below the threshold voltage Vth, the pixel transistor Tr becomes off, maintaining the state where the potential of the pixel electrode PX is lower than the GND potential.

[0083] The result is, as Figure 7 as well as Figure 8 As shown, the potential difference ΔV between the pixel electrode PX and the reset potential (GND) after the control of driver IC4 stops at time t2 is a negative value, which is considered a residual voltage (GND-ΔV). It is assumed that this residual voltage gradually disappears over time due to the leakage current when the pixel transistor Tr is turned off. However, especially when using semiconductors such as TAOS (transparent amorphous oxide semiconductor) with good voltage retention for image displays or oxide semiconductors with significantly low leakage current at cutoff as the semiconductor material 61, maintaining the residual potential difference ΔV at the pixel electrode PX for a long time may cause liquid crystal burn-in. Furthermore, it is believed that the optimal value of the common potential VCOM will change due to burn-in, which may become a major cause of flickering based on drive methods such as column inversion drive and frame inversion drive.

[0084] In this disclosure, after the driver IC4 stops controlling at time t2, the potential change of the scan line (gate line) SCL from the first potential VGH to the GND potential is slowed down, and the pixel transistor Tr is maintained in the on state. This allows the discharge rate of the parasitic capacitance CP to approach the recharge rate of the parasitic capacitance CP, suppressing the potential drop of the pixel electrode PX. Furthermore, in this disclosure, after time t2, the signal line DTL, which serves as the charge supply source for recharging the pixel electrode PX, is set to the GND potential and maintained in a low impedance state. This suppresses the potential drop of the signal line DTL caused by the charge supply for recharging the pixel electrode PX. Hereinafter, the drive circuit configuration and power-off procedure of the display device 1 according to the embodiment will be described.

[0085] Figure 9 This is a diagram illustrating an example of the drive circuit configuration of the display device according to the embodiment. Figure 10 This is a timing diagram illustrating an example of a power disconnection procedure involved in an implementation.

[0086] Figure 11 Based on Figure 10 The image shows an enlarged view of the potential changes of the pixel electrode after the power disconnection procedure has been reset. Figure 11 The solid line shown indicates the potential of the pixel electrode PX. Figure 11 The dashed line shown indicates the potential of the scan line SCL. Here, the differences between the drive circuit configuration and the power-off procedure of the display device 10 involved in the comparative example and those involved in the comparative example will be described in detail, and repeated descriptions will sometimes be omitted.

[0087] The driving circuit 40 in the embodiment includes: a first switching circuit 45, which maintains the potential of the scan line SCL at the potential of the first power supply voltage signal PSIG1 after the time t2 when the driver IC4 stops controlling; and a second switching circuit 46, which sets the potential of the signal line DTL to the GND potential and maintains it in a low impedance state after the time t2 when the driver IC4 stops controlling.

[0088] Furthermore, in the drive circuit 40 of the embodiment, a reset circuit 47 is included as a configuration for generating signals for controlling the conduction or cutoff of the first switch circuit 45 and the second switch circuit 46. The reset circuit 47 includes a first inverter circuit 471, a second inverter circuit 472, and a buffer circuit 473. The first inverter circuit 471, the second inverter circuit 472, and the buffer circuit 473 are circuits that operate when supplied with a first power supply voltage signal PSIG1 and a second power supply voltage signal PSIG2 from the power supply device 12. Furthermore, in the drive circuit 40 of the embodiment, an OR circuit 425 and a NOR circuit 426 are included instead of the AND circuit 424 configured in the comparative example.

[0089] The first inverter circuit 471 generates a Reset signal by logically inverting the reset signal XReset supplied from the display control circuit 44. The second inverter circuit 472 generates an iXReset signal by logically inverting the Reset signal output from the first inverter circuit 471. The buffer circuit 473 generates an iReset signal that is logically equal to the Reset signal output from the first inverter circuit 471. The iXReset signal generated by the second inverter circuit 472 and the iReset signal generated by the buffer circuit 473 are complementary signals that are logically inverted.

[0090] The first switching circuit 45, for example, includes a switching transistor PUTr composed of a p-type TFT.

[0091] A first power supply voltage signal PSIG1 is supplied to the source of the switching transistor PUTr. The drain of the switching transistor PUTr is connected to the scan line SCL. In addition, the iXReset signal from the second inverter circuit 472 is supplied to the gate of the switching transistor PUTr.

[0092] The second switching circuit 46 includes, for example, a switching transistor PDTr composed of an n-type TFT and a switching transistor XPDTr composed of a p-type TFT. An iReset signal from the buffer circuit 473 is supplied to the gate of the switching transistor PDTr. An iXReset signal from the second inverter circuit 472 is supplied to the gate of the switching transistor XPDTr.

[0093] To ensure a slow potential change in the scan line SCL from the first potential VGH to the GND potential after driver IC4 stops controlling at time t2, and to maintain the conduction state of the pixel transistor Tr, the first switching circuit 45 (switching transistor PUTr) needs to remain in the conducting state after time t2. Furthermore, to maintain the signal line DTL, which will become the charge supply source for recharging the pixel electrode PX, at a low impedance state after time t2, the second switching circuit 46 (switching transistors PDTr, XPDTr) needs to remain in the conducting state after time t2.

[0094] Figure 12A This is a diagram showing the circuit configuration of the first inverter circuit. Figure 12B This is a diagram showing the input and output potentials of the first inverter circuit.

[0095] like Figure 12A As shown, the first inverter circuit 471 includes, for example, a switching transistor Trp composed of a p-type TFT and a switching transistor Trn composed of, for example, an n-type TFT. A first power supply voltage signal PSIG1 is supplied to the source of the switching transistor Trp. The drain of the switching transistor Trp is connected to the drain of the switching transistor Trn. A second power supply voltage signal PSIG2 is supplied to the source of the switching transistor Trn. A reset signal XReset from the display control circuit 44 is input to the gates of the switching transistors Trn and Trp. A Reset signal is output from the connection point between the drains of the switching transistors Trp and Trn.

[0096] In this disclosure, in order to maintain the on-state of the first switching circuit 45 (switching transistor PUTr) after the driver IC4 stops controlling it at time t2, when the reset signal XReset supplied from the display control circuit 44 becomes GND at time t2, the potential of the iReset signal needs to be maintained at the potential of the first power supply voltage signal PSIG1. Furthermore, in order to maintain the on-state of the second switching circuit 46 (switching transistors PDTr, XPDTr) after the driver IC4 stops controlling it at time t2, when the reset signal XReset supplied from the display control circuit 44 becomes GND at time t2, the potential of the iReset signal needs to be maintained at the potential of the first power supply voltage signal PSIG1, and the potential of the iXReset signal needs to be maintained at the potential of the second power supply voltage signal PSIG2.

[0097] In this disclosure, in order to maintain the relationship that Idsp >> Idsn between the drain current Idsp of the switching transistor Trp and the drain current Idsn of the switching transistor Trn in the first inverter circuit 471, the relationship between the channel width Wp and the channel width Wn of the switching transistor Trp is set as Wp >> Wn. Thus, as... Figure 12B As shown, the potential of the Reset signal can be maintained at the potential of the first power supply voltage signal PSIG1 when the reset signal XReset becomes GND.

[0098] As a result, when the reset signal XReset supplied from the display control circuit 44 becomes GND at time t2, the potential of the iReset signal can be maintained at the potential of the first power supply voltage signal PSIG1, and the potential of the iXReset signal can be maintained at the potential of the second power supply voltage signal PSIG2. Therefore, during the predetermined period from the time t2 when the driver IC4 stops controlling until the first power supply voltage signal PSIG1 falls below the threshold voltage Vth of the pixel transistor Tr, the first switching circuit 45 (switching transistor PUTr) is maintained in the on state, and the second switching circuit 46 (switching transistors PDTr and XPDTr) is maintained in the on state. Specifically, the period for maintaining the on state of the first switching circuit 45 depends on the threshold voltage Vth of the switching transistor PUTr. Furthermore, the period for maintaining the on state of the second switching circuit 46 depends on the threshold voltage Vth of the switching transistors PDTr and XPDTr.

[0099] It should be noted that the circuit configuration of the second inverter circuit 472 can be formed in the same way as the first inverter circuit 471, but in the second inverter circuit 472, it is not necessary to satisfy the relationship Idsp>>Idsn(Wp>>Wn).

[0100] As described above, the first inverter circuit 471, the second inverter circuit 472, and the buffer circuit 473 operate by being supplied with a first power supply voltage signal PSIG1 and a second power supply voltage signal PSIG2 from the power supply device 12. Furthermore, the potentials of the first power supply voltage signal PSIG1 and the second power supply voltage signal PSIG2 gradually decrease due to the power supply smoothing capacitor (not shown) included in the power supply device 12. Therefore, after the moment t2 when the driver IC4 stops controlling, the potentials of the first power supply voltage signal PSIG1 and the second power supply voltage signal PSIG2 can maintain the conducting state of each transistor in the first switching circuit 45 and the second switching circuit 46 for a long time relative to the potentials of the control signals output from the driver IC. Moreover, the potentials of the first power supply voltage signal PSIG1 and the second power supply voltage signal PSIG2 converge to the GND potential as the power supply smoothing capacitor (not shown) discharges.

[0101] The following is for reference Figure 10 as well as Figure 11 The power-off procedure for the display device 1 according to the above embodiment will be described. Here, the power-off procedure for the display device 1 will be described. Figure 7 as well as Figure 8 The differences in the power-off procedure of the display device 10 involved in the comparative examples shown will be described in detail, and repeated descriptions will sometimes be omitted.

[0102] At time t1 (the first time), the display control circuit 44 sets the reset signal XReset to a low potential (second potential VGL). Consequently, the potential of the Reset signal becomes high (first potential VGH), and the potential of the iReset signal also becomes high (first potential VGH). Simultaneously, the output potential of the OR circuit 425 becomes high (first potential VGH), and the potential of the NOR circuit 426 becomes low (second potential VGL). Therefore, the first transistor Tr1, the second transistor Tr2, and the third transistor Tr3 of the scan line drive circuit 422 are turned off.

[0103] Additionally, the potential of the iXReset signal becomes low (second potential VGL). Consequently, the switching transistor PUTr of the first switching circuit 45 is turned on, the potential of the scan line SCL becomes the first potential VGH of the first power supply voltage signal PSIG1, and the pixel transistors Tr of all pixels Pix are turned on. At the same time, the switching transistors PDTr and XPDTr of the second switching circuit 46 are simultaneously turned on, and the potential of the signal line DTL becomes GND. Therefore, the pixel electrodes PX of all pixels Pix are electrically connected to the GND potential signal line DTL via the turned-on pixel transistors Tr, and the potential of the pixel electrodes PX of all pixels Pix is ​​reset to GND.

[0104] At time t2 (the second time point) after resetting the potential of the pixel electrodes PX of all pixels Pix, the power supply device 12 stops supplying the first power supply voltage signal PSIG1 and the second power supply voltage signal PSIG2 to the display device 1 based on the second power control signal PCTRL2 output from the control device 13. As a result, the driver IC4 stops control, and the potentials of the synchronization signals such as the start pulse STV, the shift clock CKV, all scan line drive signals ENB, the reset signal XReset, and the signal line selection control signals ASW and XASW corresponding to all signal lines DTL become the GND potential.

[0105] As described above, the first power supply voltage signal PSIG1 and the second power supply voltage signal PSIG2 supplied to the first inverter circuit 471, the second inverter circuit 472, and the buffer circuit 473 gradually decrease in potential through the power smoothing capacitor (not shown) provided in the power supply device 12 after the driver IC4 stops controlling at time t2. Furthermore, after time t2, all scan lines SCL are substantially connected to the source of the first switching circuit 45, thus supplying the first power supply voltage signal PSIG1 to the gate of all pixel transistors Tr. Therefore, as... Figure 11 As shown, the conduction state of the pixel transistor Tr follows the decrease in potential of the first power supply voltage signal PSIG1, maintaining the conduction state of the pixel transistor Tr for a longer period of time than that of the display device 10 of the comparative example. Specifically, when the power supply is turned off, the first power supply voltage signal PSIG1 maintains a potential above the threshold voltage of the pixel transistor Tr even after the driver IC4 stops controlling the gate driver 42 and the signal line selection circuit 43. As a result, the gate potential of the pixel transistor Tr decreases more slowly than that of the display device 10 of the comparative example, so the discharge rate of the parasitic capacitance CP is close to the recharge rate of the parasitic capacitance CP, suppressing the potential drop of the pixel electrode PX.

[0106] Furthermore, the signal line DTL, which serves as the charge supply source for recharging the pixel electrode PX, remains in a low-impedance state when set to GND. This suppresses the potential drop in the signal line DTL caused by the charge supply for recharging the pixel electrode PX. As a result, the negative potential difference ΔV1 generated at the pixel electrode PX after the moment t2 when the driver IC4 stops controlling becomes smaller than the negative potential difference ΔV generated at the pixel electrode PX after the moment t2 when the driver IC4 stops controlling in the display device 10 of the comparative example (ΔV1 < ΔV).

[0107] The display device 1 and the above-described embodiments Figure 6Compared to the configuration shown in the comparative example, the residual potential of the pixel electrode PX after the moment t2 when the driver IC4 stops controlling is suppressed, thus reducing the potential difference relative to the reset potential, i.e., the GND potential. Therefore, screen burn-in of the liquid crystal caused by the residual voltage of the pixel electrode PX after power disconnection can be suppressed. Furthermore, flickering caused by fluctuations in the optimal value of the common potential VCOM due to screen burn-in can be suppressed.

[0108] It should be noted that the display device 1 is not limited to a liquid crystal display device; for example, it can also be an organic EL display that uses an organic light-emitting diode (OLED) as a display element. Alternatively, the display device 1 can also be an inorganic EL display that uses an inorganic light-emitting diode (micro LED) as a display element. Furthermore, the display device 1 can be an electrophoretic display (EPD), and even a transparent display that displays images on a translucent display surface.

[0109] The preferred embodiments of this disclosure have been described above, but this disclosure is not limited to such embodiments. The content disclosed in the embodiments is merely an example, and various modifications can be made without departing from the spirit of this disclosure. Appropriate modifications made without departing from the spirit of this disclosure are of course also within the technical scope of this disclosure.

[0110] Explanation of reference numerals in the attached figures

[0111] 1, 10, Display device; 4, Driver IC; 11, Display panel; 12, Power supply device; 13, Control device; 40, Drive circuit; 42, Gate driver; 43, Signal line selection circuit; 44, Display control circuit; 45, First switching circuit; 46, Second switching circuit; 47, Reset circuit; AA, Display area; COML, Common electrode; CS, Holding capacitor; CP, Parasitic capacitance; DTL, Signal line; ENB, Scan line drive signal; GATE, Scan signal (gate signal); PCTRL1, First power control signal; PCTRL2, Second power control signal; Pix, Pixel; PSIG1, First power voltage signal; PSIG2, Second power voltage signal; PX, Pixel electrode; Source, Image signal; SCL, Scan line (gate line); SIG, Pixel signal; Tr, Pixel transistor; VCOM, Common potential; VGH, First potential; VGL, Second potential; Vsig, Image signal; XReset, Reset signal.

Claims

1. A display device comprising: A pixel has a pixel transistor and a pixel electrode, wherein the pixel electrode is connected to a first electrode of the pixel transistor; The scan line is connected to the gate of the pixel transistor; The signal line is connected to the second electrode of the pixel transistor; as well as The driving circuit is supplied with a positive first power supply voltage signal and a negative second power supply voltage signal to drive the pixel transistor. The driving circuit includes: A gate driver supplies a scan signal to the scan line; A signal line selection circuit supplies pixel signals to the signal lines; as well as The display control circuit controls the gate driver and the signal line selection circuit. During display operation, a holding capacitor is provided between the pixel electrode and the common electrode, which is supplied with a potential lower than the GND potential. The driving circuit includes: The first switching circuit is turned on at the first moment of the power-off procedure to supply the first power supply voltage signal to the scan line. The second switching circuit is turned on at the first moment to supply GND potential to the signal line. as well as The reset circuit maintains the conduction control state of the first switching circuit and the second switching circuit after the control of the gate driver and the signal line selection circuit stops at a second time after the first time.

2. The display device according to claim 1, wherein, The reset circuit maintains the conduction control state of the first switching circuit and the second switching circuit for a predetermined period from the time when the control of the gate driver and the signal line selection circuit stops at the second moment until the first power supply voltage signal becomes below the threshold voltage of the pixel transistor.

3. The display device according to claim 1, wherein, The display device includes at least a driver IC comprising the display control circuit.

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