Reconfigurable digital low-dropout regulator structure and control method

Abstract

This invention discloses a reconfigurable digital low-dropout regulator (DLDO) structure and control method, belonging to the field of integrated circuit technology. The reconfigurable digital low-dropout regulator of this invention includes: a first comparator, a digital logic control module, a MOS main array, an auxiliary reconfiguration array, and a voltage sampling module. The digital logic control module provides control signals to the MOS main array and digital calibration signals to the auxiliary reconfiguration array. The voltage sampling module quantifies the output voltage disturbance and configures the MOS main array and auxiliary reconfiguration array according to the disturbance magnitude. The voltage sampling module, combined with the digital logic control module, can identify and quantify dynamic load changes, achieving adaptive calibration design to improve the DLDO load regulation and reduce its voltage ripple. Furthermore, combined with off-chip calibration design, it further improves the load regulation and enhances the accuracy of power supply disturbance correction.

Description

Technical Field

[0001] This invention relates to the structure and control method of a reconfigurable digital low-dropout regulator, belonging to the field of integrated circuit technology. Background Technology

[0002] With the continuous development of modern integrated circuits, especially the rapid development of high-performance sensors and in-memory computing, the requirements for low-noise and stable power supplies in high-precision analog circuits are constantly increasing. Low-dropout linear regulators (LDOs) can provide different voltages for different functional modules and are widely used in various power chips or high-precision bias designs. At lower supply voltages (<1V), analog LDOs cannot operate in their normal operating range, leading to performance degradation. In contrast, digital LDOs (DLDOs), proposed in recent years, can be widely used in low-voltage power supply modules. The excellent performance and applicability of DLDOs make them an indispensable component of modern integrated circuits. Furthermore, in common high-performance sensor designs, DLDOs can provide low-power power supply designs for critical analog IPs; for in-memory computing chips, low-power designs can also provide greater energy efficiency. Compared to traditional LDOs, DLDOs have a smaller area and lower static power consumption.

[0003] In summary, based on its advantages in low power consumption, high efficiency, and high integration, the application of DLDOs in on-chip power chip architectures is becoming increasingly prominent, enabling them to adapt to diverse application scenarios and bringing greater flexibility, reliability, and performance improvements to the design and application of various high-performance sensors or in-memory computing chips. However, common DLDOs suffer from significant output voltage ripple and noise. These nonlinear error factors often introduce unacceptable power supply disturbances to critical analog circuits requiring high precision and low noise. Traditional DLDO designs primarily utilize comparators to compare the output voltage with a reference voltage and control the MOS array through a bidirectional shift register (S / R) to stabilize the output voltage. This type of structure has the following problems: 1. Large voltage ripple, making it unsuitable for high-precision on-chip power supplies. 2. To achieve better load regulation and line regulation, high-frequency clocks and increased area consumption are often required.

[0004] To address the aforementioned issues, in 2020, Hefei Xinsheng Optoelectronic Technology Co., Ltd. proposed a digital voltage regulator and its regulation method (CN109947163B). Although it employs a voltage sampling technology to achieve two modes of control for the output voltage, it fails to demonstrate advantages in transient response and load adjustment. In 2021, South China University of Technology et al. proposed a fast-response digital low-dropout regulator (CN112068630A). Although it has optimized transient characteristics, it exceeds the inherent design range due to disturbances caused by large load switching. In 2023, Xi'an Jiaotong University et al. proposed a step-adjustable dual-loop digital LDO structure and control method (CN114815945A). Although it can dynamically adjust the DLDO output through the voltage range quantization of Flash ADC, it cannot make precise adjustments for small-range disturbances. Summary of the Invention

[0005] To improve the accuracy of power supply disturbance correction, this invention provides a reconfigurable digital low-dropout regulator structure and control method, the technical solution of which is as follows:

[0006] The first objective of this invention is to provide a reconfigurable digital low-dropout regulator, comprising: a first comparator comp1, a digital logic control module, a MOS main array, an auxiliary reconfiguration array, and a voltage sampling module;

[0007] The input terminals of the first comparator comp1 are respectively connected to the reference voltage V. ref The output voltage is connected to the input terminal of the digital logic control module;

[0008] The digital logic control module is connected to the MOS main array via a drive switch, providing control signals to the MOS main array; the digital logic control module also provides digital calibration signals to the auxiliary reconfiguration array.

[0009] The voltage sampling module is used to acquire the output voltage. The digital logic control module quantifies the disturbance of the output voltage through the first comparator comp1 and the voltage sampling module, and configures the MOS main array and auxiliary reconfiguration array according to the disturbance magnitude.

[0010] Optionally, the digital logic control module includes: a successive approximation algorithm + bidirectional shift register (S / R) module, a digital trimming module, and a drive switch;

[0011] The input of the successive approximation algorithm + bidirectional shift register S / R module is connected to the output of the first comparator comp1 and the output of the external register. The output of the successive approximation algorithm + bidirectional shift register S / R module is connected to the input of the MOS main array through the drive switch.

[0012] The input of the digital Trimming module is connected to the output of the external register, and the output of the digital Trimming module is connected to the auxiliary reconfiguration array through the drive switch.

[0013] Optionally, the voltage sampling module includes: a second comparator comp2, a third comparator comp3, a fourth comparator comp4, a first digital gate, and a second digital gate;

[0014] The input terminals of the second comparator comp2 are respectively connected to the output voltage and the first reference voltage V. H The output terminal is connected to the input terminal of the first digital gate;

[0015] The input terminals of the third comparator comp3 are respectively connected to the output voltage and the second reference voltage V. L The output terminal is connected to the input terminal of the second digital gate;

[0016] The input terminals of the fourth comparator comp4 are respectively connected to the output voltage and the reference voltage V. ref The output terminal is connected to the input terminal of the external register;

[0017] The input terminals of the first digital gate are respectively connected to the output terminals of the second comparator comp2 and the third comparator comp3, and the output terminal is connected to the fourth comparator comp4;

[0018] The input terminals of the second digital gate are respectively connected to the output terminals of the second comparator comp2 and the third comparator comp3, and the output terminals are connected to the input terminals of the external register.

[0019] Among them, V L <V ref <V H .

[0020] Optionally, the operation of the reconfigurable digital low-dropout regulator includes:

[0021] I. Preparation Phase: The circuit is reset, and the bidirectional shift register S / R is configured in the default state;

[0022] II. Start-up Phase:

[0023] When the circuit starts up, if the output voltage Vout is less than the reference voltage Vref, the output C1 of the first comparator Comp1 is 1, the output C2 of the second comparator Comp2 is 1, and the output C3 of the third comparator Comp3 is 0, and the output voltage starts up quickly under the successive approximation algorithm.

[0024] When the output voltage Vout enters the preset voltage range (V L <Vout<Vref<V H When the outputs of the first comparator Comp1 (C1=1), the outputs of the second comparator Comp2 (C2=1), and the outputs of the third comparator Comp3 (C3=1), under the quantization of the voltage sampling module, the digital control module switches from the successive approximation algorithm to bidirectional shift register S / R controlling the MOS main array; the enable signal of the fourth comparator Comp4 is controlled by C2 and C3. When C2C3=11, Comp4 starts working, and the circuit enters the reconfiguration stage.

[0025] (III) Restructuring Phase:

[0026] When the output voltage Vout enters the preset voltage range and is less than the reference voltage (V L <Vout<V ref <V H The output C4 of the fourth comparator Comp4 is 0. Under the control of the fourth comparator Comp4, digital trimming is activated. By controlling the auxiliary reconfiguration array, the number of configured MOS is increased to achieve small-range adjustment.

[0027] When the output voltage Vout is greater than the reference voltage (V L <Vref<Vout<V H The output C4 of the fourth comparator Comp4 is 1. Under the control of the fourth comparator Comp4, digital trimming is activated. By controlling the auxiliary reconfiguration array, the number of configured MOS is reduced, and a small-range adjustment is achieved.

[0028] If the output voltage Vout changes due to dynamic changes in the load or some additional disturbances;

[0029] When the output voltage Vout is greater than the first reference voltage V H Or less than the second reference voltage V L When (Vout < V) L or V H <Vout), the output C2 of the second comparator comp2 is 0, the output C3 of the third comparator comp3 is 1, and the digital control module switches back to the successive approximation algorithm under the control of the second comparator comp2 and the third comparator comp3.

[0030] Optionally, the working process further includes: an off-chip adjustment stage, in which if the disturbance is large, all main arrays are working and the output voltage Vout is still greater than the first reference voltage V. H Or less than the second reference voltage VL At the same time, the auxiliary reconfiguration array is controlled by the off-chip configuration register to increase or decrease the number of configuration MOS, thereby achieving dynamic adjustment.

[0031] Optionally, the MOS master array includes 256 MOS transistors controlled by a successive approximation algorithm and 32 MOS transistors controlled by the bidirectional shift register S / R.

[0032] Optionally, the auxiliary reconfiguration array includes 16 MOS transistors controlled by the digital Trimming module.

[0033] Optionally, the regulator further includes a mode control circuit MODE, used to configure the bidirectional shift register S / R according to the actual working array.

[0034] A second objective of this invention is to provide a reconfigurable digital low-dropout voltage regulator method, implemented based on any of the reconfigurable digital low-dropout voltage regulators described above, comprising:

[0035] The perturbation of the output voltage is quantified by the first comparator comp1 and the voltage sampling module. The digital logic control module executes the successive approximation algorithm or the bidirectional shift register S / R according to the magnitude of the perturbation to determine how to configure the MOS array. The Trimming module is configured according to the result of the fourth comparator comp4 to realize the reconfigurable design.

[0036] The beneficial effects of this invention are:

[0037] The reconfigurable digital low-dropout regulator provided by this invention has the following advantages compared with the prior art: 1. In this invention, the voltage sampling module combined with the digital logic control module can identify and quantify dynamic changes in the load, realize adaptive calibration design to improve the load regulation of the DLDO, and reduce its voltage ripple. 2. Combined with off-chip calibration design, the load regulation is further improved, and the accuracy of power supply disturbance correction is enhanced. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a diagram of the reconfigurable digital low-dropout regulator architecture of the present invention.

[0040] Figure 2 for Figure 1 Diagram of each MOS array architecture.

[0041] Figure 3 This is a diagram illustrating the working mode of the digital logic control module of the present invention.

[0042] Figure 4 This is a timing diagram of the reconfigurable digital low-dropout regulator of the present invention.

[0043] Figure 5 This is a schematic diagram of a common DLDO circuit.

[0044] Figure 6 for Figure 1 The diagram shows a simulation of a reconfigurable digital low-dropout regulator.

[0045] Figure 7 This is a circuit architecture diagram for a high-precision bias power supply.

[0046] Figure 8 for Figure 7 MODE circuit architecture diagram. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0048] Example 1:

[0049] This embodiment provides a reconfigurable digital low-dropout regulator, including: a first comparator comp1, a digital logic control module, a MOS main array, an auxiliary reconfiguration array, and a voltage sampling module;

[0050] The input terminals of the first comparator comp1 are connected to the reference voltage Vref and the output voltage, respectively, and the output terminal is connected to the input terminal of the digital logic control module.

[0051] The digital logic control module is connected to the MOS main array via a drive switch, providing control signals to the MOS main array; the digital logic control module also provides digital calibration signals to the auxiliary reconfiguration array.

[0052] The voltage sampling module is used to acquire the output voltage. The digital logic control module quantifies the disturbance of the output voltage through the first comparator comp1 and the voltage sampling module, and determines how to configure the MOS main array and auxiliary reconfiguration array according to the magnitude of the disturbance.

[0053] Example 2:

[0054] This embodiment provides a reconfigurable digital low-dropout regulator. (See also...) Figure 1 The circuit includes: a first comparator comp1, a digital logic control module, a MOS main array, an auxiliary reconfiguration array, and a voltage sampling module;

[0055] The inputs of the first comparator comp1 are connected to the reference voltage V. ref and output voltage V out The output terminal is connected to the input terminal of the digital logic control module.

[0056] The digital logic control module includes two operating modes (Successive Approximation +S / R, Trimming). In the Successive Approximation +S / R operating mode, the algorithm module is controlled by the output of comp1 and external registers, and is connected to the MOS master array through a drive switch to provide control signals to the MOS master array. In the Trimming operating mode, the algorithm module is controlled by the output of comp1 and external registers, and is provided with digital calibration signals for the auxiliary reconstruction array through a drive switch.

[0057] The digital logic control module includes: a successive approximation algorithm + bidirectional shift register (S / R) module, a digital trimming module, and a drive switch;

[0058] The input of the successive approximation algorithm + bidirectional shift register (S / R) module is connected to the output of the first comparator comp1 and the output of the external register. The output of the successive approximation algorithm + bidirectional shift register (S / R) module is connected to the input of the MOS master array through a drive switch.

[0059] The input of the digital Trimming module is connected to the output of an external register, and the output of the digital Trimming module is connected to an auxiliary reconfiguration array via a drive switch.

[0060] The voltage sampling module is used to acquire the output voltage. The digital logic control module quantifies the disturbance of the output voltage through the first comparator comp1 and the voltage sampling module, and determines how to configure the MOS main array and auxiliary reconfiguration array according to the magnitude of the disturbance.

[0061] Specifically, the voltage sampling module includes: a second comparator comp2, a third comparator comp3, a fourth comparator comp4, a first digital gate (AND gate), and a second digital gate (XNOR gate).

[0062] The inputs of the second comparator comp2 are connected to the output voltage and the first reference voltage V, respectively. H The output terminal is connected to the input terminal of the first digital gate;

[0063] The inputs of the third comparator comp3 are connected to the output voltage and the second reference voltage V, respectively. L The output terminal is connected to the input terminal of the second digital gate;

[0064] The inputs of the fourth comparator, comp4, are connected to the output voltage and the reference voltage, V, respectively. ref The output terminal is connected to the input terminal of an external register;

[0065] The inputs of the first digital gate are connected to the outputs of the second comparator comp2 and the third comparator comp3, respectively, and the outputs are connected to the fourth comparator comp4.

[0066] The inputs of the second digital gate are connected to the outputs of the second comparator comp2 and the third comparator comp3, respectively, and the outputs are connected to the inputs of an external register.

[0067] Among them, V L <V ref <V H .

[0068] The main MOS array comprises 256 MOS transistors controlled by a successive approximation algorithm and 32 MOS transistors controlled by the bidirectional shift register S / R; the auxiliary reconfiguration array comprises 16 MOS transistors, with the specific connection relationships as follows... Figure 2 As shown.

[0069] The working principle of this embodiment is as follows: the digital logic control module consists of a successive approximation algorithm, a bidirectional shift register (S / R), and a drive switch, and in combination with digital trimming, it provides a small range of digital calibration signals for the subsequent auxiliary reconstruction array. Figure 3 This diagram illustrates the operating mode of the digital logic control module. C1, C2, C3, and C4 represent the output code values ​​of comparators Comp1, Comp2, Comp3, and Comp4, respectively. After circuit startup, the digital logic control module quantifies the disturbance to the output voltage based on load changes through the comparators and voltage sampling module, and calculates the value according to V. out Does it exceed the preset voltage range V? L and V H Decide how to configure the MOS array.

[0070] When the disturbance is large (V) out <V L or V H <V out The digital logic control module executes a successive approximation algorithm; when the disturbance is small (V L <V out <V H The digital logic control module executes the bidirectional shift register (S / R) module. The Trimming module is configured based on the comp4 results to achieve a reconfigurable design.

[0071] The timing diagram of the reconfigurable digital low-dropout regulator provided in this embodiment is as follows: Figure 4 As shown, its specific working process is as follows:

[0072] (I) Preparation phase: All circuits are reset and the registers are configured in the default state.

[0073] (II) Start-up Phase: The circuit starts up when the output voltage V out Less than the reference voltage V ref Time (V) ref <V out Comparator Comp1 outputs C1=1, Comp2 outputs C2=1, and Comp3 outputs C3=0. The output voltage starts up quickly due to the successive approximation algorithm. When the output voltage enters the preset voltage range (V... L <V out <V ref <V H When the comparators Comp1, Comp2, and Comp3 outputs C1=1, Comp2, and Comp3 respectively, the digital control module of the voltage sampling module switches from the successive approximation algorithm to the bidirectional shift register S / R controlling the MOS main array. The enable signal of Comp4 is controlled by C2 and C3. When C2C3=11, Comp4 starts working, and the circuit enters the reconstruction stage.

[0074] (III) Reconstruction Stage: When the output voltage enters the preset voltage range and is less than the reference voltage (V L <V out <V ref <V H When Comp4 outputs C4=0, digital Trimming is activated under Comp4 control. By controlling the auxiliary reconfiguration array, the number of configured MOS is increased to achieve a small-range adjustment. When the output voltage is greater than the reference voltage (V... L <V ref <V out <V H When Comp4 outputs C4=1, digital trimming is activated under Comp4 control. This reduces the number of configured MOS transistors by controlling the auxiliary reconfiguration array, achieving a small-range adjustment. If the output voltage V is affected by dynamic load changes or additional disturbances... out The change occurs. When the output voltage V out Greater than the preset voltage V H Or less than the preset voltage V L Time (V) out <V L V H <V out ), Comp2 outputs C2=0, Comp3 outputs C3=1. The digital control module switches back to the successive approximation algorithm under the control of Comp2 and Comp3; if the disturbance is large (V out <V Lor V H <V out The main array is fully operational and the output voltage V out Still greater than the preset voltage V H Or less than the preset voltage V L Furthermore, the auxiliary reconfiguration array can be controlled through the off-chip configuration register to increase or decrease the number of configuration MOS, thereby achieving a certain degree of dynamic adjustment.

[0075] (iv) External adjustment stage: When ctr_out = 1, the auxiliary reconstruction array can be directly controlled by manually configuring ctr_reg<3:0> externally.

[0076] This embodiment reduces voltage ripple and improves load regulation by using voltage sampling technology to quantize the output voltage range, combined with successive approximation algorithms and internal and external digital trimming.

[0077] Common DLDO circuits such as Figure 5 As shown, it is implemented using a comparator, a bidirectional shift register (S / R), and a MOS array. This embodiment optimizes the transient response of the DLDO by combining a successive approximation algorithm with a bidirectional shift register (S / R). Simultaneously, a reconfigurable design improves the DLDO's line regulation and load regulation. Simulation results under standard CMOS 55nm process circuit simulation are compared as follows... Figure 6 As shown, by combining the successive approximation algorithm and the bidirectional shift register (S / R), the voltage ripple of the reconfigurable digital low-dropout regulator is ΔV2, compared to the voltage ripple ΔV1 of the traditional DLDO, representing a 77.2% reduction in voltage ripple.

[0078] Example 3:

[0079] This embodiment provides a high-precision bias power supply circuit for sensor readout circuits. Based on Embodiment 2, it adds a mode control circuit (MODE) that switches with the array. The bias circuit is designed as follows: Figure 7 As shown. The MODE circuit architecture is as follows: Figure 8 As shown. The MODE circuit includes: a 16-4 encoder and four voltage level shifters.

[0080] For common readout circuits, the bias circuit does not have an additional calibration and configuration cycle during operation. Therefore, a mode control circuit that switches with the array is required. Each time the readout array switches, the bias circuit can configure the optimal result according to the load. Its working principle is as follows: when the readout circuit is operating, the MODE circuit can configure the external registers via ctr_reg<3:0> according to the actual working array to compensate for disturbances caused by load changes within a certain range.

[0081] For example: the current ctr_reg<3:0> controlled by the MODE circuit is 0111. When a new active read array is added, ctr_reg<3:0> becomes 1000, and the auxiliary reconfiguration array adds a power transistor to the MOS main array. When a new active read array is removed, ctr_reg<3:0> becomes 0110, and the auxiliary reconfiguration array removes a power transistor from the MOS main array.

[0082] Some steps in the embodiments of the present invention can be implemented using software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.

[0083] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A reconfigurable digital low-dropout regulator, characterized in that, The reconfigurable digital low-dropout regulator includes: a first comparator (comp1), a digital logic control module, a MOS main array, an auxiliary reconfiguration array, and a voltage sampling module; The input terminals of the first comparator (comp1) are connected to a reference voltage V ref and an output voltage Vout, respectively, and the output terminal is connected to an input terminal of the digital logic control module. The digital logic control module is connected to the MOS main array via a drive switch, providing control signals to the MOS main array; the digital logic control module also provides digital calibration signals to the auxiliary reconfiguration array. The voltage sampling module is used to acquire the output voltage Vout. The digital logic control module quantifies the disturbance of the output voltage Vout through the first comparator (comp1) and the voltage sampling module, and configures the MOS main array and auxiliary reconfiguration array according to the disturbance magnitude. The digital logic control module includes: a successive approximation algorithm + bidirectional shift register (S / R) module, a digital trimming module, and a drive switch; The input of the successive approximation algorithm + bidirectional shift register (S / R) module is connected to the output of the first comparator (comp1) and the output of the external register. The output of the successive approximation algorithm + bidirectional shift register (S / R) module is connected to the input of the MOS main array through the drive switch. The input of the digital Trimming module is connected to the output of the external register, and the output of the digital Trimming module is connected to the auxiliary reconfiguration array through the drive switch. The voltage sampling module includes: a second comparator (comp2), a third comparator (comp3), a fourth comparator (comp4), a first digital gate, and a second digital gate; The input terminals of the second comparator (comp2) are connected to the output voltage Vout and a first reference voltage V H , respectively, and the output terminal is connected to the input terminal of the first digital gate. The input terminals of the third comparator (comp3) are connected to the output voltage Vout and a second reference voltage Vref2, respectively L , and the output terminal is connected to the input terminal of the second digital gate. The input terminals of the fourth comparator (comp4) are connected to the output voltage Vout and a reference voltage Vref, respectively ref and the output terminal is connected to the input terminal of the external register. The input terminals of the first digital gate are respectively connected to the output terminals of the second comparator (comp2) and the third comparator (comp3), and the output terminal is connected to the fourth comparator (comp4). The input terminals of the second digital gate are respectively connected to the output terminals of the second comparator (comp2) and the third comparator (comp3), and the output terminal is connected to the input terminal of the external register; V L V ref V H ; The operation of the reconfigurable digital low-dropout regulator includes: (a) Preparation phase: The circuit is reset, and the bidirectional shift register (S / R) is configured in the default state; (II) Start-up Phase: When the circuit starts up, if the output voltage Vout is less than the reference voltage Vref, the output C1 of the first comparator (comp1) is 1, the output C2 of the second comparator (comp2) is 1, and the output C3 of the third comparator (comp3) is 0. The output voltage starts up quickly under the successive approximation algorithm. When the output voltage Vout enters the preset voltage range, that is, V L <Vout<Vref<V H With the output C1=1 of the first comparator (comp1), the output C2=1 of the second comparator (comp2), and the output C3=1 of the third comparator (comp3), the digital logic control module switches from a successive approximation algorithm to a bidirectional shift register (S / R) controlling the MOS main array under the quantization of the voltage sampling module. The enable signal of the fourth comparator (comp4) is controlled by C2 and C3. When C2C3=11, the fourth comparator (comp4) starts working, and the circuit enters the reconstruction stage. (III) Restructuring Phase: When the output voltage Vout enters the preset voltage range and is less than the reference voltage, that is, V L <Vout<V ref <V H The output C4 of the fourth comparator (comp4) is 0. Under the control of the fourth comparator (comp4), digital trimming is activated. By controlling the auxiliary reconfiguration array, the number of configured MOS is increased to achieve small-range adjustment. When the output voltage Vout is greater than the reference voltage, i.e. V L <Vref<Vout<V H The output C4 of the fourth comparator (comp4) is 1. Under the control of the fourth comparator (comp4), digital trimming is activated. By controlling the auxiliary reconfiguration array, the number of configured MOS is reduced, and a small-range adjustment is achieved. If the output voltage Vout changes due to dynamic changes in the load or some additional disturbances; When the output voltage Vout is greater than the first reference voltage V H Or less than the second reference voltage V L When, i.e., Vout < V L or V H <Vout, the output C2 of the second comparator (comp2) is 0, the output C3 of the third comparator (comp3) is 1, and the digital logic control module switches back to the successive approximation algorithm under the control of the second comparator (comp2) and the third comparator (comp3).

2. The reconfigurable digital low-dropout regulator according to claim 1, characterized in that, The working process also includes: an off-chip adjustment stage, where if the main array is fully operational and the output voltage Vout is still greater than the first reference voltage V... H Or less than the second reference voltage V L At the same time, the auxiliary reconfiguration array is controlled by the off-chip configuration register to increase or decrease the number of configuration MOS, thereby achieving dynamic adjustment.

3. The reconfigurable digital low-dropout regulator according to claim 1, characterized in that, The MOS master array includes 256 MOS transistors controlled by a successive approximation algorithm and 32 MOS transistors controlled by the bidirectional shift register (S / R).

4. The reconfigurable digital low-dropout regulator according to claim 1, characterized in that, The auxiliary reconstruction array includes 16 MOS transistors controlled by the digital Trimming module.

5. The reconfigurable digital low-dropout regulator according to claim 1, characterized in that, The voltage regulator also includes a mode control circuit (MODE) for configuring the external registers according to the actual operating array.

6. A reconfigurable digital low-dropout voltage regulation method, characterized in that, The voltage regulation method is implemented based on the reconfigurable digital low-dropout regulator according to any one of claims 1-5, and includes: The perturbation of the output voltage is quantified by the first comparator (comp1) and the voltage sampling module. The digital logic control module executes a successive approximation algorithm or a bidirectional shift register (S / R) according to the magnitude of the perturbation to determine how to configure the MOS array. The Trimming module is configured according to the result of the fourth comparator (comp4) to realize a reconfigurable design.

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