Chip layout method and device, and electronic equipment

Abstract

The present application discloses a chip layout method, device, and electronic device. The method includes: receiving a user's setting operation for preset parameters in a chip layout interface; in response to the setting operation, determining the layout of each peripheral unit in the target block based on the target block identifier and each peripheral unit identifier; projecting the center of each peripheral unit in the X direction and the Y direction to obtain a projection result; generating the peripheral unit center array based on the projection result; determining the target peripheral unit to be inserted into the peripheral unit center array based on the row information and column information of the central unit; inserting the central unit indicated by the central unit identifier into the center of each target peripheral unit, and displaying the chip layout result. The chip layout solution disclosed by the present invention can quickly and conveniently complete chip layout, saving manpower and time costs.

Description

Technical Field

[0001] The present application belongs to the field of EDA (Electronic Design Automation) technology, and in particular relates to a chip layout method and device, and an electronic device. Background Art

[0002] Since the advent of integrated circuits, IC layouts have primarily relied on manual design. Many layout designers still manually complete IC layout placement and routing, manually drawing the shapes of guard rings and each trap. With the advancement of process nodes and the increase in design complexity, the scale of integrated circuit layouts has become increasingly large. If layouts are still designed purely by hand, it will consume a lot of time and effort, reducing design efficiency. Furthermore, because the optimal layout cannot be foreseen, layout designers need to perform multiple layout iterations, undergoing multiple adjustments and redesigns to meet chip specifications. Therefore, manually completing analog layout design is a time-consuming, labor-intensive, and repetitive task.

[0003] In some analog circuit layout design scenarios, there are multiple blocks, and the blocks contain peripheral cells or units arranged in an array. The layout designer needs to place the center cell at the center of the peripheral cells in the specified block. The number of peripheral cells in different blocks is different, and the arrangement method is also different. In addition, the spacing between adjacent rows or columns of peripheral cells in the same block may be different. It is necessary to calculate the center of each peripheral cell in a short time and place the center cell at its center. If the design is completed manually by the layout designer alone, it will consume a lot of manpower and time costs. Therefore, in order to further improve the efficiency of layout design and allow engineers to focus more on creative design, the field of analog layout design urgently needs to improve the existing manual layout design method and gradually realize simulation automation. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a chip layout method and device, and electronic equipment, which can solve the problem of consuming a lot of manpower and time costs in the existing technology of relying entirely on layout designers to manually design the chip layout.

[0005] To solve the above technical problems, this application provides the following technical solutions:

[0006] An embodiment of the present application provides a chip layout method, including:

[0007] Receive a user's setting operation for preset parameters in the chip layout interface; wherein the preset parameters include: a target block identifier, identifiers of each peripheral unit, a central unit identifier, and row and column information of the central unit;

[0008] In response to the setting operation, determining the layout of each peripheral unit in the target block according to the target block identifier and each peripheral unit identifier;

[0009] Projecting the center of each peripheral unit in the X direction and the Y direction respectively to obtain projection results;

[0010] generating the peripheral unit center array based on the projection result;

[0011] Determining a target peripheral cell for inserting a central cell in the peripheral cell center array according to the row information and column information of the central cell;

[0012] A central cell indicated by the central cell identifier is inserted into the center of each target peripheral cell, and a chip layout result is displayed.

[0013] Optionally, the step of generating the peripheral unit center array based on the projection result includes:

[0014] Sorting the projection coordinates in the X direction in the projection results in ascending order and removing duplicates, and establishing a first mapping relationship between the peripheral unit center column and the x coordinate;

[0015] Sorting the projection coordinates in the Y direction in the projection results in ascending order and removing duplicates, and establishing a second mapping relationship between the peripheral unit center row and the Y coordinate;

[0016] The first mapping relationship and the second mapping relationship are converted into corresponding peripheral unit center arrays, wherein each peripheral unit center in the peripheral unit center array corresponds to a Y coordinate and an X coordinate.

[0017] Optionally, the step of determining a target peripheral cell to be inserted into the central cell in the peripheral cell center array based on the row information and column information of the central cell includes:

[0018] Searching for each first peripheral unit covered by the row information and the column information in the peripheral unit center array;

[0019] Each of the first peripheral cells is determined as a target peripheral cell to be inserted into the central cell.

[0020] Optionally, the step of receiving a user's setting operation on preset parameters in the chip layout interface includes:

[0021] In response to a user's operation of starting the preset software, a chip layout interface is displayed, wherein the chip layout interface includes a target block identification setting control, a peripheral unit identification setting control, a central unit identification setting control, a central unit row information setting control, and a central unit column information setting control;

[0022] Receive the user's operation of setting corresponding parameters in each of the controls;

[0023] Receive the user's touch operation to start the layout control.

[0024] Optionally, the preset parameters further include: central unit rotation direction information, and the steps of inserting the central unit indicated by the central unit identifier into the center of each target peripheral unit and displaying the chip layout result include:

[0025] Insert the central unit indicated by the central unit identifier into the center of each target peripheral unit;

[0026] determining a rotation direction indicated by the rotation direction information of the central unit;

[0027] The inserted central units are rotated according to the rotation direction to generate and display a chip layout result.

[0028] The present application also provides a chip layout device, including:

[0029] A receiving module, configured to receive a user's setting operation for preset parameters in the chip layout interface; wherein the preset parameters include: a target block identifier, identifiers of each peripheral unit, a central unit identifier, and row and column information for setting the central unit;

[0030] A first determining module, configured to determine, in response to the setting operation, a layout of each peripheral unit in the target block according to the target block identifier and each peripheral unit identifier;

[0031] A projection module, configured to project the center of each peripheral unit in the X direction and the Y direction to obtain a projection result;

[0032] A generating module, configured to generate the peripheral unit center array based on the projection result;

[0033] A second determining module is configured to determine a target peripheral cell to be inserted into the central cell in the peripheral cell center array according to the row information and column information of the central cell;

[0034] The inserting module is used to insert the central cell indicated by the central cell identifier into the center of each target peripheral cell and display the chip layout result.

[0035] Optionally, the generating module includes:

[0036] A first submodule is configured to sort the projection coordinates in the X direction in the projection result in ascending order and remove duplicates, and establish a first mapping relationship between the peripheral unit center column and the x coordinate;

[0037] The second submodule is used to sort the projection coordinates in the Y direction in the projection results in ascending order and remove duplicates, and establish a second mapping relationship between the peripheral unit center row and the Y coordinate;

[0038] The third submodule is configured to convert the first mapping relationship and the second mapping relationship into a corresponding peripheral unit center array, wherein each peripheral unit center in the peripheral unit center array corresponds to a Y coordinate and an X coordinate.

[0039] Optionally, the second determining module is specifically configured to:

[0040] Searching for each first peripheral cell covered by the row information and the column information in the peripheral cell center array; and determining each first peripheral cell as a target peripheral cell to be inserted into the center cell.

[0041] Optionally, the receiving module includes:

[0042] a fourth submodule, configured to display a chip layout interface in response to a user's operation of starting the preset software, wherein the chip layout interface includes a target block identification setting control, a peripheral unit identification setting control, a central unit identification setting control, a central unit row information setting control, and a central unit column information setting control;

[0043] The fifth submodule is used to receive the user's operation of setting corresponding parameters in each of the controls;

[0044] The sixth submodule is configured to receive a user's touch operation to start the layout control.

[0045] Optionally, the preset parameters further include: central unit rotation direction information, and the insertion module includes:

[0046] A seventh submodule, configured to insert a central unit indicated by the central unit identifier into the center of each of the target peripheral units;

[0047] An eighth submodule, configured to determine a rotation direction indicated by the rotation direction information of the central unit;

[0048] The ninth submodule is configured to rotate the inserted central units according to the rotation direction, generate a chip layout result, and display the result.

[0049] An embodiment of the present invention provides an electronic device, which includes a processor, a memory, and a program or instruction stored in the memory and executable on the processor. When the program or instruction is executed by the processor, the steps of any one of the above-mentioned chip layout methods are implemented.

[0050] An embodiment of the present invention provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of any one of the above chip layout methods are implemented.

[0051] The chip layout solution provided in the embodiment of the present application receives the user's setting operation of preset parameters in the chip layout interface; in response to the setting operation, determines the layout of each peripheral unit in the target block according to the target block identifier and each peripheral unit identifier; projects the center of each peripheral unit in the X direction and the Y direction respectively to obtain the projection result; generates a peripheral unit center array based on the projection result; determines the target peripheral unit to insert the central unit in the peripheral unit center array according to the row information and column information of the central unit; inserts the central unit indicated by the central unit identifier into the center of each target peripheral unit, and displays the chip layout result. The chip layout solution provided in the embodiment of the present application allows the user to set simple parameters in the chip layout interface to trigger the software to generate the chip layout, which can quickly and conveniently complete the chip layout, saving manpower and time costs. Not only that, the user can also flexibly adjust the chip layout by adjusting the parameters set in the chip layout interface, and can more quickly design a chip that meets the needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 is a flowchart showing the steps of a chip layout method according to an embodiment of the present application;

[0053] Figure 2 is a schematic diagram of a chip layout interface according to an embodiment of the present application;

[0054] Figure 3 1 is a schematic diagram showing the layout of peripheral units in a target block according to an embodiment of the present application;

[0055] Figure 4 is a schematic diagram showing a chip layout result of an embodiment of the present application;

[0056] Figure 5 is a structural block diagram showing a chip layout device according to an embodiment of the present application;

[0057] Figure 6 It is a structural block diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0058] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0059] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects; for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.

[0060] Due to the limitations of the automation level of analog board layout, the current method of placing the central unit in the center of the peripheral units can only be achieved by manual operation. When the number of peripheral units that need to be placed in the central unit is huge, the manual layout method is inefficient and requires a lot of time and energy. Therefore, it is necessary to use EDA (Electronic Design Automation) tools to quickly complete the layout of the chip, save time, and improve design efficiency. Based on this demand, the application proposes a convenient and efficient chip layout solution.

[0061] The chip layout solution provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0062] As attached Figure 1 As shown, the chip layout method of the embodiment of the present application includes the following steps:

[0063] Step 101: receiving a user's setting operation on preset parameters in a chip layout interface.

[0064] The preset parameters include the target block identifier, peripheral unit identifiers, central unit identifier, and row and column information for the central unit. A block level refers to the module level, typically referring to a circuit board in a PCB design, or a unit composed of multiple functional modules in a chip. A block can be considered a circuit layout area or functional module.

[0065] Alternatively, a method of receiving a user's setting operation of a preset parameter in the chip layout interface may be as follows:

[0066] In response to the user's operation of starting the preset software, a chip layout interface is displayed, wherein the chip layout interface includes a target block identification setting control, a peripheral unit identification setting control, a central unit identification setting control, a central unit row information setting control, and a central unit column information setting control;

[0067] Receive the user's operation of setting corresponding parameters in each control;

[0068] Receive a user touch operation to start the layout control, wherein the touch operation may include but is not limited to: single click, double click, or long press.

[0069] This method of setting chip layout related parameters in the chip layout interface is more flexible and convenient.

[0070] An exemplary chip layout interface diagram is shown as follows: Figure 2 As shown, the user opens ToolBox->Mos PatternPR, selects Block Layer in the Place interface, i.e., the chip layout interface, sets the target Block for the layout in the Block column (i.e., the target Block identification setting control), and selects the peripheral Cell in the I / O Pin Cell (i.e., the peripheral cell identification setting control). In the table of the layout interface, set the center Cell in the Mos Cell column (i.e., the center cell identification setting control), and set the layout position of the center Cell in the Rows and Columns columns, including the center cell row and column information. Click the Apply button in the lower right corner of the window (i.e., start the layout control) to trigger the software to perform chip layout according to the parameters set by the user.

[0071] Step 102: In response to the setting operation, determine the layout of each peripheral unit in the target block according to the target block identifier and each peripheral unit identifier.

[0072] An exemplary schematic diagram of the layout of peripheral units in a target block is shown as follows: Figure 3 As shown, the peripheral units in the target block are distributed along the X axis and the Y axis. It should be noted that the above is only an example, and the specific peripheral units are not limited to being arranged with equal intervals and equal row spacing.

[0073] Step 103: Project the center of each peripheral unit in the X direction and the Y direction respectively to obtain projection results.

[0074] In the embodiment of the present application, in order to achieve the layout purpose of quickly placing the center cell at the center of the peripheral cells, the center coordinates of the peripheral cells are projected onto the X and Y axes respectively, and duplicates are removed. For the same coordinates, only one point is retained. The coordinate points projected onto the X and Y directions are combined into corresponding layout positions, that is, (row, column) corresponds to (x coordinate, y coordinate). This improves the efficiency of layout design while also improving ease of use. The specific projection conversion process is shown in steps 103 and 104.

[0075] Step 104: Generate a peripheral unit center array based on the projection results.

[0076] An alternative way to generate an array of peripheral cell centers based on the projection results is as follows:

[0077] First, the projection coordinates in the X direction of the projection results are sorted in ascending order and duplicates are removed to establish a first mapping relationship between the peripheral unit center column and the X coordinate; the projection coordinates in the Y direction of the projection results are sorted in ascending order and duplicates are removed to establish a second mapping relationship between the peripheral unit center row and the Y coordinate;

[0078] Secondly, the first mapping relationship and the second mapping relationship are converted into corresponding peripheral unit center arrays.

[0079] Each peripheral unit center in the peripheral unit center array corresponds to a Y coordinate and an X coordinate.

[0080] Refer to the attached Figure 3 In the actual implementation, within the same Block area, the center of each peripheral Cell is projected in the X and Y directions respectively. Based on the results of ascending sorting in the X and Y directions, duplicates are removed. For the same coordinates, only one point is retained, and a mapping relationship between the column index and the x coordinate is established. For the X direction, <x coordinate of center point 1, column 1>, <x coordinate of center point 2, column 2>, etc. For the Y direction, <y coordinate of center point 1, row 1>, <y coordinate of center point 2, row 2>, etc. Based on the calculated mapping relationship, (row, column) is converted to the corresponding layout position (x coordinate, y coordinate), such as (1, 2) corresponds to (x1, y2).

[0081] Step 105: Determine the target peripheral cell to be inserted into the central cell in the peripheral cell center array according to the row information and column information of the central cell.

[0082] An optional method of determining the target peripheral cell to be inserted into the central cell in the peripheral cell center array based on the row information and column information of the central cell may be:

[0083] Searching for each first peripheral cell covered by row information and column information in the peripheral cell center array; and determining each first peripheral cell as a target peripheral cell to be inserted into the center cell.

[0084] For example: Figure 2 In the chip layout interface, the row information input by the user is 1-2 and the column information is 1-5, then the peripheral cell corresponding to the peripheral cell center of the 1-2 row and 1-5 column in the peripheral cell center array is determined as the first peripheral cell.

[0085] Step 106: inserting a central cell indicated by a central cell identifier into the center of each target peripheral cell, and displaying the chip layout result.

[0086] The chip layout result after inserting the center unit is shown in the attached figure. Figure 4 As shown, it can be seen that a central unit is inserted in the center of the peripheral units in rows 1-2 and columns 1-5.

[0087] In an optional embodiment, in addition to inserting central cells into peripheral cells through the software, the rotation direction of the central cells can also be set. Specifically, the user can enter the central cell rotation direction information when entering the preset parameters in the chip layout interface. The central cell indicated by the central cell identifier is inserted at the center of each target peripheral cell, and the chip layout results are displayed. The specific method is as follows:

[0088] Inserting a central cell indicated by the central cell identifier at the center of each target peripheral cell; determining a rotation direction indicated by the central cell rotation direction information; rotating each inserted central cell according to the rotation direction, generating and displaying a chip layout result.

[0089] In this optional implementation, the user can flexibly set the rotation direction of the central unit, making the chip design more flexible.

[0090] The chip layout method provided in the embodiment of the present application receives the user's setting operation of preset parameters in the chip layout interface; in response to the setting operation, determines the layout of each peripheral unit in the target block according to the target block identifier and each peripheral unit identifier; projects the center of each peripheral unit in the X direction and the Y direction respectively to obtain the projection result; generates a peripheral unit center array based on the projection result; determines the target peripheral unit to be inserted into the peripheral unit center array according to the row information and column information of the central unit; inserts the central unit indicated by the central unit identifier into the center of each target peripheral unit, and displays the chip layout result. The chip layout method provided in the embodiment of the present application allows the user to set simple parameters in the chip layout interface to trigger the software to generate the chip layout, which can quickly and conveniently complete the chip layout, saving manpower and time costs. Not only that, the user can also flexibly adjust the chip layout by adjusting the parameters set in the chip layout interface, and can more quickly design a chip that meets the needs.

[0091] Figure 5 A structural block diagram of a chip layout device for implementing an embodiment of the present application.

[0092] The chip layout device provided in the embodiment of the present application includes the following functional modules:

[0093] The receiving module 501 is configured to receive a user's setting operation for preset parameters in the chip layout interface; wherein the preset parameters include: a target block identifier, identifiers of each peripheral unit, a central unit identifier, and row and column information of the central unit;

[0094] A first determining module 502 is configured to determine, in response to the setting operation, the layout of each peripheral unit in the target block according to the target block identifier and each peripheral unit identifier;

[0095] The projection module 503 is used to project the center of each peripheral unit in the X direction and the Y direction to obtain a projection result;

[0096] A generating module 504 is configured to generate the peripheral unit center array based on the projection result;

[0097] A second determining module 505 is configured to determine a target peripheral cell to be inserted into the central cell in the peripheral cell center array according to the row information and column information of the central cell;

[0098] The inserting module 506 is configured to insert the central cell indicated by the central cell identifier into the center of each of the target peripheral cells and display the chip layout result.

[0099] Optionally, the generating module includes:

[0100] A first submodule is configured to sort the projection coordinates in the X direction in the projection result in ascending order and remove duplicates, and establish a first mapping relationship between the peripheral unit center column and the x coordinate;

[0101] The second submodule is used to sort the projection coordinates in the Y direction in the projection results in ascending order and remove duplicates, and establish a second mapping relationship between the peripheral unit center row and the Y coordinate;

[0102] The third submodule is configured to convert the first mapping relationship and the second mapping relationship into a corresponding peripheral unit center array, wherein each peripheral unit center in the peripheral unit center array corresponds to a Y coordinate and an X coordinate.

[0103] Optionally, the second determining module is specifically configured to:

[0104] Searching for each first peripheral cell covered by the row information and the column information in the peripheral cell center array; and determining each first peripheral cell as a target peripheral cell to be inserted into the center cell.

[0105] Optionally, the receiving module includes:

[0106] a fourth submodule, configured to display a chip layout interface in response to a user's operation of starting the preset software, wherein the chip layout interface includes a target block identification setting control, a peripheral unit identification setting control, a central unit identification setting control, a central unit row information setting control, and a central unit column information setting control;

[0107] The fifth submodule is used to receive the user's operation of setting corresponding parameters in each of the controls;

[0108] The sixth submodule is configured to receive a user's touch operation to start the layout control.

[0109] Optionally, the preset parameters further include: central unit rotation direction information, and the insertion module includes:

[0110] A seventh submodule, configured to insert a central unit indicated by the central unit identifier into the center of each of the target peripheral units;

[0111] An eighth submodule, configured to determine a rotation direction indicated by the rotation direction information of the central unit;

[0112] The ninth submodule is configured to rotate the inserted central units according to the rotation direction, generate a chip layout result, and display the result.

[0113] The chip layout device provided in the application embodiment allows users to trigger the software to generate a chip layout by simply setting simple parameters in the chip layout interface. This allows for quick and convenient chip layout, saving manpower and time. Furthermore, users can flexibly adjust the chip layout by adjusting the parameters set in the chip layout interface, enabling faster design of chips that meet their needs.

[0114] In the embodiment of the present application Figure 5 The chip layout device shown can be provided in a mobile device or a server. The mobile device or server provided with the device can be a device having an operating system. The operating system can be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiments of the present application.

[0115] The embodiments of the present application provide Figure 5 The chip layout shown enables Figure 1 To avoid repetition, the various processes implemented in the method embodiment are not described here.

[0116] Optionally, refer to Figure 6It is shown that an embodiment of the present application further provides an electronic device 600, including a processor 601, a memory 602, and a program or instruction stored in the memory and executable on the processor. When the program or instruction is executed by the processor, the various processes performed by the above-mentioned chip layout device are implemented and the same technical effects can be achieved. To avoid repetition, they are not described here.

[0117] It should be noted that the electronic device in the embodiment of the present application includes the server described above.

[0118] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer-readable storage medium, such as a computer read-only memory (ROM), random access memory (RAM), a magnetic disk, or an optical disk.

[0119] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0120] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A chip layout method, characterized in that: include: Receive a user's setting operation for preset parameters in the chip layout interface; wherein the preset parameters include: a target block identifier, identifiers of each peripheral unit, a central unit identifier, and row and column information of the central unit; In response to the setting operation, determining the layout of each peripheral unit in the target block according to the target block identifier and each peripheral unit identifier; Projecting the center of each peripheral unit in the X direction and the Y direction respectively to obtain projection results; Based on the projection results, the peripheral unit center array is generated, wherein the step includes: sorting the projection coordinates in the X direction of the projection results in ascending order and removing duplicates, and establishing a first mapping relationship between the peripheral unit center column and the x coordinate; sorting the projection coordinates in the Y direction of the projection results in ascending order and removing duplicates, and establishing a second mapping relationship between the peripheral unit center row and the Y coordinate; converting the first mapping relationship and the second mapping relationship into a corresponding peripheral unit center array, wherein each peripheral unit center in the peripheral unit center array corresponds to a Y coordinate and an X coordinate; Determining a target peripheral cell for inserting a central cell in the peripheral cell center array according to the row information and column information of the central cell; A central cell indicated by the central cell identifier is inserted into the center of each target peripheral cell, and a chip layout result is displayed.

2. The method according to claim 1, characterized in that The step of determining a target peripheral cell to be inserted into the central cell in the peripheral cell center array based on the row information and column information of the central cell comprises: Searching for each first peripheral unit covered by the row information and the column information in the peripheral unit center array; Each of the first peripheral cells is determined as a target peripheral cell to be inserted into the central cell.

3. The method according to claim 1, characterized in that The step of receiving a user's setting operation on preset parameters in the chip layout interface includes: In response to a user's operation of starting the preset software, a chip layout interface is displayed, wherein the chip layout interface includes a target block identification setting control, a peripheral unit identification setting control, a central unit identification setting control, a central unit row information setting control, and a central unit column information setting control; Receive the user's operation of setting corresponding parameters in each of the controls; Receive the user's touch operation to start the layout control.

4. The method according to claim 1, wherein The preset parameters also include: central unit rotation direction information, and the steps of inserting the central unit indicated by the central unit identifier into the center of each target peripheral unit and displaying the chip layout result include: Insert the central unit indicated by the central unit identifier into the center of each target peripheral unit; determining a rotation direction indicated by the rotation direction information of the central unit; The inserted central units are rotated according to the rotation direction to generate and display a chip layout result.

5. A chip layout device, characterized in that: include: A receiving module, configured to receive a user's setting operation for preset parameters in the chip layout interface; wherein the preset parameters include: a target block identifier, identifiers of each peripheral unit, a central unit identifier, and row and column information for setting the central unit; A first determining module is configured to determine, in response to the setting operation, a layout of each peripheral unit in the target block according to the target block identifier and each peripheral unit identifier; A projection module, configured to project the center of each peripheral unit in the X direction and the Y direction respectively to obtain a projection result; a generation module for generating the peripheral cell center array based on the projection result, wherein the generation module includes: a first submodule for sorting the projection coordinates in the X direction of the projection result in ascending order and removing duplicates, and establishing a first mapping relationship between the peripheral cell center column and the x-coordinate; a second submodule for sorting the projection coordinates in the Y direction of the projection result in ascending order and removing duplicates, and establishing a second mapping relationship between the peripheral cell center row and the Y coordinate; and a third submodule for converting the first mapping relationship and the second mapping relationship into a corresponding peripheral cell center array, wherein each peripheral cell center in the peripheral cell center array corresponds to one Y coordinate and one X coordinate; a second determining module, configured to determine a target peripheral cell to be inserted into the central cell in the peripheral cell center array according to the row information and column information of the central cell; The inserting module is used to insert the central cell indicated by the central cell identifier into the center of each target peripheral cell and display the chip layout result.

6. The device according to claim 5, characterized in that The second determining module is specifically configured to: Searching for each first peripheral cell covered by the row information and the column information in the peripheral cell center array; and determining each first peripheral cell as a target peripheral cell to be inserted into the center cell.

7. The device according to claim 5, characterized in that The receiving module includes: a fourth submodule, configured to display a chip layout interface in response to a user's operation of starting the preset software, wherein the chip layout interface includes a target block identification setting control, a peripheral unit identification setting control, a central unit identification setting control, a central unit row information setting control, and a central unit column information setting control; The fifth submodule is used to receive the user's operation of setting corresponding parameters in each of the controls; The sixth submodule is configured to receive a user's touch operation to start the layout control.

8. An electronic device, characterized in that: The electronic device includes a processor, a memory, and a program or instruction stored in the memory and executable on the processor. The program or instruction is used by the processor to execute the steps of the chip layout method according to any one of claims 1 to 4.

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