Method and apparatus for acquiring a line hammer refresh address

Abstract

This application provides a method and apparatus for obtaining the hammer refresh address. The method includes obtaining the current sampling address after the arrival of the previous hammer refresh signal, determining whether a high-order address has been locked within the current hammer refresh cycle, and if so, determining whether the high-order address of the current sampling address is the same as the high-order address locked within the current hammer refresh cycle. If they are the same, updating the access frequency of the locked high-order address and updating the access frequency of the low-order address using the low-order address of the current sampling address. When the next hammer refresh signal arrives, the low-order address with the highest access frequency is used as the low-order address of the hammer refresh address, and the locked high-order address is used as the high-order address of the hammer refresh address. This setup eliminates the need to count all sampling addresses, simplifies the method, reduces the required circuitry, and accurately obtains the hammer refresh address.

Description

Technical Field

[0001] This application relates to, but is not limited to, a method and apparatus for obtaining the row hammer refresh address. Background Technology

[0002] In semiconductor memory, when the word line corresponding to a row address in a memory cell is frequently turned on, it may cause the leakage rate of the capacitors at adjacent addresses (generally called "row hammer addresses") to exceed the natural leakage rate. This can lead to data loss due to excessive charge loss in the capacitors at adjacent addresses before the refresh signal arrives. This phenomenon is generally called the "row hammer effect." To suppress the row hammer effect, timely refresh commands are needed for the row hammer addresses to replenish the charge and prevent data errors.

[0003] There are generally two ways to obtain the row hammer address: one is to randomly select a row address as the row hammer address, and the other is to count each complete row address. The method of randomly selecting the row address is not very accurate, and the method of counting each complete row address is more complicated, requires a complex circuit structure, and consumes more chip area. Summary of the Invention

[0004] One embodiment of this application provides a method for obtaining the row hammer refresh address, including:

[0005] After the previous hammer refresh signal arrives, obtain the current sampling address and determine whether the high-order address has been locked within the current hammer refresh cycle;

[0006] If it is already locked, then determine whether the high-order address of the current sampling address is the same as the high-order address that has been locked in the current row hammer refresh cycle;

[0007] If they are the same, update the access frequency of the locked high-order address and update the access frequency of the low-order address using the low-order address of the current sampled address.

[0008] When the next hammer refresh signal arrives, the low-order address with the highest access frequency is used as the low-order address of the hammer refresh address, and the locked high-order address is used as the high-order address of the hammer refresh address.

[0009] In some embodiments, the method further includes:

[0010] If the high-order address of the current sampling address is different from the locked high-order address, update the access frequency of the high-order address using the high-order address of the current sampling address;

[0011] When it is determined that the next hammer refresh signal has not arrived, the next sampling address is obtained, and it is determined whether the high-order address of the next sampling address is the same as the high-order address that has been locked in the current hammer refresh cycle.

[0012] In some embodiments, the method further includes:

[0013] If the high-order address is not locked within the current row hammer refresh cycle, the access frequency of the high-order address is updated using the high-order address of the current sampling address;

[0014] Determine if there is a high-order address that meets the high-order frequency condition based on the access frequency of the high-order address. If so, lock the high-order address that meets the high-order frequency condition and initialize the access frequency of the low-order address.

[0015] In some embodiments, the method further includes:

[0016] If no high-order address in the high-order address of the recorded access frequency meets the high-order frequency condition, obtain the next sampling address when it is determined that the next row hammer refresh signal has not arrived, update the access frequency of the high-order address using the high-order address of the next sampling address, and determine whether there is a high-order address that meets the high-order frequency condition based on the access frequency of the high-order address.

[0017] In some embodiments, the high-frequency condition includes:

[0018] The access frequency of the high-order address is greater than or equal to the first frequency threshold.

[0019] In some embodiments, the semiconductor memory includes a low-order register group and a counter corresponding to each low-order register;

[0020] Update the access frequency of the low-order address using the low-order address of the current sampling address, specifically including:

[0021] Determine whether the low-order address of the current sampling address has been stored in the low-order register group;

[0022] If there is a low-order address of the current sampling address, update the access frequency of the low-order address of the current sampling address;

[0023] If there is no low-order address to store the current sampling address, check if there is a free low-order register in the low-order register group.

[0024] If there is a free low-order register, the low-order address of the current sampling address is stored in the free low-order register, and the access frequency of the low-order address of the current sampling address is updated.

[0025] In some embodiments, the semiconductor memory includes a high-order register group and a counter corresponding to each high-order register;

[0026] Update the access frequency of the high-order address using the high-order address of the current sampling address, specifically including:

[0027] Determine whether the high-order register group has already stored the high-order address of the current sampling address;

[0028] If the high-order address of the current sampling address is stored, update the access frequency of the high-order address of the current sampling address;

[0029] If the high-order address of the current sampling address is not stored, determine whether there is a free high-order register in the high-order register group;

[0030] If so, the high-order address of the current sampling address is stored in the free high-order register, and the access frequency of the high-order address of the current sampling address is updated.

[0031] In some embodiments, updating the access frequency of the high-order address using the high-order address of the current sampling address further includes:

[0032] If there are no free high-order registers in the high-order register group, determine whether the clearing condition is met. If the clearing condition is met, determine whether the high-order address with the lowest access frequency is a locked high-order address. If it is not a locked high-order address, delete the address data in the high-order register containing the high-order address with the lowest access frequency, and clear the corresponding access frequency.

[0033] Store the high-order address of the current sampling address in the high-order register of the deleted address data, and update the access frequency of the high-order address of the current sampling address.

[0034] In some embodiments, the method further includes:

[0035] When performing the row hammer refresh operation in the current row hammer refresh cycle, delete the address data in the high-order register where the high-order address with an access frequency less than the second frequency threshold is located, and clear the corresponding access frequency; wherein, the second frequency threshold is positively correlated with the number of row hammer refresh operations that have been performed.

[0036] In some embodiments, the method further includes:

[0037] After completing the row hammer refresh operation of the current row hammer refresh cycle, delete the low-order address of the row hammer refresh address stored in the low-order register group, clear the access frequency of the low-order address of the row hammer refresh address, and deduct the access frequency of the low-order address of the row hammer refresh address from the access frequency of the high-order address of the row hammer refresh address.

[0038] In some embodiments, the method further includes:

[0039] After completing the row hammer refresh operation of the current row hammer refresh cycle, delete the address data in the low-order register where the low-order address with an access frequency less than the third frequency threshold is located; clear the access frequency of the low-order address with an access frequency less than the third frequency threshold; and deduct the total access frequency of the low-order address with an access frequency less than the third frequency threshold from the access frequency of the locked high-order address in the current row hammer refresh cycle.

[0040] In some embodiments, the method further includes:

[0041] After the next hammer refresh signal arrives, if the high-order address with the highest access frequency is the high-order address locked in the previous hammer refresh cycle, and the access frequency of the high-order address locked in the previous hammer refresh cycle meets the high-order frequency condition, the high-order address locked in the previous hammer refresh cycle is used as the high-order address locked in the current hammer refresh cycle to obtain the next sampling address.

[0042] After the next row hammer refresh signal arrives, if the high-order address with the highest access frequency is not the high-order address locked in the previous row hammer refresh cycle, and the high-order address with the highest access frequency meets the high-order frequency condition, the high-order address with the highest access frequency will be used as the high-order address locked in the current row hammer refresh cycle to obtain the next sampling address.

[0043] In some embodiments, the method further includes:

[0044] After the next row hammer refresh signal arrives, if the high-order address with the highest access frequency is not the high-order address locked in the previous row hammer refresh cycle, and the high-order address with the highest access frequency cannot meet the high-order frequency condition, the next sampling address is obtained, and the access frequency of the high-order address is updated using the high-order address of the next sampling address; and it is determined whether there is a high-order address that meets the high-order frequency condition based on the access frequency of the high-order address. If it does, the high-order address that meets the high-order frequency condition is locked, and the access frequency of the low-order address is initialized.

[0045] One embodiment of this application provides a control device for implementing the methods involved in the above embodiments.

[0046] One embodiment of this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the methods involved in the above embodiments.

[0047] One embodiment of this application provides a computer program product, including a computer program that, when executed by a processor, implements the methods involved in the above embodiments.

[0048] This application provides a method and apparatus for obtaining the refresh address of a row hammer. Within each row hammer refresh cycle, the sampling address is divided into high-order addresses and low-order addresses. When a high-order address is determined to be locked, it is determined whether the high-order address of the current sampling address is the same as the locked high-order address. If they are the same, the access frequency of the low-order address is updated using the low-order address of the current sampling address. By locking the high-order addresses with higher access frequencies in the early stages, and then recording the access frequency of the low-order addresses based on the locked high-order addresses, it is possible to avoid recording the access frequency of all sampling addresses, resulting in a simple circuit structure and low area consumption. Furthermore, by recording the access frequencies of both high-order and low-order addresses, the row hammer refresh address can be accurately captured, reducing the risk of row hammer attacks. Attached Figure Description

[0049] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0050] Figure 1 A schematic diagram of a semiconductor memory provided in an embodiment of this application;

[0051] Figure 2 This is a schematic diagram illustrating the connection between a high-order register and a low-order register according to an embodiment of this application.

[0052] Figure 3 This is a flowchart illustrating a method for obtaining the row hammer refresh address according to an embodiment of this application;

[0053] Figure 4 A flowchart illustrating the process of updating the access frequency of the low-order address according to an embodiment of this application;

[0054] Figure 5 A flowchart illustrating the process of updating the access frequency of high-order addresses according to an embodiment of this application;

[0055] Figure 6 A schematic diagram of the process for locking the high-order address according to an embodiment of this application;

[0056] Figure 7 This is a schematic diagram of an apparatus for obtaining the row hammer refresh address according to an embodiment of this application.

[0057] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0058] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0059] like Figure 1 As shown, one embodiment of this application provides a semiconductor memory, which includes a sampling circuit 10, an address latch 20, a high-order register 30, a low-order register 50, and a control device (not shown).

[0060] The input terminal of the address latch 20 continuously receives the row address. The sampling circuit 20 is used to control the address latch 20 to latch the row address received at the input terminal, thereby sampling the continuously input row address and outputting the sampled address through the output terminal of the address latch 20.

[0061] The high-order register group includes m high-order registers 30, each of which stores the high-order address of the sampling address. Each high-order register 30 is configured with a counter 40 to record the access frequency of the high-order address stored in the high-order register 30.

[0062] The low-order register group includes n low-order registers 50, each of which stores the low-order address of the sampling address. Each low-order register 50 is configured with a counter 60 to record the access frequency of the low-order address stored in the low-order register 50.

[0063] For example: The row address is 16 bits, labeled RA<15:0>. The row address is divided into high-order address RA<15:8> and low-order address RA<7:0>. High-order register 30 is used to store address RA<15:8>, and the counter 40 corresponding to high-order register 30 has a count of 9 bits, labeled Cnt<8:0>. Low-order register 50 is used to store address RA<7:0>, and the counter 60 corresponding to low-order register 50 has a count of 4 bits, labeled Cnt<3:0>.

[0064] The control device is used to implement the method for obtaining the row hammer refresh address as described in the following method embodiments.

[0065] like Figure 1As shown, after the previous row hammer refresh signal arrives, address latch 20 outputs a sampling address each time, and stores the high-order bits of the sampling address in the high-order register 30 sequentially. The storage principle is as follows: the high-order bits of the current sampling address are compared with the address data in the high-order register 30 of all already stored addresses. If they are the same, the counter of the corresponding high-order register 30 is incremented by 1. If they are all different, the address is stored in the high-order register 30 where no address has been stored. If the high-order register 30 is full, it is determined whether the address data in the high-order register 30 can be deleted before storing the high-order bits of the current sampling address. The implementation of determining whether the address in the high-order register 30 can be deleted has been described in detail in the following method embodiment and will not be described again here. If the address data in the high-order register 30 cannot be deleted, the current sampling address is discarded. Whether the high-order register 30 is full can be indicated by a flag signal or a counter count of 0.

[0066] like Figure 2 As shown, before the next row hammer refresh signal arrives, if the counter value of a certain high-order register 30 reaches the first frequency threshold first, the high-order address stored in high-order register 30 is used as the locked high-order address. The low-order register group is then connected to this high-order register 30. After connection, the high-order address of the sampling address is compared with the address data in high-order register 30. If the high-order address of the sampling address is the same as the locked high-order address, the low-order address of the current sampling address is stored sequentially in low-order register 50. When storing the low-order address in low-order register 50, the storage principle is as follows: the low-order address of the sampling address is compared with the already used low-order register 50. If they are the same, the corresponding counter is incremented by 1. If they are different, the low-order address is stored in an unused low-order register 50. If all low-order registers 50 are used up, the low-order address of the current sampling address is discarded.

[0067] When the next row hammer refresh signal arrives, the locked high-order address and the low-order address stored in register 50 with the largest counter value will be output as the row hammer refresh address.

[0068] like Figure 3 As shown, one embodiment of this application provides a method for obtaining the row hammer refresh address, the method including the following steps:

[0069] S101. After the previous row hammer refresh signal arrives, obtain the current sampling address.

[0070] Among them, the row hammer refresh signal is used to indicate that after obtaining the row hammer address, the victim row word line corresponding to the row hammer address should be refreshed.

[0071] After the previous row hammer refresh signal arrives, multiple row addresses are received in sequence, and multiple sample addresses are obtained by sampling multiple row addresses.

[0072] For example: After the previous row hammer refresh signal arrives, m row addresses are received, and these m row addresses are sampled to obtain n sample addresses. These n sample addresses are labeled as sample address 1, sample address 2, ..., sample address n in chronological order. The current sample address is sample address i, where 1 ≤ i ≤ n, and i is a positive integer.

[0073] S102. Determine whether the high-order address has been locked within the current row hammer refresh cycle. If yes, proceed to S103; otherwise, proceed to S106.

[0074] The current hammer refresh cycle refers to the time period between the previous hammer refresh signal and the next hammer refresh signal.

[0075] There is generally a locked high-order address in each hammer refresh cycle, but the locking time is different in each hammer refresh cycle. If there is no locked high-order address in the hammer refresh cycle, no hammer address will be generated when the hammer refresh signal arrives.

[0076] The locked high-order address is the high-order address that first meets the high-order frequency condition. Meeting the high-order frequency condition means that the access frequency of the high-order address is greater than or equal to the first frequency threshold. Not meeting the high-order frequency condition means that the access frequency of the high-order address is less than the first frequency threshold.

[0077] Example 1: At a certain sampling time, the addresses and access frequencies of the first to fifth most significant registers are shown in Table 1 below:

[0078] Table 1. Frequency of access to the high-order address in Example 1

[0079] High-order register 1 High-order register 2 High-order register 3 High-order register 4 High-order register 5 address High address 1 High address 2 High address 3 High address 4 High address 5 Frequency 10 20 50 30 40

[0080] If the first frequency threshold is set to 50 times, the high-order address that first meets the high-order frequency condition is high-order address 3. High-order address 3 is locked within the current row hammer refresh cycle, and the locking time is when the counting frequency of high-order address 3 equals 50.

[0081] S103. Determine whether the high-order address of the current sampling address is the same as the high-order address locked in the current row hammer refresh cycle. If yes, proceed to S104; otherwise, proceed to S110.

[0082] Specifically, the current sampling address is divided into a high-order address and a low-order address, with the number of bits in the high-order address being the same as the number of bits in the high-order address stored in the high-order register. The high-order address of the current sampling address is compared with the high-order address that has been locked during the current row hammer refresh cycle to determine whether the two high-order addresses are the same.

[0083] It should be noted that in other embodiments, the number of bits in the high-order address and the number of bits in the low-order address after partitioning can be different; that is, the number of bits in the high-order address can be less than or greater than the number of bits in the low-order address.

[0084] S104. Update the access frequency of the locked high-order address and update the access frequency of the low-order address using the low-order address of the current sampled address.

[0085] Updating the access frequency of the high-order address means incrementing the access frequency of the locked high-order address by 1.

[0086] The access frequency of the low-order address is recorded after the high-order address is locked, so as to determine the row hammer refresh address based on the access frequency of the high-order address and the low-order address after locking.

[0087] Update the access frequency of the low-order address using the low-order address of the current sampling address. Specifically, this includes: determining whether the access frequency of the low-order address of the current sampling address has already been recorded; if so, incrementing the access frequency of the low-order address of the current sampling address by 1. If not, determining whether there is storage space to store the low-order address of the current sampling address; if so, storing the low-order address of the current sampling address and setting the access frequency of the low-order address of the current sampling address to 1.

[0088] Continuing with Example 1, if the high-order address of the current sampling address is the same as the high-order address 3, and the access frequency of the high-order address 3 at the previous sampling time was 104, then the access frequency of the high-order address 3 will be updated to 105.

[0089] After locking the high-order address 3, at the current sampling time, the first to fifth low-order registers recorded the five low-order addresses and access frequencies, as shown in Table 2 below:

[0090] Table 2 shows the access frequency of the low-order address in Example 1.

[0091] Low-order register 1 Low-order register 2 Low-order register 3 Low-order register 4 Low-order register 5 address Low address 1 Low address 2 Low address 3 Low address 4 Low address 5 Frequency 5 8 11 18 12

[0092] If the low-order address of the current sampling address is the same as the low-order address 1, then the access frequency of the low-order address 1 will be updated to 6 times.

[0093] If the least significant byte of the current sampling address is least significant byte 6, there is currently no least significant byte register 50 to store least significant byte 6. If there are 6 least significant byte registers, and 5 of them are already used, then there is 1 free least significant byte register remaining. In this case, the least significant byte register of the current sampling address is stored in the last free least significant byte register. If there are only 5 least significant byte registers, and all 5 are already used, then there is no free least significant byte register, and the least significant byte of the current sampling address is discarded.

[0094] S105. When the next row hammer refresh signal arrives, the low-order address with the highest access frequency is used as the low-order address of the row hammer refresh address, and the locked high-order address is used as the high-order address of the row hammer refresh address.

[0095] Specifically, when the next hammer refresh signal arrives, the hammer address is obtained. The low-order address with the highest access frequency is used as the low-order address of the hammer refresh address, and the locked high-order address is used as the high-order address of the hammer refresh address.

[0096] For example: Continuing with example 1, the high-order address locked in the current hammer refresh cycle is high-order address 3. Among the five low-order addresses, low-order address 4 has the highest access frequency. Therefore, the hammer refresh address is high-order address 3 + low-order address 4.

[0097] In the above technical solution, within each row hammer refresh cycle, the sampling address is divided into high-order addresses and low-order addresses. When it is determined that a high-order address has been locked, it is checked whether the high-order address of the current sampling address is the same as the locked high-order address. If they are the same, the access frequency of the low-order address is updated using the low-order address of the current sampling address. By setting it up in this way, the high-order addresses with higher access frequencies are locked in the early stage, and then the access frequency of the low-order addresses is recorded based on the locked high-order addresses. This setting eliminates the need to record the access frequency of all sampling addresses, resulting in a simple circuit structure and smaller area consumption. Furthermore, by recording the access counts of the high-order and low-order addresses, the row hammer refresh address can be accurately captured, reducing the risk of row hammer attacks.

[0098] S106. If the high-order address is not locked within the current row hammer refresh cycle, update the access frequency of the high-order address using the high-order address of the current sampling address.

[0099] Among them, the high-order address was not locked within the current row hammer refresh cycle, that is, none of the high-order address access frequencies recorded met the high-order frequency condition.

[0100] Example 2: At the current sampling time, the first to fifth high-order registers record the five high-order addresses and access frequencies, as shown in Table 3:

[0101] Table 3. Frequency of access to the high-order address in Example 2

[0102] High-order register 1 High-order register 2 High-order register 3 High-order register 4 High-order register 5 address High address 1 High address 2 High address 3 High address 4 High address 5 Frequency 10 20 48 30 40

[0103] If the first frequency threshold is set to 50 times, then none of the access frequencies of the five recorded high-order addresses meet the high-order frequency condition. Therefore, the access frequency of the high-order addresses is updated using the high-order addresses of the current sampled address.

[0104] The process of updating the access frequency of the high-order address using the high-order address of the current sampling address specifically includes: determining whether the access frequency of the high-order address of the current sampling address has already been recorded; if so, incrementing the access frequency by 1. If not, determining whether there is storage space to store the high-order address of the current sampling address; if so, storing the high-order address and setting its access frequency to 1. If there is no storage space, determining whether the high-order address clearing condition is met; if so, further determining whether the high-order address with the lowest access frequency is a locked high-order address; if not, deleting the high-order address with the lowest access frequency, storing the high-order address of the current sampling address, and setting its access frequency to 1. If the clearing condition is not met, discarding the high-order address.

[0105] S107. Determine whether there is a high-order address that meets the high-order frequency condition based on the access frequency of the updated high-order address. If yes, proceed to S108; otherwise, proceed to S109.

[0106] In S106, the access frequency of the high-order address has been updated. Here, it is necessary to determine whether there are any high-order addresses that meet the high-order frequency condition in the updated access frequency of the high-order address.

[0107] S108. Lock the high-order address that meets the high-order frequency condition, and initialize the access frequency of the low-order address. S111.

[0108] Since only the access frequency of a single high-order address is updated, only one high-order address satisfies the high-order frequency condition. If a high-order frequency condition is met, that high-order address is directly locked. After locking the high-order address, the access frequency of the low-order addresses begins to be recorded. At this point, only the access records of the low-order addresses of the current sampling address are available, so it is only necessary to set the access frequency of the low-order addresses of the current sampling address to 1. After completing the frequency recording for the current sampling address, since the high-order address has already been latched, the process proceeds to S111.

[0109] S109. If the high-order address of the current sampling address cannot meet the high-order frequency condition, obtain the next sampling address when it is determined that the next row hammer refresh signal has not arrived, and return to S106.

[0110] If the high-order address of the current sampling address cannot meet the high-order frequency condition, the next sampling address is obtained when it is determined that the next row hammer refresh signal has not arrived, and S106 and S107 are executed until the high-order address is locked.

[0111] In other words, after obtaining the next sampling address, the access frequency of the high-order address is updated using the high-order address of the next sampling address. Based on the updated access frequency of the high-order address, it is determined whether there is a high-order address that meets the high-order frequency condition. If there is a high-order address that meets the high-order frequency condition, the high-order address is locked. Otherwise, a new next sampling address is obtained, and the access frequency of the high-order address is updated using the high-order address of the next sampling address. Based on the updated access frequency of the high-order address, it is determined whether there is a high-order address that meets the high-order frequency condition, until the high-order address is locked.

[0112] In the above technical solution, when it is determined that no high-order address is locked within the current hammer cycle, the access frequency of the high-order address is updated using the high-order address of the current sampled address, and it is determined whether there is a high-order address that meets the high-order frequency condition. If there is, the high-order address is locked. If not, address sampling continues, and the access frequency of the high-order address is updated using the next sample, until a high-order address that meets the high-order frequency condition is found. By setting it in this way, the high-order address is locked, laying the foundation for recording the access frequency of subsequent low-order addresses.

[0113] S110. If the high-order address of the current sampling address is different from the locked high-order address, update the access frequency of the high-order address using the high-order address of the current sampling address.

[0114] The process of updating the access frequency of the high-order address using the high-order address of the current sampling address specifically includes: determining whether the access frequency of the high-order address of the current sampling address exists in the access frequency list; if it exists, incrementing the access frequency of the high-order address of the current sampling address by 1. If it does not exist, determining whether there is storage space to store the high-order address of the current sampling address; if so, storing the high-order address of the current sampling address and setting its access frequency to 1. If there is no storage space, determining whether the clearing condition is met; if so, further determining whether the high-order address with the lowest access frequency is a locked high-order address; if not, deleting the high-order address with the lowest access frequency, storing the high-order address of the current sampling address, and setting its access frequency to 1. If the clearing condition is not met, discarding the high-order address.

[0115] S111. If it is determined that the next row hammer refresh signal has not arrived, obtain the next sampling address and return to S103.

[0116] If the high-order address of the current sampling address is different from the locked high-order address, the access frequency of the high-order address is updated using the high-order address of the current sampling address, thus completing the access frequency recording of the current sampling address. If it is determined that the next horizontal hammer refresh signal has not arrived, the next sampling address is acquired, and the access frequency of the next sampling address is recorded. If the high-order address of the next sampling address is different from the locked high-order address within the current horizontal hammer refresh cycle, proceed to S110, which means only recording the access frequency of the high-order address of the next sampling address. If they are the same, proceed to S104, and record both the high-order and low-order addresses of the next sampling address.

[0117] In the above technical solution, after locking the high-order address, the high-order address of the current sampling address is compared with the locked high-order address. If they are the same, the access frequency of both the locked high-order address and the low-order address is updated; if they are different, only the access frequency of the high-order address is updated. This setting allows for the recording of the access frequency of the low-order address corresponding to the locked high-order address. When using the locked high-order address as the high-order address of the hammer refresh address, the low-order address of the hammer refresh address is determined based on the access frequency of the low-order address. This enables accurate capture of the hammer refresh address, reduces the risk of hammer attacks, and also helps reduce the number of registers accessed and the amount of register usage.

[0118] In some embodiments, the semiconductor memory includes a group of low-order registers and a counter corresponding to each low-order register. Each low-order register stores a low-order address. The counter corresponding to each low-order register is used to record the access frequency of the low-order address.

[0119] like Figure 4 As shown, updating the access frequency of the low-order address using the low-order address of the current sampling address specifically includes:

[0120] S201. Determine whether the low-order address of the current sampling address has been stored in the low-order register group. If yes, proceed to S202; otherwise, proceed to S203.

[0121] Specifically, for a low-order register that already stores the low-order address, it is determined whether the low-order address stored in the low-order register is the same as the low-order address of the current sampling address. If they are the same, it is determined that the low-order address of the current sampling address has already been stored. If they are different, it is determined that the low-order address of the current sampling address has not been stored.

[0122] S202. If there is a low-order address of the current sampling address, update the access frequency of the low-order address of the current sampling address.

[0123] If it is determined that the low-order address of the current sampling address has already been stored, then the access frequency of the low-order address of the current sampling address is directly incremented by 1.

[0124] S203. If there is no low-order address storing the current sampling address, determine if there is a free low-order register in the low-order register group.

[0125] S204. If there is a free low-order register, store the low-order address of the current sampling address in the free low-order register and update the access frequency of the low-order address of the current sampling address.

[0126] If there is an idle low-order register, the low-order address of the current sampling address is stored in the idle low-order register, and the access frequency of the low-order address of the current sampling address is set to 1.

[0127] S205. If there is no free low-order register, discard the low-order address of the current sampling address.

[0128] It should be noted that in some embodiments, when a clearing condition is set for the high-order address, a clearing condition can also be set for the low-order address. This ensures that when there are no free low-order registers, the system first checks if the clearing condition is met. If the condition is met, the low-order address with the smallest count is cleared, and the low-order address of the current sampling address is stored and counted as 1. It should also be noted that the above clearing condition can be implemented by setting a time interval, setting the number of received sampling addresses, or setting the total access frequency of the stored low-order addresses.

[0129] Specifically, a time window can be set at regular intervals. If a new low-order address exists within this window and no register is available, the low-order address with the smallest count value is deleted; otherwise, it is discarded. Alternatively, a time window can be set at regular intervals, and this window will continue until a new low-order address exists and no register is available, thus requiring the deletion of the low-order address with the smallest count value. After deleting the low-order address with the smallest count value, the window time interval is refreshed and recalculated, i.e., the aforementioned time window is generated again after a preset time interval. Alternatively, a time window can be set every first preset number of sampled addresses received. It can be understood that the first preset number can be a fixed value or an incrementing value that increases with the number of received sampled addresses. Alternatively, the total access frequency of low-order addresses can be counted, and a time window can be set every second preset number of total access frequencies.

[0130] In addition, a threshold for the number of clearing attempts can be set. When the number of clearing attempts equals the threshold, the smallest low-order address will not be cleared even if the clearing conditions are met, thereby improving data stability.

[0131] In other embodiments, the clearing condition may be set only for the high-order address while not for the low-order address, or the clearing condition may be set for the low-order address while not for the high-order address, thereby further improving the stability and accuracy of the low-order or high-order address.

[0132] In some embodiments, the semiconductor memory includes a set of high-order registers and a counter corresponding to each high-order register. Each high-order register stores a high-order address. The counter corresponding to each high-order register is used to record the access frequency of the high-order address.

[0133] like Figure 5 As shown, updating the access frequency of the high-order address using the high-order address of the current sampling address specifically includes:

[0134] S301. Determine whether the high-order register group has already stored the high-order address of the current sampling address. If yes, proceed to S302; otherwise, proceed to S303.

[0135] Specifically, for the high-order register that already stores the high-order address, it is determined whether the high-order address stored in the high-order register is the same as the high-order address of the current sampling address. If they are the same, it is determined that the high-order address of the current sampling address has already been stored. If they are different, it is determined that the high-order address of the current sampling address has not been stored.

[0136] S302. If the high-order address of the current sampling address is stored, update the access frequency of the high-order address of the current sampling address.

[0137] If it is determined that the high-order address of the current sampling address has already been stored, then the access frequency of the high-order address of the current sampling address is directly incremented by 1.

[0138] Example 3: At the current sampling moment, the first to fifth high-order registers record the five high-order addresses and access frequencies, as shown in Table 4. High-order address 3 is locked within the current row hammer refresh cycle.

[0139] Table 4 shows the access frequency of the high-order address in Example 3.

[0140] High-order register 1 High-order register 2 High-order register 3 High-order register 4 High-order register 5 address High address 1 High address 2 High address 3 High address 4 High address 5 Frequency 20 20 56 40 43

[0141] If the high-order address of the current sampling address is the same as high-order address 3, the access frequency of high-order address 3 will be updated to 57 times.

[0142] S303. If there is no high-order address of the current sampling address, determine if there is a free high-order register in the high-order register group. If yes, proceed to S304; otherwise, proceed to S305.

[0143] S304. If there is a free high-order register, store the high-order address of the current sampling address in the free high-order register and update the access frequency of the high-order address of the current sampling address.

[0144] If there is an available high-order register, the high-order address of the current sampling address is stored in the available high-order register, and the access frequency of the high-order address of the current sampling address is set to 1.

[0145] Continuing with Example 3, if the high-order address of the current sampling address is high-order address 6, and there is currently no access frequency for high-order address 6, and there are 6 high-order registers, and 5 high-order registers have already been used, then there is 1 free high-order register left. This last free high-order register will be used to store the high-order address of the current sampling address.

[0146] S305. If there is no free high-order register, determine whether the clearing condition is met. If yes, proceed to S306; otherwise, proceed to S309.

[0147] In some embodiments, satisfying the clearing condition includes a time interval between the current sampling time and the time of the last clearing of the most frequently accessed high-order address being greater than or equal to a preset time interval threshold. Failing to satisfy the clearing condition includes a time interval between the current sampling time and the time of the last clearing of the most frequently accessed high-order address being less than the preset time interval threshold.

[0148] In some embodiments, a time window can be set at regular intervals. If no register is available at a new high-order address within this window, the high-order address with the smallest count value is deleted; otherwise, it is discarded. Alternatively, a time window can be set every first preset number of sampled addresses received. This first preset number can be a fixed value or an incrementing value that increases with the number of received sampled addresses. It is understood that the time window described above has two forms: one lasts until the high-order address with the smallest count value is deleted, and the other is a fixed duration where the address is discarded if the window is missed. In actual control, the time window can be set and selected according to actual needs.

[0149] In some embodiments, satisfying the clearing condition includes having performed a row hammer refresh operation more than or equal to a clearing count threshold. Failing to satisfy the clearing condition includes having performed a row hammer refresh operation less than the clearing count threshold.

[0150] S306. When the clearing condition is met, determine whether the high-order address with the lowest access frequency is a locked high-order address. If yes, proceed to S309; ​​otherwise, proceed to S307.

[0151] S307. Delete the address data in the high-order register containing the high-order address with the lowest access frequency, and clear the corresponding access frequency.

[0152] In some embodiments, if there are multiple high-order addresses with the lowest access frequency, and none of these high-order addresses are locked, then a high-order address is randomly selected for deletion.

[0153] For example, continuing with Example 3, the most frequently accessed addresses are high-order address 1 and high-order address 2, and the locked high-order address is high-order address 3. Since they are different, one of the first and second high-order registers is randomly selected, and the access frequency of the corresponding counter is cleared. If the first high-order register is selected, the address data in the first high-order register is deleted, and the access frequency of the counter corresponding to the first high-order register is cleared.

[0154] S308. Store the high-order address of the current sampling address in the high-order register of the deleted address data, and update the access frequency of the high-order address of the current sampling address.

[0155] If the data at the address in the first high-order register is selected for deletion, the high-order address of the current sampling address is stored in the first high-order register. The access frequency of the counter corresponding to the first high-order register is set to 1.

[0156] S309. Discard the high-order bits of the current sampling address.

[0157] Specifically, if there is no high-order address of the current sampling address recorded, no free low-order register to store the low-order address, and the clearing condition is not met, the high-order address of the current sampling address is discarded. Alternatively, if there is no high-order address of the current sampling address recorded, no free low-order register to store the low-order address, the clearing condition is met, but the high-order address with the lowest access frequency is a locked high-order address, the high-order address of the current sampling address is discarded.

[0158] In the above technical solution, when neither the high-order address of the current sampling address is recorded nor there is a free low-order register to store the low-order address, the system continues to determine whether the clearing condition is met and whether the high-order address to be cleared is a locked high-order address. If the clearing condition is met and the high-order address is not locked, the high-order address of the current sampling address is stored. This setting allows for recording more access frequencies of high-order addresses, preventing earlier high-order addresses from occupying storage space while later, frequently accessed high-order addresses remain unrecorded, thus affecting the accuracy of the row hammer address.

[0159] In some embodiments, the method for obtaining the row hammer refresh address provided in this application further includes the following steps:

[0160] S112. When performing the row hammer refresh operation of the current row hammer refresh cycle, delete the address data in the high-order register where the high-order address with an access frequency less than the second frequency threshold is located, and clear the corresponding access frequency.

[0161] The second frequency threshold is positively correlated with the number of row hammer refresh operations that have been performed. For example, the second frequency threshold is calculated according to the formula TH = 10 * a, where a represents the number of row hammer refresh operations that have been performed, and TH is the second frequency threshold.

[0162] When performing the row hammer refresh operation in the current row hammer refresh cycle, the second frequency threshold is updated based on the number of row hammer refresh operations already performed. The frequency count of the high-order addresses stored in each high-order register is obtained. The frequency count of each high-order address is compared with the second frequency threshold; if it is less than the second frequency threshold, the data at that address in the high-order register is deleted, and the access frequency in the corresponding counter is cleared.

[0163] In the above technical solution, during each row hammer refresh operation, high-order register address data with an access frequency lower than the second frequency threshold is deleted. This allows for the recording of more high-order address access frequencies, preventing earlier high-order addresses from occupying storage space while later, frequently accessed high-order addresses remain unrecorded, affecting the accuracy of the row hammer address. Performing the deletion operation after each row hammer refresh operation reduces the impact of deletion on the accumulation of access frequencies. Furthermore, setting the second frequency threshold is positively correlated with the number of row hammer refresh operations already performed to accommodate the increasing frequency of high-order addresses. This avoids the situation where a fixed frequency threshold fails to delete high-order addresses with slowly increasing or no access frequency but exceeding the fixed threshold.

[0164] In some embodiments, the method for obtaining the row hammer refresh address provided in this application further includes the following steps:

[0165] S113. After completing the row hammer refresh operation of the current row hammer refresh cycle, delete the low-order address of the row hammer refresh address stored in the low-order register group, clear the access frequency of the low-order address of the row hammer refresh address, and deduct the access frequency of the low-order address of the row hammer refresh address from the access frequency of the high-order address of the row hammer refresh address.

[0166] Example 4: The first to fifth high-order registers record five high-order addresses and their access frequencies, as shown in Table 5 below. High-order address 3 is locked within the current row hammer refresh cycle.

[0167] Table 5 shows the access frequency of the high-order address in Example 4.

[0168] High-order register 1 High-order register 2 High-order register 3 High-order register 4 High-order register 5 address High address 1 High address 2 High address 3 High address 4 High address 5 Frequency 10 20 84 30 43

[0169] The first to fifth least significant registers record five least significant addresses and their access frequencies, as shown in Table 6 below:

[0170] Table 6 shows the access frequency of the low-order address in Example 4.

[0171] Low-order register 1 Low-order register 2 Low-order register 3 Low-order register 4 Low-order register 5 address Low address 1 Low address 2 Low address 3 Low address 4 Low address 5 Frequency 4 6 7 9 8

[0172] The row hammer refresh address is selected as high address 3 + low address 4. After refreshing this row hammer refresh address, the address data in the fourth low register is deleted, the access frequency of the counter corresponding to the fourth low register is cleared, and the access frequency of the high address 3 is subtracted from the access frequency of the low address 4. The updated access frequency of the high address 3 is (84-9) = 75 times.

[0173] After removing the influence of the row hammer refresh address, the access frequency of the high-order and low-order addresses is shown in Tables 7 and 8 below:

[0174] Table 7 shows the frequency of access to the high-order address after a deletion operation in Example 4.

[0175] High-order register 1 High-order register 2 High-order register 3 High-order register 4 High-order register 5 address High address 1 High address 2 High address 3 High address 4 High address 5 Frequency 10 20 75 30 43

[0176] The first to fifth least significant registers record five least significant addresses and their access frequencies, as shown in Table 8 below:

[0177] Table 8 shows the frequency of access to the low-order address after a deletion operation in Example 4.

[0178] Low-order register 1 Low-order register 2 Low-order register 3 Low-order register 4 Low-order register 5 address Low address 1 Low address 2 Low address 3 idle Low address 5 Frequency 4 6 7 - 8

[0179] In the above technical solution, after obtaining the row hammer refresh address within the current row hammer refresh cycle and performing a row hammer refresh operation on the row hammer refresh address, the records of the row hammer refresh address in the access frequency of the high-order address and the access frequency of the low-order address are cleared. This prevents the access frequency of the row hammer refresh address from continuing to affect the access frequency of other recorded high-order addresses and low-order addresses, thus avoiding repeated refresh of the row hammer refresh address. By clearing the influence of the row hammer refresh address, preparation is made for the next acquisition of the row hammer refresh address.

[0180] In some embodiments, the method for obtaining the row hammer refresh address provided in this application further includes the following steps:

[0181] S114. After completing the row hammer refresh operation of the current row hammer refresh cycle, delete the address data in the low-order register where the low-order address with an access frequency less than the third frequency threshold is located; clear the access frequency of the low-order address with an access frequency less than the third frequency threshold; and deduct the total access frequency of the low-order address with an access frequency less than the third frequency threshold from the access frequency of the locked high-order address in the current row hammer refresh cycle.

[0182] Continuing with Example 4, let's set the third frequency threshold to 7 times. Then, modify the access frequencies in Tables 7 and 8. The low-order addresses with access frequencies less than 7 include low-order address 1 and low-order address 2. Delete the address data within the first and second low-order registers, and clear the access frequency of the counter corresponding to the first and second low-order registers. Subtract the access frequencies corresponding to the first and second low-order registers from the access frequency of high-order address 3, updating the access frequency of high-order address 3 to (75 - (4 + 6)) = 65.

[0183] In the above technical solution, after performing a row hammer refresh operation, the low-frequency addresses are deleted, and the influence of low-frequency addresses on the access frequency of high-frequency addresses is eliminated. This allows for the recording of access frequencies for more low-frequency addresses, preventing earlier-appearing low-frequency addresses from occupying storage space while later-appearing, frequently accessed low-frequency addresses remain unrecorded, thus affecting the accuracy of the row hammer addresses. Performing the deletion operation after a row hammer refresh operation reduces the impact of the deletion operation on the accumulation process of access frequencies.

[0184] In some embodiments, such as Figure 6 As shown, the method for obtaining the row hammer refresh address provided in this application further includes the following steps:

[0185] S401. After the next row hammer refresh signal arrives, determine whether the high-order address locked in the previous row hammer refresh cycle is the high-order address with the highest access frequency. If yes, proceed to S402; otherwise, proceed to S404.

[0186] The most frequently accessed high-order address can be one or more. If there is only one most frequently accessed high-order address, it is determined whether this high-order address was locked during the previous hammer refresh week. If there are multiple most frequently accessed high-order addresses, it is determined whether any of these multiple most frequently accessed high-order addresses was locked during the previous hammer refresh week.

[0187] Continuing with Example 4, after performing two deletion operations on the access frequencies in Tables 5 and 6—that is, after performing the deletion operation to eliminate the influence of the row hammer refresh address and the deletion operation of the low-order address whose access frequency is less than the third frequency threshold—the access frequencies are updated to Tables 9 and 10 below, and the locked high-order address is high-order address 3.

[0188] Table 9 shows the access frequency of the high-order address after two deletion operations in Example 4.

[0189] High-order register 1 High-order register 2 High-order register 3 High-order register 4 High-order register 5 address High address 1 High address 2 High address 3 High address 4 High address 5 Frequency 10 20 65 30 43

[0190] Table 10 shows the access frequency of the low-order address after two deletion operations in Example 4.

[0191] Low-order register 1 Low-order register 2 Low-order register 3 Low-order register 4 Low-order register 5 address idle idle Low address 3 idle Low address 5 Frequency - - 7 - 8

[0192] In Example 4, the high-order address after locking is accessed most frequently, so jump to S402.

[0193] S402. Determine whether the access frequency of the high-order address locked in the previous row refresh week meets the high-order frequency condition. If yes, proceed to S403; otherwise, proceed to S407.

[0194] Among them, meeting the high-frequency requirement includes having a high-frequency address access frequency greater than or equal to the first frequency threshold.

[0195] S403. Use the high-order address locked in the previous hammer refresh cycle as the high-order address locked in the current hammer refresh cycle.

[0196] If it is determined that the high-order address locked in the previous hammer refresh cycle is still the most frequently accessed address in the current hammer refresh cycle, and also meets the high-order frequency condition, then the high-order address locked in the previous hammer refresh cycle will continue to be used.

[0197] Continuing with Example 4, the high-order address 3 locked in the previous row hammer refresh cycle still meets the high-order frequency condition, so the high-order address 3 will continue to be used as the locked high-order address in the current row hammer refresh cycle.

[0198] S404. Get the most frequently accessed high-order address.

[0199] Among them, there can be one or more high-order addresses with the highest access frequency. If there are multiple high-order addresses with the highest access frequency, one of them is selected according to the order of appearance time of the high-order addresses. It can be selected that appears earlier or later. It is then determined whether the access address of the high-order address meets the high-order frequency condition. If it does, the high-order address will be locked.

[0200] S405. Determine whether the most frequently accessed high-order address meets the high-order frequency condition. If yes, proceed to S406; otherwise, proceed to S407.

[0201] S406. Use the high-frequency address with the highest access frequency as the high-frequency address locked in the current row hammer refresh week, and initialize the access frequency of the low-frequency address.

[0202] The frequency of accessing the initial low-order address refers to the frequency of accessing the previous low-order address and the low-order address itself.

[0203] S407. Obtain the next sampling address and update the access frequency of the high-order address using the high-order address of the next sampling address.

[0204] The frequency of accessing the high-order address has been explained in detail in steps S301 to S309, and will not be explained here again.

[0205] S408. Determine whether there is a high-order address that meets the high-order frequency condition based on the access frequency of the high-order address. If yes, proceed to S409; otherwise, proceed to S407.

[0206] S409. Lock the high-order address that meets the high-order frequency condition, and initialize the access frequency of the low-order address.

[0207] The initialization of the low-order address access frequency refers to clearing the previous low-order address and the low-order address access frequency, recording the low-order address of the next sampled address, and setting the access frequency to 1.

[0208] In the above scheme, after the next hammer refresh signal arrives, the high-order address needs to be re-locked. If multiple high-order addresses meet the high-order frequency condition, and the access frequencies of these multiple high-order addresses are different, then the high-order address with the highest access frequency is selected as the locked high-order address. If the high-order address locked in the previous hammer refresh cycle meets the high-order frequency condition and also has the highest access frequency, then this high-order address can continue to be selected. By setting it in this way, the high-order address with the highest access frequency can be locked, preparing for the determination of the hammer refresh address.

[0209] Understandably, during the process of locking the high-order address, if no high-order address reaches the required access frequency within the row hammer refresh cycle, then no row hammer refresh will be performed when the subsequent row hammer refresh signal arrives; alternatively, after the next row hammer refresh signal arrives, the high-order address with the highest access frequency among the updated access frequencies (updating the access frequencies of the high-order and low-order addresses, for example, the updated access frequencies of high and low address 3 being 65 and low address 3 being 7) from the previous row hammer refresh cycle will be locked. If multiple high-order addresses with the same access frequency exist, it is determined whether they include the locked address from the previous period. If they do, the locked address from the previous period is used as the high-order locked address for the current period. If they do not, a high-order address is randomly selected as the high-order locked address, or the high-order address that first reached the access frequency is selected as the locked address, or the determination of whether it includes the locked address from the previous period is not made, and a high-order address is randomly selected as the locked address, or the high-order address that first reached the current access frequency is selected as the locked address.

[0210] like Figure 7As shown, one embodiment of this application provides an apparatus for obtaining the row hammer refresh address, comprising:

[0211] The acquisition module 501 is used to acquire the current sampling address after the previous row hammer refresh signal arrives;

[0212] Processing module 601 is used to determine whether the high-order address has been locked within the current row hammer refresh cycle;

[0213] If it is already locked, then determine whether the high-order address of the current sampling address is the same as the high-order address that has been locked in the current row hammer refresh cycle;

[0214] If they are the same, update the access frequency of the locked high-order address and update the access frequency of the low-order address using the low-order address of the current sampled address.

[0215] When the next hammer refresh signal arrives, the low-order address with the highest access frequency is used as the low-order address of the hammer refresh address, and the locked high-order address is used as the high-order address of the hammer refresh address.

[0216] In some embodiments, the processing module 601 is further configured to:

[0217] If the high-order address of the current sampling address is different from the locked high-order address, update the access frequency of the high-order address using the high-order address of the current sampling address;

[0218] When it is determined that the next hammer refresh signal has not arrived, the next sampling address is obtained, and it is determined whether the high-order address of the next sampling address is the same as the high-order address that has been locked in the current hammer refresh cycle.

[0219] In some embodiments, the processing module 601 is further configured to:

[0220] If the high-order address is not locked within the current row hammer refresh cycle, the access frequency of the high-order address is updated using the high-order address of the current sampling address;

[0221] Determine if there is a high-order address that meets the high-order frequency condition based on the access frequency of the high-order address. If so, lock the high-order address that meets the high-order frequency condition and initialize the access frequency of the low-order address.

[0222] In some embodiments, the processing module 601 is further configured to:

[0223] If no high-order address in the high-order address of the recorded access frequency meets the high-order frequency condition, obtain the next sampling address when it is determined that the next row hammer refresh signal has not arrived, update the access frequency of the high-order address using the high-order address of the next sampling address, and determine whether there is a high-order address that meets the high-order frequency condition based on the access frequency of the high-order address.

[0224] In some embodiments, the high-frequency condition includes:

[0225] The access frequency of the high-order address is greater than or equal to the first frequency threshold.

[0226] In some embodiments, the semiconductor memory includes a low-order register group and a counter corresponding to each low-order register;

[0227] Processing module 601 is also used for:

[0228] Determine whether the low-order address of the current sampling address has been stored in the low-order register group;

[0229] If there is a low-order address of the current sampling address, update the access frequency of the low-order address of the current sampling address;

[0230] If there is no low-order address to store the current sampling address, check if there is a free low-order register in the low-order register group.

[0231] If there is a free low-order register, the low-order address of the current sampling address is stored in the free low-order register, and the access frequency of the low-order address of the current sampling address is updated.

[0232] In some embodiments, the semiconductor memory includes a high-order register group and a counter corresponding to each high-order register;

[0233] Processing module 601 is also used for:

[0234] Determine whether the high-order register group has already stored the high-order address of the current sampling address;

[0235] If the high-order address of the current sampling address is stored, update the access frequency of the high-order address of the current sampling address;

[0236] If the high-order address of the current sampling address is not stored, determine whether there is a free high-order register in the high-order register group;

[0237] If so, the high-order address of the current sampling address is stored in the free high-order register, and the access frequency of the high-order address of the current sampling address is updated.

[0238] In some embodiments, the processing module 601 is further configured to:

[0239] If there are no free high-order registers in the high-order register group, determine whether the clearing condition is met. If the clearing condition is met, determine whether the high-order address with the lowest access frequency is a locked high-order address. If it is not a locked high-order address, delete the address data in the high-order register containing the high-order address with the lowest access frequency, and clear the corresponding access frequency.

[0240] Store the high-order address of the current sampling address in the high-order register of the deleted address data, and update the access frequency of the high-order address of the current sampling address.

[0241] In some embodiments, the processing module 601 is further configured to:

[0242] When performing the row hammer refresh operation in the current row hammer refresh cycle, delete the high-order address data in the high-order register where the access frequency is less than the second frequency threshold, and clear the corresponding access frequency; wherein, the second frequency threshold is determined based on the number of row hammer refresh operations that have been performed.

[0243] In some embodiments, the processing module 601 is further configured to:

[0244] After completing the row hammer refresh operation of the current row hammer refresh cycle, delete the low-order address of the row hammer refresh address stored in the low-order register group, clear the access frequency of the low-order address of the row hammer refresh address, and deduct the access frequency of the low-order address of the row hammer refresh address from the access frequency of the high-order address of the row hammer refresh address.

[0245] In some embodiments, the processing module 601 is further configured to:

[0246] After completing the row hammer refresh operation of the current row hammer refresh cycle, delete the address data in the low-order register where the low-order address with an access frequency less than the third frequency threshold is located; clear the access frequency of the low-order address with an access frequency less than the third frequency threshold; and deduct the total access frequency of the low-order address with an access frequency less than the third frequency threshold from the access frequency of the locked high-order address in the current row hammer refresh cycle.

[0247] In some embodiments, the processing module 601 is further configured to:

[0248] After the next hammer refresh signal arrives, if the high-order address with the highest access frequency is the high-order address locked in the previous hammer refresh cycle, and the access frequency of the high-order address locked in the previous hammer refresh cycle meets the high-order frequency condition, the high-order address locked in the previous hammer refresh cycle is used as the high-order address locked in the current hammer refresh cycle to obtain the next sampling address.

[0249] After the next row hammer refresh signal arrives, if the high-order address with the highest access frequency is not the high-order address locked in the previous row hammer refresh cycle, and the high-order address with the highest access frequency meets the high-order frequency condition, the high-order address with the highest access frequency will be used as the high-order address locked in the current row hammer refresh cycle to obtain the next sampling address.

[0250] In some embodiments, the processing module 601 is further configured to:

[0251] After the next row hammer refresh signal arrives, if the high-order address with the highest access frequency is not the high-order address locked in the previous row hammer refresh cycle, and the high-order address with the highest access frequency cannot meet the high-order frequency condition, the next sampling address is obtained, and the access frequency of the high-order address is updated using the high-order address of the next sampling address; and it is determined whether there is a high-order address that meets the high-order frequency condition based on the access frequency of the high-order address. If it does, the high-order address that meets the high-order frequency condition is locked, and the access frequency of the low-order address is initialized.

[0252] This application also provides a computer-readable storage medium storing computer instructions, which, when executed by a processor, implement the steps of the methods described above.

[0253] This application also provides a computer program product, including computer instructions that, when executed by a processor, implement the various steps in the methods described above.

[0254] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0255] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for obtaining the row hammer refresh address, characterized in that, include: After the previous hammer refresh signal arrives, obtain the current sampling address and determine whether the high-order address has been locked within the current hammer refresh cycle; If it is already locked, then determine whether the high-order address of the current sampling address is the same as the high-order address that has been locked in the current row hammer refresh cycle; If they are the same, then update the access frequency of the locked high-order address, and update the access frequency of the low-order address using the low-order address of the current sampling address. When the next hammer refresh signal arrives, the low-order address with the highest access frequency is used as the low-order address of the hammer refresh address, and the locked high-order address is used as the high-order address of the hammer refresh address. When performing the row hammer refresh operation of the current row hammer refresh cycle, delete the address data in the high-order register where the high-order address with an access frequency less than the second frequency threshold is located, and clear the corresponding access frequency; wherein, the second frequency threshold is positively correlated with the number of row hammer refresh operations that have been performed.

2. The method according to claim 1, characterized in that, The method further includes: If the high-order address of the current sampling address is different from the locked high-order address, the access frequency of the high-order address is updated using the high-order address of the current sampling address; When it is determined that the next row hammer refresh signal has not arrived, the next sampling address is obtained, and it is determined whether the high-order address of the next sampling address is the same as the high-order address that has been locked in the current row hammer refresh cycle.

3. The method according to claim 1, characterized in that, The method further includes: If the high-order address is not locked within the current row hammer refresh cycle, the access frequency of the high-order address is updated using the high-order address of the current sampling address; Based on the access frequency of the high-order address, determine whether there is a high-order address that meets the high-order frequency condition. If so, lock the high-order address that meets the high-order frequency condition and initialize the access frequency of the low-order address.

4. The method according to claim 3, characterized in that, The method further includes: If no high-order address in the high-order address of the recorded access frequency meets the high-order frequency condition, when it is determined that the next row hammer refresh signal has not arrived, the next sampling address is obtained, the high-order address of the next sampling address is used to update the access frequency of the high-order address, and it is determined whether there is a high-order address that meets the high-order frequency condition based on the access frequency of the high-order address.

5. The method according to claim 3, characterized in that, The high-frequency conditions include: The access frequency of the high-order address is greater than or equal to the first frequency threshold.

6. The method according to claim 1, characterized in that, Semiconductor memory includes a low-order register group and a counter corresponding to each low-order register; Updating the access frequency of the low-order address using the low-order address of the current sampling address specifically includes: Determine whether the low-order address of the current sampling address is already stored in the low-order register group; If the low-order address of the current sampling address is available, update the access frequency of the low-order address of the current sampling address; If there is no low-order address storing the current sampling address, determine whether there is a free low-order register in the low-order register group; If there is an available low-order register, the low-order address of the current sampling address is stored in the available low-order register, and the access frequency of the low-order address of the current sampling address is updated.

7. The method according to claim 2 or 3, characterized in that, Semiconductor memory includes a high-order register group and a counter corresponding to each high-order register; Updating the access frequency of the high-order address using the high-order address of the current sampling address specifically includes: Determine whether the high-order register group has already stored the high-order address of the current sampling address; If the high-order address of the current sampling address is stored, update the access frequency of the high-order address of the current sampling address; If the high-order address of the current sampling address is not stored, determine whether there is a free high-order register in the high-order register group; If so, the high-order address of the current sampling address is stored in the idle high-order register, and the access frequency of the high-order address of the current sampling address is updated.

8. The method according to claim 7, characterized in that, Updating the access frequency of the high-order address using the high-order address of the current sampling address also includes: If there are no free high-order registers in the high-order register group, determine whether the clearing condition is met. If the clearing condition is met, determine whether the high-order address with the lowest access frequency is a locked high-order address. If it is not a locked high-order address, delete the address data in the high-order register where the high-order address with the lowest access frequency is located, and clear the corresponding access frequency. The high-order address of the current sampling address is stored in the high-order register where the address data is deleted, and the access frequency of the high-order address of the current sampling address is updated.

9. The method according to any one of claims 1 to 3, characterized in that, The method further includes: After completing the row hammer refresh operation of the current row hammer refresh cycle, delete the low-order address of the row hammer refresh address stored in the low-order register group, clear the access frequency of the low-order address of the row hammer refresh address, and deduct the access frequency of the low-order address of the row hammer refresh address from the access frequency of the high-order address of the row hammer refresh address.

10. The method according to any one of claims 1 to 3, characterized in that, The method further includes: After completing the row hammer refresh operation of the current row hammer refresh cycle, delete the address data in the low-order register where the low-order address with an access frequency less than the third frequency threshold is located; clear the access frequency of the low-order address with an access frequency less than the third frequency threshold; and deduct the total access frequency of the low-order address with an access frequency less than the third frequency threshold from the access frequency of the locked high-order address in the current row hammer refresh cycle.

11. The method according to claim 1, characterized in that, The method further includes: After the next hammer refresh signal arrives, if the high-order address with the highest access frequency is a high-order address locked in the previous hammer refresh cycle, and the access frequency of the high-order address locked in the previous hammer refresh cycle meets the high-order frequency condition, then the high-order address locked in the previous hammer refresh cycle is used as the locked high-order address in the current hammer refresh cycle, and the next sampling address is obtained. After the next row hammer refresh signal arrives, if the high-order address with the highest access frequency is not the high-order address locked in the previous row hammer refresh cycle, and the high-order address with the highest access frequency meets the high-order frequency condition, then the high-order address with the highest access frequency is taken as the high-order address locked in the current row hammer refresh cycle, and the next sampling address is obtained.

12. The method according to claim 11, characterized in that, The method further includes: After the next row hammer refresh signal arrives, if the high-order address with the highest access frequency is not the high-order address locked in the previous row hammer refresh cycle, and the high-order address with the highest access frequency cannot meet the high-order frequency condition, the next sampling address is obtained, and the access frequency of the high-order address is updated using the high-order address of the next sampling address; and it is determined whether there is a high-order address that meets the high-order frequency condition based on the access frequency of the high-order address. If it does, the high-order address that meets the high-order frequency condition is locked, and the access frequency of the low-order address is initialized.

13. A control device, characterized in that, include: Used to implement the method as described in any one of claims 1 to 12.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1 to 12.

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