Shift register unit, gate drive circuit, display device, and driving method

Abstract

The shift register unit, the gate drive circuit, the display device and the driving method provided by the embodiments of the present disclosure, wherein the shift register unit comprises: a first control circuit configured to control signals of a first node and a second node according to signals of an input signal end and a first clock signal end; a second control circuit configured to control signals of at least two driving nodes according to signals of the first node, the second node and a second clock signal end; a cascade output circuit configured to provide a signal of one of the at least two driving nodes to a cascade output end according to a cascade selection signal end; and a driving output circuit configured to provide a signal of at least one of the at least two driving nodes to a driving output end of a corresponding driving node according to a driving selection signal end.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to shift register units, gate drive circuits, display devices, and driving methods. Background Technology

[0002] With the rapid development of display technology, display devices are increasingly moving towards higher integration and lower cost. Among these technologies, GOA (Gate Driver on Array) integrates the TFT (Thin Film Transistor) gate driving circuitry onto the array substrate of the display device to drive the display. The driving control circuit typically consists of multiple cascaded shift register units. Summary of the Invention

[0003] The shift register unit provided in this embodiment includes:

[0004] The first control circuit is configured to control the signals of the first node and the second node according to the signals of the input signal terminal and the first clock signal terminal;

[0005] The second control circuit is configured to control the signals of at least two drive nodes based on the signals of the first node, the second node, and the second clock signal terminal.

[0006] The cascaded output circuit is configured to provide a signal from one of the at least two driving nodes to the cascaded output terminal according to the cascaded selection signal terminal.

[0007] The drive output circuit is configured to provide a signal of at least one of the at least two drive nodes to the drive output terminal corresponding to the drive node, based on the drive selection signal terminal.

[0008] In some possible embodiments disclosed herein, the driving node includes M driving nodes, the second clock signal terminal includes M second clock signal terminals, and the driving output terminal includes M driving output terminals; M is an integer greater than 1;

[0009] The second control circuit includes M second control circuits; wherein the m-th second control circuit of the M second control circuits corresponds to the m-th drive node of the M drive nodes, and the m-th second control circuit corresponds to the m-th second clock signal terminal of the M second clock signal terminals; and the m-th second control circuit is configured to provide the signal of the m-th second clock signal terminal to the m-th drive node in response to the signal of the first node, and to provide the signal of the first reference signal terminal to the m-th drive node in response to the signal of the second node; 1≤m≤M, and m is an integer;

[0010] The cascaded output circuit includes M cascaded output circuits, and the cascaded selection signal terminal includes M cascaded selection signal terminals; wherein, the m-th cascaded output circuit of the M cascaded output circuits corresponds to the m-th driving node, and the m-th cascaded output circuit corresponds to the m-th cascaded selection signal terminal of the M cascaded selection signal terminals; the m-th cascaded output circuit is configured to provide the signal of the m-th driving node to the cascaded output terminal in response to the signal of the m-th cascaded selection signal terminal;

[0011] The drive output circuit includes M drive output circuits, and the drive selection signal terminal includes M drive selection signal terminals; the m-th drive output circuit of the M drive output circuits corresponds to the m-th drive node, and the m-th drive output circuit corresponds to the m-th drive selection signal terminal of the M drive selection signal terminals; the m-th drive output circuit is configured to provide the signal of the m-th drive node to the m-th drive output terminal in response to the signal of the m-th drive selection signal terminal.

[0012] In some possible embodiments of this disclosure, the m-th cascaded output circuit includes: the m-th first transistor;

[0013] The control electrode of the m-th first transistor is coupled to the m-th cascade selection signal terminal, the first electrode of the m-th first transistor is coupled to the m-th driving node, and the second electrode of the m-th first transistor is coupled to the cascade output terminal.

[0014] In some possible embodiments of this disclosure, the m-th drive output circuit includes: the m-th second transistor;

[0015] The control electrode of the m-th second transistor is coupled to the m-th drive selection signal terminal, the first electrode of the m-th second transistor is coupled to the m-th drive node, and the second electrode of the m-th second transistor is coupled to the drive output terminal.

[0016] In some possible embodiments of the present disclosure, the m-th second control circuit includes: an m-th third transistor, an m-th fourth transistor, and an m-th first capacitor;

[0017] The control electrode of the m-th third transistor is coupled to the first node, the first electrode of the m-th third transistor is coupled to the m-th second clock signal terminal, and the second electrode of the m-th third transistor is coupled to the m-th driving node;

[0018] The control electrode of the m-th fourth transistor is coupled to the second node, the first electrode of the m-th fourth transistor is coupled to the first reference signal terminal, and the second electrode of the m-th fourth transistor is coupled to the m-th driving node;

[0019] The first electrode plate of the m-th first capacitor is coupled to the first node, and the second electrode plate of the m-th first capacitor is coupled to the m-th driving node.

[0020] In some possible embodiments of the present disclosure, the m-th second control circuit further includes: an m-th fifth transistor; the control electrode of the m-th third transistor is coupled to the first node through the m-th fifth transistor; the first electrode of the m-th fifth transistor is coupled to the first node, and the second electrode of the m-th fifth transistor is coupled to the control electrode of the m-th third transistor;

[0021] When m = 1, the control electrode of the m-th fifth transistor is coupled to the second reference signal terminal;

[0022] When 1 < m ≤ M, the control electrode of the m-th fifth transistor is coupled to the first clock signal terminal.

[0023] In some possible embodiments of the present disclosure, the first control circuit includes: an input circuit and a node control circuit;

[0024] The input circuit is configured to provide the signal of the input signal terminal to the first node in response to the signal of the first clock signal terminal;

[0025] The node control circuit is configured to provide the signal of the second reference signal terminal to the second node in response to the signal of the first clock signal terminal, provide the signal of the first clock signal terminal to the second node in response to the signal of the first node, and provide the signal of the first reference signal terminal to the first node in response to the signals of the second node and the first second clock signal terminal.

[0026] In some possible embodiments of this disclosure, the input circuit includes: a sixth transistor; the control electrode of the sixth transistor is coupled to the first clock signal terminal, the first electrode of the sixth transistor is coupled to the input signal terminal, and the second electrode of the sixth transistor is coupled to the first node;

[0027] The node control circuit includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and a second capacitor; wherein, the control electrode of the seventh transistor is coupled to the first clock signal terminal, the first electrode of the seventh transistor is coupled to the second reference signal terminal, and the second electrode of the seventh transistor is coupled to the second node; the control electrode of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the first clock signal terminal, and the second electrode of the eighth transistor is coupled to the second node; the control electrode of the ninth transistor is coupled to the second node, the first electrode of the ninth transistor is coupled to the first reference signal terminal, and the second electrode of the ninth transistor is coupled to the first electrode of the tenth transistor; the control electrode of the tenth transistor is coupled to the first second clock signal terminal, and the second electrode of the tenth transistor is coupled to the first node; the first electrode plate of the second capacitor is coupled to the second node, and the second electrode plate of the second capacitor is coupled to the first reference signal terminal.

[0028] This disclosure also provides a gate drive circuit, including a plurality of cascaded shift register units as described above;

[0029] The input signal terminal of the first-stage shift register unit is coupled to the frame start signal line;

[0030] In each pair of adjacent shift register units, the input signal terminal of the next shift register unit is coupled to the cascaded output terminal of the previous shift register unit.

[0031] This disclosure also provides a display device, including a display panel; the display panel includes: multiple gate lines, multiple clock signal lines, multiple cascaded selection signal lines, multiple drive selection signal lines, and the aforementioned gate drive circuit;

[0032] Each drive output terminal of each shift register unit in the gate drive circuit is coupled one-to-one with the plurality of gate lines, and one of the shift register units in the gate drive circuit is coupled with the plurality of clock signal lines.

[0033] The cascade selection signal terminal of the shift register unit in the gate drive circuit is coupled to the cascade selection signal line;

[0034] The drive selection signal terminal of the shift register unit in the gate drive circuit is coupled to the drive selection signal line.

[0035] In some possible embodiments disclosed herein, the display panel further includes a plurality of pixel units arranged in an array; one row of the pixel units corresponds to one of the shift register units in the gate driving circuit;

[0036] The pixel unit includes multiple sub-pixels of different colors arranged along the column direction, and a row of the sub-pixels is coupled to a gate line;

[0037] The m-th drive output of each shift register unit is coupled to the gate line corresponding to the same color sub-pixel.

[0038] In some possible embodiments of this disclosure, M=3, and the pixel unit includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel arranged sequentially in the column direction;

[0039] The multiple clock signal lines include a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line; wherein, the first clock signal terminal of the 4k_3 level shift register unit, the first second clock signal terminal of the 4k_2 level shift register unit, the second second clock signal terminal of the 4k_1 level shift register unit, and the third second clock signal terminal of the 4k level shift register unit are all coupled to the first clock signal line; the first second clock signal terminal of the 4k_3 level shift register unit, the second second clock signal terminal of the 4k_2 level shift register unit, the third second clock signal terminal of the 4k_1 level shift register unit, and the first second clock signal terminal of the 4k level shift register unit are all coupled to the first clock signal line; The clock signal terminals are all coupled to the second clock signal line; the second second clock signal terminal of the 4k_3 level shift register unit, the third second clock signal terminal of the 4k_2 level shift register unit, the first clock signal terminal of the 4k_1 level shift register unit, and the first second clock signal terminal of the 4k level shift register unit are all coupled to the third clock signal line; the third second clock signal terminal of the 4k_3 level shift register unit, the first clock signal terminal of the 4k_2 level shift register unit, the first second clock signal terminal of the 4k_1 level shift register unit, and the second second clock signal terminal of the 4k level shift register unit are all coupled to the third clock signal line; k is an integer greater than 0;

[0040] The multiple cascaded selection signal lines include a first cascaded selection signal line, a second cascaded selection signal line, and a third cascaded selection signal line; wherein, the first cascaded selection signal terminal of each shift register unit is coupled to the first cascaded selection signal line, the second cascaded selection signal terminal of each shift register unit is coupled to the second cascaded selection signal line, and the third cascaded selection signal terminal of each shift register unit is coupled to the third cascaded selection signal line;

[0041] The multiple drive selection signal lines include a first drive selection signal line, a second drive selection signal line, and a third drive selection signal line; wherein, the first drive selection signal terminal of each shift register unit is coupled to the first drive selection signal line, the second drive selection signal terminal of each shift register unit is coupled to the second drive selection signal line, and the third drive selection signal terminal of each shift register unit is coupled to the third drive selection signal line.

[0042] This disclosure also provides a driving method for the above-described shift register unit, including:

[0043] In the first driving mode, a display frame includes a first input phase, a first output phase, and a first reset phase;

[0044] In the first input stage, the first control circuit controls the signals of the first node and the second node according to the signals of the input signal terminal and the first clock signal terminal; the second control circuit controls the signals of at least two driving nodes according to the signals of the first node, the second node, and the second clock signal terminal; the cascade output circuit provides the signal of the Mth driving node among the at least two driving nodes to the cascade output terminal according to the cascade selection signal terminal; the drive output circuit provides the signal of each of the at least two driving nodes to the drive output terminal corresponding to each of the driving nodes according to the drive selection signal terminal.

[0045] In the first output stage, the second control circuit controls the signals of at least two driving nodes according to the signals of the first node and the second clock signal terminal; the cascade output circuit provides the signal of the Mth driving node among the at least two driving nodes to the cascade output terminal according to the cascade selection signal terminal; the drive output circuit provides the signal of each of the at least two driving nodes to the drive output terminal corresponding to each of the driving nodes according to the drive selection signal terminal.

[0046] During the first reset phase, the first control circuit controls the signals of the first node and the second node according to the signal of the first clock signal terminal; the second control circuit controls the signals of at least two driving nodes according to the signal of the second node; the cascade output circuit provides the signal of the Mth driving node among the at least two driving nodes to the cascade output terminal according to the cascade selection signal terminal; the drive output circuit provides the signal of each of the at least two driving nodes to the drive output terminal corresponding to each of the driving nodes according to the drive selection signal terminal.

[0047] In the second driving mode, a display frame includes a second input phase, a second output phase, and a second reset phase;

[0048] In the second input stage, the first control circuit controls the signals of the first node and the second node according to the signals of the input signal terminal and the first clock signal terminal; the second control circuit controls the signals of at least two driving nodes according to the signals of the first node, the second node, and the second clock signal terminal; the cascade output circuit provides the signal of the m-th driving node among the at least two driving nodes to the cascade output terminal according to the cascade selection signal terminal; the drive output circuit provides the signal of the m-th driving node among the at least two driving nodes to the corresponding drive output terminal according to the drive selection signal terminal.

[0049] In the second output stage, the second control circuit controls the signals of at least two drive nodes according to the signals of the first node and the second clock signal terminal; the cascade output circuit provides the signal of the mth drive node among the at least two drive nodes to the cascade output terminal according to the cascade selection signal terminal; the drive output circuit provides the signal of the mth drive node among the at least two drive nodes to the corresponding drive output terminal according to the drive selection signal terminal.

[0050] During the second reset phase, the first control circuit controls the signals of the first node and the second node according to the signal of the first clock signal terminal; the second control circuit controls the signals of at least two driving nodes according to the signal of the second node; the cascade output circuit provides the signal of the m-th driving node among the at least two driving nodes to the cascade output terminal according to the cascade selection signal terminal; and the drive output circuit provides the signal of the m-th driving node among the at least two driving nodes to the corresponding drive output terminal according to the drive selection signal terminal.

[0051] This disclosure also provides a driving method for the above-described display device, including:

[0052] In the first driving mode, within a display frame, different first clock signals are loaded onto each of the clock signal lines, gate turn-on signals are loaded onto each of the drive selection signal lines, gate turn-on signals are loaded onto the cascade selection signal lines coupled to the Mth drive output circuit, and gate turn-off signals are loaded onto the remaining cascade selection signal lines. This controls each of the shift register units to work sequentially, providing the signal of the Mth drive node among the at least two drive nodes to the cascade output terminal, and providing the signal of each of the at least two drive nodes to the drive output terminal corresponding to each of the drive nodes, thereby scanning the multiple gate lines line by line.

[0053] In the second driving mode, within a display frame, a second clock signal is applied to each of the clock signal lines, a gate-on signal is applied to the drive selection signal line coupled to the m-th cascaded output circuit, a gate-off signal is applied to the remaining drive selection signal lines, a gate-on signal is applied to the cascaded selection signal line coupled to the m-th drive output circuit, and a gate-off signal is applied to the remaining cascaded selection signal lines. This controls the sequential operation of each of the shift register units, providing the signal of the m-th drive node among the at least two drive nodes to the cascaded output terminal, and providing the signal of the m-th drive node to the corresponding drive output terminal, thereby performing interlaced scanning of the multiple gate lines. The clock period of the second clock signal is different from the clock period of the first clock signal.

[0054] In some possible embodiments of this disclosure, in the second driving mode, the same second clock signal is applied to the first clock signal line and the third clock signal line, and the same second clock signal is applied to the second clock signal line and the fourth clock signal line. A gate-on signal is applied to the first cascade selection signal line, and a gate-off signal is applied to both the second cascade selection signal line and the third cascade selection signal line. A gate-on signal is applied to the first drive selection signal line, and a gate-off signal is applied to both the second drive selection signal line and the third drive selection signal line. The shift register units are controlled to work sequentially, providing the signal of the first drive node to the cascade output terminal and providing the signal of the first drive node to the first drive output terminal, and scanning the gate line coupled to each first color sub-pixel row; wherein the second clock signals applied to the first clock signal line and the second clock signal line are different.

[0055] In some possible embodiments of this disclosure, the clock period of the second clock signal is no greater than 3 / 2 of the clock period of the first clock signal.

[0056] In some possible embodiments of this disclosure, in the second driving mode, different second clock signals are loaded onto the first to fourth clock signal lines respectively, a gate-on signal is loaded onto the second cascade selection signal line, and a gate-off signal is loaded onto both the first and third cascade selection signal lines. A gate-on signal is loaded onto the second driving selection signal line, and a gate-off signal is loaded onto both the first and third driving selection signal lines. This controls each of the shift register units to operate sequentially, providing the signal of the second driving node to the cascade output terminal and providing the signal of the second driving node to the second driving output terminal, and scanning the gate line coupled to each second color sub-pixel row; wherein the second clock signal has two different clock cycles.

[0057] In some possible embodiments of this disclosure, the two different clock cycles include a first clock cycle and a second clock cycle; the first clock cycle is no greater than 3 / 4 of the clock cycle of the first clock signal, and the second clock cycle is no greater than 9 / 4 of the clock cycle of the first clock signal.

[0058] In some possible embodiments of this disclosure, in the second driving mode, different second clock signals are loaded onto the first to fourth clock signal lines respectively, a gate-on signal is loaded onto the third cascade selection signal line, and a gate-off signal is loaded onto both the first and second cascade selection signal lines. A gate-on signal is loaded onto the third driving selection signal line, and a gate-off signal is loaded onto both the first and second driving selection signal lines. The shift register units are controlled to work sequentially, providing the signal of the third driving node to the cascade output terminal and providing the signal of the third driving node to the third driving output terminal, and scanning the gate line coupled to each third color sub-pixel row.

[0059] In some possible implementations of this disclosure, the second clock period is no greater than three times the clock period of the first clock signal.

[0060] In some possible embodiments of this disclosure, the duration of the effective level of the second clock signal within one clock cycle is not less than the duration of the effective level of the first clock signal within one clock cycle.

[0061] In some possible implementations of this disclosure, when scanning the gate line coupled to the first color sub-pixel row, the duration of the effective level of the second clock signal within one clock cycle is longer than the duration of the effective level of the first clock signal within one clock cycle.

[0062] When scanning the gate line coupled to the second color sub-pixel row, the duration of the effective level of the second clock signal within one clock cycle is equal to the duration of the effective level of the first clock signal within one clock cycle.

[0063] When scanning the gate line coupled to the third color sub-pixel row, the duration of the effective level of the second clock signal within one clock cycle is equal to the duration of the effective level of the first clock signal within one clock cycle. Attached Figure Description

[0064] Figure 1 Some structural schematic diagrams of the shift register unit provided in the embodiments of this disclosure;

[0065] Figure 2 Other structural schematic diagrams of the shift register unit provided in the embodiments of this disclosure;

[0066] Figure 3 Schematic diagrams of specific structures of the shift register unit provided in the embodiments of this disclosure;

[0067] Figure 4 A flowchart illustrating the shift register unit provided in the embodiments of this disclosure in the first driving mode;

[0068] Figure 5a Some signal timing diagrams of the shift register unit provided in the embodiments of this disclosure in the first driving mode;

[0069] Figure 5b Other signal timing diagrams for the shift register unit provided in the embodiments of this disclosure in the first driving mode;

[0070] Figure 6 A flowchart illustrating the shift register unit provided in the second driving mode according to an embodiment of this disclosure;

[0071] Figure 7a Some signal timing diagrams of the shift register unit provided in the embodiments of this disclosure in the second driving mode;

[0072] Figure 7b Other signal timing diagrams for the shift register unit provided in the embodiments of this disclosure in the second driving mode;

[0073] Figure 7c Further signal timing diagrams for the shift register unit provided in the embodiments of this disclosure in the second driving mode;

[0074] Figure 8 Further signal timing diagrams for the shift register unit provided in the embodiments of this disclosure in the second driving mode;

[0075] Figure 9 Further signal timing diagrams for the shift register unit provided in the embodiments of this disclosure in the second driving mode;

[0076] Figure 10 Some schematic diagrams of the gate drive circuit provided in the embodiments of this disclosure;

[0077] Figure 11 Some structural schematic diagrams of the display device provided in the embodiments of this disclosure;

[0078] Figure 12 Some structural schematic diagrams of the display panel provided in the embodiments of this disclosure;

[0079] Figure 13 These are some other structural schematic diagrams of the display panel provided in the embodiments of this disclosure;

[0080] Figure 14 Some schematic flowcharts of the display device provided in the embodiments of this disclosure;

[0081] Figure 15 Some signal timing diagrams of the display device in the first driving mode provided in the embodiments of this disclosure;

[0082] Figure 16a Some signal timing diagrams of the display device in the second driving mode provided in the embodiments of this disclosure;

[0083] Figure 16b Other signal timing diagrams of the display device provided in the embodiments of this disclosure in the second driving mode;

[0084] Figure 16c Further signal timing diagrams of the display device provided in the second driving mode according to embodiments of this disclosure;

[0085] Figure 17a Further signal timing diagrams of the display device provided in the second driving mode according to embodiments of this disclosure;

[0086] Figure 17b Further signal timing diagrams of the display device provided in the second driving mode according to embodiments of this disclosure;

[0087] Figure 18a Further signal timing diagrams of the display device provided in the second driving mode according to embodiments of this disclosure;

[0088] Figure 18b Further signal timing diagrams for the display device provided in the embodiments of this disclosure in the second driving mode. Detailed Implementation

[0089] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0090] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “may include” or “comprising” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0091] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0092] The shift register unit provided in the embodiments of this disclosure, such as Figure 1 As shown, it may include:

[0093] The first control circuit 01 is configured to control the signals of the first node N1 and the second node N2 according to the signals of the input signal terminal INP and the first clock signal terminal CK1.

[0094] The second control circuit 02 is configured to control at least two drive nodes N0_1 to N0_3 based on the signals from the first node N1, the second node N2, and the second clock signal terminal. Figure 1 (Taking 3 driving nodes as an example) signals;

[0095] Cascaded output circuit 03 is configured to select signals JX_1 to JX_3 according to the cascaded selection terminals. Figure 1 Taking three cascaded selection signal terminals as an example, the signal of one of the driving nodes N0_1 to N0_3 is provided to the cascaded output terminal JO.

[0096] The drive output circuit 04 is configured to select the drive selection signals GX_1 to GX_3 according to the drive selection signals. Figure 1 Taking three drive selection signal terminals as an example, at least two drive nodes N0_1 to N0_3 ( Figure 1 (Taking three driver nodes as an example) At least one driver node's signal is provided to the corresponding driver node's drive output terminals GO_1 to GO_3. Figure 1 (Taking three drive output terminals as an example).

[0097] The shift register unit provided in this embodiment, through the cooperation of a first control circuit, a second control circuit, a cascaded output circuit, and a drive output circuit, can select the signal of one drive node from the signals of multiple drive nodes and provide it to the cascaded output terminal JO as a cascaded signal output, so as to input a corresponding signal to the input signal terminal of the next stage shift register unit. Furthermore, since one drive output terminal is coupled to one gate line, the shift register unit in this embodiment can be coupled to multiple gate lines. This allows the selection of at least one drive node's signal from the signals of multiple drive nodes and providing it to the drive output terminal as a gate scan signal output, so as to input a corresponding gate scan signal to at least one of the coupled multiple gate lines, thereby enabling one shift register unit to drive multiple coupled gate lines or drive one gate line among the multiple coupled gate lines. Moreover, since the shift register unit in this embodiment can be coupled to multiple gate lines, compared to one shift register unit connected to one gate line, the number of shift register units set in the display panel can be reduced, thereby enabling a narrow bezel design for the display panel.

[0098] In some embodiments of this disclosure, the driving nodes may include M driving nodes, the second clock signal terminals may include M second clock signal terminals, the driving output terminals may include M driving output terminals, the cascade selection signal terminals may include M cascade selection signal terminals, and the driving selection signal terminals may include M driving selection signal terminals. The second control circuit may include M second control circuits, the cascade output circuit may include M cascade output circuits, and the driving output circuit may include M driving output circuits. The m-th second control circuit among the M second control circuits corresponds to the m-th driving node among the M driving nodes, and the m-th second control circuit corresponds to the m-th second clock signal terminal among the M second clock signal terminals; furthermore, the m-th second control circuit is configured to provide the signal of the m-th second clock signal terminal to the m-th driving node in response to a signal from the first node, and to provide the signal of the first reference signal terminal VREF1 to the m-th driving node in response to a signal from the second node. Furthermore, the m-th cascaded output circuit in the M cascaded output circuits corresponds to the m-th drive node, and the m-th cascaded output circuit corresponds to the m-th cascaded selection signal terminal in the M cascaded selection signal terminals; the m-th cascaded output circuit is configured to provide the signal of the m-th drive node to the cascaded output terminal JO in response to the signal of the m-th cascaded selection signal terminal. Also, the m-th drive output circuit in the M drive output circuits corresponds to the m-th drive node, and the m-th drive output circuit corresponds to the m-th drive selection signal terminal in the M drive selection signal terminals; the m-th drive output circuit is configured to provide the signal of the m-th drive node to the m-th drive output terminal in response to the signal of the m-th drive selection signal terminal. And M is an integer greater than 1, 1 ≤ m ≤ M, and m is an integer;

[0099] The following explanation uses M=3 as an example. Of course, in practical applications, M can be set to other values, such as 2, 4, 5, 6 or more, which are not limited here.

[0100] In some embodiments of this disclosure, such as Figure 2As shown, the driving nodes can include three driving nodes: the first driving node N0_1, the second driving node N0_2, and the third driving node N0_3. The second clock signal terminals can include three second clock signal terminals: the first second clock signal terminal CK2_1, the second second clock signal terminal CK2_2, and the third second clock signal terminal CK2_3. The driving output terminals can include three driving output terminals: the first driving output terminal GO_1, the second driving output terminal GO_2, and the third driving output terminal GO_3. The cascading selection signal terminals can include three cascading selection signal terminals: the first cascading selection signal terminal JX_1, the second cascading selection signal terminal JX_2, and the third cascading selection signal terminal JX_3. The driving selection signal terminals can include three driving selection signal terminals: the first driving selection signal terminal GX_1, the second driving selection signal terminal GX_2, and the third driving selection signal terminal GX_3. The second control circuit may include three second control circuits: the first second control circuit 02_1, the second second control circuit 02_2, and the third second control circuit 02_3. The cascaded output circuit may include three cascaded output circuits: the first cascaded output circuit 03_1, the second cascaded output circuit 03_2, and the third cascaded output circuit 03_3. The drive output circuit may include three drive output circuits: the first drive output circuit 04_1, the second drive output circuit 04_2, and the third drive output circuit 04_3.

[0101] In some embodiments of this disclosure, such as Figure 2 As shown, the first second control circuit 02_1 is configured to correspond to the first drive node N0_1 and the first second clock signal terminal CK2_1, and the first second control circuit 02_1 is configured to provide the signal of the first second clock signal terminal CK2_1 to the first drive node N0_1 in response to the signal of the first node N1, and to provide the signal of the first reference signal terminal VREF1 to the first drive node N0_1 in response to the signal of the second node N2. The first cascade output circuit 03_1 corresponds to the first drive node N0_1 and the first cascade selection signal terminal JX_1, and the first cascade output circuit 03_1 is configured to provide the signal of the first drive node N0_1 to the cascade output terminal JO in response to the signal of the first cascade selection signal terminal JX_1. Furthermore, the first drive output circuit 04_1 corresponds to the first drive node N0_1 and the first drive selection signal terminal GX_1, and the first drive output circuit 04_1 is configured to provide the signal of the first drive node N0_1 to the first drive output terminal GO_1 in response to the signal of the first drive selection signal terminal GX_1.

[0102] In some embodiments of this disclosure, such as Figure 2As shown, the second control circuit 02_2 is configured to correspond to the second drive node N0_2 and the second clock signal terminal CK2_2. The second control circuit 02_2 is configured to provide the signal of the second clock signal terminal CK2_2 to the second drive node N0_2 in response to the signal of the first node N1, and to provide the signal of the first reference signal terminal VREF1 to the second drive node N0_2 in response to the signal of the second node N2. The second cascade output circuit 03_2 corresponds to the second drive node N0_2 and the second cascade selection signal terminal JX_2. The second cascade output circuit 03_2 is configured to provide the signal of the second drive node N0_2 to the cascade output terminal JO in response to the signal of the second cascade selection signal terminal JX_2. Furthermore, the second drive output circuit 04_2 corresponds to the second drive node N0_2 and the second drive selection signal terminal GX_2, and the second drive output circuit 04_2 is configured to provide the signal of the second drive node N0_2 to the second drive output terminal GO_2 in response to the signal of the second drive selection signal terminal GX_2.

[0103] In some embodiments of this disclosure, such as Figure 2 As shown, the third second control circuit 02_3 is configured to correspond to the third drive node N0_3 and the third second clock signal terminal CK2_3. The third second control circuit 02_3 is configured to provide the signal of the third second clock signal terminal CK2_3 to the third drive node N0_3 in response to the signal of the first node N1, and to provide the signal of the first reference signal terminal VREF1 to the third drive node N0_3 in response to the signal of the second node N2. The third cascade output circuit 03_3 corresponds to the third drive node N0_3 and the third cascade selection signal terminal JX_3. The third cascade output circuit 03_3 is configured to provide the signal of the third drive node N0_3 to the cascade output terminal JO in response to the signal of the third cascade selection signal terminal JX_3. Furthermore, the third drive output circuit 04_3 corresponds to the third drive node N0_3 and the third drive selection signal terminal GX_3, and the third drive output circuit 04_3 is configured to provide the signal of the third drive node N0_3 to the third drive output terminal GO_3 in response to the signal of the third drive selection signal terminal GX_3.

[0104] In some embodiments of this disclosure, such as Figure 2As shown, the first control circuit 01 may include an input circuit 011 and a node control circuit 012. The input circuit 011 is configured to provide the input signal terminal INP to the first node N1 in response to the signal of the first clock signal terminal CK1. The node control circuit 012 is configured to provide the signal of the second reference signal terminal VREF2 to the second node N2 in response to the signal of the first clock signal terminal CK1, provide the signal of the first clock signal terminal CK1 to the second node N2 in response to the signal of the first node N1, and provide the signal of the first reference signal terminal VREF1 to the first node N1 in response to the signals of the second node N2 and the first second clock signal terminal CK2_1.

[0105] In some embodiments of this disclosure, such as Figure 3 As shown, the first cascaded output circuit 03_1 may include a first transistor M1_1. The control electrode of the first transistor M1_1 is coupled to the first cascade selection signal terminal JX_1, the first electrode of the first transistor M1_1 is coupled to the first driving node N0_1, and the second electrode of the first transistor M1_1 is coupled to the cascaded output terminal JO. For example, the first transistor M1_1 can be turned on when the signal at the first cascade selection signal terminal JX_1 is at an active level and turned off when the signal at the first cascade selection signal terminal JX_1 is at an inactive level. For instance, if the first transistor M1_1 is an N-type transistor, then the active level of the signal at the first cascade selection signal terminal JX_1 is high, and the inactive level is low. Alternatively, if the first transistor M1_1 is a P-type transistor, then the active level of the signal at the first cascade selection signal terminal JX_1 is low, and the inactive level is high.

[0106] In some embodiments of this disclosure, such as Figure 3 As shown, the second cascaded output circuit 03_2 may include a second first transistor M1_2. The control electrode of the second first transistor M1_2 is coupled to the second cascade selection signal terminal JX_2, the first electrode of the second first transistor M1_2 is coupled to the second driving node N0_2, and the second electrode of the second first transistor M1_2 is coupled to the cascaded output terminal JO. For example, the second first transistor M1_2 can be turned on when the signal at the second cascade selection signal terminal JX_2 is at an active level and turned off when the signal at the second cascade selection signal terminal JX_2 is at an inactive level. For example, if the second first transistor M1_2 is an N-type transistor, then the active level of the signal at the second cascade selection signal terminal JX_2 is high, and the inactive level is low. Alternatively, if the second first transistor M1_2 is a P-type transistor, then the active level of the signal at the second cascade selection signal terminal JX_2 is low, and the inactive level is high.

[0107] In some embodiments of this disclosure, such as Figure 3 As shown, the third cascaded output circuit 03_3 may include a third first transistor M1_3. The control electrode of the third first transistor M1_3 is coupled to the third cascade selection signal terminal JX_3, the first electrode of the third first transistor M1_3 is coupled to the third driving node N0_3, and the second electrode of the third first transistor M1_3 is coupled to the cascaded output terminal JO. For example, the third first transistor M1_3 can be turned on when the signal at the third cascade selection signal terminal JX_3 is at an active level and turned off when the signal at the third cascade selection signal terminal JX_3 is at an inactive level. For example, if the third first transistor M1_3 is an N-type transistor, then the active level of the signal at the third cascade selection signal terminal JX_3 is high, and the inactive level is low. Alternatively, if the third first transistor M1_3 is a P-type transistor, then the active level of the signal at the third cascade selection signal terminal JX_3 is low, and the inactive level is high.

[0108] In some embodiments of this disclosure, such as Figure 3 As shown, the first drive output circuit 04_1 may include a first second transistor M2_1. The control electrode of the first second transistor M2_1 is coupled to the first drive selection signal terminal GX_1, the first electrode of the first second transistor M2_1 is coupled to the first drive node N0_1, and the second electrode of the first second transistor M2_1 is coupled to the drive output terminal. For example, the first second transistor M2_1 can be turned on when the signal at the first drive selection signal terminal GX_1 is at an active level and turned off when the signal at the first drive selection signal terminal GX_1 is at an inactive level. For instance, if the first second transistor M2_1 is an N-type transistor, then the active level of the signal at the first drive selection signal terminal GX_1 is high, and the inactive level is low. Alternatively, if the first second transistor M2_1 is a P-type transistor, then the active level of the signal at the first drive selection signal terminal GX_1 is low, and the inactive level is high.

[0109] In some embodiments of this disclosure, such as Figure 3As shown, the second drive output circuit 04_2 may include a second transistor M2_2. The control electrode of the second transistor M2_2 is coupled to the second drive selection signal terminal GX_2, the first electrode of the second transistor M2_2 is coupled to the second drive node N0_2, and the second electrode of the second transistor M2_2 is coupled to the drive output terminal. For example, the second transistor M2_2 can be turned on when the signal at the second drive selection signal terminal GX_2 is at an active level and turned off when the signal at the second drive selection signal terminal GX_2 is at an inactive level. For instance, if the second transistor M2_2 is an N-type transistor, then the active level of the signal at the second drive selection signal terminal GX_2 is high, and the inactive level is low. Alternatively, if the second transistor M2_2 is a P-type transistor, then the active level of the signal at the second drive selection signal terminal GX_2 is low, and the inactive level is high.

[0110] In some embodiments of this disclosure, such as Figure 3 As shown, the third drive output circuit 04_3 may include a third second transistor M2_3. The control electrode of the third second transistor M2_3 is coupled to the third drive selection signal terminal GX_3, the first electrode of the third second transistor M2_3 is coupled to the third drive node N0_3, and the second electrode of the third second transistor M2_3 is coupled to the drive output terminal. For example, the third second transistor M2_3 can be turned on when the signal at the third drive selection signal terminal GX_3 is at an active level and turned off when the signal at the third drive selection signal terminal GX_3 is at an inactive level. For instance, if the third second transistor M2_3 is an N-type transistor, then the active level of the signal at the third drive selection signal terminal GX_3 is high, and the inactive level is low. Alternatively, if the third second transistor M2_3 is a P-type transistor, then the active level of the signal at the third drive selection signal terminal GX_3 is low, and the inactive level is high.

[0111] In some embodiments of this disclosure, such as Figure 3As shown, the first second control circuit 02_1 may include: a first third transistor M3_1, a first fourth transistor M4_1, and a first capacitor C1_1. The control electrode of the first third transistor M3_1 is coupled to the first node N1, the first electrode of the first third transistor M3_1 is coupled to the first second clock signal terminal CK2_1, and the second electrode of the first third transistor M3_1 is coupled to the first driving node N0_1. The control electrode of the first fourth transistor M4_1 is coupled to the second node N2, the first electrode of the first fourth transistor M4_1 is coupled to the first reference signal terminal VREF1, and the second electrode of the first fourth transistor M4_1 is coupled to the first driving node N0_1. The first electrode plate of the first first capacitor C1_1 is coupled to the first node N1, and the second electrode plate of the first first capacitor C1_1 is coupled to the first driving node N0_1. For example, the first third transistor M3_1 can be turned on when the signal at the first node N1 is at an active level and turned off when the signal at the first node N1 is at an inactive level. For example, if the first third transistor M3_1 is an N-type transistor, then the active level of the signal at the first node N1 is high and the inactive level is low. Alternatively, if the first third transistor M3_1 is a P-type transistor, then the active level of the signal at the first node N1 is low and the inactive level is high. Similarly, the first fourth transistor M4_1 can be turned on when the signal at the second node N2 is at an active level and turned off when the signal at the second node N2 is at an inactive level. For example, if the first fourth transistor M4_1 is an N-type transistor, then the active level of the signal at the second node N2 is high and the inactive level is low. Alternatively, if the first fourth transistor M4_1 is a P-type transistor, then the active level of the signal at the second node N2 is low and the inactive level is high. Furthermore, the first first capacitor C1_1 can maintain a stable voltage on its two electrode plates.

[0112] In some embodiments of this disclosure, such as Figure 3As shown, the second control circuit 02_2 may include: a second third transistor M3_2, a second fourth transistor M4_2, and a second first capacitor C1_2. The control electrode of the second third transistor M3_2 is coupled to the first node N1, the first electrode of the second third transistor M3_2 is coupled to the second second clock signal terminal CK2_2, and the second electrode of the second third transistor M3_2 is coupled to the second driving node N0_2. The control electrode of the second fourth transistor M4_2 is coupled to the second node N2, the first electrode of the second fourth transistor M4_2 is coupled to the first reference signal terminal VREF1, and the second electrode of the second fourth transistor M4_2 is coupled to the second driving node N0_2. The first electrode plate of the second first capacitor C1_2 is coupled to the first node N1, and the second electrode plate of the second first capacitor C1_2 is coupled to the second driving node N0_2. For example, the second third transistor M3_2 can be turned on when the signal at the first node N1 is at an active level and turned off when the signal at the first node N1 is at an inactive level. For example, if the second third transistor M3_2 is an N-type transistor, then the active level of the signal at the first node N1 is high and the inactive level is low. Alternatively, if the second third transistor M3_2 is a P-type transistor, then the active level of the signal at the first node N1 is low and the inactive level is high. Similarly, the second fourth transistor M4_2 can be turned on when the signal at the second node N2 is at an active level and turned off when the signal at the second node N2 is at an inactive level. For example, if the second fourth transistor M4_2 is an N-type transistor, then the active level of the signal at the second node N2 is high and the inactive level is low. Alternatively, if the second fourth transistor M4_2 is a P-type transistor, then the active level of the signal at the second node N2 is low and the inactive level is high. Furthermore, the second first capacitor C1_2 can maintain a stable voltage on its two electrode plates.

[0113] In some embodiments of this disclosure, such as Figure 3As shown, the third second control circuit 02_3 may include: a third transistor M3_3, a third fourth transistor M4_3, and a third first capacitor C1_3. The control electrode of the third transistor M3_3 is coupled to the first node N1, the first electrode of the third transistor M3_3 is coupled to the third second clock signal terminal CK2_3, and the second electrode of the third transistor M3_3 is coupled to the third driving node N0_3. The control electrode of the third fourth transistor M4_3 is coupled to the second node N2, the first electrode of the third fourth transistor M4_3 is coupled to the first reference signal terminal VREF1, and the second electrode of the third fourth transistor M4_3 is coupled to the third driving node N0_3. The first electrode plate of the third first capacitor C1_3 is coupled to the first node N1, and the second electrode plate of the third first capacitor C1_3 is coupled to the third driving node N0_3. For example, the third transistor M3_3 can be turned on when the signal at the first node N1 is at an active level and turned off when the signal at the first node N1 is at an inactive level. For example, if the third transistor M3_3 is an N-type transistor, then the active level of the signal at the first node N1 is high and the inactive level is low. Alternatively, if the third transistor M3_3 is a P-type transistor, then the active level of the signal at the first node N1 is low and the inactive level is high. Similarly, the third fourth transistor M4_3 can be turned on when the signal at the second node N2 is at an active level and turned off when the signal at the second node N2 is at an inactive level. For example, if the third fourth transistor M4_3 is an N-type transistor, then the active level of the signal at the second node N2 is high and the inactive level is low. Alternatively, if the third fourth transistor M4_3 is a P-type transistor, then the active level of the signal at the second node N2 is low and the inactive level is high. Furthermore, the third first capacitor C1_3 can maintain a stable voltage on its two electrode plates.

[0114] In some embodiments of this disclosure, such as Figure 3As shown, the first second control circuit 02_1 may further include: a first fifth transistor M5_1. The control electrode of the first third transistor M3_1 is coupled to the first node N1 through the first fifth transistor M5_1. The first electrode of the first fifth transistor M5_1 is coupled to the first node N1, and the second electrode of the first fifth transistor M5_1 is coupled to the control electrode of the first third transistor M3_1. Furthermore, the control electrode of the first fifth transistor M5_1 is coupled to the second reference signal terminal VREF2. For example, the first fifth transistor M5_1 can be an N-type transistor, in which case the signal at the second reference signal terminal VREF2 is a low-level signal to control the first fifth transistor M5_1 to conduct. Alternatively, the first fifth transistor M5_1 can also be a P-type transistor, in which case the signal at the second reference signal terminal VREF2 is a high-level signal to control the first fifth transistor M5_1 to conduct.

[0115] In some embodiments of this disclosure, such as Figure 3 As shown, the second control circuit 02_2 may further include a second fifth transistor M5_2. The control electrode of the second third transistor M3_2 is coupled to the first node N1 through the second fifth transistor M5_2. The first electrode of the second fifth transistor M5_2 is coupled to the first node N1, and the second electrode of the second fifth transistor M5_2 is coupled to the control electrode of the second third transistor M3_2. Furthermore, the control electrode of the second fifth transistor M5_2 is coupled to the first clock signal terminal CK1. Exemplarily, the second fifth transistor M5_2 can be turned on when the signal at the first clock signal terminal CK1 is at an active level and turned off when the signal at the first clock signal terminal CK1 is at an inactive level. For example, the second fifth transistor M5_2 can be an N-type transistor, in which case the active level of the signal at the first clock signal terminal CK1 is high and the inactive level is low. Alternatively, the second fifth transistor M5_2 can also be a P-type transistor, in which case the active level of the signal at the first clock signal terminal CK1 is low and the inactive level is high.

[0116] In some embodiments of this disclosure, such as Figure 3As shown, the third second control circuit 02_3 may further include a third fifth transistor M5_3. The control electrode of the third third transistor M3_3 is coupled to the first node N1 through the third fifth transistor M5_3. The first electrode of the third fifth transistor M5_3 is coupled to the first node N1, and the second electrode of the third fifth transistor M5_3 is coupled to the control electrode of the third third transistor M3_3. Furthermore, the control electrode of the third fifth transistor M5_3 is coupled to the first clock signal terminal CK1. Exemplarily, the third fifth transistor M5_3 can be turned on when the signal at the first clock signal terminal CK1 is at an active level and turned off when the signal at the first clock signal terminal CK1 is at an inactive level. For example, the third fifth transistor M5_3 can be an N-type transistor, in which case the active level of the signal at the first clock signal terminal CK1 is high and the inactive level is low. Alternatively, the third fifth transistor M5_3 can also be a P-type transistor, in which case the active level of the signal at the first clock signal terminal CK1 is low and the inactive level is high.

[0117] In some embodiments of this disclosure, such as Figure 3 As shown, the input circuit 011 may include a sixth transistor M6. The control electrode of the sixth transistor M6 is coupled to the first clock signal terminal CK1, the first electrode of the sixth transistor M6 is coupled to the input signal terminal INP, and the second electrode of the sixth transistor M6 is coupled to the first node N1. Exemplarily, the sixth transistor M6 can be turned on when the signal at the first clock signal terminal CK1 is at an active level and turned off when the signal at the first clock signal terminal CK1 is at an inactive level. For example, the sixth transistor M6 can be an N-type transistor, in which case the active level of the signal at the first clock signal terminal CK1 is high and the inactive level is low. Alternatively, the sixth transistor M6 can also be a P-type transistor, in which case the active level of the signal at the first clock signal terminal CK1 is low and the inactive level is high.

[0118] In some embodiments of this disclosure, such as Figure 3As shown, the node control circuit 012 may include: a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and a second capacitor C2. Specifically, the control electrode of the seventh transistor M7 is coupled to the first clock signal terminal CK1, the first electrode of the seventh transistor M7 is coupled to the second reference signal terminal VREF2, and the second electrode of the seventh transistor M7 is coupled to the second node N2; the control electrode of the eighth transistor M8 is coupled to the first node N1, the first electrode of the eighth transistor M8 is coupled to the first clock signal terminal CK1, and the second electrode of the eighth transistor M8 is coupled to the second node N2; the control electrode of the ninth transistor M9 is coupled to the second node N2, the first electrode of the ninth transistor M9 is coupled to the first reference signal terminal VREF1, and the second electrode of the ninth transistor M9 is coupled to the first electrode of the tenth transistor M10; the control electrode of the tenth transistor M10 is coupled to the first second clock signal terminal CK2_1, and the second electrode of the tenth transistor M10 is coupled to the first node N1; the first electrode plate of the second capacitor C2 is coupled to the second node N2, and the second electrode plate of the second capacitor C2 is coupled to the first reference signal terminal VREF1. For example, the seventh transistor M7 can be turned on when the signal at the first clock signal terminal CK1 is at an active level and turned off when the signal at the first clock signal terminal CK1 is at an inactive level. For example, the seventh transistor M7 can be an N-type transistor, in which case the active level of the signal at the first clock signal terminal CK1 is high and the inactive level is low. Alternatively, the seventh transistor M7 can be a P-type transistor, in which case the active level of the signal at the first clock signal terminal CK1 is low and the inactive level is high. Similarly, the eighth transistor M8 can be turned on when the signal at the first node N1 is at an active level and turned off when the signal at the first node N1 is at an inactive level. For example, the eighth transistor M8 can be an N-type transistor, in which case the active level of the signal at the first node N1 is high and the inactive level is low. Alternatively, the eighth transistor M8 can be a P-type transistor, in which case the active level of the signal at the first node N1 is low and the inactive level is high. Finally, the ninth transistor M9 can be turned on when the signal at the second node N2 is at an active level and turned off when the signal at the second node N2 is at an inactive level. For example, if the ninth transistor M9 is an N-type transistor, then the effective level of the signal at the second node N2 is high, and the ineffective level is low. Alternatively, if the ninth transistor M9 is a P-type transistor, then the effective level of the signal at the second node N2 is low, and the ineffective level is high. Furthermore, the tenth transistor M10 can be turned on when the signal at the first second clock signal terminal CK2_1 is active, and turned off when the signal at the first second clock signal terminal CK2_1 is inactive. For example, if the tenth transistor M10 is an N-type transistor, then the effective level of the signal at the first second clock signal terminal CK2_1 is high, and the ineffective level is low.Alternatively, the tenth transistor M10 can be a P-type transistor, in which case the effective level of the signal at the first second clock signal terminal CK2_1 is low, and the ineffective level is high. Furthermore, the second capacitor C2 can maintain a stable voltage on its two plates.

[0119] The above are merely illustrative examples illustrating the specific structures of each circuit in the shift register unit provided in the embodiments of this disclosure. In specific implementations, the specific structures of each circuit are not limited to those provided in the embodiments of this disclosure, but may be other structures known to those skilled in the art, and are not limited here.

[0120] Optionally, in the shift register unit provided in the embodiments of this disclosure, all transistors can be made of the same material. In specific implementations, such as... Figure 3 As shown, all transistors can be P-type transistors. Furthermore, the signal at the first reference signal terminal VREF1 is a high-level signal, and the signal at the second reference signal terminal VREF2 is a low-level signal. Of course, all transistors can also be N-type transistors, with the first reference signal terminal VREF1 being a low-level signal and the second reference signal terminal VREF2 being a high-level signal; this is not a limitation.

[0121] It should be noted that the transistors mentioned in the above embodiments of this disclosure can be thin-film transistors (TFTs) or metal-oxide-semiconductor field-effect transistors (MOSs), and are not limited thereto. In specific implementations, the control electrode of these transistors serves as their gate. Furthermore, depending on the transistor type and the signal at the signal terminal, the first electrode of these transistors can serve as the source or drain of the transistor, and the second electrode can serve as the drain or source of the transistor, and are not limited thereto.

[0122] The shift register unit provided in this embodiment can implement two driving modes: a first driving mode and a second driving mode. In the first driving mode, the signal of each driving node can be provided to the corresponding driving output terminal, so that each driving output terminal outputs a signal. In the second driving mode, the signal of one of the multiple driving nodes can be provided to the corresponding driving output terminal, so that only one driving output terminal outputs a signal.

[0123] The driving method for the shift register unit provided in the embodiments of this disclosure, such as... Figure 4 As shown, in the first driving mode, a display frame may include a first input phase T11, a first output phase T12, and a first reset phase T13.

[0124] S110, In the first input stage T11, the first control circuit controls the signals of the first node and the second node according to the signals of the input signal terminal and the first clock signal terminal; the second control circuit controls the signals of at least two driving nodes according to the signals of the first node, the second node and the second clock signal terminal; the cascade output circuit provides the signal of the Mth driving node among the at least two driving nodes to the cascade output terminal according to the cascade selection signal terminal; the drive output circuit provides the signal of each of the at least two driving nodes to the drive output terminal corresponding to each driving node according to the drive selection signal terminal.

[0125] S120, in the first output stage T12, the second control circuit controls the signals of at least two drive nodes according to the signals of the first node and the second clock signal terminal; the cascade output circuit provides the signal of the Mth drive node among the at least two drive nodes to the cascade output terminal according to the cascade selection signal terminal; the drive output circuit provides the signal of each of the at least two drive nodes to the drive output terminal corresponding to each drive node according to the drive selection signal terminal.

[0126] S130, in the first reset phase T13, the first control circuit controls the signals of the first node and the second node according to the signal of the first clock signal terminal; the second control circuit controls the signals of at least two driving nodes according to the signal of the second node; the cascade output circuit provides the signal of the Mth driving node among the at least two driving nodes to the cascade output terminal according to the cascade selection signal terminal; the drive output circuit provides the signal of each of the at least two driving nodes to the drive output terminal corresponding to each driving node according to the drive selection signal terminal.

[0127] In some embodiments of this disclosure, taking a low effective level as an example, in the first driving mode, the signals at the drive selection signal terminals are all low-level signals. Furthermore, the signal at the cascade selection signal terminal corresponding to the cascaded output circuit coupled to the Mth drive node is a low-level signal, while the signals at the remaining cascade selection signal terminals are all high-level signals.

[0128] In some examples, the following are... Figure 3 Taking the structure of the shift register unit shown as an example, combined with... Figure 5a The signal timing diagram shown describes the operation of the shift register unit provided in the embodiments of this disclosure in the first driving mode. Exemplarily, the following are mainly selected: Figure 5a The signal timing diagram shown includes a first input stage T11, a first output stage T12, and a first reset stage T13. The first output stage T12 may include three stages: T121, T122, and T123.

[0129] Furthermore, inp represents the signal of the input signal terminal INP, ck1 represents the signal of the first clock signal terminal CK1, ck2_1 represents the signal of the first second clock signal terminal CK2_1, ck2_2 represents the signal of the second second clock signal terminal CK2_2, ck2_3 represents the signal of the third second clock signal terminal CK2_3, n0_1 represents the signal of the first driver node N0_1, n0_2 represents the signal of the second driver node N0_2, n0_3 represents the signal of the third driver node N0_3, go_1 represents the signal of the first driver output terminal GO_1, go_2 represents the signal of the second driver output terminal GO_2, go_3 represents the signal of the third driver output terminal GO_3, and jo represents the signal of the cascaded output terminal JO. Additionally, the signals of the first driver selection signal terminal GX_1 to the third driver selection signal terminal GX_3 are all low-level signals. The signal at the third cascade selection terminal JX_3 is a low-level signal, while the signals at the first cascade selection terminal JX_1 and the second cascade selection terminal JX_2 are both high-level signals.

[0130] In the first input stage T11, signal ck1 is a low-level signal, which controls the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2, and the third fifth transistor M5_3 to all conduct. The conducting sixth transistor M6 provides the low-level signal inp to the first node N1, making the signal at the first node N1 a low-level signal. The eighth transistor M8, controlled by the low-level signal at the first node N1, can conduct to provide the low-level signal ck1 to the second node N2, making the signal at the second node N2 a low-level signal. The conducting seventh transistor M7 provides the low-level signal of the second reference signal terminal VREF2 to the second node N2, further making the signal at the second node N2 a low-level signal, thereby controlling the first fourth transistor M4_1, the second fourth transistor M4_2, and the third fourth transistor M4_3 to all conduct. The first conducting fourth transistor M4_1 provides the high-level signal of the first reference signal terminal VREF1 to the first driving node N0_1, making the signal of the first driving node N0_1 a high-level signal. The second conducting fourth transistor M4_2 provides the high-level signal of the first reference signal terminal VREF1 to the second driving node N0_2, making the signal of the second driving node N0_2 a high-level signal. The third conducting fourth transistor M4_3 provides the high-level signal of the first reference signal terminal VREF1 to the third driving node N0_3, making the signal of the third driving node N0_3 a high-level signal. Since the signal of the second reference signal terminal VREF2 is a low-level signal, the first fifth transistor M5_1 can be controlled to conduct. Therefore, the first third transistor M3_1 conducts to provide the high-level signal of the signal ck2_1 to the first driving node N0_1, further making the signal of the first driving node N0_1 a high-level signal. Since the signal at the first node N1 is low and the second fifth transistor M5_2 is turned on, the second third transistor M3_2 is turned on to provide the high-level signal ck2_2 to the second driving node N0_2, further making the signal at the second driving node N0_2 high. Since the signal at the first node N1 is low and the third fifth transistor M5_3 is turned on, the third third transistor M3_3 is turned on to provide the high-level signal ck2_3 to the third driving node N0_3, further making the signal at the third driving node N0_3 high. Since the signal at the first drive selection signal terminal GX_1 is low, the first second transistor M2_1 is turned on to provide the high-level signal from the first driving node N0_1 to the first drive output terminal GO_1, causing the first drive output terminal GO_1 to output a high-level signal.Since the signal at the second drive selection signal terminal GX_2 is low, the second transistor M2_2 is turned on, providing the high-level signal of the second drive node N0_2 to the second drive output terminal GO_2, so that the second drive output terminal GO_2 outputs a high-level signal. Since the signal at the third drive selection signal terminal GX_3 is low, the third transistor M2_3 is turned on, providing the high-level signal of the third drive node N0_3 to the third drive output terminal GO_3, so that the third drive output terminal GO_3 outputs a high-level signal. Since the signal at the third cascade selection signal terminal JX_3 is low, and the signals at the first cascade selection signal terminal JX_1 and the second cascade selection signal terminal JX_2 are both high, the third transistor M1_3 is turned on, while the first transistor M1_1 and the second transistor M1_2 are both turned off. The third transistor M1_3, which is turned on, provides a high-level signal to the cascade output terminal JO, so that the cascade output terminal JO outputs a high-level signal.

[0131] In stage T121 of the first output stage T12, signal ck1 is high, which controls the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2, and the third fifth transistor M5_3 to be cut off. Therefore, the first node N1 is in a floating state. Due to the effect of the first capacitor C1_1, the signal of the first node N1 can be kept low. The eighth transistor M8 is turned on by the low-level signal of the first node N1 to provide the high level of signal ck1 to the second node N2, so that the signal of the second node N2 is high, which controls the first fourth transistor M4_1, the second fourth transistor M4_2, and the third fourth transistor M4_3 to be cut off. Since the signal of the second reference signal terminal VREF2 is low, the first fifth transistor M5_1 can be turned on. Therefore, the first third transistor M3_1 is turned on to provide the low level of signal ck2_1 to the first driving node N0_1, so that the signal of the first driving node N0_1 is low. Due to the bootstrap effect of the first capacitor C1_1, the voltage level of the first node N1 can be further pulled low, so that the first third transistor M3_1 can be fully turned on as much as possible, and the low-level signal of signal ck2_1 can be provided to the first driving node N0_1 with as little voltage loss as possible, making the signal of the first driving node N0_1 a low-level signal. Since the signal of the first node N1 is a low-level signal and the second fifth transistor M5_2 is turned on, the second third transistor M3_2 is turned on, so that the high-level signal of signal ck2_2 is provided to the second driving node N0_2, making the signal of the second driving node N0_2 a high-level signal. Since the signal of the first node N1 is a low-level signal and the third fifth transistor M5_3 is turned on, the third third transistor M3_3 is turned on, so that the high-level signal of signal ck2_3 is provided to the third driving node N0_3, making the signal of the third driving node N0_3 a high-level signal. Since the signal at the first drive selection signal terminal GX_1 is low, the first second transistor M2_1 is turned on to provide the low-level signal of the first drive node N0_1 to the first drive output terminal GO_1, causing GO_1 to output a low-level signal. Since the signal at the second drive selection signal terminal GX_2 is low, the second second transistor M2_2 is turned on to provide the high-level signal of the second drive node N0_2 to the second drive output terminal GO_2, causing GO_2 to output a high-level signal. Since the signal at the third drive selection signal terminal GX_3 is low, the third second transistor M2_3 is turned on to provide the high-level signal of the third drive node N0_3 to the third drive output terminal GO_3, causing GO_3 to output a high-level signal.Since the signal at the third cascade selection signal terminal JX_3 is low, and the signals at the first cascade selection signal terminal JX_1 and the second cascade selection signal terminal JX_2 are both high, the third first transistor M1_3 is turned on, while the first first transistor M1_1 and the second first transistor M1_2 are both turned off. The turned-on third first transistor M1_3 provides the high-level signal of the third drive node N0_3 to the cascade output terminal JO, causing the cascade output terminal JO to output a high-level signal.

[0132] In stage T122 of the first output stage T12, signal ck1 is high, which controls the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2, and the third fifth transistor M5_3 to be cut off. Therefore, the first node N1 is in a floating state. Due to the effect of the first capacitor C1_1, the signal of the first node N1 can be kept at a low level. The eighth transistor M8 is controlled by the low-level signal of the first node N1 to conduct, so as to provide the high level of signal ck1 to the second node N2, making the signal of the second node N2 a high level, thereby controlling the first fourth transistor M4_1, the second fourth transistor M4_2, and the third fourth transistor M4_3 to be cut off. Since the signal of the second reference signal terminal VREF2 is low, the first fifth transistor M5_1 can be controlled to conduct. Therefore, the first third transistor M3_1 conducts, so as to provide the high level of signal ck2_1 to the first driving node N0_1, making the signal of the first driving node N0_1 a high level. Because the second fifth transistor M5_2 is off, and due to the effect of the second first capacitor C1_2, the control electrode signal of the second third transistor M3_2 can be kept low, causing the second third transistor M3_2 to conduct. This allows the low-level signal ck2_2 to be provided to the second driving node N0_2, making the signal of the second driving node N0_2 low. Due to the bootstrap effect of the second first capacitor C1_2, the control electrode level of the second third transistor M3_2 can be further pulled low, so that the second third transistor M3_2 can be turned on as fully as possible. This allows the low-level signal ck2_2 to be provided to the second driving node N0_2 with as little voltage loss as possible, making the signal of the second driving node N0_2 low. Because of the function of the third first capacitor C1_3, the control electrode level of the third third transistor M3_3 is kept low. Therefore, the third third transistor M3_3 is turned on, providing the high-level signal ck2_3 to the third drive node N0_3, making the signal of the third drive node N0_3 high. Because the signal of the first drive selection signal terminal GX_1 is low, the first second transistor M2_1 is turned on, providing the high-level signal of the first drive node N0_1 to the first drive output terminal GO_1, making the first drive output terminal GO_1 output a high-level signal. Because the signal of the second drive selection signal terminal GX_2 is low, the second second transistor M2_2 is turned on, providing the low-level signal of the second drive node N0_2 to the second drive output terminal GO_2, making the second drive output terminal GO_2 output a low-level signal.Since the signal at the third drive selection signal terminal GX_3 is low, the third second transistor M2_3 is turned on, providing the high-level signal of the third drive node N0_3 to the third drive output terminal GO_3, causing GO_3 to output a high-level signal. Since the signal at the third cascade selection signal terminal JX_3 is low, and the signals at the first cascade selection signal terminal JX_1 and the second cascade selection signal terminal JX_2 are both high, the third first transistor M1_3 is turned on, while the first first transistor M1_1 and the second first transistor M1_2 are both turned off. The turned-on third first transistor M1_3 provides the high-level signal of the third drive node N0_3 to the cascade output terminal JO, causing JO to output a high-level signal.

[0133] In stage T123 of the first output stage T12, signal ck1 is high, which controls the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2, and the third fifth transistor M5_3 to be cut off. Therefore, the first node N1 is in a floating state. Due to the effect of the first capacitor C1_1, the signal of the first node N1 can be kept at a low level. The eighth transistor M8 is turned on by the low-level signal of the first node N1 to provide the high level of signal ck1 to the second node N2, so that the signal of the second node N2 is high, which controls the first fourth transistor M4_1, the second fourth transistor M4_2, and the third fourth transistor M4_3 to be cut off. Since the signal of the second reference signal terminal VREF2 is low, the first fifth transistor M5_1 can be turned on. Therefore, the first third transistor M3_1 is turned on to provide the high level of signal ck2_1 to the first driving node N0_1, so that the signal of the first driving node N0_1 is high. Because the second fifth transistor M5_2 is off, and due to the effect of the second first capacitor C1_2, the control electrode signal of the second third transistor M3_2 is kept low, causing the second third transistor M3_2 to conduct. This provides the high-level signal ck2_2 to the second driving node N0_2, making the signal of the second driving node N0_2 high. Because of the effect of the third first capacitor C1_3, the control electrode level of the third third transistor M3_3 is kept low, causing the third third transistor M3_3 to conduct. This provides the low-level signal ck2_3 to the third driving node N0_3, making the signal of the third driving node N0_3 low. Due to the bootstrap effect of the third capacitor C1_3, the control electrode level of the third transistor M3_3 can be further pulled low, so that the third transistor M3_3 can be fully turned on as much as possible. This allows the low-level signal of signal ck2_3 to be provided to the third drive node N0_3 with as little voltage loss as possible, making the signal of the third drive node N0_3 a low-level signal. Since the signal of the first drive selection signal terminal GX_1 is low, the first second transistor M2_1 is turned on, so that the high-level signal of the first drive node N0_1 is provided to the first drive output terminal GO_1, so that the first drive output terminal GO_1 outputs a high-level signal. Since the signal of the second drive selection signal terminal GX_2 is low, the second second transistor M2_2 is turned on, so that the high-level signal of the second drive node N0_2 is provided to the second drive output terminal GO_2, so that the second drive output terminal GO_2 outputs a high-level signal.Since the signal at the third drive selection signal terminal GX_3 is low, the third second transistor M2_3 is turned on, providing the low-level signal of the third drive node N0_3 to the third drive output terminal GO_3, causing GO_3 to output a low-level signal. Since the signal at the third cascade selection signal terminal JX_3 is low, and the signals at the first cascade selection signal terminal JX_1 and the second cascade selection signal terminal JX_2 are both high, the third first transistor M1_3 is turned on, while the first first transistor M1_1 and the second first transistor M1_2 are both turned off. The turned-on third first transistor M1_3 provides the low-level signal of the third drive node N0_3 to the cascade output terminal JO, causing JO to output a low-level signal.

[0134] During the first reset phase T13, signal ck1 is low, which turns on the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2, and the third fifth transistor M5_3. The turned-on sixth transistor M6 provides a high-level signal inp to the first node N1, making the signal at the first node N1 high. The eighth transistor M8 can be turned off under the control of the high-level signal at the first node N1. The turned-on seventh transistor M7 provides a low-level signal from the second reference signal terminal VREF2 to the second node N2, making the signal at the second node N2 low, thus turning on the first fourth transistor M4_1, the second fourth transistor M4_2, and the third fourth transistor M4_3. The turned-on first fourth transistor M4_1 provides a high-level signal from the first reference signal terminal VREF1 to the first driving node N0_1, making the signal at the first driving node N0_1 high. The second fourth transistor M4_2, when turned on, provides the high-level signal of the first reference signal terminal VREF1 to the second driving node N0_2, making the signal of the second driving node N0_2 a high-level signal. The third fourth transistor M4_3, when turned on, provides the high-level signal of the first reference signal terminal VREF1 to the third driving node N0_3, making the signal of the third driving node N0_3 a high-level signal. Since the signal of the second reference signal terminal VREF2 is a low-level signal, the first fifth transistor M5_1 can be turned on. Therefore, the first third transistor M3_1 can be turned off under the control of the high-level signal of the first node N1. Since the signal of the first node N1 is a high-level signal and the second fifth transistor M5_2 is turned on, the second third transistor M3_2 is turned off. Since the signal of the first node N1 is a high-level signal and the third fifth transistor M5_3 is turned on, the third third transistor M3_3 is turned off. Since the signal at the first drive selection signal terminal GX_1 is low, the first second transistor M2_1 is turned on to provide the high-level signal of the first drive node N0_1 to the first drive output terminal GO_1, causing GO_1 to output a high-level signal. Since the signal at the second drive selection signal terminal GX_2 is low, the second second transistor M2_2 is turned on to provide the high-level signal of the second drive node N0_2 to the second drive output terminal GO_2, causing GO_2 to output a high-level signal. Since the signal at the third drive selection signal terminal GX_3 is low, the third second transistor M2_3 is turned on to provide the high-level signal of the third drive node N0_3 to the third drive output terminal GO_3, causing GO_3 to output a high-level signal.Since the signal at the third cascade selection signal terminal JX_3 is low, and the signals at the first cascade selection signal terminal JX_1 and the second cascade selection signal terminal JX_2 are both high, the third first transistor M1_3 is turned on, while the first first transistor M1_1 and the second first transistor M1_2 are both turned off. The turned-on third first transistor M1_3 provides the high-level signal of the third drive node N0_3 to the cascade output terminal JO, causing the cascade output terminal JO to output a high-level signal.

[0135] It should be noted that the signals output from the first drive output terminal GO_1 to the third drive output terminal GO_3 are the gate scan signals. Figure 5a In this process, there is a hold phase between two adjacent stages. That is, when signals inp, ck1, ck2_1, ck2_2, and ck2_3 are all high, the shift register unit can proceed to the next stage after the signals stabilize. This creates a time interval between the low levels of the gate scan signals in two adjacent input gate lines. For example, this time interval can be 1H, where H represents the duration of the low level of a gate-loaded gate scan signal.

[0136] It should be noted that, due to the presence of the first capacitor C1_1, the second capacitor C1_2, and the third capacitor C1_3, if the second and third fifth transistors M5_2 are not used and instead conventional wires are replaced at these locations, then when the signal at the first drive output terminal GO_1 changes, the coupling effect between the first capacitor C1_1, the second capacitor C1_2, and the third capacitor C1_3 will cause voltage spikes in the output signals at the second drive output terminal GO_2 and the third drive output terminal GO_3. Similarly, when the signal at the second drive output terminal GO_2 changes, the coupling effect between the first capacitor C1_1, the second capacitor C1_2, and the third capacitor C1_3 will cause voltage spikes in the output signals at the first drive output terminal GO_1 and the third drive output terminal GO_3. Furthermore, when the signal at the third drive output terminal GO_3 changes, due to the coupling effect between the first capacitor C1_1, the second capacitor C1_2, and the third capacitor C1_3, voltage spikes will appear in the signals output from the second drive output terminal GO_2 and the first drive output terminal GO_1. Based on this, this embodiment of the present disclosure provides a second fifth transistor M5_2 and a third fifth transistor M5_3. By providing the second fifth transistor M5_2 and the third fifth transistor M5_3, the control electrodes of the second and third third transistors M3_2 and M3_3 can be isolated from other signals, thereby avoiding mutual interference between signals and improving output stability.

[0137] In other examples, the following is used... Figure 3 Taking the structure of the shift register unit shown as an example, combined with... Figure 5b The signal timing diagram shown illustrates some additional operational processes of the shift register unit provided in the embodiments of this disclosure during the first driving mode. Exemplarily, the following are mainly selected... Figure 5b The signal timing diagram shown includes a first input stage T11, a first output stage T12, and a first reset stage T13. The first output stage T12 may include three stages: T121, T122, and T123. Figure 3 The shift register unit shown is combined with Figure 5b The signal timing diagram shown represents the first input stages T11, T121, T122, and T123, and the first reset stage T13 during operation. Figure 3 The shift register unit shown is combined with Figure 5a The working processes of the first input stages T11, T121, T122, and T123 and the first reset stage T13 in the signal timing diagram shown are basically the same, and will not be described in detail here.

[0138] It should be noted that the signals output from the first drive output terminal GO_1 to the third drive output terminal GO_3 are the gate scan signals. Figure 5b In this configuration, no holding phase is provided between two adjacent phases, thus eliminating the aforementioned interval duration between the low levels of the gate scan signals in the two adjacent input gate lines. This allows the shift register unit to be combined with... Figure 5b The refresh time of the signal timing diagram shown for scanning the gate lines line by line is less than the time required for the shift register unit to combine. Figure 5a The signal timing diagram shown illustrates the scan time during line-by-line scanning of the gate lines, which can reduce the scan time of a display frame and thus increase the refresh rate.

[0139] It should be noted that, Figure 3 The shift register unit shown is combined with Figure 5a and Figure 5b The signal timing diagram shown allows for the output of a gate scan signal for each gate line during operation, enabling line-by-line scanning of these gate lines. Furthermore, Figure 5a The clock period of the signals ck2_1 to ck2_3 shown is 8H. Figure 5b The clock period of the signals ck2_1 to ck2_3 shown is 4H.

[0140] The driving method for the shift register unit provided in the embodiments of this disclosure, such as... Figure 6 As shown, in the second driving mode, a display frame may include a second input phase T21, a second output phase T22, and a second reset phase T23.

[0141] S210, in the second input stage T21, the first control circuit controls the signals of the first node and the second node according to the signals of the input signal terminal and the first clock signal terminal; the second control circuit controls the signals of at least two driving nodes according to the signals of the first node, the second node, and the second clock signal terminal; the cascade output circuit provides the signal of the m-th driving node among the at least two driving nodes to the cascade output terminal according to the cascade selection signal terminal; the drive output circuit provides the signal of the m-th driving node among the at least two driving nodes to the corresponding drive output terminal according to the drive selection signal terminal.

[0142] S220, in the second output stage T22, the second control circuit controls the signals of at least two drive nodes according to the signals of the first node and the second clock signal terminal; the cascade output circuit provides the signal of the m-th drive node among the at least two drive nodes to the cascade output terminal according to the cascade selection signal terminal; the drive output circuit provides the signal of the m-th drive node among the at least two drive nodes to the corresponding drive output terminal according to the drive selection signal terminal.

[0143] S230, in the second reset phase T23, the first control circuit controls the signals of the first node and the second node according to the signal of the first clock signal terminal; the second control circuit controls the signals of at least two driving nodes according to the signal of the second node; the cascade output circuit provides the signal of the m-th driving node among the at least two driving nodes to the cascade output terminal according to the cascade selection signal terminal; the drive output circuit provides the signal of the m-th driving node among the at least two driving nodes to the corresponding drive output terminal according to the drive selection signal terminal.

[0144] In some embodiments of this disclosure, taking a low effective level as an example, in the second driving mode, the signal at the cascade selection signal terminal corresponding to the m-th driving node can be a low-level signal, while the signals at the remaining cascade selection signal terminals can be high-level signals. Furthermore, the signal at the drive selection signal terminal corresponding to the m-th driving node can be a low-level signal, while the signals at the remaining drive selection signal terminals can be high-level signals.

[0145] In some embodiments of this disclosure, in the second driving mode, the first drive output terminal GO_1 of each stage shift register unit can be controlled to output a gate scan signal to the coupled gate line to achieve interlaced scanning.

[0146] In some examples, the following are... Figure 3 Taking the structure of the shift register unit shown as an example, combined with... Figure 7a The signal timing diagram shown illustrates the operation of the shift register unit provided in this embodiment of the present disclosure in the second driving mode. Exemplarily, the following are mainly selected: Figure 7aThe signal timing diagram shown includes the second input stage T21, the second output stage T22, and the second reset stage T23.

[0147] Furthermore, inp represents the input signal terminal INP, ck1 represents the first clock signal terminal CK1, ck2_1 represents the first second clock signal terminal CK2_1, ck2_2 represents the second second clock signal terminal CK2_2, ck2_3 represents the third second clock signal terminal CK2_3, n0_1 represents the first driver node N0_1, go_1 represents the first driver output terminal GO_1, and jo represents the cascade output terminal JO. Additionally, the first driver selection signal terminal GX_1 is low, while the second and third driver selection signals GX_2 and GX_3 are high. The first cascade selection signal terminal JX_1 is low, while the second and third cascade selection signals JX_2 and JX_3 are both high. Since both the second drive selection signal terminal GX_2 and the third drive selection signal terminal GX_3 are high-level signals, in this embodiment, both the second second transistor M2_2 and the third second transistor M2_3 are turned off. Also, since both the second cascade selection signal terminal JX_2 and the third cascade selection signal terminal JX_3 are high-level signals, in this embodiment, both the second first transistor M1_2 and the third first transistor M1_3 are turned off. Therefore, in this embodiment, only the signal of the first drive node N0_1 can be output to the cascade output terminal JO and the first drive output terminal GO_1, while the signals of the second drive node N0_2 and the third drive node N0_3 are not output. Therefore, the signal changes of the second driving node N0_2 and the third driving node N0_3 have no impact on this embodiment. Therefore, the changes of the signal of the first driving node N0_1 will be described below, and the changes of the signals of the second driving node N0_2 and the third driving node N0_3 will not be described again.

[0148] In the second input stage T21, signal ck1 is a low-level signal, which controls the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2, and the third fifth transistor M5_3 to all conduct. The conducting sixth transistor M6 provides the low-level signal inp to the first node N1, making the signal at the first node N1 a low-level signal. The eighth transistor M8, controlled by the low-level signal at the first node N1, can conduct to provide the low-level signal ck1 to the second node N2, making the signal at the second node N2 a low-level signal. The conducting seventh transistor M7 provides the low-level signal of the second reference signal terminal VREF2 to the second node N2, further making the signal at the second node N2 a low-level signal, thereby controlling the first fourth transistor M4_1, the second fourth transistor M4_2, and the third fourth transistor M4_3 to all conduct. The first fourth transistor M4_1, when turned on, provides a high-level signal from the first reference signal terminal VREF1 to the first driving node N0_1, making the signal of the first driving node N0_1 a high-level signal. Since the signal at the second reference signal terminal VREF2 is a low-level signal, the first fifth transistor M5_1 can be turned on. Therefore, the first third transistor M3_1 is turned on to provide a high-level signal from the signal ck2_1 to the first driving node N0_1, further making the signal of the first driving node N0_1 a high-level signal. Furthermore, the first second transistor M2_1, when turned on, provides a high-level signal from the first driving node N0_1 to the first driving output terminal GO_1, causing the first driving output terminal GO_1 to output a high-level signal. Finally, the first first transistor M1_1, when turned on, provides a high-level signal from the first driving node N0_1 to the cascaded output terminal JO, causing the cascaded output terminal JO to output a high-level signal.

[0149] In the second output stage T22, signal ck1 is high, which controls the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2, and the third fifth transistor M5_3 to be cut off. Therefore, the first node N1 is in a floating state. Due to the effect of the first capacitor C1_1, the signal of the first node N1 can be kept low. The eighth transistor M8 is turned on by the low signal of the first node N1 to provide the high level of signal ck1 to the second node N2, so that the signal of the second node N2 is high, which controls the first fourth transistor M4_1, the second fourth transistor M4_2, and the third fourth transistor M4_3 to be cut off. Since the signal of the second reference signal terminal VREF2 is low, the first fifth transistor M5_1 can be turned on. Therefore, the first third transistor M3_1 is turned on to provide the low level of signal ck2_1 to the first driving node N0_1, so that the signal of the first driving node N0_1 is low. Due to the bootstrap effect of the first capacitor C1_1, the voltage level of the first node N1 can be further pulled low, so that the first third transistor M3_1 can be fully turned on as much as possible. This allows the low-level signal of signal ck2_1 to be provided to the first driving node N0_1 with as little voltage loss as possible, making the signal of the first driving node N0_1 a low-level signal. Furthermore, the turned-on first second transistor M2_1 provides the low-level signal of the first driving node N0_1 to the first driving output terminal GO_1, causing the first driving output terminal GO_1 to output a low-level signal. Also, the turned-on first first transistor M1_1 provides the low-level signal of the first driving node N0_1 to the cascaded output terminal JO, causing the cascaded output terminal JO to output a low-level signal.

[0150] During the second reset phase T23, signal ck1 is low, which turns on the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2, and the third fifth transistor M5_3. The turned-on sixth transistor M6 provides a high-level signal inp to the first node N1, making the signal at the first node N1 high. The eighth transistor M8 can be turned off under the control of the high-level signal at the first node N1. The turned-on seventh transistor M7 provides a low-level signal from the second reference signal terminal VREF2 to the second node N2, making the signal at the second node N2 low, thus turning on the first fourth transistor M4_1, the second fourth transistor M4_2, and the third fourth transistor M4_3. The turned-on first fourth transistor M4_1 provides a high-level signal from the first reference signal terminal VREF1 to the first driving node N0_1, making the signal at the first driving node N0_1 high. Since the signal at the second reference signal terminal VREF2 is low, the first fifth transistor M5_1 can be turned on. Therefore, the first third transistor M3_1 can be turned off under the control of the high-level signal at the first node N1. Furthermore, the turned-on first second transistor M2_1 provides the high-level signal from the first drive node N0_1 to the first drive output terminal GO_1, causing GO_1 to output a high-level signal. Also, the turned-on first first transistor M1_1 provides the high-level signal from the first drive node N0_1 to the cascaded output terminal JO, causing JO to output a high-level signal.

[0151] It should be noted that the signal output from the first drive output terminal GO_1 is the gate scan signal. Figure 7a In this process, there is a hold phase between two adjacent stages. That is, when signals inp, ck1, ck2_1, ck2_2, and ck2_3 are all high, the shift register unit can enter the next stage after the signals stabilize. This ensures that there is a time interval between the low levels of the gate scan signals output by the first drive output terminal GO_1 of two adjacent shift register units. For example, this time interval can be 5H.

[0152] In other examples, the following is used... Figure 3 Taking the structure of the shift register unit shown as an example, combined with... Figure 7b The signal timing diagram shown illustrates some additional operational processes of the shift register unit provided in the embodiments of this disclosure in the second driving mode. Exemplarily, the following are mainly selected... Figure 7b The signal timing diagram shown includes the second input stage T21, the second output stage T22, and the second reset stage T23. Furthermore, Figure 3 The shift register unit shown is combined with Figure 7bThe signal timing diagram shown depicts the second input stage T21, the second output stage T22, and the second reset stage T23 during operation, which are related to... Figure 3 The shift register unit shown is combined with Figure 7a The working processes of the second input stage T21, the second output stage T22, and the second reset stage T23 in the signal timing diagram shown are basically the same, and will not be described in detail here.

[0153] It should be noted that the signal output from the first drive output terminal GO_1 is the gate scan signal. Figure 7b In this process, there is a hold phase between two adjacent stages. That is, when signals inp, ck1, ck2_1, ck2_2, and ck2_3 are all high, the shift register unit can enter the next stage after the signals stabilize. This ensures that there is a time interval between the low levels of the gate scan signals output by the first drive output terminal GO_1 of two adjacent shift register units. For example, this time interval can be 1H.

[0154] In some other examples, the following are... Figure 3 Taking the structure of the shift register unit shown as an example, combined with... Figure 7c The signal timing diagram shown illustrates some additional operational processes of the shift register unit provided in the embodiments of this disclosure in the second driving mode. Exemplarily, the following are mainly selected... Figure 7b The signal timing diagram shown includes the second input stage T21, the second output stage T22, and the second reset stage T23. Furthermore, Figure 3 The shift register unit shown is combined with Figure 7c The signal timing diagram shown depicts the second input stage T21, the second output stage T22, and the second reset stage T23 during operation, which are related to... Figure 3 The shift register unit shown is combined with Figure 7a The working processes of the second input stage T21, the second output stage T22, and the second reset stage T23 in the signal timing diagram shown are basically the same, and will not be described in detail here.

[0155] It should be noted that the signal output from the first drive output terminal GO_1 is the gate scan signal. Figure 7c In this configuration, no holding phase is set between two adjacent stages, thus ensuring that the low level of the gate scan signal output from the first drive output terminal GO_1 of two adjacent shift register units does not have the aforementioned interval duration. This allows the shift register units to combine Figure 7c The refresh time of the signal timing diagram shown for interlaced gate scanning is less than the time required to combine the shift register unit. Figure 7b The signal timing diagram shown illustrates the refresh time during interlaced scanning of the grid lines, which can reduce the scan time of a display frame and thus increase the refresh rate.

[0156] It should be noted that, Figure 3 The shift register unit shown is combined with Figures 7a to 7c When the signal timing diagram shown is in operation, a gate scan signal can be output to the gate line coupled to the first drive output terminal GO_1 of each stage shift register unit, so that only these gate lines are scanned. Furthermore, Figure 7a The clock period of the signals ck2_1 to ck2_3 shown is 12H. Figure 7b The clock period of the signals ck2_1 to ck2_3 shown is 4H. Figure 7c The clock period of the signals ck2_1 to ck2_3 shown is 2H.

[0157] In other embodiments of this disclosure, in the second driving mode, the second drive output terminal GO_2 of each stage shift register unit can be controlled to output a gate scan signal to the coupled gate line to achieve interlaced scanning.

[0158] In some examples, the following are... Figure 3 Taking the structure of the shift register unit shown as an example, combined with... Figure 8 The signal timing diagram shown illustrates the operation of the shift register unit provided in this embodiment of the present disclosure in the second driving mode. Exemplarily, the following are mainly selected: Figure 8 The signal timing diagram shown includes the second input stage T21, the second output stage T22, and the second reset stage T23.

[0159] Furthermore, inp represents the input signal terminal INP, ck1 represents the first clock signal terminal CK1, ck2_1 represents the first second clock signal terminal CK2_1, ck2_2 represents the second second clock signal terminal CK2_2, ck2_3 represents the third second clock signal terminal CK2_3, n0_2 represents the second driver node N0_2, go_2 represents the second driver output terminal GO_2, and jo represents the cascade output terminal JO. Additionally, the second driver selection signal terminal GX_2 is low, while the first and third driver selection signals GX_1 and GX_3 are high. The second cascade selection signal terminal JX_2 is low, while the first and third cascade selection signals JX_1 and JX_3 are both high. Since both the first drive selection signal terminal GX_1 and the third drive selection signal terminal GX_3 are high-level signals, in this embodiment, both the first second transistor M2_1 and the third second transistor M2_3 are turned off. Also, since both the first cascade selection signal terminal JX_1 and the third cascade selection signal terminal JX_3 are high-level signals, in this embodiment, both the first first transistor M1_1 and the third first transistor M1_3 are turned off. Therefore, in this embodiment, only the signal of the second drive node N0_2 can be output to the cascade output terminal JO and the second drive output terminal GO_2, while the signals of the first drive node N0_1 and the third drive node N0_3 are not output. Therefore, the signal changes of the first driving node N0_1 and the third driving node N0_3 have no impact on this embodiment. Therefore, the changes of the signal of the second driving node N0_2 will be described below, and the changes of the signals of the first driving node N0_1 and the third driving node N0_3 will not be described again.

[0160] In the second input stage T21, signal ck1 is a low-level signal, which controls the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2, and the third fifth transistor M5_3 to all conduct. The conducting sixth transistor M6 provides the low-level signal inp to the first node N1, making the signal at the first node N1 a low-level signal. The eighth transistor M8, controlled by the low-level signal at the first node N1, can conduct to provide the low-level signal ck1 to the second node N2, making the signal at the second node N2 a low-level signal. The conducting seventh transistor M7 provides the low-level signal of the second reference signal terminal VREF2 to the second node N2, further making the signal at the second node N2 a low-level signal, thereby controlling the first fourth transistor M4_1, the second fourth transistor M4_2, and the third fourth transistor M4_3 to all conduct. The second fourth transistor M4_2, when turned on, provides the high-level signal of the first reference signal terminal VREF1 to the second driving node N0_2, making the signal of the second driving node N0_2 a high-level signal. Since the signal of the second reference signal terminal VREF2 is a low-level signal, the first fifth transistor M5_1 can be turned on. Furthermore, the second fifth transistor M5_2 also turns on, causing the control electrode of the second third transistor M3_2 to be low. Therefore, the second third transistor M3_2 turns on, providing the high-level signal of signal ck2_2 to the second driving node N0_2, further making the signal of the second driving node N0_2 a high-level signal. Additionally, the second second transistor M2_2, when turned on, provides the high-level signal of the second driving node N0_2 to the second driving output terminal GO_2, causing the second driving output terminal GO_2 to output a high-level signal. Furthermore, the second conducting first transistor M1_2 provides the high-level signal of the second driving node N0_2 to the cascade output terminal JO, so that the cascade output terminal JO outputs a high-level signal.

[0161] In the second output stage T22, signal ck1 is a high-level signal, which can control the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2, and the third fifth transistor M5_3 to all be turned off. Therefore, the first node N1 is in a floating state. Due to the effect of the first capacitor C1_1, the signal of the first node N1 can be kept at a low level. The eighth transistor M8 can be turned on by the low-level signal of the first node N1 to provide the high level of signal ck1 to the second node N2, so that the signal of the second node N2 is a high-level signal, which controls the first fourth transistor M4_1, the second fourth transistor M4_2, and the third fourth transistor M4_3 to all be turned off. Due to the effect of the second first capacitor C1_2, the level of the control electrode of the second third transistor M3_2 can be kept at a low level. Therefore, the second third transistor M3_2 is turned on to provide the low-level signal ck2_2 to the second driving node N0_2, so that the signal of the second driving node N0_2 is a low-level signal. Due to the bootstrap effect of the second first capacitor C1_2, the control electrode level of the second third transistor M3_2 can be further pulled low, so that the second third transistor M3_2 can be fully turned on as much as possible. This allows the low-level signal of signal ck2_2 to be provided to the second drive node N0_2 with as little voltage loss as possible, making the signal of the second drive node N0_2 a low-level signal. Furthermore, the turned-on second second transistor M2_2 provides the low-level signal of the second drive node N0_2 to the second drive output terminal GO_2, causing the second drive output terminal GO_2 to output a low-level signal. And, the turned-on second first transistor M1_2 provides the low-level signal of the second drive node N0_2 to the cascaded output terminal JO, causing the cascaded output terminal JO to output a low-level signal.

[0162] During the second reset phase T23, signal ck1 is low, which turns on the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2, and the third fifth transistor M5_3. The turned-on sixth transistor M6 provides a high-level signal inp to the first node N1, making the signal at the first node N1 high. The eighth transistor M8 can be turned off under the control of the high-level signal at the first node N1. The turned-on seventh transistor M7 provides a low-level signal from the second reference signal terminal VREF2 to the second node N2, making the signal at the second node N2 low, thus turning on the first fourth transistor M4_1, the second fourth transistor M4_2, and the third fourth transistor M4_3. The turned-on second fourth transistor M4_2 provides a high-level signal from the first reference signal terminal VREF1 to the second driving node N0_2, making the signal at the second driving node N0_2 high. Since the signal at the first node N1 is high and the second fifth transistor M5_2 is turned on, the second third transistor M3_2 is turned off. Furthermore, the turned-on second second transistor M2_2 provides the high-level signal from the second driving node N0_2 to the second driving output terminal GO_2, causing GO_2 to output a high-level signal. Additionally, the turned-on second first transistor M1_2 provides the high-level signal from the second driving node N0_2 to the cascaded output terminal JO, causing JO to output a high-level signal.

[0163] It should be noted that the signal output from the second drive output terminal GO_2 is the gate scan signal. Figure 8 In this process, there is a hold phase between two adjacent stages. That is, when signals inp, ck1, ck2_1, ck2_2, and ck2_3 are all high, the shift register unit can enter the next stage after the signal stabilizes. This creates a time interval between the low levels of the gate scan signals output by the second drive output terminal GO_2 of two adjacent shift register units. For example, this time interval can be 5H. For example, when controlling the signal output by the second drive output terminal GO_2 of the shift register unit, the clock period of signals ck1, ck2_1, ck2_2, and ck2_3 can be reduced to decrease, or even eliminate, the time interval between the low levels of the gate scan signals output by the second drive output terminal GO_2 of two adjacent shift register units. This reduces the scan time of one display frame and thus increases the refresh rate.

[0164] In some embodiments of this disclosure, in the second driving mode, the third drive output terminal GO_3 of each stage shift register unit can be controlled to output a gate scan signal to the coupled gate line to achieve interlaced scanning.

[0165] In some examples, the following are... Figure 3 Taking the structure of the shift register unit shown as an example, combined with... Figure 9 The signal timing diagram shown illustrates the operation of the shift register unit provided in this embodiment of the present disclosure in the second driving mode. Exemplarily, the following are mainly selected: Figure 9 The signal timing diagram shown includes the second input stage T21, the second output stage T22, and the second reset stage T23.

[0166] Furthermore, inp represents the input signal terminal INP, ck1 represents the first clock signal terminal CK1, ck2_1 represents the first second clock signal terminal CK2_1, ck2_2 represents the second second clock signal terminal CK2_2, ck2_3 represents the third second clock signal terminal CK2_3, n0_2 represents the second driver node N0_2, go_2 represents the second driver output terminal GO_2, and jo represents the cascade output terminal JO. Additionally, the third driver selection signal terminal GX_3 is low, while the first and second driver selection signals GX_1 and GX_2 are high. The third cascade selection signal terminal JX_3 is low, while the first and second cascade selection signals JX_1 and JX_2 are both high. Since both the first drive selection signal terminal GX_1 and the second drive selection signal terminal GX_2 are high-level signals, in this embodiment, both the first second transistor M2_1 and the second second transistor M2_2 are turned off. Also, since both the first cascade selection signal terminal JX_1 and the second cascade selection signal terminal JX_2 are high-level signals, in this embodiment, both the first first transistor M1_1 and the second first transistor M1_2 are turned off. Therefore, in this embodiment, only the signal of the third drive node N0_3 can be output to the cascade output terminal JO and the third drive output terminal GO_3, while the signals of the first drive node N0_1 and the second drive node N0_2 are not output. Therefore, the signal changes of the first driving node N0_1 and the second driving node N0_2 have no impact on this embodiment. Therefore, the changes of the signal of the third driving node N0_3 will be described below, and the changes of the signals of the first driving node N0_1 and the second driving node N0_2 will not be described again.

[0167] In the second input stage T21, signal ck1 is a low-level signal, which controls the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2, and the third fifth transistor M5_3 to all conduct. The conducting sixth transistor M6 provides the low-level signal inp to the first node N1, making the signal at the first node N1 a low-level signal. The eighth transistor M8, controlled by the low-level signal at the first node N1, can conduct to provide the low-level signal ck1 to the second node N2, making the signal at the second node N2 a low-level signal. The conducting seventh transistor M7 provides the low-level signal of the second reference signal terminal VREF2 to the second node N2, further making the signal at the second node N2 a low-level signal, thereby controlling the first fourth transistor M4_1, the second fourth transistor M4_2, and the third fourth transistor M4_3 to all conduct. The third transistor M4_3, when turned on, provides the high-level signal from the first reference signal terminal VREF1 to the third driving node N0_3, making the signal of the third driving node N0_3 a high-level signal. Since the signal at the second reference signal terminal VREF2 is a low-level signal, the first transistor M5_1 can be turned on. Furthermore, the third transistor M5_3 also turns on, causing the control electrode of the third transistor M3_3 to be low. Therefore, the third transistor M3_3 turns on, providing the high-level signal ck2_3 to the third driving node N0_3, further making the signal of the third driving node N0_3 a high-level signal. Additionally, the third transistor M2_3, when turned on, provides the high-level signal from the third driving node N0_3 to the third driving output terminal GO_3, causing GO_3 to output a high-level signal. Furthermore, the third first transistor M1_3, which is turned on, provides the high-level signal of the third driving node N0_3 to the cascade output terminal JO, so that the cascade output terminal JO outputs a high-level signal.

[0168] In the second output stage T22, signal ck1 is a high-level signal, which controls the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2, and the third fifth transistor M5_3 to all be turned off. Therefore, the first node N1 is in a floating state. Due to the effect of the first capacitor C1_1, the signal of the first node N1 can be kept at a low level. The eighth transistor M8 is turned on by the low-level signal of the first node N1 to provide the high-level signal ck1 to the second node N2, so that the signal of the second node N2 is a high-level signal, which controls the first fourth transistor M4_1, the second fourth transistor M4_2, and the third fourth transistor M4_3 to all be turned off. Due to the effect of the third first capacitor C1_3, the level of the control electrode of the third third transistor M3_3 can be kept at a low level. Therefore, the third third transistor M3_3 is turned on to provide the low-level signal ck2_3 to the third driving node N0_3, so that the signal of the third driving node N0_3 is a low-level signal. Due to the bootstrap effect of the third first capacitor C1_3, the control electrode level of the third third transistor M3_3 can be further pulled low, so that the third third transistor M3_3 can be turned on as fully as possible. This allows the low-level signal of signal ck2_3 to be provided to the third driving node N0_3 with as little voltage loss as possible, making the signal of the third driving node N0_3 a low-level signal. Furthermore, the turned-on third second transistor M2_3 provides the low-level signal of the third driving node N0_3 to the third driving output terminal GO_3, causing the third driving output terminal GO_3 to output a low-level signal. And, the turned-on third first transistor M1_3 provides the low-level signal of the third driving node N0_3 to the cascaded output terminal JO, causing the cascaded output terminal JO to output a low-level signal.

[0169] During the second reset phase T23, signal ck1 is low, which turns on the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2, and the third fifth transistor M5_3. The turned-on sixth transistor M6 provides a high-level signal inp to the first node N1, making the signal at the first node N1 high. The eighth transistor M8 can be turned off under the control of the high-level signal at the first node N1. The turned-on seventh transistor M7 provides a low-level signal from the second reference signal terminal VREF2 to the second node N2, making the signal at the second node N2 low, thus turning on the first fourth transistor M4_1, the second fourth transistor M4_2, and the third fourth transistor M4_3. The turned-on third fourth transistor M4_3 provides a high-level signal from the first reference signal terminal VREF1 to the third driving node N0_3, making the signal at the third driving node N0_3 high. Since the signal at the first node N1 is high and the third fifth transistor M5_3 is turned on, the third third transistor M3_3 is turned off. Furthermore, the turned-on third second transistor M2_3 provides the high-level signal of the third driving node N0_3 to the third driving output terminal GO_3, causing GO_3 to output a high-level signal. Additionally, the turned-on third first transistor M1_3 provides the high-level signal of the third driving node N0_3 to the cascaded output terminal JO, causing JO to output a high-level signal.

[0170] It should be noted that the signal output from the third drive output terminal GO_3 is the gate scan signal. Figure 7a In this process, there is a hold phase between two adjacent stages. That is, when signals inp, ck1, ck2_1, ck2_2, and ck2_3 are all high, the shift register unit can enter the next stage after the signal stabilizes. This creates a time interval between the low levels of the gate scan signals output by the first drive output terminal GO_1 of two adjacent shift register units. For example, this time interval can be 5H. For example, when controlling the signal output by the third drive output terminal GO_3 of the shift register unit, the clock period of signals ck1, ck2_1, ck2_2, and ck2_3 can be reduced to decrease, or even eliminate, the time interval between the low levels of the gate scan signals output by the third drive output terminal GO_3 of two adjacent shift register units. This reduces the scan time of one display frame and thus increases the refresh rate.

[0171] This disclosure also provides a gate driving circuit, which may include multiple cascaded shift register units as described above. The input signal terminal of the first-stage shift register unit is coupled to the frame start signal line. Furthermore, in every two adjacent shift register units, the input signal terminal of the next-stage shift register unit is coupled to the cascaded output terminal of the previous-stage shift register unit. This allows the signal output from the cascaded output terminal of the previous-stage shift register unit to be input to the input signal terminal of the next-stage shift register unit, so that the cascaded signal terminal and the drive signal terminal of the next-stage shift register unit can output corresponding signals.

[0172] For example, with Figure 3 The structure of the shift register unit shown, and taking the first-stage shift register unit to the fourth-stage shift register unit as an example, are as follows: Figure 10 As shown, the input signal terminal INP of the first-stage shift register unit SR1 is coupled to the start-of-frame signal line STV. The input signal terminal INP of the second-stage shift register unit SR2 is coupled to the cascaded output terminal JO of the first-stage shift register unit SR1. The input signal terminal INP of the third-stage shift register unit SR3 is coupled to the cascaded output terminal JO of the second-stage shift register unit SR2. The input signal terminal INP of the fourth-stage shift register unit SR4 is coupled to the cascaded output terminal JO of the third-stage shift register unit SR3.

[0173] It should be noted that the specific structure of each shift register unit in the above gate drive circuit is the same as that of the shift register unit in this disclosure in terms of function and structure, and the repetition will not be repeated.

[0174] In some embodiments of this disclosure, the first reference signal terminal VREF1 of each shift register unit is coupled to the same first reference signal line, and the second reference signal terminal VREF2 of each shift register unit is coupled to the same second reference signal line.

[0175] This disclosure also provides a display device, such as... Figure 11 As shown, the display device may include a display panel 100 and a timing controller 200. The display panel 100 may include: a plurality of pixel units arranged in an array, a plurality of gate lines GA, a plurality of data lines DA intersecting and insulated from the gate lines GA, a gate driving circuit 110 coupled to each gate line GA, and a source driving circuit 120 coupled to each data line DA. Exemplarily, there may be two source driving circuits 120, with one source driving circuit 120 coupled to half of the data lines and the other source driving circuit 120 coupled to the other half. Of course, there may also be three, four, or more source driving circuits 120, which can be designed and determined according to the actual application requirements, and are not limited here.

[0176] In some embodiments of this disclosure, each pixel unit may include multiple sub-pixels (SPX). Exemplarily, a pixel unit may include multiple sub-pixels of different colors arranged along a column direction. For example, a pixel unit may include a first-color sub-pixel, a second-color sub-pixel, and a third-color sub-pixel arranged sequentially along a column direction. This allows a row of sub-pixels to have the same color. For example, they may be arranged in a repeating pattern of a first-color sub-pixel row, a second-color sub-pixel row, and a third-color sub-pixel row.

[0177] For example, the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel can be selected from red sub-pixels, green sub-pixels, and blue sub-pixels. For instance, if the first color sub-pixel is red, the second color sub-pixel is green, and the third color sub-pixel is blue, they can be arranged in a repeating pattern of red sub-pixel rows, green sub-pixel rows, and blue sub-pixel rows to achieve color display through red-green-blue-white color mixing. For example, as... Figure 12 As shown, the first row of sub-pixels consists of red sub-pixels R11 to R16, the second row consists of green sub-pixels G11 to G16, the third row consists of blue sub-pixels B11 to B16, the fourth row consists of red sub-pixels R21 to R26, the fifth row consists of green sub-pixels G21 to G26, the sixth row consists of blue sub-pixels B21 to B26, the seventh row consists of red sub-pixels R31 to R36, the eighth row consists of green sub-pixels G31 to G36, the ninth row consists of blue sub-pixels B31 to B36, the tenth row consists of red sub-pixels R41 to R46, the eleventh row consists of green sub-pixels G41 to G46, and the twelfth row consists of blue sub-pixels B41 to B46. Furthermore, red sub-pixels R11, green sub-pixels G11, and blue sub-pixels B11 form one pixel unit; red sub-pixels R12, green sub-pixels G12, and blue sub-pixels B12 form one pixel unit; red sub-pixels R13, green sub-pixels G13, and blue sub-pixels B13 form one pixel unit; red sub-pixels R14, green sub-pixels G14, and blue sub-pixels B14 form one pixel unit; red sub-pixels R15, green sub-pixels G15, and blue sub-pixels B15 form one pixel unit; and red sub-pixels R16, green sub-pixels G16, and blue sub-pixels B16 form one pixel unit. The rest follow the same logic and will not be elaborated further here.

[0178] It should be noted that in practical applications, the emission color of the sub-pixels in a pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0179] For example, see Figure 13As shown, each pixel SPX may include a transistor 11 and a pixel electrode 12. For example, a row of sub-pixels SPX is coupled to a gate line, and a column of sub-pixels SPX is coupled to a data line. For example, the gate of transistor 11 is coupled to the corresponding gate line, the source of transistor 11 is coupled to the corresponding data line, and the drain of transistor 11 is coupled to the pixel electrode 12. It should be noted that the pixel array structure of this disclosure can also be a dual-gate structure, that is, two gate lines are set between two adjacent rows of sub-pixels. This arrangement can reduce the number of data lines by half. That is, some adjacent columns of sub-pixels may contain data lines, while some adjacent columns of sub-pixels may not contain data lines. The specific sub-pixel arrangement structure and the arrangement of data lines and scan lines are not limited.

[0180] For example, the timing controller 200 can acquire display data of the image to be displayed in each display frame. The timing controller 200 can input a clock signal to the gate driving circuit 110, so that the gate driving circuit 110 can output a gate scan signal to the gate line GA according to the input clock signal, thereby scanning the gate line GA to control the transistors in the coupled sub-pixels to turn on. Additionally, the timing controller 200 inputs corresponding display data to the source driving circuit 120, so that the source driving circuit 120 can input a corresponding data voltage to the coupled data line DA according to the input display data, thereby inputting the voltage on the data line DA to the sub-pixel through the transistors turned on in the sub-pixel to charge the sub-pixel, thus charging each sub-pixel with the corresponding data voltage to achieve the image display function.

[0181] It should be noted that the display panel in this embodiment can be a liquid crystal display panel, an OLED display panel, etc., and is not limited thereto. Exemplarily, a liquid crystal display panel generally includes an upper substrate and a lower substrate of a cell, and liquid crystal molecules encapsulated between the upper and lower substrates. When displaying an image, a voltage difference exists between the data voltage applied to the pixel electrode of the sub-pixel and the common electrode voltage on the common electrode. This voltage difference forms an electric field, causing the liquid crystal molecules to deflect under the influence of this electric field. Because different intensities of electric fields cause different degrees of deflection of the liquid crystal molecules, the transmittance of the sub-pixels differs, enabling the sub-pixels (SPX) to achieve different grayscale brightness levels, thereby realizing image display.

[0182] In some embodiments of this disclosure, such as Figure 10 As shown, the gate drive circuit may include multiple cascaded shift register units. Each drive output terminal of each shift register unit in the gate drive circuit is coupled one-to-one with multiple gate lines, so that a gate scan signal can be output to the coupled gate through the drive output terminal. For example, with Figure 3 The structure of the shift register unit shown, and taking the first-stage shift register unit to the fourth-stage shift register unit as an example, are as follows: Figure 10 As shown, the first drive output terminal GO_1 of the first-stage shift register unit SR1 is coupled to gate line GA1, the second drive output terminal GO_2 of the first-stage shift register unit SR1 is coupled to gate line GA2, and the third drive output terminal GO_3 of the first-stage shift register unit SR1 is coupled to gate line GA3. The first drive output terminal GO_1 of the second-stage shift register unit SR2 is coupled to gate line GA4, the second drive output terminal GO_2 of the second-stage shift register unit SR2 is coupled to gate line GA5, and the third drive output terminal GO_3 of the second-stage shift register unit SR2 is coupled to gate line GA6. The first drive output terminal GO_1 of the third-stage shift register unit SR3 is coupled to gate line GA7, the second drive output terminal GO_2 of the third-stage shift register unit SR3 is coupled to gate line GA8, and the third drive output terminal GO_3 of the third-stage shift register unit SR3 is coupled to gate line GA9. The first drive output terminal GO_1 of the fourth-stage shift register unit SR4 is coupled to the gate line GA10, the second drive output terminal GO_2 of the fourth-stage shift register unit SR4 is coupled to the gate line GA11, and the third drive output terminal GO_3 of the fourth-stage shift register unit SR4 is coupled to the gate line GA12.

[0183] For example, an active level of the gate scan signal can control the transistor in the corresponding gate-coupled sub-pixel to turn on, and an inactive level can control the transistor in the corresponding gate-coupled sub-pixel to turn off. For example, combined with Figure 3 The shift register unit shown can have an effective gate scan signal level of low and an invalid gate scan signal level of high. Of course, it's also possible to have the effective gate scan signal level of high and the invalid gate scan signal level of low; this is not a limitation here.

[0184] In some embodiments of this disclosure, the display panel may further include multiple clock signal lines and frame start signal lines, and these multiple clock signal lines and frame start signal lines are respectively coupled to the gate driving circuit. This allows multiple clock signals to be input to the gate driving circuit via the clock signal lines. These multiple clock signals are respectively input to the first clock signal terminal CK1 and M second clock signal terminals of the shift register unit, thereby causing the shift register unit to output a gate scan signal to the coupled gate lines. For example, using... Figure 3 The structure of the shift register unit shown, and taking the first-stage shift register unit to the fourth-stage shift register unit as an example, are as follows: Figure 10As shown, the display panel may include four clock signal lines CKS1 to CKS4 and one frame start signal line STVS_1. The four clock signal lines CKS1 to CKS4 and the frame start signal line STVS_1 are coupled to the gate drive circuit 110. Furthermore, CKS1 serves as the first clock signal line, CKS2 as the second clock signal line, CKS3 as the third clock signal line, and CKS4 as the fourth clock signal line. Furthermore, the first clock signal terminal CK1 of the 4k_3 level shift register unit, the first second clock signal terminal CK2_1 of the 4k_2 level shift register unit, the second second clock signal terminal CK2_2 of the 4k_1 level shift register unit, and the third second clock signal terminal CK2_3 of the 4k level shift register unit are all coupled to the first clock signal line; the first second clock signal terminal CK2_1 of the 4k_3 level shift register unit, the second second clock signal terminal CK2_2 of the 4k_2 level shift register unit, the third second clock signal terminal CK2_3 of the 4k_1 level shift register unit, and the first clock signal terminal CK1 of the 4k level shift register unit are all coupled to the second clock signal line; the 4k The second second clock signal terminal CK2_2 of the _3-level shift register unit, the third second clock signal terminal CK2_3 of the 4k_2-level shift register unit, the first clock signal terminal CK1 of the 4k_1-level shift register unit, and the first second clock signal terminal CK2_1 of the 4k-level shift register unit are all coupled to the third clock signal line; the third second clock signal terminal CK2_3 of the 4k_3-level shift register unit, the first clock signal terminal CK1 of the 4k_2-level shift register unit, the first second clock signal terminal CK2_1 of the 4k_1-level shift register unit, and the second second clock signal terminal CK2_2 of the 4k-level shift register unit are all coupled to the third clock signal line; k is an integer greater than 0.

[0185] It should be noted that, Figure 10 This example uses 4 clock signal lines and 1 frame start signal line. In practical applications, the specific number of clock signal lines and frame start signal lines can be determined according to the actual application requirements and is not limited here. For example, it can also be other numbers of clock signal lines and frame start signal lines that are multiples of 2, such as 2, 4, 6, 10, 12, etc.

[0186] In some embodiments of this disclosure, the display panel may further include multiple cascaded select signal lines and multiple drive select signal lines, and the cascaded select signal terminal of the shift register unit in the gate drive circuit is coupled to the cascaded select signal lines, and the drive select signal terminal of the shift register unit in the gate drive circuit is coupled to the drive select signal lines. For example, using... Figure 3The structure of the shift register unit shown, and taking the first-stage shift register unit to the fourth-stage shift register unit as an example, are as follows: Figure 10 As shown, the display panel may include three cascaded selection signal lines JXS1 to JXS3 and three drive selection signal lines GXS1 to GXS3. The three cascaded selection signal lines JXS1 to JXS3 are respectively coupled to the cascaded selection signal terminals of the shift register units in the gate drive circuit 110. Similarly, the three drive selection signal lines GXS1 to GXS3 are respectively coupled to the drive selection signal terminals of the shift register units in the gate drive circuit 110. JXS1 serves as the first cascaded selection signal line, JXS2 as the second cascaded selection signal line, and JXS3 as the third cascaded selection signal line. GXS1 serves as the first drive selection signal line, GXS2 as the second drive selection signal line, and GXS3 as the third drive selection signal line. Furthermore, the first cascade selection signal terminal JX_1 of each shift register unit is coupled to the first cascade selection signal line, the second cascade selection signal terminal JX_2 of each shift register unit is coupled to the second cascade selection signal line, and the third cascade selection signal terminal JX_3 of each shift register unit is coupled to the third cascade selection signal line. Also, the first drive selection signal terminal GX_1 of each shift register unit is coupled to the first drive selection signal line, the second drive selection signal terminal GX_2 of each shift register unit is coupled to the second drive selection signal line, and the third drive selection signal terminal GX_3 of each shift register unit is coupled to the third drive selection signal line.

[0187] It should be noted that, Figure 10 This explanation uses only three cascaded selection signal lines JXS1 to JXS3 and three drive selection signal lines GXS1 to GXS3 as an example. In practical applications, the specific number of cascaded selection signal lines and drive selection signal lines can be determined according to the actual application requirements, and is not limited here.

[0188] In some embodiments of this disclosure, a row of pixel units can correspond to a shift register unit in the gate driving circuit. Furthermore, the m-th drive output of each shift register unit is coupled to the gate line corresponding to the same color sub-pixel. For example, using... Figure 3 The structure of the shift register unit shown, and taking the first-stage shift register unit to the fourth-stage shift register unit as an example, are as follows: Figure 10 and Figure 12As shown, the first drive output terminal GO_1 of the first-stage shift register unit to the fourth-stage shift register unit is coupled to the gate lines GA1, GA4, GA7, and GA10 corresponding to the red sub-pixels. The second drive output terminal GO_2 of the first-stage shift register unit to the fourth-stage shift register unit is coupled to the gate lines GA2, GA5, GA8, and GA11 corresponding to the green sub-pixels. The third drive output terminal GO_3 of the first-stage shift register unit to the fourth-stage shift register unit is coupled to the gate lines GA3, GA6, GA9, and GA12 corresponding to the red sub-pixels.

[0189] In some embodiments of this disclosure, a gate drive circuit may be provided only at the first end of the gate line. Alternatively, a gate drive circuit may be provided only at the second end of the gate line. Gate drive circuits may also be provided at both the first and second ends of the gate line, so that shift register units coupled to the same gate line simultaneously input the effective level of the gate scan signal to the gate line. For example, as... Figure 11 As shown, a gate drive circuit is placed on the left side of multiple gate lines. Alternatively, as... Figure 13 As shown, a gate drive circuit is set on the left and right sides of multiple gate lines respectively.

[0190] This disclosure also provides a control method for a display device, such as... Figure 14 As shown, it may include the following steps:

[0191] S10. In the first driving mode, in a display frame, different first clock signals are loaded onto each clock signal line, gate turn-on signals are loaded onto each driving selection signal line, gate turn-on signals are loaded onto the cascade selection signal line coupled to the Mth driving output circuit, and gate turn-off signals are loaded onto the remaining cascade selection signal lines. This controls each shift register unit to work sequentially, providing the signal of the Mth driving node among at least two driving nodes to the cascade output terminal, and providing the signal of each driving node among at least two driving nodes to the driving output terminal corresponding to each driving node, and scanning multiple gate lines line by line.

[0192] In some examples, the gate drive circuit outputs a gate scan signal to the coupled gate line via a drive output terminal. The effective level of this gate scan signal controls the transistor coupled to the corresponding gate line to turn on, while the ineffective level controls the transistor coupled to turn off. For example, the effective level of the gate scan signal can be high, and the ineffective level can be low. Alternatively, the effective level of the gate scan signal can also be low, and the ineffective level can be high; this is not limited to this.

[0193] Optionally, the effective level of the first clock signal is used to output the effective level of the gate scan signal for scanning the gate lines. Optionally, the duration of the effective level of the first clock signal is the same. Optionally, the clock period of the first clock signal is the same.

[0194] For example, with Figure 3 The structure of the shift register unit shown, and taking the first-level shift register unit to the fourth-level shift register unit as an example, in the first driving mode, Figure 10 The signal timing diagram corresponding to the gate drive circuit shown is as follows: Figure 15 As shown in the diagram. Here, cks1_1 represents the first clock signal input to the first clock signal line CKS1, cks2_1 represents the first clock signal input to the second clock signal line CKS2, cks3_1 represents the first clock signal input to the third clock signal line CKS3, cks4_1 represents the first clock signal input to the fourth clock signal line CKS4, and stvs_1 represents the frame start signal input to the frame start signal line STVS_1. Furthermore, signal ga1_1 represents the gate scan signal output by the gate drive circuit 110 to gate line GA1, signal ga2_1 represents the gate scan signal output by the gate drive circuit 110 to gate line GA2, ..., signal ga10_1 represents the gate scan signal output by the gate drive circuit 110 to gate line GA10, signal ga11_1 represents the gate scan signal output by the gate drive circuit 110 to gate line GA11, and signal ga12_1 represents the gate scan signal output by the gate drive circuit 110 to gate line GA12. Furthermore, a low-level gate-on signal is applied to the first drive selection signal line to turn on the first second transistor M2_1 in each shift register unit. A low-level gate-on signal is applied to the second drive selection signal line to turn on the second second transistor M2_2 in each shift register unit. A low-level gate-on signal is applied to the third drive selection signal line to turn on the third second transistor M2_3 in each shift register unit. Additionally, a high-level gate-off signal is applied to the first cascade selection signal line to turn off the first first transistor M1_1 in each shift register unit. A high-level gate-off signal is applied to the second drive selection signal line to turn off the second first transistor M1_2 in each shift register unit. A low-level gate-on signal is applied to the third drive selection signal line to turn on the third first transistor M1_3 in each shift register unit. Of course, the gate turn-on signal can also be a high-level signal, and the gate turn-off signal can also be a low-level signal; there are no restrictions here.

[0195] Furthermore, taking a low level as the effective level of the gate scan signal as an example, the signal stvs_1 is input to the input signal terminal INP of the shift register unit SR1. The shift register unit SR1 outputs the first low level of the first clock signal cks2_1 to the gate line GA1 through the first drive output terminal GO_1 to generate the low level in the gate scan signal ga1_1. The shift register unit SR1 outputs the first low level of the first clock signal cks3_1 to the gate line GA2 through the second drive output terminal GO_2 to generate the low level in the gate scan signal ga2_1. The shift register unit SR1 outputs the first low level of the first clock signal cks4_1 to the gate line GA3 through the third drive output terminal GO_3 to generate the low level in the gate scan signal ga3_1. The gate scan signal ga3_1 is input to the input signal terminal INP of shift register unit SR2. Shift register unit SR2 outputs the second low level of the first clock signal cks1_1 to gate line GA4 through the first drive output terminal GO_1 to generate the low level in the gate scan signal ga4_1. Shift register unit SR2 outputs the second low level of the first clock signal cks2_1 to gate line GA5 through the second drive output terminal GO_2 to generate the low level in the gate scan signal ga5_1. Shift register unit SR2 outputs the second low level of the first clock signal cks3_1 to gate line GA6 through the third drive output terminal GO_3 to generate the low level in the gate scan signal ga6_1. The gate scan signal ga6_1 is input to the input signal terminal INP of shift register unit SR3. Shift register unit SR3 outputs the second low level of the first clock signal cks4_1 to gate line GA7 through the first drive output terminal GO_1 to generate the low level in the gate scan signal ga7_1. Shift register unit SR3 outputs the third low level of the first clock signal cks1_1 to gate line GA8 through the second drive output terminal GO_2 to generate the low level in the gate scan signal ga8_1. Shift register unit SR3 outputs the third low level of the first clock signal cks2_1 to gate line GA9 through the third drive output terminal GO_3 to generate the low level in the gate scan signal ga9_1. The gate scan signal ga9_1 is input to the input signal terminal INP of the shift register unit SR4. The shift register unit SR4 outputs the third low level of the first clock signal cks3_1 to the gate line GA10 through the first drive output terminal GO_1 to generate the low level in the gate scan signal ga10_1. The shift register unit SR4 outputs the third low level of the first clock signal cks4_1 to the gate line GA11 through the second drive output terminal GO_2 to generate the low level in the gate scan signal ga11_1.The shift register unit SR4 outputs the fourth low level of the first clock signal cks1_1 to the gate line GA12 through the third drive output terminal GO_3 to generate the low level in the gate scan signal ga12_1.

[0196] And, as Figure 15 As shown, the low-level duration of each of the first clock signals cks1_1 to cks4_1 is the same, and the clock period ts11 of each of the first clock signals cks1_1 to cks4_1 is the same. Furthermore, the low level of each of the first clock signals cks1_1 to cks4_1 can be considered its valid level, and the high level its invalid level. Of course, when the shift register unit outputs the high level of the first clock signal to generate the high-level signal controlling the transistor's conduction in the gate scan signal, the high level of the first clock signal can be considered its valid level, and the low level its invalid level.

[0197] Optionally, such as Figure 15 As shown, the clock period ts11 of each of the first clock signals cks1_1 to cks4_1 can be 8H. Alternatively, the clock period of each first clock signal can be 4H. In practical applications, the specific value of the clock period of each first clock signal can be determined according to the actual application requirements, and is not limited here.

[0198] S20. In the second driving mode, within a display frame, a second clock signal is applied to each clock signal line, a gate-on signal is applied to the drive selection signal line coupled to the m-th cascaded output circuit, and a gate-off signal is applied to the remaining drive selection signal lines. A gate-on signal is applied to the cascaded selection signal line coupled to the m-th drive output circuit, and a gate-off signal is applied to the remaining cascaded selection signal lines. This controls the sequential operation of each shift register unit, providing the signal of the m-th drive node (among at least two drive nodes) to the cascaded output terminal, and providing the signal of the m-th drive node to the corresponding drive output terminal, thus performing interlaced scanning of multiple gate lines. Optionally, the clock period of the second clock signal is different from the clock period of the first clock signal.

[0199] In some embodiments of this disclosure, M=3, and step S20 may include: in the second driving mode, loading the same second clock signal onto the first clock signal line and the third clock signal line, and loading the same second clock signal onto the second clock signal line and the fourth clock signal line; loading a gate-on signal onto the first cascade selection signal line, and loading a gate-off signal onto both the second cascade selection signal line and the third cascade selection signal line; loading a gate-on signal onto the first driving selection signal line, and loading a gate-off signal onto both the second driving selection signal line and the third driving selection signal line; controlling each shift register unit to work sequentially; providing the signal of the first driving node to the cascade output terminal; and providing the signal of the first driving node to the first driving output terminal; and scanning the gate line coupled to each first color sub-pixel row; wherein the second clock signals loaded onto the first clock signal line and the second clock signal line are different.

[0200] For example, the first color sub-pixel row can be a red sub-pixel row. In the second driving mode, the same second clock signal is applied to the first and third clock signal lines, and the same second clock signal is applied to the second and fourth clock signal lines. A gate-on signal is applied to the first cascade selection signal line, and a gate-off signal is applied to both the second and third cascade selection signal lines. A gate-on signal is applied to the first drive selection signal line, and a gate-off signal is applied to both the second and third drive selection signal lines. This controls the sequential operation of each shift register unit, providing the signal of the first drive node to the cascade output terminal and the signal of the first drive node to the first drive output terminal, scanning the gate lines coupled to each red sub-pixel row. In other words, in the second driving mode, within a display frame, only the gates coupled to the red sub-pixel rows can be output with gate scan signals, thus inputting data voltage only to the red sub-pixels.

[0201] Optionally, the clock period of the second clock signal can be no greater than 3 / 2 of the clock period of the first clock signal. For example, the clock period of the second clock signal can be equal to 3 / 2 of the clock period of the first clock signal. Figure 15 and Figure 16a As shown, the clock period ts11 of the first clock signals cks1_1 to cks4_1 is 8H, and the clock period ts21 of the second clock signals cks1_2 to cks4_2 can be 12H. Alternatively, the clock period of the second clock signal can be equal to half the clock period of the first clock signal. For example, as... Figure 15 and Figure 16bAs shown, the clock period ts11 of the first clock signals cks1_1 to cks4_1 is 8H, and the clock period ts22 of the second clock signals cks1_2 to cks4_2 can be 4H. The clock period of the first clock signal is 4H, and the clock period of the second clock signal can be 2H. Alternatively, the clock period of the second clock signal can be equal to 1 / 4 of the clock period of the first clock signal. For example, as... Figure 15 and Figure 16c As shown, the clock period ts11 of the first clock signal cks1_1~cks4_1 is 8H, and the clock period ts23 of the second clock signal cks1_2~cks4_2 can be 2H.

[0202] Of course, in practical applications, the relationship between the clock period of the second clock signal and the clock period of the first clock signal when scanning only the gate line coupled to the first color sub-pixel row in a display frame can be determined according to the needs of the actual application, and is not limited here.

[0203] For example, with Figure 3 The structure of the shift register unit shown, and taking the first to fourth level shift register units as examples, in the second driving mode, when scanning the row-coupled gate lines of each red sub-pixel, the corresponding signal timing diagram is as follows: Figures 16a to 16c As shown in the diagram. Here, cks1_2 represents the second clock signal input to the first clock signal line CKS1, cks2_2 represents the second clock signal input to the second clock signal line CKS2, cks3_2 represents the second clock signal input to the third clock signal line CKS3, cks4_2 represents the second clock signal input to the fourth clock signal line CKS4, and stvs_2 represents the frame start signal input to the frame start signal line STVS_2. Furthermore, signal ga1_2 represents the gate scan signal output by the gate drive circuit 110 to the gate line GA1, signal ga4_2 represents the gate scan signal output by the gate drive circuit 110 to the gate line GA4, ..., signal ga7_2 represents the gate scan signal output by the gate drive circuit 110 to the gate line GA7, and signal ga10_2 represents the gate scan signal output by the gate drive circuit 110 to the gate line GA10.

[0204] Furthermore, a low-level gate-on signal is applied to the first drive selection signal line to turn on the first second transistor M2_1 in each shift register unit. A high-level gate-off signal is applied to the second drive selection signal line to turn off the second second transistor M2_2 in each shift register unit. A high-level gate-off signal is applied to the third drive selection signal line to turn off the third second transistor M2_3 in each shift register unit. Also, a low-level gate-on signal is applied to the first cascade selection signal line to turn on the first first transistor M1_1 in each shift register unit. A high-level gate-off signal is applied to the second drive selection signal line to turn off the second first transistor M1_2 in each shift register unit. A high-level gate-off signal is applied to the third drive selection signal line to turn off the third first transistor M1_3 in each shift register unit. Of course, the gate-on signal can also be a high-level signal, and the gate-off signal can also be a low-level signal; this is not limited here.

[0205] Furthermore, taking a low level as the effective level of the gate scan signal as an example, signal stvs_2 is input to the input signal terminal INP of shift register unit SR1. Shift register unit SR1 outputs the first low level of the second clock signal cks2_2 to gate line GA1 through the first drive output terminal GO_1 to generate the low level in gate scan signal ga1_2. Gate scan signal ga1_2 is input to the input signal terminal INP of shift register unit SR2. Shift register unit SR2 outputs the second low level of the second clock signal cks1_2 to gate line GA4 through the first drive output terminal GO_1 to generate the low level in gate scan signal ga4_2. Gate scan signal ga4_2 is input to the input signal terminal INP of shift register unit SR3. Shift register unit SR3 outputs the second low level of the second clock signal cks4_2 to gate line GA7 through the first drive output terminal GO_1 to generate the low level in gate scan signal ga7_2. The gate scan signal ga7_2 is input to the input signal terminal INP of the shift register unit SR4. The shift register unit SR4 outputs the third low level of the second clock signal cks3_2 to the gate line GA10 through the first drive output terminal GO_1 to generate the low level in the gate scan signal ga10_2.

[0206] Optionally, the low-level duration of each of the second clock signals cks1_2 to cks4_2 is the same, and the clock period of each of the second clock signals cks1_2 to cks4_2 is the same. Furthermore, the low level of the second clock signals cks1_2 to cks4_2 can be their valid level, and the high level their invalid level. Of course, when the shift register unit outputs the high level of the second clock signal to generate the high-level signal controlling the transistor's conduction in the gate scan signal, the high level of the second clock signal can be used as its valid level, and the low level as its invalid level.

[0207] Optionally, such as Figure 16a As shown, the clock period ts21 of each of the second clock signals cks1_2 to cks4_2 can be 12H. Figure 16b As shown, the clock period ts22 of each of the second clock signals cks1_2 to cks4_2 can be 4H. Figure 16c As shown, the clock period ts23 of each of the second clock signals cks1_2 to cks4_2 can be 2H. In this embodiment of the present disclosure, by reducing the clock period of the second clock signal, the scanning time of the gate line coupled to the red sub-pixel can be reduced, thereby reducing the scanning time of a display frame and thus increasing the refresh rate.

[0208] In other embodiments of this disclosure, M=3, and step S20 may include: in the second driving mode, loading different second clock signals onto the first to fourth clock signal lines respectively, loading a gate-on signal onto the second cascade selection signal line, and loading a gate-off signal onto both the first and third cascade selection signal lines, loading a gate-on signal onto the second driving selection signal line, and loading a gate-off signal onto both the first and third driving selection signal lines, controlling each shift register unit to work sequentially, providing the signal of the second driving node to the cascade output terminal, and providing the signal of the second driving node to the second driving output terminal, and scanning the gate line coupled to each second color sub-pixel row; wherein the second clock signal has two different clock cycles.

[0209] For example, the second color sub-pixel row can be a green sub-pixel row. In the second driving mode, different second clock signals are applied to the first to fourth clock signal lines respectively. A gate-on signal is applied to the second cascade selection signal line, and a gate-off signal is applied to both the first and third cascade selection signal lines. A gate-on signal is applied to the second driving selection signal line, and a gate-off signal is applied to both the first and third driving selection signal lines. This controls the sequential operation of each shift register unit, providing the signal of the second driving node to the cascade output terminal and the signal of the second driving node to the second driving output terminal, scanning the gate lines coupled to each green sub-pixel row. In other words, in the second driving mode, within a display frame, only the gates coupled to the green sub-pixel rows can be output with gate scan signals, thus inputting data voltage only to the green sub-pixels.

[0210] Optionally, the two different clock cycles may include a first clock cycle and a second clock cycle. The first clock cycle is no greater than 3 / 4 of the clock cycle of the first clock signal, and the second clock cycle is no greater than 9 / 4 of the clock cycle of the first clock signal.

[0211] For example, the first clock period can be equal to 3 / 4 of the clock period of the first clock signal, and the second clock period can be equal to 9 / 4 of the clock period of the first clock signal. For example, as... Figure 15 and Figure 17a As shown, the clock period ts11 of the first clock signals cks1_1 to cks4_1 is 8H, the second clock period ts31_2 of the second clock signals cks1_2 to cks4_2 can be 18H, and the first clock period ts31_1 is 6H. Alternatively, the first clock period can be equal to 2 / 3 of the clock period of the first clock signal, and the second clock period can be equal to 3 / 2 of the clock period of the first clock signal. For example, as... Figure 15 and Figure 17b As shown, the clock period ts11 of the first clock signal cks1_1~cks4_1 is 8H, the second clock period ts32_2 of the second clock signal cks1_2~cks4_2 can be 12H, and the first clock period ts32_1 is 4H.

[0212] Of course, in practical applications, when only the grid lines coupled to the second color sub-pixel row are scanned in a display frame, the relationship between the first clock period and the second clock period of the loaded second clock signal and the clock period of the first clock signal can be determined according to the needs of the actual application, and is not limited here.

[0213] For example, with Figure 3The structure of the shift register unit shown, and taking the first to fourth level shift register units as examples, in the second driving mode, when scanning the row-coupled gate lines of each green sub-pixel, the corresponding signal timing diagram is as follows: Figure 17a and Figure 17b As shown in the diagram. Here, cks1_2 represents the second clock signal input to the first clock signal line CKS1, cks2_2 represents the second clock signal input to the second clock signal line CKS2, cks3_2 represents the second clock signal input to the third clock signal line CKS3, cks4_2 represents the second clock signal input to the fourth clock signal line CKS4, and stvs_2 represents the frame start signal input to the frame start signal line STVS_2. Furthermore, signal ga2_2 represents the gate scan signal output by the gate drive circuit 110 to gate line GA2, signal ga5_2 represents the gate scan signal output by the gate drive circuit 110 to gate line GA5, ..., signal ga8_2 represents the gate scan signal output by the gate drive circuit 110 to gate line GA8, and signal ga11_2 represents the gate scan signal output by the gate drive circuit 110 to gate line GA11.

[0214] Furthermore, a low-level gate-on signal is applied to the second drive selection signal line to turn on the second second transistor M2_2 in each shift register unit. A high-level gate-off signal is applied to the first drive selection signal line to turn off the first second transistor M2_1 in each shift register unit. A high-level gate-off signal is applied to the third drive selection signal line to turn off the third second transistor M2_3 in each shift register unit. Additionally, a low-level gate-on signal is applied to the second cascade selection signal line to turn on the second first transistor M1_2 in each shift register unit. A high-level gate-off signal is applied to the first drive selection signal line to turn off the first first transistor M1_1 in each shift register unit. A high-level gate-off signal is applied to the third drive selection signal line to turn off the third first transistor M1_3 in each shift register unit. Of course, the gate-on signal can also be a high-level signal, and the gate-off signal can also be a low-level signal; this is not limited here.

[0215] Furthermore, taking a low level as the effective level of the gate scan signal as an example, signal stvs_2 is input to the input signal terminal INP of shift register unit SR1. Shift register unit SR1 outputs the first low level of the second clock signal cks3_2 to gate line GA2 through the second drive output terminal GO_2 to generate the low level in gate scan signal ga2_2. Gate scan signal ga2_2 is input to the input signal terminal INP of shift register unit SR2. Shift register unit SR2 outputs the second low level of the second clock signal cks2_2 to gate line GA5 through the second drive output terminal GO_2 to generate the low level in gate scan signal ga5_2. Gate scan signal ga5_2 is input to the input signal terminal INP of shift register unit SR3. Shift register unit SR3 outputs the second low level of the second clock signal cks1_2 to gate line GA8 through the second drive output terminal GO_2 to generate the low level in gate scan signal ga8_2. The gate scan signal ga8_2 is input to the input signal terminal INP of the shift register unit SR4. The shift register unit SR4 outputs the third low level of the second clock signal cks4_2 to the gate line GA11 through the second drive output terminal GO_2 to generate the low level in the gate scan signal ga11_2.

[0216] Optionally, the low-level duration of each of the second clock signals cks1_2 to cks4_2 is the same, and the first clock period and the second clock period of each of the second clock signals cks1_2 to cks4_2 are the same. Furthermore, the low level of the second clock signals cks1_2 to cks4_2 can be their valid level, and the high level their invalid level. Of course, when the shift register unit outputs the high level of the second clock signal to generate the high-level signal controlling the transistor's conduction in the gate scan signal, the high level of the second clock signal can be used as its valid level, and the low level as its invalid level.

[0217] Optionally, such as Figure 17a As shown, the second clock period ts31_2 of each of the second clock signals cks1_2 to cks4_2 can be 18H, and the first clock period ts31_1 can be 6H. For example... Figure 17b As shown, the second clock period ts32_2 of each of the second clock signals cks1_2 to cks4_2 can be 12H, and the first clock period ts32_1 can be 4H. In this embodiment of the present disclosure, by reducing the first clock period and the second clock period, the scanning time of the gate line coupled to the green sub-pixel can be reduced, thereby reducing the scanning time of a display frame and thus increasing the refresh rate.

[0218] In some embodiments of this disclosure, M=3, and step S20 may include: in the second driving mode, loading different second clock signals onto the first to fourth clock signal lines respectively, loading a gate-on signal onto the third cascade selection signal line, and loading a gate-off signal onto both the first and second cascade selection signal lines, loading a gate-on signal onto the third driving selection signal line, and loading a gate-off signal onto both the first and second driving selection signal lines, controlling each shift register unit to work sequentially, providing the signal of the third driving node to the cascade output terminal, and providing the signal of the third driving node to the third driving output terminal, and scanning the gate line coupled to each third color sub-pixel row.

[0219] For example, the third color sub-pixel row can be a blue sub-pixel row. In the second driving mode, different second clock signals are applied to the first to fourth clock signal lines respectively. A gate-on signal is applied to the third cascade selection signal line, and a gate-off signal is applied to both the first and second cascade selection signal lines. A gate-on signal is applied to the third drive selection signal line, and a gate-off signal is applied to both the first and second drive selection signal lines. This controls the sequential operation of each shift register unit, providing the signal of the third drive node to the cascade output terminal and the signal of the third drive node to the third drive output terminal, thus scanning the gate lines coupled to each third color sub-pixel row. In other words, in the second driving mode, within a display frame, only the gates coupled to the blue sub-pixel row can be output with gate scan signals, thereby inputting data voltage only to the blue sub-pixels.

[0220] Optionally, the second clock period can be no greater than three times the clock period of the first clock signal. For example, the second clock period can be equal to three times the clock period of the first clock signal. Figure 15 and Figure 18a As shown, the clock period ts11 of the first clock signals cks1_1 to cks4_1 is 8H, and the clock period ts41 of the second clock signals cks1_2 to cks4_2 can be 24H. Alternatively, the second clock period can be twice the clock period of the first clock signal. For example, the clock period of the first clock signals cks1_1 to cks4_1 is 8H, and the clock period of the second clock signals cks1_2 to cks4_2 can be 16H. Alternatively, the second clock period can be half the clock period of the first clock signal. For example, as... Figure 15 and Figure 18b As shown, the clock period ts11 of the first clock signal cks1_1~cks4_1 is 8H, and the clock period ts42 of the second clock signal cks1_2~cks4_2 can be 4H.

[0221] Of course, in practical applications, the relationship between the clock period of the second clock signal and the clock period of the first clock signal when scanning only the grid lines coupled to the third color sub-pixel row in a display frame can be determined according to the needs of the actual application, and is not limited here.

[0222] For example, with Figure 3 The structure of the shift register unit shown, and taking the first to fourth level shift register units as examples, in the second driving mode, when scanning the row-coupled gate lines of each red sub-pixel, the corresponding signal timing diagram is as follows: Figure 18a and Figure 18b As shown in the diagram. Here, cks1_2 represents the second clock signal input to the first clock signal line CKS1, cks2_2 represents the second clock signal input to the second clock signal line CKS2, cks3_2 represents the second clock signal input to the third clock signal line CKS3, cks4_2 represents the second clock signal input to the fourth clock signal line CKS4, and stvs_2 represents the frame start signal input to the frame start signal line STVS_2. Furthermore, signal ga3_2 represents the gate scan signal output by the gate drive circuit 110 to gate line GA3, signal ga6_2 represents the gate scan signal output by the gate drive circuit 110 to gate line GA6, ..., signal ga9_2 represents the gate scan signal output by the gate drive circuit 110 to gate line GA9, and signal ga12_2 represents the gate scan signal output by the gate drive circuit 110 to gate line GA12.

[0223] Furthermore, a low-level gate-on signal is applied to the third drive selection signal line to turn on the third second transistor M2_3 in each shift register unit. A high-level gate-off signal is applied to the second drive selection signal line to turn off the second second transistor M2_2 in each shift register unit. A high-level gate-off signal is applied to the first drive selection signal line to turn off the first second transistor M2_1 in each shift register unit. Additionally, a low-level gate-on signal is applied to the third cascade selection signal line to turn on the third first transistor M1_3 in each shift register unit. A high-level gate-off signal is applied to the second drive selection signal line to turn off the second first transistor M1_2 in each shift register unit. A high-level gate-off signal is applied to the first drive selection signal line to turn off the first first transistor M1_1 in each shift register unit. Of course, the gate-on signal can also be a high-level signal, and the gate-off signal can also be a low-level signal; this is not limited here.

[0224] Furthermore, taking a low level as the effective level of the gate scan signal as an example, signal stvs_2 is input to the input signal terminal INP of shift register unit SR1. Shift register unit SR1 outputs the first low level of the second clock signal cks4_2 to gate line GA3 through the third drive output terminal GO_3 to generate the low level in gate scan signal ga3_2. Gate scan signal ga3_2 is input to the input signal terminal INP of shift register unit SR2. Shift register unit SR2 outputs the first low level of the second clock signal cks3_2 to gate line GA6 through the third drive output terminal GO_3 to generate the low level in gate scan signal ga6_2. Gate scan signal ga6_2 is input to the input signal terminal INP of shift register unit SR3. Shift register unit SR3 outputs the first low level of the second clock signal cks2_2 to gate line GA9 through the third drive output terminal GO_3 to generate the low level in gate scan signal ga9_2. The gate scan signal ga9_2 is input to the input signal terminal INP of the shift register unit SR4. The shift register unit SR4 outputs the second low level of the second clock signal cks1_2 to the gate line GA12 through the third drive output terminal GO_3 to generate the low level in the gate scan signal ga12_2.

[0225] Optionally, the low-level duration of each of the second clock signals cks1_2 to cks4_2 is the same, and the clock period of each of the second clock signals cks1_2 to cks4_2 is the same. Furthermore, the low level of the second clock signals cks1_2 to cks4_2 can be their valid level, and the high level their invalid level. Of course, when the shift register unit outputs the high level of the second clock signal to generate the high-level signal controlling the transistor's conduction in the gate scan signal, the high level of the second clock signal can be used as its valid level, and the low level as its invalid level.

[0226] Optionally, such as Figure 18a As shown, the clock period ts41 of each of the second clock signals cks1_2 to cks4_2 can be 24H. Figure 18b As shown, the clock period ts42 of each of the second clock signals cks1_2 to cks4_2 can be 4H. In this embodiment of the present disclosure, by reducing the clock period of the second clock signal, the scanning time of the gate line coupled to the blue sub-pixel can be reduced, thereby reducing the scanning time of a display frame and thus increasing the refresh rate.

[0227] In some embodiments of this disclosure, the duration of the effective level of the second clock signal within one clock cycle is not less than the duration of the effective level of the first clock signal within one clock cycle. Exemplarily, the duration of the effective level of the second clock signal within one clock cycle can be equal to the duration of the effective level of the first clock signal within one clock cycle. For example, when scanning the row-coupled gate lines of the first color sub-pixel, the duration of the effective level of the second clock signal within one clock cycle is equal to the duration of the effective level of the first clock signal within one clock cycle; when scanning the row-coupled gate lines of the second color sub-pixel, the duration of the effective level of the second clock signal within one clock cycle is equal to the duration of the effective level of the first clock signal within one clock cycle; and when scanning the row-coupled gate lines of the third color sub-pixel, the duration of the effective level of the second clock signal within one clock cycle is equal to the duration of the effective level of the first clock signal within one clock cycle. Alternatively, when scanning the row-coupled gate lines of the first color sub-pixel, the duration of the effective level of the second clock signal within one clock cycle is greater than the duration of the effective level of the first clock signal within one clock cycle; the duration of the effective level of the second clock signal within one clock cycle when scanning the row-coupled gate lines of the second color sub-pixel is equal to the duration of the effective level of the first clock signal within one clock cycle; and the duration of the effective level of the second clock signal within one clock cycle when scanning the row-coupled gate lines of the third color sub-pixel is equal to the duration of the effective level of the first clock signal within one clock cycle. This can improve the charging rate of the red sub-pixel.

[0228] In some embodiments of this disclosure, the operation of the second driving mode can be performed for the same color sub-pixel in each of the multiple display frames. For example, in each of the multiple display frames, a scanning process can be performed on the row-coupled grid lines of each red sub-pixel to charge the red sub-pixel and achieve the display of a red image. Alternatively, in each of the multiple display frames, a scanning process can be performed on the row-coupled grid lines of each green sub-pixel to charge the green sub-pixel and achieve the display of a green image. Alternatively, in each of the multiple display frames, a scanning process can be performed on the row-coupled grid lines of each blue sub-pixel to charge the blue sub-pixel and achieve the display of a blue image.

[0229] In some embodiments of this disclosure, the operation of a second driving mode can be performed on different color sub-pixels in multiple adjacent display frames. For example, the operation of the second driving mode can be performed in the order of red sub-pixels, green sub-pixels, and blue sub-pixels in multiple display frames. For instance, the multiple display frames may include: a (q-1)th display frame Fq-1, a qth display frame Fq, and a (q+1)th display frame Fq+1. Specifically, in the (q-1)th display frame Fq-1, a scanning process is performed on the row-coupled gate lines of each red sub-pixel to charge the red sub-pixel. In the qth display frame Fq, a scanning process is performed on the row-coupled gate lines of each green sub-pixel to charge the green sub-pixel. In the (q+1)th display frame Fq+1, a scanning process is performed on the row-coupled gate lines of each blue sub-pixel to charge the blue sub-pixel.

[0230] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable storage media (which may include, but are not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0231] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0232] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture that may include instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0233] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0234] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to include both the preferred embodiments and all changes and modifications falling within the scope of this disclosure.

[0235] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A shift register unit, comprising: a first control circuit configured to control signals of a first node and a second node according to signals of an input signal terminal and a first clock signal terminal; a second control circuit configured to control signals of at least two driving nodes according to signals of the first node, the second node and a second clock signal terminal; a cascade output circuit configured to provide a signal of one of the at least two driving nodes to a cascade output terminal according to a cascade selection signal terminal; a driving output circuit configured to provide a signal of at least one of the at least two driving nodes to a driving output terminal corresponding to the at least one driving node according to a driving selection signal terminal; wherein the driving nodes comprise M driving nodes, the second clock signal terminal comprises M second clock signal terminals, and the driving output terminal comprises M driving output terminals; M is an integer greater than 1; the second control circuit comprises M second control circuits; wherein an mth second control circuit of the M second control circuits corresponds to an mth driving node of the M driving nodes, and the mth second control circuit corresponds to an mth second clock signal terminal of the M second clock signal terminals; and the mth second control circuit is configured to provide a signal of the mth second clock signal terminal to the mth driving node in response to a signal of the first node, and provide a signal of a first reference signal terminal to the mth driving node in response to a signal of the second node; 1≤m≤M, and m is an integer; the cascade output circuit comprises M cascade output circuits, and the cascade selection signal terminal comprises M cascade selection signal terminals; wherein an mth cascade output circuit of the M cascade output circuits corresponds to the mth driving node, and the mth cascade output circuit corresponds to an mth cascade selection signal terminal of the M cascade selection signal terminals; the mth cascade output circuit is configured to provide a signal of the mth driving node to the cascade output terminal in response to a signal of the mth cascade selection signal terminal; the driving output circuit comprises M driving output circuits, and the driving selection signal terminal comprises M driving selection signal terminals; an mth driving output circuit of the M driving output circuits corresponds to the mth driving node, and the mth driving output circuit corresponds to an mth driving selection signal terminal of the M driving selection signal terminals; the mth driving output circuit is configured to provide a signal of the mth driving node to the mth driving output terminal in response to a signal of the mth driving selection signal terminal. the mth cascade output circuit comprises: an mth first transistor; a control electrode of the mth first transistor is coupled to the mth cascade selection signal terminal, a first electrode of the mth first transistor is coupled to the mth driving node, and a second electrode of the mth first transistor is coupled to the cascade output terminal; the mth driving output circuit comprises: an mth second transistor; ​ ​ ​ ​ ​ ​ ​ ​ 2. The shift register cell of claim 1, wherein, ​ ​ 3. The shift register cell of claim 1, wherein, ​ A control electrode of the mth second transistor is coupled with the mth driving selection signal terminal, a first electrode of the mth second transistor is coupled with the mth driving node, and a second electrode of the mth second transistor is coupled with the driving output terminal.

4. The shift register cell of any of claims 1-3, wherein, The mth second control circuit includes an mth third transistor, an mth fourth transistor, and an mth first capacitor. A control electrode of the mth third transistor is coupled with the first node, a first electrode of the mth third transistor is coupled with the mth second clock signal terminal, and a second electrode of the mth third transistor is coupled with the mth driving node. A control electrode of the mth fourth transistor is coupled with the second node, a first electrode of the mth fourth transistor is coupled with the first reference signal terminal, and a second electrode of the mth fourth transistor is coupled with the mth driving node. A first electrode plate of the mth first capacitor is coupled with the first node, and a second electrode plate of the mth first capacitor is coupled with the mth driving node.

5. The shift register cell of claim 4, wherein, The mth second control circuit further includes an mth fifth transistor, the control electrode of the mth third transistor is coupled with the first node through the mth fifth transistor, a first electrode of the mth fifth transistor is coupled with the first node, and a second electrode of the mth fifth transistor is coupled with the control electrode of the mth third transistor. When m=1, the control electrode of the mth fifth transistor is coupled with the second reference signal terminal. When 1 6. The shift register cell of any of claims 1-5, wherein, The first control circuit includes an input circuit and a node control circuit. The input circuit is configured to provide a signal of the input signal terminal to the first node in response to a signal of the first clock signal terminal. The node control circuit is configured to provide a signal of the second reference signal terminal to the second node in response to a signal of the first clock signal terminal, to provide a signal of the first clock signal terminal to the second node in response to a signal of the first node, and to provide a signal of the first reference signal terminal to the first node in response to signals of the second node and the first second clock signal terminal.

7. The shift register cell of claim 6, wherein, The input circuit includes a sixth transistor, a control electrode of the sixth transistor is coupled with the first clock signal terminal, a first electrode of the sixth transistor is coupled with the input signal terminal, and a second electrode of the sixth transistor is coupled with the first node. The node control circuit comprises a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor and a second capacitor; a control electrode of the seventh transistor is coupled with the first clock signal terminal, a first electrode of the seventh transistor is coupled with the second reference signal terminal, and a second electrode of the seventh transistor is coupled with the second node; a control electrode of the eighth transistor is coupled with the first node, a first electrode of the eighth transistor is coupled with the first clock signal terminal, and a second electrode of the eighth transistor is coupled with the second node; a control electrode of the ninth transistor is coupled with the second node, a first electrode of the ninth transistor is coupled with the first reference signal terminal, and a second electrode of the ninth transistor is coupled with a first electrode of the tenth transistor; a control electrode of the tenth transistor is coupled with the first second clock signal terminal, and a second electrode of the tenth transistor is coupled with the first node; a first electrode plate of the second capacitor is coupled with the second node, and a second electrode plate of the second capacitor is coupled with the first reference signal terminal.

8. A gate drive circuit comprising a plurality of shift register units cascaded as claimed in any one of claims 1-7; the input signal terminal of the first stage shift register unit is coupled with a frame start signal line; in each two adjacent stage shift register units, the input signal terminal of the next stage shift register unit is coupled with the cascaded output terminal of the previous stage shift register unit.

9. A display device comprising a display panel; the display panel comprising: a plurality of gate lines, a plurality of clock signal lines, a plurality of cascaded selection signal lines, a plurality of drive selection signal lines and the gate drive circuit as claimed in claim 8; each drive output terminal of each shift register unit in the gate drive circuit is coupled with one of the plurality of gate lines in one-to-one correspondence, and one shift register unit in the gate drive circuit is coupled with the plurality of clock signal lines; the cascaded selection signal terminal of the shift register unit in the gate drive circuit is coupled with the cascaded selection signal line; the drive selection signal terminal of the shift register unit in the gate drive circuit is coupled with the drive selection signal line.

10. The display device of claim 9, wherein, The display panel further comprises a plurality of pixel units arranged in an array; one row of the pixel units corresponds to one shift register unit in the gate drive circuit; the pixel unit comprises a plurality of sub-pixels of different colors arranged in a column direction, and one row of the sub-pixels is coupled with one gate line; the mth drive output terminal of each shift register unit is coupled with the gate line corresponding to the sub-pixel of the same color.

11. The display device of claim 10, wherein, M=3, the pixel unit comprises a first color sub-pixel, a second color sub-pixel and a third color sub-pixel arranged in a column direction in sequence; The plurality of clock signal lines comprises a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line; wherein a first clock signal end of the 4k_3 stage shift register unit, a first second clock signal end of the 4k_2 stage shift register unit, a second second clock signal end of the 4k_1 stage shift register unit and a third second clock signal end of the 4k stage shift register unit are coupled with the first clock signal line; a first second clock signal end of the 4k_3 stage shift register unit, a second second clock signal end of the 4k_2 stage shift register unit, a third second clock signal end of the 4k_1 stage shift register unit and a first clock signal end of the 4k stage shift register unit are coupled with the second clock signal line; a second second clock signal end of the 4k_3 stage shift register unit, a third second clock signal end of the 4k_2 stage shift register unit, a first clock signal end of the 4k_1 stage shift register unit and a first second clock signal end of the 4k stage shift register unit are coupled with the third clock signal line; a third second clock signal end of the 4k_3 stage shift register unit, a first clock signal end of the 4k_2 stage shift register unit, a first second clock signal end of the 4k_1 stage shift register unit and a second second clock signal end of the 4k stage shift register unit are coupled with the third clock signal line; k is an integer greater than 0; The plurality of cascaded selection signal lines comprises a first cascaded selection signal line, a second cascaded selection signal line and a third cascaded selection signal line; wherein a first cascaded selection signal end of each stage shift register unit is coupled with the first cascaded selection signal line, a second cascaded selection signal end of each stage shift register unit is coupled with the second cascaded selection signal line, and a third cascaded selection signal end of each stage shift register unit is coupled with the third cascaded selection signal line; The plurality of driving selection signal lines comprises a first driving selection signal line, a second driving selection signal line and a third driving selection signal line; wherein a first driving selection signal end of each stage shift register unit is coupled with the first driving selection signal line, a second driving selection signal end of each stage shift register unit is coupled with the second driving selection signal line, and a third driving selection signal end of each stage shift register unit is coupled with the third driving selection signal line.

12. A driving method of the shift register unit according to any one of claims 1-7, comprising: In the first driving mode, one display frame comprises a first input stage, a first output stage and a first reset stage; In the first input stage, the first control circuit controls the signals of the first node and the second node according to the signals of the input signal end and the first clock signal end; The second control circuit controls the signals of the at least two driving nodes according to the signals of the first node, the second node and the second clock signal end; The cascade output circuit provides a signal of an Mth driving node among the at least two driving nodes to a cascade output terminal according to a cascade selection signal terminal; The driving output circuit provides a signal of each of the at least two driving nodes to a driving output terminal corresponding to each of the driving nodes according to a driving selection signal terminal; In the first input stage, the first control circuit controls signals of the first node and the second node according to signals of the input signal terminal and the first clock signal terminal; The cascade output circuit provides a signal of an Mth driving node among the at least two driving nodes to a cascade output terminal according to a cascade selection signal terminal; The driving output circuit provides a signal of each of the at least two driving nodes to a driving output terminal corresponding to each of the driving nodes according to a driving selection signal terminal; In the first reset stage, the first control circuit controls signals of the first node and the second node according to a signal of the first clock signal terminal; The second control circuit controls signals of the at least two driving nodes according to a signal of the second node; The cascade output circuit provides a signal of an Mth driving node among the at least two driving nodes to a cascade output terminal according to a cascade selection signal terminal; The driving output circuit provides a signal of each of the at least two driving nodes to a driving output terminal corresponding to each of the driving nodes according to a driving selection signal terminal; In the second driving mode, one display frame includes a second input stage, a second output stage and a second reset stage; In the second input stage, the first control circuit controls signals of the first node and the second node according to signals of the input signal terminal and the first clock signal terminal; The second control circuit controls signals of the at least two driving nodes according to signals of the first node, the second node and the second clock signal terminal; The cascade output circuit provides a signal of an Mth driving node among the at least two driving nodes to a cascade output terminal according to a cascade selection signal terminal; The driving output circuit provides a signal of each of the at least two driving nodes to a driving output terminal corresponding to each of the driving nodes according to a driving selection signal terminal; In the second reset stage, the first control circuit controls signals of the first node and the second node according to a signal of the first clock signal terminal; The second control circuit controls signals of the at least two driving nodes according to a signal of the second node; The cascade output circuit provides a signal of an Mth driving node among the at least two driving nodes to a cascade output terminal according to a cascade selection signal terminal; ​ ​ ​ The driving output circuit provides the signal of the mth driving node of the at least two driving nodes to the corresponding driving output end according to the driving selection signal end.

13. A driving method of the display device according to any one of claims 9-11, comprising: in the first driving mode, in a display frame, loading different first clock signals to each of the clock signal lines, loading a gate-on signal to each of the driving selection signal lines, loading a gate-on signal to the cascade selection signal line coupled to the Mth driving output circuit, loading a gate-off signal to the remaining cascade selection signal lines, controlling the shift register units to work sequentially, providing the signal of the Mth driving node of the at least two driving nodes to the cascade output end, and providing the signal of each of the at least two driving nodes to the driving output end corresponding to each of the driving nodes, and scanning the gate lines row by row; in the second driving mode, in a display frame, loading a second clock signal to each of the clock signal lines, loading a gate-on signal to the driving selection signal line coupled to the mth cascade output circuit, loading a gate-off signal to the remaining driving selection signal lines, loading a gate-on signal to the cascade selection signal line coupled to the mth driving output circuit, and loading a gate-off signal to the remaining cascade selection signal lines, controlling the shift register units to work sequentially, providing the signal of the mth driving node of the at least two driving nodes to the cascade output end, and providing the signal of the mth driving node to the corresponding driving output end, and scanning the gate lines line by line; wherein the clock period of the second clock signal is different from the clock period of the first clock signal.

14. The driving method of a display device according to claim 13, wherein M=3, in the second driving mode, loading the same second clock signal to the first clock signal line and the third clock signal line, and loading the same second clock signal to the second clock signal line and the fourth clock signal line, loading a gate-on signal to the first cascade selection signal line, and loading a gate-off signal to the second cascade selection signal line and the third cascade selection signal line, loading a gate-on signal to the first driving selection signal line, and loading a gate-off signal to the second driving selection signal line and the third driving selection signal line, controlling the shift register units to work sequentially, providing the signal of the first driving node to the cascade output end, and providing the signal of the first driving node to the first driving output end, and scanning the gate lines coupled to each of the first color sub-pixel rows; wherein the second clock signal loaded to the first clock signal line and the second clock signal end is different.

15. The driving method of a display device according to claim 14, wherein The clock period of the second clock signal is not more than 3 / 2 of the clock period of the first clock signal.

16. The driving method of a display device according to claim 13, wherein In the second driving mode, different second clock signals are loaded on the first clock signal line to the fourth clock signal line respectively, the gate-on signal is loaded on the second cascade selection signal line, the gate-off signal is loaded on the first cascade selection signal line and the third cascade selection signal line, the gate-on signal is loaded on the second driving selection signal line, and the gate-off signal is loaded on the first driving selection signal line and the third driving selection signal line, the shift register units are sequentially controlled to work, the signal of the second driving node is provided to the cascade output end, and the signal of the second driving node is provided to the second driving output end, and the gate line coupled to each second color sub-pixel row is scanned.

17. The driving method of a display device according to claim 16, wherein The two different clock periods include a first clock period and a second clock period; the first clock period is not greater than 3 / 4 of the clock period of the first clock signal, and the second clock period is not greater than 9 / 4 of the clock period of the first clock signal.

18. The driving method of a display device according to claim 13, wherein M=3, in the second driving mode, different second clock signals are loaded on the first clock signal line to the fourth clock signal line respectively, the gate-on signal is loaded on the third cascade selection signal line, the gate-off signal is loaded on the first cascade selection signal line and the second cascade selection signal line, the gate-on signal is loaded on the third driving selection signal line, and the gate-off signal is loaded on the first driving selection signal line and the second driving selection signal line, the shift register units are sequentially controlled to work, the signal of the third driving node is provided to the cascade output end, and the signal of the third driving node is provided to the third driving output end, and the gate line coupled to each third color sub-pixel row is scanned.

19. The driving method of a display device according to claim 18, wherein The second clock period is not greater than three times of the clock period of the first clock signal.

20. The driving method of the display device according to any one of claims 14 to 19, wherein, The maintenance time length of the effective level of the second clock signal in one clock period is not less than the maintenance time length of the effective level of the first clock signal in one clock period.

21. The driving method of a display device according to claim 20, wherein The maintenance time length of the effective level of the corresponding second clock signal in one clock period is greater than the maintenance time length of the effective level of the first clock signal in one clock period when the gate line coupled to the first color sub-pixel row is scanned; The maintenance time length of the effective level of the corresponding second clock signal in one clock period is equal to the maintenance time length of the effective level of the first clock signal in one clock period when the gate line coupled to the second color sub-pixel row is scanned; The maintenance time length of the effective level of the corresponding second clock signal in one clock period is equal to the maintenance time length of the effective level of the first clock signal in one clock period when the gate line coupled to the third color sub-pixel row is scanned.

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