A power terminal device FPGA remote upgrading method

Abstract

The application provides a power terminal device FPGA remote upgrading method, comprising the following steps: a cloud server sends a remote upgrading instruction; after the ARM of the power terminal device receives the remote upgrading instruction, the ARM firstly controls the FPGA to be powered off, and then loads an upgrading program; after the FPGA is restarted after being powered off, the FPGA automatically loads a program upgrading special code; after the FPGA completes the loading of the program upgrading special code, the FPGA prepares to update the upgrading code, and performs erasing on the updating code storage area of the Flash, and then writes the upgrading code; after the upgrading code is written into the Flash, the ARM configures the FPGA reloading address as the updating code storage area of the Flash, and performs a reloading operation on the FPGA; the ARM checks the state of the FPGA after reloading, if the loading is successful, the upgrading code after updating is normally run; if the loading is not successful, the program of the upgrading code cannot be normally run, and the Flash reloads the program upgrading special code.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of remote upgrading, in particular to a power terminal device FPGA remote upgrading method. BACKGROUND

[0002] The power terminal FPGA device on the high-voltage transmission line is usually installed on the high-voltage line and is mainly used for real-time monitoring and management of the transmission line. The power terminal FPGA device can quickly diagnose the fault of the transmission line and issue a warning message to the operation and maintenance personnel through real-time monitoring of the state of the transmission line. In order to solve the unexpected problems of the power terminal FPGA device during operation or add new functions, it is necessary to update / upgrade the program of the power terminal FPGA device.

[0003] The existing update / upgrade method, such as offline upgrade, requires the device to establish a physical connection with the computer or other devices, and the upgrade file is transmitted to the power terminal FPGA device through a wired method. However, considering the environment of the power terminal FPGA device on the actual high-voltage transmission line, it is actually impossible to use JTAG or PCIE communication interface for direct wired upgrade. Due to the particularity of the environment, the power terminal FPGA device cannot be controlled at any time and any place, so the code cannot be updated in time, which leads to the failure of FPGA version upgrade or the high cost of upgrade.

[0004] There are also some online upgrade methods, but the existing online upgrade method is prone to interruption due to unstable signals, which may lead to upgrade failure. Once the upgrade fails, the device will be unavailable. Considering the high safety requirement of the device on the transmission line, it is necessary to ensure the high reliability of the FPGA upgrade process to avoid causing many inconveniences in economy and engineering.

[0005] The current power terminal FPGA device has limited resources, and once the online upgrade occupies too many resources, it will be difficult to ensure the normal operation of the device. Therefore, considering the limited resources of the FPGA, it is expected to minimize the resource waste caused by remote upgrade and improve the overall resource utilization of the FPGA.

[0006] In addition, the existing upgrade method is mostly offline upgrade, and considering the requirement of real-time monitoring and management, it is also desirable to provide an upgrade method without shutdown. SUMMARY

[0007] The present application aims to overcome the shortcomings of the prior art and provide a power terminal device FPGA remote upgrading method, which can improve the overall resource utilization of the FPGA and does not require shutdown during the upgrade process.

[0008] To achieve the above objectives, a first aspect of the present invention provides a method for remotely upgrading an FPGA-based power terminal device, comprising:

[0009] After the cloud server completes the preparations for the upgrade, it sends the remote upgrade command.

[0010] After receiving the remote upgrade command, the ARM of the power terminal equipment begins the remote upgrade process. First, it controls the FPGA to power off, then loads the upgrade program. At the same time, the ARM receives and stores the upgrade code data.

[0011] After the FPGA is powered off and restarted, it automatically loads the dedicated program upgrade code; the dedicated program upgrade code only has the functions required for the FPGA code upgrade process.

[0012] The Flash memory is pre-divided into a program upgrade function area and an update code storage area, wherein the program upgrade-specific code is stored in the program upgrade function area;

[0013] After the FPGA completes the loading of the dedicated upgrade code, it prepares to update the upgrade code and erases the Flash update code storage area.

[0014] After the FPGA erases the Flash update code storage area, it writes the upgrade code.

[0015] After the FPGA completes the upgrade code writing to the Flash, the ARM configures the FPGA to reload to the Flash's updated code storage area and performs a reload operation on the FPGA.

[0016] The ARM processor checks the FPGA status after reloading. If the loading is successful, the updated upgrade code runs normally. If the loading fails, the upgrade code program cannot run normally, and the Flash reloads the upgrade-specific code.

[0017] ARM returns a success or failure indication to the cloud server.

[0018] Based on the above, the update code storage area is divided into functional code area I for storing the latest upgrade code and functional code area II for storing the next newest upgrade code. The next newest upgrade code is the old version upgrade code that was running before the upgrade.

[0019] After the FPGA completes the loading of the dedicated upgrade code, when it is ready to update the upgrade code, the functional code area I of the Flash memory is erased as the storage area for the update code.

[0020] Before ARM returns a success or failure indication to the cloud server, it also performs the following:

[0021] The ARM decides whether to rewrite the upgrade code. If so, the FPGA rewrites the upgrade code to update it; otherwise, the ARM configures the FPGA to reload the function code area II at the Flash address, and the FPGA reloads the second-new upgrade code.

[0022] Based on the above, when the FPGA of the power terminal equipment leaves the factory, the initial version upgrade code is pre-stored in function code area II, while the initial version upgrade code is pre-stored in function code area I or left blank.

[0023] During the first upgrade, after the FPGA completes the loading of the program upgrade-specific code, when it is ready to update the upgrade code, the Flash function code area I is erased as the update code storage area, and then the subsequent upgrade steps are executed until the upgrade is successful.

[0024] During the second upgrade, after the FPGA completes the loading of the program upgrade-specific code, when it is ready to update the upgrade code, the Flash function code area II is erased as the update code storage area, and then the subsequent upgrade steps are executed until the upgrade is successful.

[0025] During the third upgrade, Flash's function code area I was erased as the update code storage area; during the fourth upgrade, Flash's function code area II was erased as the update code storage area.

[0026] In this cycle, function code region I and function code region II alternately serve as the storage area for update code.

[0027] To achieve the above objectives, a second aspect of the present invention provides a remote upgrade system for FPGA of power terminal equipment, comprising:

[0028] The cloud server remotely sends upgrade data to the ARM of the power terminal equipment;

[0029] ARM is used to receive upgrade data and transmit it to the FPGA of the power terminal equipment;

[0030] FPGA is used to perform the upgrade process according to the configuration instructions of ARM;

[0031] The FSMC module is used to establish a communication channel between the FPGA and the ARM.

[0032] Flash memory is used to store program upgrade code and upgrade code.

[0033] The cloud server is connected to the ARM, the ARM is connected to the FPGA through the FSMC module, and the FPGA is connected to the Flash, in order to implement the steps of the FPGA remote upgrade method for power terminal equipment.

[0034] Based on the above, the FPGA includes an FSMC module, a data storage module, an SPI module, a control module, and an upgrade configuration module;

[0035] The data storage module is used to cache the upgrade code received by the FPGA through the FSMC module;

[0036] The control module is used to perform corresponding operations according to the configuration instructions sent by the ARM, including erasure operations and upgrade code writing;

[0037] The SPI module is used to implement the timing drive of the interface between the FPGA and the Flash.

[0038] The upgrade configuration module is used to perform corresponding operations according to the configuration instructions sent by the ARM, including loading the starting address configuration and reloading the program.

[0039] To achieve the above objectives, a third aspect of the present invention provides a method for remotely upgrading an FPGA-based power terminal device without downtime:

[0040] Set up two FPGAs with identical structure and function, with a working module and a coordination module set up in each FPGA;

[0041] The two FPGAs are each connected to a power supply.

[0042] Each FPGA communicates with the ARM via the FSMC module; the coordination module of the two FPGAs is connected via a dedicated bus.

[0043] Each FPGA is connected to an SPI selector on the SPI bus via an SPI interface, and the coordination module of each FPGA is connected to the SPI selector via a simulated SPI interface; the SPI selector is connected to a unique Flash memory; the simulated SPI interface is used to simulate the Flash memory providing data services to external devices.

[0044] Each FPGA's control signal output interface is connected to the SPI bus to output control signals during normal operation;

[0045] The ARM processor coordinates the SPI gate through two FPGAs and uses the aforementioned power terminal equipment FPGA remote upgrade method to upgrade the Flash memory, including three modes:

[0046] Mode 1: Normal working state

[0047] The ARM controls the power supply and randomly powers on either FPGA I or FPGA II; the ARM controls the SPI selector to connect the SPI interface of the FPGA to be powered on and the Flash memory.

[0048] At this time, the ARM transfers the power terminal equipment's tasks to the powered FPGA through the FSMC module;

[0049] The ARM selects the function code area of ​​the latest upgrade code in the Flash memory through the powered-on FPGA, and the working module performs the operation.

[0050] Mode 2: A mixed state in which normal operation and normal upgrades occur simultaneously:

[0051] The ARM control power supply can be either FPGAⅠ or FPGAⅡ powered on first.

[0052] After power-on, the FPGA that is powered on first operates in mode one;

[0053] When preparing for an upgrade, the ARM controls the powered-on FPGA coordination module to map the address of the function code area of ​​the code to be upgraded in the Flash to the emulated SPI interface of the powered-on FPGA, and then controls the SPI selector to connect the path between the SPI interface of the FPGA to be powered on and the emulated SPI interface of the powered-on FPGA.

[0054] After completion, the ARM control power supply powers on the FPGA I and FPGA II that were not powered on.

[0055] After the FPGA that was powered on last completes its power-on process, the ARM selects the FPGA that was powered on last to be responsible for the upgrade work.

[0056] Mode 3: A mixed state in which normal operation and abnormal upgrades occur simultaneously.

[0057] If an upgrade fails, the FPGA responsible for the upgrade will restart and enter an abnormal upgrade mode. That is, the ARM controls the FPGA coordination module to map the addresses of the program upgrade function area and the failed upgrade function code area in the Flash to the emulated SPI interface of the normal FPGA. Then, it controls the SPI selector to connect the path between the SPI interface of the FPGA responsible for the upgrade and the emulated SPI interface of the normal FPGA, and then restarts the FPGA responsible for the upgrade.

[0058] After the FPGA responsible for the upgrade restarts, the upgrade process is completed again until the upgrade is successful.

[0059] Based on the above, it also includes Mode 4: a mixed state in which normal work and test work modes are carried out simultaneously;

[0060] After the FPGA responsible for the upgrade successfully completes the code upgrade, the ARM controls the coordination module in the normally operating FPGA to map the complete real physical address in Flash to the emulated SPI interface of the normally operating FPGA. The SPI selector keeps the emulated SPI interface of the normally operating FPGA and the SPI interface of the FPGA responsible for the upgrade connected.

[0061] The ARM controller is responsible for restarting the FPGA that is being upgraded;

[0062] After the FPGA responsible for the upgrade is powered on, the ARM command for the FPGA responsible for the upgrade works in normal working state, working synchronously with the normal working FPGA and handling the same tasks. However, the control signals generated by the FPGA responsible for the upgrade are not sent to the control signal output bus, but are sent to the coordination module of the normal working FPGA through a dedicated bus. The coordination module of the normal working FPGA compares whether the control information generated by the two FPGAs is consistent, and verifies whether the effect of this upgrade is normal.

[0063] If the test results are normal, in order to complete the handover of tasks between the two FPGAs, the ARM controls at a certain moment:

[0064] (1) The SPI selector connects the SPI interface between the Flash and the FPGA responsible for the upgrade;

[0065] (2) The FPGA responsible for the upgrade sends the control signals for normal operation to the control signal output bus;

[0066] (3) Cut off the power supply to the FPGA that is working normally, so that it loses power.

[0067] To achieve the above objectives, a fourth aspect of the present invention provides a non-stop FPGA remote upgrade system for power terminal equipment, comprising:

[0068] The cloud server remotely sends upgrade data to the ARM of the power terminal equipment;

[0069] ARM is used to receive upgrade data and transmit it to the FPGA of the power terminal equipment;

[0070] Two FPGAs are used to perform upgrade and normal operation tasks according to the ARM's configuration instructions;

[0071] The FSMC module is used to establish a communication channel between the FPGA and the ARM.

[0072] Flash memory is used to store program upgrade code and upgrade code.

[0073] The cloud server is connected to the ARM, the ARM is connected to two FPGAs through the FSMC module, and the two FPGAs are connected to the Flash, so as to realize the method for remote upgrading of FPGAs of power terminal equipment without interruption.

[0074] The beneficial effects of this invention are as follows:

[0075] (1) Ensure the safety of transmission line equipment according to the upgrade strategy designed;

[0076] This invention divides the code stored in the FPGA's Flash memory into three parts: dedicated program upgrade code, latest upgrade code, and second-newest upgrade code. The dedicated program upgrade code is factory-set and will not be modified later. The latest upgrade code and second-newest upgrade code are the normal function code of the power terminal equipment, which serve as backups for each other. This ensures that even if the upgrade fails, the power terminal equipment can still load the previous normal function code, ensuring that the normal function of the online power terminal equipment is not affected and guaranteeing the security of the online power terminal equipment's functions. At the same time, the upgrade strategy of not modifying the dedicated program upgrade code ensures that the upgrade function of the power terminal equipment is always in a normal state, keeping the power terminal equipment within a controllable range and ensuring the security of the upgrade function.

[0077] (2) Maximize the resource utilization of the FPGA according to the upgrade strategy of the design;

[0078] This invention divides the code storage of the FPGA-side Flash into three parts: a program upgrade function area, function code area I, and function code area II. Considering the occasional nature of upgrade functions, which are only used in specific scenarios, and the characteristic of normal functions, which run continuously for a long time, the upgrade function and normal functions are decoupled. The upgrade program function is implemented separately, minimizing the resource consumption caused by the upgrade function and maximizing the availability of FPGA resources during the development of normal functions. This upgrade strategy can improve the overall resource utilization of the FPGA while ensuring the upgrade function.

[0079] (3) Upgrade without stopping the machine

[0080] This invention enables remote upgrades of power terminal equipment FPGAs without downtime by configuring working module I, working module II, and coordination module within the FPGA. Attached Figure Description

[0081] Figure 1 This is a schematic diagram of the remote upgrade system of the present invention.

[0082] Figure 2 This is the FSMC synchronous multiplexing read timing diagram.

[0083] Figure 3 This is the FSMC synchronous multiplexing write timing diagram.

[0084] Figure 4 This is a schematic diagram of the ping-pong operation principle of the data storage module.

[0085] Figure 5 This is a flowchart of the erase operation of the control module.

[0086] Figure 6 This is a flowchart of the program upgrade operation for the control module.

[0087] Figure 7 This is the timing diagram for page write operations of the SPI module.

[0088] Figure 8 This is the program loading process for upgrading the configuration module.

[0089] Figure 9 This is a diagram showing the partitioning of Flash storage space.

[0090] Figure 10 This is a flowchart of the remote upgrade method of the present invention.

[0091] Figure 11 This is a diagram of the update process for a two-stage code storage scheme.

[0092] Figure 12 This is a schematic diagram of a remote FPGA upgrade system for uninterrupted power terminal equipment. Detailed Implementation

[0093] The technical solution of the present invention will be further described in detail below through specific embodiments.

[0094] Example 1

[0095] This embodiment provides a remote upgrade system for FPGA-based power terminal equipment, such as... Figure 1 As shown, it includes:

[0096] Cloud server: Prepare for the upgrade by selecting the power terminal equipment to be upgraded and uploading the .bin file to be upgraded to the terminal server; after preparation, start transmitting the upgrade file, which is sent to the power terminal equipment via 4G base station;

[0097] The ARM, the 4G module of the power terminal equipment, receives the upgrade data and performs caching and CRC verification on the upgrade data. If the verification fails, the 4G module sends a failure indication command to request the cloud server to resend the data. Data that passes the verification is transmitted to the FPGA through the FSMC module.

[0098] FPGA, the FPGA of power terminal equipment, establishes a communication channel with ARM through the FSMC module; the FPGA executes different upgrade processes according to the configuration instructions of ARM, the upgrade process includes erasure, writing, and boot;

[0099] The FSMC module is used to establish a communication channel between the FPGA and the ARM.

[0100] Flash memory is used to store program upgrade code and upgrade code.

[0101] The cloud server is connected to the ARM, the ARM is connected to the FPGA through the FSMC module, and the FPGA is connected to the Flash, so as to realize the method of remote upgrading of FPGA of power terminal equipment.

[0102] FPGA module design

[0103] The FPGA includes an FSMC module, a data storage module, an SPI module, a control module, and an upgrade configuration module;

[0104] ①FSMC module:

[0105] A communication channel is established between the FPGA and the ARM, with an interface clock rate of 8MHz. The content transmitted between the ARM and the FPGA is mainly divided into two types: instructions and data. Instructions include: erase instructions, write instructions, and start instructions. Data mainly refers to upgrade data.

[0106] The FSMC module interface enables the ARM to control and transmit the internal state of the FPGA.

[0107] The FSMC module interface includes two operation timings: synchronous multiplexed read timing and synchronous multiplexed write timing, such as... Figure 2 and Figure 3 ;

[0108] The FSMC module implements the above read and write functions, receives corresponding configuration instructions based on the read / write address and read / write data, and then the subsequent modules perform corresponding operations based on the configuration instructions.

[0109] ② Data storage module:

[0110] The FPGA receives upgrade data through the FSMC module interface. The received upgrade data is cached in the FPGA's internal BRAM, with a cache depth of 1k*16bit at a time. After one cache is completed, a packet of data is written to the Flash via the SPI module.

[0111] The main function of this section is to perform ping-pong operations on the RAM blocks within the FPGA (such as...). Figure 4As shown, the upgrade data sent from the FSMC module interface is cached, with 1k*16bit of data cached at a time; once caching is complete, a packet of upgrade data is sent to the subsequent module.

[0112] ③ Control module:

[0113] The control module executes corresponding operations according to the received configuration instructions; the implementation principle is to execute different operations based on the address of the ARM operation and the data written to that address, thereby executing different operation processes.

[0114] The operation process performed by the control module includes two operations: both operations are set according to the Flash (W25Q128M);

[0115] Erasure operation: such as Figure 5 As shown, the Flash space is erased according to the set address, with each 64KB block erase operation; based on the effective program storage address allocation, a 32Mbit address space needs to be erased at once, and after the erasure is completed, it waits for the upgrade data to be written.

[0116] Perform upgrade data writing: such as Figure 6 As shown, according to the cache module's instructions, an upgrade data is written to the Flash once, with 1k*16bit written at a time; using the W25Q128M's page programming mode, one page of data, 256 bytes, is written at a time, and 1k*16bit of cached data is written in 8 pages at a time; after one data write is completed, the system waits for the cache completion indication for the next data packet; the upgrade data programming continues until 32Mbit of programming data is written.

[0117] ④SPI module:

[0118] like Figure 7 As shown, this module mainly implements the timing drive for the FPGA's interface with the Flash (W25Q128M), using a standard SPI bus with an interface clock rate of 5MHz. Based on the received instructions, this module performs erase and write operations respectively. The SPI clock drive is implemented using the startupe2 soft core.

[0119] The instruction for 64KB block erase is D8h, the instruction for write enable is 06h, the instruction for page programming is 02h, and the instruction for read operation is 03h.

[0120] ⑤ Upgrade configuration module:

[0121] like Figure 8As shown, the startup process is triggered by the startup command. The IP soft core icape2 performs operations such as configuring the loading start address and reloading the program to ensure that the upgrade data is written to the correct address, that the upgrade program is loaded at the correct address during reloading, and that the upgrade program is loaded normally and the function runs normally.

[0122] Program storage space design

[0123] The FPGA function code is stored in Flash memory, specifically a W25Q128M flash memory with a capacity of 128Mbit. The maximum function code file size is 32Mbit. Based on this, the storage space is divided into three parts to ensure full resource utilization and compatibility with function and upgrade codes. Figure 9 As shown:

[0124] Part 1: Program upgrade function area. The upgrade program function area code is the factory initial configuration code and will not be modified in subsequent upgrade processes. It only has the functions required for the FPGA code upgrade process, including communication with ARM, writing flash code, reloading program address configuration, etc. This part of the code function can be automatically loaded by the FPGA through power-off reset.

[0125] Part Two: Function Code Area I, is the normal function code storage area and the update code storage area, used to store the latest updated code; it serves as a backup for Part Three, both acting as normal function code storage areas.

[0126] Part Three: Function Code Area II, which is the storage area for normal function code and also the storage area for update code, used to store the latest update code; it serves as a backup for Part Two, both serving as storage areas for normal function code; the latest upgrade code is the old version upgrade code that ran before the upgrade;

[0127] Function code area II ensures that if the FPGA update code fails, the next newer code can be reloaded to ensure that the device can operate normally and the FPGA functions normally, while waiting for the next code update.

[0128] Remote upgrade method

[0129] Specific methods for remotely upgrading FPGAs of power terminal equipment, such as Figure 10 As shown:

[0130] ①After the cloud server completes the preparations for the upgrade, it sends a remote upgrade command;

[0131] ② After receiving the remote upgrade command, the ARM of the power terminal equipment begins the remote upgrade process; first, it controls the FPGA to power off, then loads the upgrade program; at the same time, the ARM receives the upgrade code data and stores it.

[0132] ③ After the FPGA is powered off and restarted, the default program upgrade code is loaded starting from address 0, so the program upgrade code will be loaded automatically.

[0133] ④ After the FPGA completes the loading of the dedicated program upgrade code, it prepares to update the upgrade code and erase the functional code area I of the Flash memory;

[0134] ⑤ After the FPGA completes the erasure of the Flash functional code area I, it writes the upgrade code;

[0135] ⑥ After the FPGA completes the upgrade code writing to Flash, the ARM configures the FPGA to reload the function code area I of Flash and performs a reload operation on the FPGA;

[0136] ⑦ The ARM checks the FPGA status after reloading. If the loading is successful, the updated upgrade code runs normally. If the loading fails, the upgrade code program cannot run normally. The Flash reloads the program upgrade code to ensure the normal operation of the FPGA and the power terminal equipment.

[0137] ⑧ The ARM decides whether to rewrite the upgrade code. If yes, it returns to ④ and the FPGA rewrites the upgrade code to update the upgrade code; otherwise, the ARM configures the FPGA to reload the function code area II at the address of Flash, and the FPGA reloads the second-new upgrade code.

[0138] ⑨ ARM returns a success or failure indication to the cloud server.

[0139] Two-stage code storage scheme

[0140] In remote upgrade projects, to address upgrade failures and prevent system malfunctions, the previous functional version is backed up before the update is written. This ensures that the previous version can be reloaded in case of upgrade failure. This embodiment proposes a two-segment code storage scheme based on storing upgrade code for both old and new versions. Two normal functional code storage areas are divided within Flash memory: Functional Code Area I and Functional Code Area II. These areas serve as backups for each other during the remote upgrade process.

[0141] The update process is as follows Figure 11 As shown:

[0142] When the FPGA of the power terminal equipment leaves the factory, the initial version upgrade code is pre-stored in function code area II, while the initial version upgrade code is pre-stored in function code area I or left blank.

[0143] During the first upgrade, after the FPGA completes the loading of the program upgrade-specific code, when it is ready to update the upgrade code, the Flash function code area I is erased as the update code storage area, and then the subsequent upgrade steps are executed until the upgrade is successful.

[0144] During the second upgrade, after the FPGA completes the loading of the program upgrade-specific code, when it is ready to update the upgrade code, the Flash function code area II is erased as the update code storage area, and then the subsequent upgrade steps are executed until the upgrade is successful.

[0145] During the third upgrade, Flash's function code area I was erased as the update code storage area; during the fourth upgrade, Flash's function code area II was erased as the update code storage area.

[0146] In this cycle, function code region I and function code region II alternately serve as the storage area for update code.

[0147] In the above update process, the storage area for each updated code differs from the functional code area running before the upgrade. After each update, the startup address of the updated code area is configured. This ensures that after each update, the solidified code consists of two parts: the backup code from before the upgrade and the new code after the upgrade. This upgrade code storage structure enables the backup of the code before the upgrade without requiring additional time to move the code, saving upgrade time. The mutual backup also prevents code erasure during the device upgrade process in case of upgrade failure.

[0148] Example 2

[0149] This embodiment proposes a non-stop FPGA remote upgrade system for power terminal equipment, such as... Figure 12 As shown:

[0150] The cloud server remotely sends upgrade data to the ARM of the power terminal equipment;

[0151] ARM is used to receive upgrade data and transmit it to the FPGA of the power terminal equipment;

[0152] Two FPGAs are used to perform upgrade and normal operation tasks according to the ARM's configuration instructions; such as Figure 12As shown, the two FPGAs have identical structures and functions, with each FPGA containing a working module and a coordination module. Each FPGA is connected to a power supply. Each FPGA communicates with the ARM processor via an FSMC module. The coordination modules of the two FPGAs are connected via a dedicated bus. Each FPGA is connected to an SPI selector on the SPI bus via an SPI interface, and the coordination module of each FPGA is connected to the SPI selector via a simulated SPI interface. The SPI selector is connected to a unique Flash memory. The simulated SPI interface is used to simulate the Flash memory providing data services. The control signal output interface of each FPGA is connected to the SPI bus for outputting control signals during normal operation.

[0153] The FSMC module is used to establish a communication channel between the FPGA and the ARM.

[0154] Flash memory is used to store program upgrade code and upgrade code.

[0155] The cloud server is connected to the ARM, the ARM is connected to two FPGAs through the FSMC module, and the two FPGAs are connected to the Flash, so as to realize a method for remotely upgrading FPGAs of power terminal equipment without interrupting power supply.

[0156] The specific method for remotely upgrading the FPGA of a power terminal device without downtime is as follows: The ARM coordinates the SPI selector through two FPGAs, and upgrades the Flash memory using the remote FPGA upgrade method for power terminal devices described in Example 1, including four working modes:

[0157] Set up two FPGAs with identical structure and function, with a working module and a coordination module set up in each FPGA;

[0158] The two FPGAs are each connected to a power supply.

[0159] Each FPGA communicates with the ARM via the FSMC module; the coordination module of the two FPGAs is connected via a dedicated bus.

[0160] Each FPGA is connected to an SPI selector on the SPI bus via an SPI interface, and the coordination module of each FPGA is connected to the SPI selector via a simulated SPI interface; the SPI selector is connected to a unique Flash memory; the simulated SPI interface is used to simulate the Flash memory providing data services to external devices.

[0161] Each FPGA's control signal output interface is connected to the SPI bus to output control signals during normal operation;

[0162] The ARM processor coordinates the SPI gate through two FPGAs and uses the aforementioned power terminal equipment FPGA remote upgrade method to upgrade the Flash memory, including three modes:

[0163] Mode 1: Normal working state

[0164] The ARM controls the power supply and randomly powers on either FPGA I or FPGA II; the ARM controls the SPI selector to connect the SPI interface of the FPGA to be powered on and the Flash memory.

[0165] At this time, the ARM transfers the power terminal equipment's tasks to the powered FPGA through the FSMC module;

[0166] The ARM selects the latest upgrade code (the latest upgrade code is relative to the two versions of upgrade code currently stored in the Flash) function code area in the Flash through the powered-on FPGA, and the working module performs the operation.

[0167] Mode 2: A mixed state in which normal operation and normal upgrades occur simultaneously:

[0168] The ARM control power supply can be either FPGAⅠ or FPGAⅡ powered on first.

[0169] After power-on, the FPGA that is powered on first operates in mode one;

[0170] When preparing for an upgrade, the ARM controls the powered-on FPGA coordination module to map the address of the function code area of ​​the code to be upgraded in the Flash to the emulated SPI interface of the powered-on FPGA, and then controls the SPI selector to connect the path between the SPI interface of the FPGA to be powered on and the emulated SPI interface of the powered-on FPGA.

[0171] After completion, the ARM control power supply powers on the FPGA I and FPGA II that were not powered on.

[0172] After the FPGA that was powered on last completes its power-on process, the ARM selects the FPGA that was powered on last to be responsible for the upgrade work.

[0173] Mode 3: A mixed state in which normal operation and abnormal upgrades occur simultaneously.

[0174] If an upgrade fails, the FPGA responsible for the upgrade will restart and enter an abnormal upgrade mode. That is, the ARM controls the FPGA coordination module to map the addresses of the program upgrade function area and the failed upgrade function code area in the Flash to the emulated SPI interface of the normal FPGA. Then, it controls the SPI selector to connect the path between the SPI interface of the FPGA responsible for the upgrade and the emulated SPI interface of the normal FPGA, and then restarts the FPGA responsible for the upgrade.

[0175] After the FPGA responsible for the upgrade restarts, the upgrade process is completed again until the upgrade is successful.

[0176] Mode 4: A hybrid state in which normal operation and test operation modes occur simultaneously;

[0177] After the FPGA responsible for the upgrade successfully completes the code upgrade, the ARM controls the coordination module in the normally working FPGA to map the complete real physical address in Flash to the emulated SPI interface of the normally working FPGA. The SPI selector keeps the emulated SPI interface of the normally working FPGA (the FPGA that starts first) and the SPI interface of the FPGA responsible for the upgrade (the FPGA that starts later) connected.

[0178] The FPGA, which was started under ARM control, was restarted;

[0179] Because the upgrade was successful, the newly upgraded functional area code was automatically loaded after the FPGA started. After the FPGA started later was powered on, the ARM command for the FPGA started later was to work in normal working state, working synchronously with the FPGA started earlier and handling the same tasks. However, the control signals generated by the FPGA started later were not sent to the control signal output bus, but were sent to the coordination module of the FPGA started earlier through a dedicated bus. The coordination module of the FPGA started earlier compared whether the control information generated by the two FPGAs was consistent, and verified whether the effect of this upgrade was normal.

[0180] If the test results are normal, in order to complete the handover of tasks between the two FPGAs, the ARM controls at a certain moment:

[0181] (1) The SPI selector connects the SPI interface between the Flash and the FPGA that is started later;

[0182] (2) The FPGA that starts up later sends the control signals for normal operation to the control signal output bus;

[0183] (3) Cut off the power supply to the FPGA that was started first, so that it loses power.

[0184] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them; although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications can still be made to the specific implementation of the present invention or equivalent substitutions can be made to some technical features without departing from the spirit of the technical solutions of the present invention, and all such modifications and substitutions should be covered within the scope of the technical solutions claimed in the present invention.

Claims

1. A method for remotely upgrading an FPGA-based power terminal device without shutting down the system, characterized in that: include: Set up two FPGAs with identical structure and function, with a working module and a coordination module set up in each FPGA; The two FPGAs are connected to power supplies respectively; Each FPGA communicates with the ARM via the FSMC module; the coordination module of the two FPGAs is connected via a dedicated bus. Each FPGA is connected to an SPI selector on the SPI bus via an SPI interface, and the coordination module of each FPGA is connected to the SPI selector via a simulated SPI interface; the SPI selector is connected to a unique Flash memory; the simulated SPI interface is used to simulate the Flash memory providing data services to external devices. Each FPGA's control signal output interface is connected to the SPI bus to output control signals during normal operation; The ARM processor coordinates the SPI gate through two FPGAs. The specific method for remotely upgrading FPGAs in power terminal equipment is as follows: After the cloud server completes the preparations for the upgrade, it sends the remote upgrade command. After receiving the remote upgrade command, the ARM of the power terminal equipment begins the remote upgrade process. First, it controls the FPGA to power off, then loads the upgrade program. At the same time, the ARM receives and stores the upgrade code data. After the FPGA is powered off and restarted, it automatically loads the dedicated program upgrade code; the dedicated program upgrade code only has the functions required for the FPGA code upgrade process. The Flash memory is pre-divided into a program upgrade function area and an update code storage area, wherein the program upgrade-specific code is stored in the program upgrade function area; After the FPGA completes the loading of the dedicated upgrade code, it prepares to update the upgrade code and erases the Flash update code storage area. After the FPGA erases the Flash update code storage area, it writes the upgrade code. After the FPGA completes the upgrade code writing to the Flash, the ARM configures the FPGA to reload to the Flash's updated code storage area and performs a reload operation on the FPGA. ARM checks the FPGA status after reloading. If the reloading is successful, it runs normally and updates the code after the update. If loading fails, the upgrade code program will not run properly, and Flash will reload the upgrade-specific code. ARM returns a success or failure indication to the cloud server. The aforementioned FPGA remote upgrade method for power terminal equipment is used to upgrade the Flash memory, including Mode 2: a mixed state where normal operation and normal upgrade are performed simultaneously. The ARM control power supply can be either FPGAⅠ or FPGAⅡ powered on first. After power-on, the ARM controls the SPI selector to connect the SPI interface of the FPGA to be powered on and the Flash memory. At this time, the ARM transfers the power terminal equipment's tasks to the powered FPGA through the FSMC module; The ARM selects the function code area of ​​the latest upgrade code in the Flash memory through the powered-on FPGA, and the working module performs the operation. When preparing for an upgrade, the ARM controls the powered-on FPGA coordination module to map the address of the function code area of ​​the code to be upgraded in the Flash to the emulated SPI interface of the powered-on FPGA, and then controls the SPI selector to connect the path between the SPI interface of the FPGA to be powered on and the emulated SPI interface of the powered-on FPGA. After completion, the ARM control power supply powers on the FPGA I and FPGA II that were not powered on. After the FPGA that was powered on last completes its power-on process, the ARM selects the FPGA that was powered on last to be responsible for the upgrade work.

2. The method for remotely upgrading FPGA of power terminal equipment without shutdown as described in claim 1, characterized in that: The update code storage area is divided into functional code area I, which stores the latest upgrade code, and functional code area II, which stores the next newest upgrade code. The next newest upgrade code is the old version upgrade code that was running before the upgrade. After the FPGA completes the loading of the dedicated upgrade code, when it is ready to update the upgrade code, the functional code area I of the Flash memory is erased as the storage area for the update code. Before ARM returns a success or failure indication to the cloud server, it also performs the following: The ARM decides whether to rewrite the upgrade code. If so, the FPGA rewrites the upgrade code to update it; otherwise, the ARM configures the FPGA to reload the function code area II at the Flash address, and the FPGA reloads the second-new upgrade code.

3. The method for remotely upgrading FPGA of power terminal equipment without shutdown as described in claim 2, characterized in that: When the FPGA of the power terminal equipment leaves the factory, the initial version upgrade code is pre-stored in function code area II, while the initial version upgrade code is pre-stored in function code area I or left blank. During the first upgrade, after the FPGA completes the loading of the program upgrade-specific code, when it is ready to update the upgrade code, the Flash function code area I is erased as the update code storage area, and then the subsequent upgrade steps are executed until the upgrade is successful. During the second upgrade, after the FPGA completes the loading of the program upgrade-specific code, when it is ready to update the upgrade code, the Flash function code area II is erased as the update code storage area, and then the subsequent upgrade steps are executed until the upgrade is successful. During the third upgrade, the Flash function code area I was erased as the update code storage area; During the fourth upgrade, Flash's function code area II was erased as the update code storage area; In this cycle, function code region I and function code region II alternately serve as the storage area for update code.

4. A method for remotely upgrading an FPGA-based power terminal device without shutting down the system, characterized in that: The FPGA remote upgrade method for power terminal equipment as described in claim 3 is used to upgrade the Flash memory, including the following modes: Mode 1: Normal working state The ARM controls the power supply and randomly powers on either FPGA I or FPGA II; the ARM controls the SPI selector to connect the SPI interface of the FPGA to be powered on and the Flash memory. At this time, the ARM transfers the power terminal equipment's tasks to the powered FPGA through the FSMC module; The ARM selects the function code area of ​​the latest upgrade code in the Flash memory through the powered-on FPGA, and the working module performs the operation. Mode 3: A mixed state in which normal operation and abnormal upgrades occur simultaneously. If an upgrade fails, the FPGA responsible for the upgrade will restart and enter an abnormal upgrade mode. That is, the ARM controls the FPGA coordination module to map the addresses of the program upgrade function area and the failed upgrade function code area in the Flash to the emulated SPI interface of the normal FPGA. Then, it controls the SPI selector to connect the path between the SPI interface of the FPGA responsible for the upgrade and the emulated SPI interface of the normal FPGA, and then restarts the FPGA responsible for the upgrade. After the FPGA responsible for the upgrade restarts, the upgrade process is completed again until the upgrade is successful.

5. The method for remotely upgrading FPGA of power terminal equipment without shutdown as described in claim 4, characterized in that, It also includes Mode 4: a hybrid state in which normal operation and test operation modes are carried out simultaneously; After the FPGA responsible for the upgrade successfully completes the code upgrade, the ARM controls the coordination module in the normally operating FPGA to map the complete real physical address in Flash to the emulated SPI interface of the normally operating FPGA. The SPI selector keeps the emulated SPI interface of the normally operating FPGA and the SPI interface of the FPGA responsible for the upgrade connected. The ARM controller is responsible for restarting the FPGA that is being upgraded; After the FPGA responsible for the upgrade is powered on, the ARM command for the FPGA responsible for the upgrade works in normal working state, working synchronously with the normal working FPGA and handling the same tasks. However, the control signals generated by the FPGA responsible for the upgrade are not sent to the control signal output bus, but are sent to the coordination module of the normal working FPGA through a dedicated bus. The coordination module of the normal working FPGA compares whether the control information generated by the two FPGAs is consistent, and verifies whether the effect of this upgrade is normal. If the test results are normal, in order to complete the handover of tasks between the two FPGAs, the ARM controls at a certain moment: (1) The SPI selector connects the SPI interface between the Flash and the FPGA responsible for the upgrade; (2) The FPGA responsible for the upgrade sends the control signals for normal operation to the control signal output bus; (3) Cut off the power supply to the FPGA that is working normally, so that it loses power.

6. A non-stop FPGA remote upgrade system for power terminal equipment, characterized in that, include: The cloud server remotely sends upgrade data to the ARM of the power terminal equipment; ARM is used to receive upgrade data and transmit it to the FPGA of the power terminal equipment; Two FPGAs are used to perform upgrade and normal operation tasks according to the ARM's configuration instructions; The FSMC module is used to establish a communication channel between the FPGA and the ARM. Flash memory is used to store program upgrade code and upgrade code. The cloud server is connected to the ARM, the ARM is connected to two FPGAs through the FSMC module, and the two FPGAs are connected to the Flash, so as to implement the non-stop power terminal equipment FPGA remote upgrade method according to any one of claims 1-5.

7. The FPGA remote upgrade system for power terminal equipment without shutdown as described in claim 6, characterized in that: The FPGA includes an FSMC module, a data storage module, an SPI module, a control module, and an upgrade configuration module; The data storage module is used to cache the upgrade code received by the FPGA through the FSMC module; The control module is used to perform corresponding operations according to the configuration instructions sent by the ARM, including erasure operations and upgrade code writing; The SPI module is used to implement the timing drive of the interface between the FPGA and the Flash. The upgrade configuration module is used to perform corresponding operations according to the configuration instructions sent by the ARM, including loading the starting address configuration and reloading the program.

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