Redundancy-based error detection in memory devices

Abstract

The present application relates to redundancy-based error detection in a memory device. A memory device may read multiple copies of a codeword from a memory and generate an error detection bit for each codeword copy indicating whether the memory device has detected an error in the codeword. Additionally, the memory device may compare the codeword copies and generate one or more match bits indicating whether corresponding portions of the codewords match. Using the combination of the error detection bits and the match bits, the memory device is able to determine the error status of each codeword.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 17 / 934,452, filed by SCHAEFER et al. on September 22, 2022, entitled “REDUNDANCY-BASED ERROR DETECTION IN AMEMORY DEVICE,” which is assigned to its assignee and is expressly incorporated herein by reference.

[0003] TECHNICAL FIELD The field relates to redundancy-based error detection in memory devices. Background Art

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, any of which can be stored. To access the stored information, a component can read (e.g., sense, detect, retrieve, identify, determine, evaluate) a stored state in a memory device. To store information, a component can write (e.g., program, set, assign) a state in a memory device.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-select memory, chalcogenide memory technology, "NOR" and "NAND" memory devices, and others. Memory cells can be described according to a volatile configuration or a non-volatile configuration. Memory cells configured in a non-volatile configuration can maintain a stored logic state for an extended period of time even in the absence of an external power source. Memory cells configured in a volatile configuration may lose the stored state when disconnected from the external power source. Summary of the invention

[0006] A method is described. The method may include: reading from a memory a first codeword including a first set of data bits representing a set of data and a second codeword including a second set of data bits representing the set of data; generating an error detection bit based at least in part on reading the first codeword from the memory, the error detection bit indicating whether an error has been detected in the first codeword; generating a match bit based at least in part on reading the first codeword and the second codeword from the memory, the match bit indicating whether a portion of the first codeword matches a corresponding portion of the second codeword; and determining an error state of the first codeword based at least in part on the match bit and the error detection bit.

[0007] A method is described. The method may include: transmitting a read command for a set of data associated with a first codeword and a second codeword, wherein the first codeword includes a first set of data bits representing the set of data, and wherein the second codeword includes a second set of data bits representing the set of data; determining, based at least in part on transmitting the read command, a match bit indicating whether a portion of the first codeword matches a corresponding portion of the second codeword, and an error detection bit indicating whether a memory device detected an error in the first codeword; and determining an error state of the first codeword based at least in part on the match bit and the error detection bit.

[0008] An apparatus is described. The apparatus may include: a memory; and a controller coupled to the memory and configured to cause the apparatus to: read from the memory a first codeword including a first set of data bits representing a set of data and a second codeword including a second set of data bits representing the set of data; generate an error detection bit based at least in part on reading the first codeword from the memory, the error detection bit indicating whether an error has been detected in the first codeword; generate a match bit based at least in part on reading the first codeword and the second codeword from the memory, the match bit indicating whether a portion of the first codeword matches a corresponding portion of the second codeword; and determine an error state of the first codeword based at least in part on the match bit and the error detection bit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system supporting redundancy-based error detection according to examples as disclosed herein is described.

[0010] Figure 2 An example of a memory die supporting redundancy based error detection according to examples as disclosed herein is described.

[0011] Figure 3 An example of a memory device supporting redundancy based error detection according to examples as disclosed herein is described.

[0012] Figure 4 An example of a process flow supporting redundancy-based error detection in a memory device according to examples as disclosed herein is described.

[0013] Figure 5 An example of a memory device supporting redundancy based error detection according to examples as disclosed herein is described.

[0014] Figure 6 An example of a process flow supporting redundancy-based error detection in a memory device according to examples as disclosed herein is described.

[0015] Figure 7 A block diagram of a memory device supporting redundancy based error detection according to examples as disclosed herein is shown.

[0016] Figure 8 A block diagram of a host device supporting redundancy-based error detection according to examples as disclosed herein is shown.

[0017] Fig. 9 and 10 A flow chart illustrating a method of supporting redundancy-based error detection in a memory device according to examples as disclosed herein is shown. DETAILED DESCRIPTION

[0018] A memory device may use on-device error correction techniques, such as error correction codes (ECC), to detect and potentially correct errors in codewords stored in the memory device. However, on-device error correction techniques, such as ECC, may not support error classification (e.g., to define what types of errors are in a codeword). In addition, on-device error correction techniques, such as ECC, may be limited (e.g., due to overhead reasons) to detecting a threshold number of errors per codeword (which may be referred to as ECC capability, among other terms), meaning that on-device error correction techniques, such as ECC, may not be able to detect errors that exceed the threshold number. In certain high-reliability applications (e.g., in automotive safety), techniques for determining the error status of codewords may be needed, including codewords with errors that exceed a threshold number of errors per codeword (e.g., ECC capability).

[0019] According to the techniques described herein, a memory device may determine the error status of a codeword (including a codeword with errors that exceed the ECC capability) by storing redundant copies of the codeword and generating error information bits for the codeword. For example, the memory device may generate an error detection bit for each codeword copy, the error detection bit indicating whether the memory device detected one or more errors in the codeword. Additionally, the memory device may compare the redundant copies of the codewords and generate one or more of A) a data match bit indicating whether the data bits of the codewords match or B) a parity match bit indicating whether the parity bits of the codewords match. Using the error information bits (e.g., the error detection bits or the match bits or both), the memory device may determine the error status of each codeword, which may be provided to a host device in some form so that the host device may initiate appropriate action.

[0020] First, in the reference Figure 1 and 2 The features of the present disclosure are described in the context of the systems and dies described in the present disclosure. First, in the context of the systems and dies described in the present disclosure, the features of the present disclosure are described in the context of the systems and dies described in the present disclosure. Figures 3 to 6 Features of the present disclosure are described in the context of the memory system and process flow described herein. Figures 7 to 10 These and other features of the present disclosure are further illustrated and referenced to apparatus diagrams and flow charts related to redundancy-based error detection in a described memory device.

[0021] Figure 1 An example of a system 100 that supports redundancy-based error detection according to examples as disclosed herein is illustrated. The system 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 with the memory device 110. The system 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0022] System 100 may include portions of an electronic device such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, system 100 may illustrate aspects of a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, or the like. Memory device 110 may be a component of system 100 that is operable to store data for one or more other components of system 100.

[0023] Portions of system 100 may be instances of host device 105. Host device 105 may be an instance of a processor (e.g., circuitry, processing circuitry, processing component) within a device that uses memory to perform processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop, a tablet, a smartphone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, a system on a chip (SoC), or some other fixed or portable electronic device, among other examples. In some examples, host device 105 may refer to hardware, firmware, software, or any combination thereof that implements the functionality of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host (e.g., host device 105).

[0024] Memory device 110 may be a stand-alone device or component that is operable to provide a physical memory address / space that may be used or referenced by system 100. In some examples, memory device 110 may be configured to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: a modulation scheme to modulate a signal, various pin configurations for communicating a signal, various form factors for physical packaging of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other functions.

[0025] Memory device 110 is operable to store data for components of host device 105. In some examples, memory device 110 (e.g., operating as an assist-type device of host device 105, operating as a slave-type device of host device 105) may respond to and execute commands provided by host device 105 through external memory controller 120. Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0026] Host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components (such as one or more peripheral components or one or more input / output controllers). The components of host device 105 may be coupled to each other using a bus 135.

[0027] The processor 125 is operable to provide functionality (e.g., control functionality) for the system 100 or the host device 105. The processor 125 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. In such examples, the processor 125 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, among other examples. In some examples, the external memory controller 120 may be implemented by or be part of the processor 125.

[0028] BIOS component 130 may be a software component including a BIOS operating as firmware that may initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage the flow of data between processor 125 and various components of system 100 or host device 105. BIOS component 130 may include instructions (e.g., programs, software) stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0029] The memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support capacity (e.g., expected capacity, specified capacity) for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more storage bodies, one or more tiles, one or more sectors), wherein each memory cell is operable to store one or more data bits. A memory device 110 including two or more memory dies 160 may be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.

[0030] The device memory controller 155 may include components (e.g., circuitry, logic) operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device 110. The device memory controller 155 may be operable to communicate with one or more of the external memory controller 120, one or more memory dies 160, or the processor 125. In some examples, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160.

[0031] In some examples, memory device 110 can communicate information (e.g., data, commands, or both) with host device 105. For example, memory device 110 can receive a write command indicating that memory device 110 is to store data received from host device 105, or receive a read command indicating that memory device 110 is to provide data stored in memory die 160 to host device 105, among other types of information communications.

[0032] The local memory controller 165 (e.g., local to the memory die 160) may include components (e.g., circuitry, logic) operable to control the operation of the memory die 160. In some examples, the local memory controller 165 may be operable to communicate (e.g., receive or transmit data or commands or both) with the device memory controller 155. In some examples, the memory device 110 may not include a device memory controller 155 and a local memory controller 165, or an external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120, or the processor 125, or any combination thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other components operable to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0033] The external memory controller 120 may be operable to enable communication of information (e.g., data, commands, or both) between components of the system 100 (e.g., between components of the host device 105 (e.g., the processor 125) and the memory device 110). The external memory controller 120 may process (e.g., convert or translate) communications exchanged between components of the host device 105 and components of the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or the host device 105, or the functions thereof described herein, may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 125 or other components of the system 100 or the host device 105. Although the external memory controller 120 is described as being external to the memory device 110, in some examples, the external memory controller 120 or the functions thereof described herein may be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165), or vice versa.

[0034] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium that carries information between host device 105 and memory device 110. Each channel 115 may include one or more signal paths (e.g., transmission media, conductors) between terminals associated with components of system 100. A signal path may be an example of a conductive path that is operable to carry a signal. For example, a channel 115 may be associated with a first terminal (e.g., including one or more pins, including one or more pads) at host device 105 and a second terminal at memory device 110. A terminal may be an example of a conductive input or output point of a device of system 100, and a terminal may be operable to serve as part of a channel.

[0035] The channels 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, the channels 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or any combination thereof. In some examples, signaling may be conveyed through the channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered for each clock cycle (e.g., on either the rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be registered for each clock cycle (e.g., on both the rising and falling edges of a clock signal).

[0036] The memory device may use on-device error correction techniques to detect and potentially correct errors in information stored in the memory device. For example, the memory device may use on-device ECC to detect and correct single bit errors (SBEs) that occur in stored codewords. A codeword may refer to a combination of data bits and parity bits generated based on the data bits. For example, each parity bit in a codeword may be generated by performing an "exclusive OR" (XOR) on a subset of the data bits according to an error correction code.

[0037] As memory devices shrink in size, a greater number of memory cells (which may have a smaller area for storing charge) may have retention challenges because data stored by the memory cells may be compromised unless the memory cells are frequently refreshed. However, applying frequent refresh operations to ensure the integrity of data in cells with retention challenges may undesirably increase power consumption of the memory. To save power, the memory device may apply refresh operations less frequently and use error correction, such as ECC, to detect and correct errors caused by memory cells with retention challenges. However, using ECC for memory cells with retention challenges may prevent the memory device from detecting additional errors (e.g., errors that exceed the capabilities of the ECC) that occur during operation of the memory device.

[0038] In order to enable detection and classification of errors (including errors that exceed the ECC capability), the memory device 110 may generate and store multiple copies of a codeword of a set of data bits. For example, the memory device 110 may store A) a first codeword including a first set of parity bits and a first copy of a set of data bits, and B) a second codeword including a second set of parity bits and a second copy of the set of data bits. After reading the codeword, the memory device may generate error information bits based on the codeword. For example, the memory device may generate an error detection bit indicating whether the memory device has detected an error in the codeword. In addition, the memory device generates one or more of A) a data match bit indicating whether the data bits of the codeword match and B) a parity match bit indicating whether the parity bits of the codeword match. The memory device may then use the error information bit to determine the error state of the codeword. This technology may allow the memory device to detect and classify errors that exceed the ECC capability without increasing the ECC capability (which may be associated with increased overhead), as well as other benefits.

[0039] Figure 2 An example of a memory die 200 supporting redundancy-based error detection according to an example disclosed herein is illustrated. The memory die 200 may be a reference Figure 11. An example of a memory die 160 is described. In some examples, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205 that may be programmed to store different logic states (e.g., programmed to be one of a set of two or more possible states). For example, the memory cell 205 may be operable to store one bit of information at a time (e.g., a logical 0 or a logical 1). In some examples, the memory cell 205 (e.g., a multi-level memory cell) may be operable to store more than one bit of information at a time (e.g., a logical 00, a logical 01, a logical 10, a logical 11). In some examples, the memory cells 205 may be arranged in an array, such as with reference to FIG. Figure 1 Memory array 170 is described.

[0040] In some examples, memory cell 205 may store charge representing a programmable state in a capacitor. A DRAM architecture may include a capacitor including a dielectric material for storing charge representing a programmable state. In other memory architectures, other storage devices and components are possible. For example, nonlinear dielectric materials may be used. Memory cell 205 may include a logic storage component, such as capacitor 230 and a switching component 235 (e.g., a cell select component). Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. A node of capacitor 230 may be coupled to a voltage source 240, which may be a cell plate reference voltage, such as Vpl, or may be grounded, such as Vss.

[0041] Memory die 200 may include access lines (e.g., word lines 210, digit lines 215) arranged in a pattern such as a grid-like pattern. Access lines may be conductive lines coupled to memory cells 205 and may be used to perform access operations on memory cells 205. In some examples, word lines 210 may be referred to as row lines. In some examples, digit lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, or bit lines, or the like, may be interchangeable without loss of understanding. Memory cells 205 may be positioned at the intersection of word lines 210 and digit lines 215.

[0042] By activating an access line, such as a word line 210 or a digit line 215, operations such as reading and writing can be performed on the memory cell 205. By biasing the word line 210 and the digit line 215 (e.g., applying a voltage to the word line 210 or the digit line 215), a single memory cell 205 can be accessed at its intersection. The intersection of a word line 210 and a digit line 215 in a two-dimensional or three-dimensional configuration can be referred to as the address of the memory cell 205. Activating a word line 210 or a digit line 215 can include applying a voltage to the respective line.

[0043] Access to the memory cell 205 may be controlled by a row decoder 220 or a column decoder 225, or any combination thereof. For example, the row decoder 220 may receive a row address from the local memory controller 260 and activate the word line 210 based on the received row address. The column decoder 225 may receive a column address from the local memory controller 260 and activate the digit line 215 based on the received column address.

[0044] Selecting or deselecting the memory cell 205 may be accomplished by activating or deactivating the switching component 235 using the word line 210. The capacitor 230 may be coupled to the digit line 215 using the switching component 235. For example, when the switching component 235 is deactivated, the capacitor 230 may be isolated from the digit line 215, and when the switching component 235 is activated, the capacitor 230 may be coupled to the digit line 215.

[0045] The sensing component 245 is operable to detect a state (e.g., charge) stored on the capacitor 230 of the memory cell 205 and determine a logic state of the memory cell 205 based on the stored state. The sensing component 245 may include one or more sense amplifiers to amplify or otherwise convert a signal originating from accessing the memory cell 205. The sensing component 245 may compare the signal detected from the memory cell 205 with a reference 250 (e.g., a reference voltage). The detected logic state of the memory cell 205 may be provided as an output of the sensing component 245 (e.g., to the input / output 255), and the detected logic state may be indicated to another component of a memory device (e.g., the memory device 110) that includes the memory die 200.

[0046] The local memory controller 260 may control access to the memory cell 205 through various components (eg, the row decoder 220, the column decoder 225, the sensing component 245). The local memory controller 260 may be a reference Figure 11. An example of a local memory controller 165 is described. In some examples, one or more of the row decoder 220, the column decoder 225, and the sense component 245 can be co-located with the local memory controller 260. The local memory controller 260 can be operated to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), translate the command or data (or both) into information that can be used by the memory die 200, perform one or more operations on the memory die 200, and communicate data from the memory die 200 to the host (e.g., the host device 105) based on performing the one or more operations. The local memory controller 260 can generate row signals and column address signals to activate the target word line 210 and the target digital line 215. The local memory controller 260 can also generate and control various signals (e.g., voltages, currents) used during the operation of the memory die 200. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein may vary or be different for the various operations discussed in operating the memory die 200 .

[0047] The local memory controller 260 is operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activate operations, among others. In some examples, the access operations may be performed or otherwise coordinated by the local memory controller 260 in response to various access commands (e.g., from the host device 105). The local memory controller 260 is operable to perform other access operations not listed here, or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0048] The local memory controller 260 is operable to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 may be programmed to store a desired state (e.g., a logic state, a charge state). The local memory controller 260 may identify a target memory cell 205 on which a write operation is performed. The local memory controller 260 may identify a target word line 210 and a target digit line 215 coupled to the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 260 may activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The local memory controller 260 may apply a signal (e.g., a write pulse, a write voltage) to the digit line 215 during a write operation to store a specific state (e.g., a charge) in the capacitor 230 of the memory cell 205. The signal used as part of a write operation may include one or more voltage levels over a duration.

[0049] The local memory controller 260 is operable to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During a read operation, a state (e.g., a logic state, a charge state) stored in a memory cell 205 of the memory die 200 may be evaluated (e.g., read, determined, identified). The local memory controller 260 may identify a target memory cell 205 on which a read operation is to be performed. The local memory controller 260 may identify a target word line 210 and a target digit line 215 coupled to the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 260 may activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The target memory cell 205 may transmit a signal (e.g., a charge, a voltage) to the sensing component 245 in response to biasing the access line. The sensing component 245 may amplify the signal. Local memory controller 260 can activate sense component 245 (e.g., latch sense component) and compare the signal received from memory cell 205 with a reference (e.g., reference 250). Based on the comparison, sense component 245 can determine the logic state stored on memory cell 205.

[0050] To improve the reliability of information stored in memory die 200, a memory device including memory die 200 may implement the techniques described herein, which enable detection of errors in the stored information (including errors that exceed the ECC capability). For example, a memory device may store a first codeword for a first copy of a set of data bits and a second codeword for a second copy of the set of data bits. Storing redundant copies of codewords may allow a memory device to detect whether one of the codewords has an error (e.g., by comparing the codewords) during a read operation. However, without more information, the memory device may not be able to distinguish which codeword has an error. For example, a memory device may determine that a codeword (or a segment of a memory array) has an error, but may not be able to identify which codeword (or segment of a memory array) has the error. Although storing a third copy of a codeword (a technique known as triple redundancy) may allow a memory device to distinguish additional error information, storing three copies of a codeword may increase storage overhead and processing complexity, among other disadvantages.

[0051] According to the present disclosure, a memory device can improve (relative to other techniques) the ability of the memory device to determine error information of stored information by implementing a pseudo triple redundancy technique, which can also be referred to as an enhanced redundancy technique. In the pseudo triple redundancy technique, the memory device can store two copies of a codeword and use the two copies to generate error information bits (e.g., error detection bits, data matching bits, parity matching bits) indicating the error state of the codeword. The memory device can provide the error information bits (or the error state itself) to a host device so that the host device can take appropriate action.

[0052] Figure 3 An example of a memory device 300 supporting redundancy-based error detection according to an example as disclosed herein is described. The memory device 300 may be an example of a memory device as described herein. The memory device 300 may store redundant copies of codewords (e.g., one or more redundant copies), and use the codewords to generate error information bits indicating an error state of the codewords. The memory device 300 may be configured to support ECC decoding and codeword comparison in parallel (e.g., at at least partially overlapping times), which may reduce latency of the process relative to a memory device (e.g., memory device 500) that supports serial ECC decoding and codeword comparison. The configuration of the memory device 300 may be referred to as a parallel configuration.

[0053] At a high level, the memory device 300 may store a redundant copy of the codeword in the memory array. In response to a read command, the memory device 300 may read the codeword and input the codeword into the ECC engine 315 and the comparison engine 320, so that the memory device 300 may perform ECC decoding and codeword comparison in parallel (e.g., at partially or fully overlapping times). The ECC engine 315 may generate error detection bits, and the comparison engine 320 may generate matching bits (e.g., data matching bits, parity matching bits), which together indicate the error state of the codeword. The selection component 325 may use the error information bits to select one of the codewords for communication to the host device. In some examples, the selection component 325 may be a controller or logic.

[0054] The memory device 300 may include a memory array 305 configured to store information, such as codewords. The memory array 305 may be divided into two sections (e.g., section A and section B) and may be configured to potentially concurrently (e.g., at completely or partially overlapping times) perform the same access operation on the sections. For example, the memory array 305 may be configured to write a first codeword (e.g., codeword A) to a portion 310-a and a second codeword (e.g., codeword B) to a portion 310-b. The first codeword may include 1) a first set of data bits (data A) representing a first copy of a set of data and 2) a first set of parity bits (parity A). The second codeword may include 1) a second set of data bits (data B) representing a second copy of the set of data and 2) a second set of parity bits (parity B). The same set of parity bits (e.g., generated based on data A or data B) may be used for parity A and parity B. Alternatively, parity A and parity B may be generated separately (eg, parity A may be generated based on data A, and parity B may be generated based on data B).

[0055] Although described with reference to a single memory array, the pseudo triple redundancy techniques described herein may be implemented using multiple memory arrays. For example, a first codeword (codeword A) may be stored in a first memory array, and a second codeword (codeword B) may be stored in a second memory array. Other configurations for storing codewords are contemplated and within the scope of the present disclosure.

[0056] The ECC engine 315 may be configured to perform ECC decoding on the codeword and generate error detection bits based on the ECC decoding. For example, the ECC engine 315 may perform ECC decoding to detect and correct errors in the codeword (if errors exist). The ECC engine 315 may also generate error detection bits, the values ​​of which indicate whether the ECC engine 315 has detected an error in the codeword. For example, an error detection bit with a value of '0' may indicate that the ECC engine 315 has not detected an error in the codeword, while an error detection bit with a value of '1' may indicate that the ECC engine has indeed detected an error in the codeword. The error detection bits may also be referred to as syndrome check bits, error check bits, or other suitable terms. The ECC engine 315 may be configured to detect and correct single bit errors. Correcting an error in a codeword may refer to inverting a bit in an error state before communicating the codeword to another component of the memory device (and may not involve correction of errors in the memory array 305).

[0057] Thus, the ECC engine 315-a may perform ECC decoding on codeword A and may generate error detection bits A (ED_A) based on the ECC decoding for codeword A. Similarly, the ECC engine 315-b may perform ECC decoding on codeword B and may generate error detection bits B (ED_B) based on the ECC decoding for codeword B. Error detection bits A and error detection bits B may be communicated to the selection component 325 so that the selection component 325 may use the error detection bits as a basis for selecting one of codeword A and codeword B for returning to the host device.

[0058] In some examples, error detection bits for a codeword may be generated based on syndrome bits of the codeword. For example, the error detection bits for the codeword may be generated by ORing the syndrome bits of the codeword, which may be generated by XORing each stored parity bit with a corresponding parity bit generated from a read data bit of the codeword. For example, stored parity bit P0 may be XORed with generated parity bit P0, stored parity bit P1 may be XORed with generated parity bit P1, and so on, to generate the syndrome bits for the codeword. The syndrome bits resulting from the XOR operation may be ORed such that the resulting error detection bit indicates whether an error has been detected in the codeword.

[0059] The comparison engine 320 may be configured to compare codewords received from the memory array 305. For example, the comparison engine 320 may be configured to compare codeword A to codeword B. Comparing codeword A to codeword B may refer to comparing data A to data B, comparing parity A to parity B, or both. Thus, the comparison engine 320 may compare one or more portions of codeword A to one or more corresponding portions of codeword B. Comparing the codewords may allow the comparison engine 320 to determine if there is a mismatch between bits in the codewords.

[0060] The comparison engine 320 may generate a data match bit (M_Data) indicating whether there is a mismatch between data A and data B, may generate a parity match bit (M_Parity) indicating whether there is a mismatch between parity A and parity B, or both. If there is a mismatch in the data bits (e.g., a mismatch between data A and data B), the comparison engine 320 may generate a data match bit (M_Data) having a value of '1'. If the data bits match (e.g., if each bit in data A has the same value as the corresponding bit in data B), the comparison engine 320 may generate a data match bit (M_Data) having a value of '0'. If there is a mismatch in the parity bits (e.g., a mismatch between parity A and parity B), the comparison engine 320 may generate a parity bit (M_Parity) having a value of '1'. If the parity bits match (e.g., if each bit in parity A has the same value as the corresponding bit in parity B), the comparison engine 320 can generate a parity match bit (M_Parity) having a value of '0.' The data match bit, the parity match bit, or both can be communicated to the selection component 325 so that the selection component 325 can use the match bit as a basis for selecting one of codeword A and codeword B for returning to the host device.

[0061] In some examples, the memory device 300 may count the number of mismatches between portions of the codewords. For example, the memory device 300 may count the number of mismatches between data A and data B (e.g., data bits having the same bit position but different values). Additionally, or alternatively, the memory device 300 may count the number of mismatches between parity A and parity B (e.g., parity bits having the same bit position but different values). The number of mismatches per codeword may be used to provide additional insight into the reliability and functionality of the memory array 305.

[0062] Memory device 300 (eg, via selection component 325) can use the error information bits to determine the error status of the codewords. For example, memory device 300 can use Table 1, error detection bits, data match bits, and parity match bits to determine the error status of codeword A and the error status of codeword B.

[0063] Table 1 - Error Status Based on Error Information Bits for Parallel Configuration

[0064]

[0065]

[0066] The parallel configuration of memory device 300 may allow memory device 300 to be more efficient than alternative configurations (e.g., Figure 5The serial configuration described above can determine the error status of a codeword faster (with lower latency). However, the error status information provided by the parallel configuration may not be as comprehensive as the error status information provided by the serial configuration, which may result in reduced diagnostic coverage and / or the memory device 300 complying with fewer data requests relative to a memory device having a serial configuration.

[0067] In some examples, the selection component 325 may use Table 1 to select between codewords for communication to the host device. For example, the selection component 325 may determine whether to communicate data A from codeword A or data B from codeword B. If none of the codewords has an error, the selection component 325 may select any codeword for communication to the host device. If codeword A is error-free and the error state of codeword B is unknown, the memory device 300 may select codeword A for communication (or vice versa). If the error state of both codewords is unknown, the memory device may 1) select any codeword for communication and indicate the error state of the codeword, or 2) not select any codeword for communication and may instead communicate an error flag. If codeword A is error-free and codeword B has an error, the memory device 300 may select codeword A for communication (or vice versa). If data A and data B are each error-free, but parity A and parity B each have one or more errors, the memory device may select any codeword for communication. If both codewords have one or more errors, the memory device may 1) select either codeword for communication and indicate the error status of the codeword, or 2) select neither codeword for communication and may communicate an error flag instead.

[0068] In addition to communicating the selected data to the host device, the memory device 300 may also communicate or otherwise provide an indication of an error status of one or both of the codewords to the host device. In some examples, the memory device 300 may provide the error status by writing the error status to one or more mode registers at the memory device 300 for the host device to read. In other examples, the memory device 300 may provide the error status by writing error information bits to one or more mode registers at the memory device 300 for the host device to read. The host device may read the mode register periodically or in response to a trigger condition (e.g., receiving a prompt from the memory device 300).

[0069] In some examples, memory device 300 may provide error status by transmitting an error status to a host device (e.g., via a communication bus between memory device 300 and the host device). In other examples, memory device 300 may provide error status by transmitting error information bits to a host device (e.g., via a communication bus between memory device 300 and the host device).

[0070] The host device may determine the error status of the codeword based on the indication of the error status provided by the memory device 300, and may perform one or more operations based on the error status. For example, if the error status indicates that the data received by the host device is error-free, the host device may process the data. If the error status indicates that the received data has an error (e.g., an uncorrectable error), the host device may discard the data and enter a safe mode. An uncorrectable error may refer to a number of errors that exceeds the ECC capability. For example, if the ECC engine 315 is configured to detect and correct single-bit errors, the uncorrectable error may refer to a multi-bit error. If the error status indicates that one of the codewords has an error, the host device may record the address associated with the codeword as part of the error recording process to ensure the reliability of the memory device 300. For example, if a threshold number of errors accumulate in a row, the host device may retire a portion of the memory (e.g., a row) (e.g., no longer use the portion). Other actions performed by the host device are contemplated and within the scope of the present disclosure.

[0071] Therefore, memory device 300 may determine the error status of a codeword by storing a redundant copy of the codeword and using the codeword to generate error information bits.

[0072] Figure 4 An example of a process flow 400 for supporting redundancy-based error detection in a memory device according to an example disclosed herein is described. Various aspects of the process flow 400 may be implemented by a memory device as described herein. For example, aspects of the process flow 400 may be implemented by a memory device as described herein. Figure 3 4. By implementing aspects of process flow 400, a memory device may determine an error status of a codeword associated with a set of data requested by a host device.

[0073] Prior to 405, the memory device may receive (e.g., from a host device) a write command for a set of data. In response to the write command, the memory device may generate a first codeword (e.g., codeword A) that includes a first set of parity bits (parity A) and a first set of data bits (data A) representing the set of data. The memory device may also generate a second codeword (e.g., codeword B) that includes a second set of parity bits (parity B) and a second set of data bits (data B) representing the set of data. The memory device may then store the first codeword and the second codeword in a memory.

[0074] At 405, the memory device may receive (e.g., from a host device) a read command for the set of data. At 410, the memory device may read a first codeword (e.g., codeword A) and a second codeword (e.g., codeword B) associated with the set of data. The memory device may read the first codeword and the second codeword based on (e.g., in response to) the read command.

[0075] At 415, the memory device may compare the codewords. For example, the memory device may (e.g., via comparison engine 320) compare a first portion of a first codeword (e.g., data A) with a corresponding first portion of a second codeword (e.g., data B). The memory device may additionally or alternatively compare a second portion of the first codeword (e.g., parity A) with a corresponding second portion of the second codeword (e.g., parity B). At 420, the memory device may (e.g., via comparison engine 320) generate one or more match bits. For example, the memory device may generate a data match bit indicating whether there is a mismatch between data A and data B. The memory device may additionally or alternatively generate a parity match bit indicating whether there is a mismatch between parity A and parity B. A mismatch between two groups of bits may refer to corresponding bits in the same bit position in each group having different values.

[0076] At 425, which may partially or completely overlap with 415 in time, the memory device may decode the codewords (e.g., via the ECC engine 315). For example, the memory device may decode a first codeword (e.g., codeword A) using the ECC engine 315-a and may decode a second codeword (e.g., codeword B) using the ECC engine 315-b. At 430, the memory device may determine (e.g., via the ECC engine 315) whether any errors were detected in the codewords during decoding. If any errors are detected at 430, the memory device may correct the errors at 435 (e.g., by the ECC engine 315). For example, if an error is detected in the first codeword (e.g., codeword A), the ECC engine 315-a may correct the error by inverting the bits that are in the error state. If an error is detected in the second codeword (e.g., codeword B), the ECC engine 315-b may correct the error by inverting the bits that are in the error state.

[0077] At 440, the memory device may generate (e.g., via the ECC engine 315) one or more error detection bits. The error detection bits may be generated based on the decoding. For example, the ECC engine 315-a may generate an error detection bit ED_A based on decoding of a first codeword (e.g., codeword A) to indicate whether an error was detected in the first codeword. Similarly, the ECC engine 315-b may generate an error detection bit ED_B based on decoding of a second codeword (e.g., codeword B) to indicate whether an error was detected in the second codeword.

[0078] Because codeword comparison occurs in parallel with ECC decoding, codeword comparison is independent of ECC decoding; and ECC decoding is independent of codeword comparison. In other words, the codewords compared by comparison engine 320 may not feature any corrections performed by ECC engine 215.

[0079] At 445, the memory device may communicate the error information bits to the selection component 325. For example, the ECC engine 315 may communicate the error detection bits to the selection component 325, and the comparison engine 320 may communicate the match bits to the selection component 325.

[0080] At 450, the memory device may (e.g., via the selection component 325) use the error information bits to determine an error state of the codeword. For example, the memory device may determine an error state of a first codeword (e.g., codeword A), and may determine an error state of a second codeword (e.g., codeword B). The error state of the first codeword may be determined based on the data match bit M_Data, the parity bit M_Parity, the error detection bit ED_A, or any combination thereof. The error state of the second codeword may be determined based on the data match bit M_Data, the parity match bit M_Parity, the error detection bit ED_B, or any combination thereof. In some examples, the error state may be determined based on Table 1.

[0081] At 455, the memory device may select (e.g., via selection component 325) one of the codewords for communication to the host device. For example, the memory device may select codeword A or codeword B for communication to the host device. The memory device may select the codeword for communication based on the error status of the codeword. For example, if one codeword is error-free and the other codeword has an error, the memory device may select the error-free codeword for communication to the host device. At 460, the memory device may provide one or both of the error status of the codewords to the host device. For example, the memory device may transmit an error status or an error information bit to the host device. Alternatively, the memory device may write the error status or information bit to one or more registers at the memory device for the host device to read.

[0082] Thus, the memory device may determine an error state for a codeword associated with a set of data requested by a host device. Alternative examples of the foregoing may be implemented, where some operations are performed in a different order than described, in parallel, or not performed at all. In some cases, the operations may include additional features not mentioned herein, or additional operations may be added. In addition, one or more operations may be performed multiple times, or certain combinations of operations may be repeated or looped.

[0083] Figure 5An example of a memory device 500 supporting redundancy-based error detection according to an example as disclosed herein is described. The memory device 500 may be an example of a memory device as described herein. The memory device 500 may store redundant copies of codewords and use the codewords to generate error information bits indicating an error state of the codewords. The memory device 500 may be configured to support serial (e.g., one-by-one) ECC decoding and codeword comparison, which may improve diagnostic coverage relative to a memory device (e.g., memory device 300) that supports parallel ECC decoding and codeword comparison. The configuration of the memory device 500 may be referred to as a serial configuration.

[0084] At a high level, memory device 500 operates similarly to memory device 300. For example, memory device 500 may store redundant copies of codewords in memory array 505, and may read codewords from memory array 505 in response to a read command. However, memory device 500 may perform ECC decoding and codeword comparison serially, rather than performing ECC decoding and codeword comparison in parallel. For example, memory device 500 may perform ECC decoding before comparing codewords so that the compared codewords include any corrections made by the ECC engine. Performing ECC decoding and codeword comparison serially (as opposed to in parallel) may improve diagnostic coverage at the expense of latency.

[0085] The memory device 500 may include a memory array 505 configured to store information, such as codewords. The memory array 505 may be divided into two sections (e.g., section A and section B) and may be configured to potentially perform the same access operation on the sections simultaneously (e.g., at completely or partially overlapping times). For example, the memory array 505 may be configured to write a first codeword (e.g., codeword A) to a portion 510-a and a second codeword (e.g., codeword B) to a portion 510-b. The first codeword may include 1) a first set of data bits (data A) representing a first copy of a set of data and 2) a first set of parity bits (parity A). The second codeword may include 1) a second set of data bits (data B) representing a second copy of the set of data and 2) a second set of parity bits (parity B).

[0086] The ECC engine 515 may be configured to perform ECC decoding on the codeword and generate error detection bits based on the ECC decoding. For example, the ECC engine 515 may perform ECC decoding to detect and correct errors in the codeword (if any). The ECC engine 515 may also generate an error detection bit, the value of which indicates whether the ECC engine 515 has detected an error in the codeword. For example, the ECC engine 515-a may perform ECC decoding on the codeword A and may generate error detection bit A (ED_A) for the codeword A based on the ECC decoding. Similarly, the ECC engine 515-b may perform ECC decoding on the codeword B and may generate error detection bit B (ED_B) for the codeword B based on the ECC decoding.

[0087] The comparison engine 520 may be configured to compare codewords received from the ECC engine 515. For example, the comparison engine 520 may be configured to compare codeword A, which may be received from the ECC engine 515-a, with codeword B, which may be received from the ECC engine 515-b. Because the comparison engine 520 operates on codewords from the ECC engine 515 (rather than codewords received directly from the memory array 505), the codewords operated on by the comparison engine 520 may include corrected bits. For example, if the ECC engine 515-a detects and corrects bits in codeword A, the comparison engine 520 may perform a comparison on the corrected codeword A. For example, if the ECC engine 515-b detects and corrects bits in codeword B, the comparison engine 520 may perform a comparison on the corrected codeword B.

[0088] The comparison engine 520 may generate a data match bit (M_Data) indicating whether there is a mismatch between data A and data B, may generate a parity match bit (M_Parity) indicating whether there is a mismatch between parity A and parity B, or both. If there is a mismatch in the data bits (e.g., a mismatch between data A and data B), the comparison engine 520 may generate a data match bit (M_Data) having a value of '1'. If the data bits match (e.g., if each bit in data A has the same value as the corresponding bit in data B), the comparison engine 520 may generate a data match bit (M_Data) having a value of '0'. If there is a mismatch in the parity bits (e.g., a mismatch between parity A and parity B), the comparison engine 520 may generate a parity bit (M_Parity) having a value of '1'. If the parity bits match (e.g., if each bit in parity A has the same value as the corresponding bit in parity B), then the comparison engine 520 can generate a parity match bit (M_Parity) having a value of '0'. In some examples, the memory device 500 can count the number of mismatches between portions of the codeword, as shown in FIG. Figure 3 described.

[0089] Memory device 500 (eg, via selection component 525) can use the error information bits to determine the error status of the codewords. For example, memory device 500 can use Table 2, error detection bits, data match bits, and parity match bits to determine the error status of codeword A and the error status of codeword B.

[0090] Table 2 - Error Status Based on Error Information Bits for Serial Configuration

[0091]

[0092]

[0093] Relative to a memory device having a parallel configuration, the serial configuration of the memory device 500 may allow the memory device 500 to improve diagnostic coverage and comply with more data requests. However, relative to alternative configurations, such as reference Figure 3 With the described parallel configuration, memory device 500 may take longer to determine the error status of a codeword.

[0094] In some examples, the comparison engine 520 may generate data match bits (M_Data) but not parity match bits (M_parity), which may reduce the complexity of the memory device 500 at the expense of reduced diagnostic coverage (e.g., inability to distinguish between data errors and parity errors). In such examples, the memory device 500 may use a subset of error information bits (e.g., error detection bits and data match bits) to determine the error state of a codeword. For example, the memory device 500 may use Table 3, error detection bits, and data match bits to determine the error state of codeword A and the error state of codeword B.

[0095] Table 3 - Error status based on ED bit and data match bit for serial configuration

[0096]

[0097]

[0098] In some examples, the memory device 500 may generate error detection bits but not data match bits (M_Data) or parity match bits (M_parity), which may reduce the complexity of the memory device 500 at the expense of reduced diagnostic coverage (e.g., inability to distinguish between data errors and parity errors). In such examples, the memory device 500 may use a subset of error information bits (e.g., error detection bits) to determine the error state of a codeword. For example, the memory device 500 may use Table 4 and error detection bits to determine the error state of codeword A and the error state of codeword B.

[0099] Table 4 - ED bit based error states for serial configuration

[0100] ED_A ED_B A-state B-state 0 0 Codeword A has no errors Codeword B has no errors 0 1 Codeword A has no errors Codeword B error 1 0 Codeword A error Codeword B has no errors 1 1 Codeword A error Codeword B error

[0101] Selection component 525 can use Table 2, Table 3, or Table 4 to select between codewords for communication to the host device. For example, selection component 525 can determine whether to communicate data A from codeword A or data B from codeword B. In some examples, selection component 525 can select the codeword with the fewest errors overall or in the fewest errors in the data bits for communication.

[0102] In addition to communicating the selected data to the host device, the memory device 500 may communicate or otherwise provide an indication of an error status of one or both of the codewords to the host device. In some examples, the memory device 500 may provide the error status by writing the error status to one or more mode registers at the memory device 500 for the host device to read. In other examples, the memory device 300 may provide the error status by writing error information bits to one or more mode registers at the memory device 500 for the host device to read. The host device may read the mode register periodically or in response to a trigger condition (e.g., receiving a prompt from the memory device 500).

[0103] In some examples, memory device 500 may provide the error status by transmitting the error status to a host device (e.g., via a communication bus between memory device 500 and the host device). In other examples, memory device 500 may provide the error status by transmitting error information bits to the host device (e.g., via a communication bus between memory device 500 and the host device). The host device may determine the error status of the codeword based on the indication of the error status provided by memory device 500, and perform one or more actions based on the error status.

[0104] Therefore, memory device 500 can determine the error status of a codeword by storing a redundant copy of the codeword and using the codeword to generate error information bits.

[0105] Figure 6 An example of a process flow 600 for supporting redundancy-based error detection in a memory device according to an example disclosed herein is described. Various aspects of the process flow 600 can be implemented by a memory device as described herein. For example, aspects of the process flow 600 can be implemented by a memory device as described in reference to Figure 5 6. By implementing aspects of process flow 600, a memory device may determine an error status of a codeword associated with a set of data requested by a host device.

[0106] Prior to 605, the memory device may receive (e.g., from a host device) a write command for a set of data. In response to the write command, the memory device may generate a first codeword (e.g., codeword A) that includes a first set of parity bits (parity A) and a first set of data bits (data A) representing the set of data. The memory device may also generate a second codeword (e.g., codeword B) that includes a second set of parity bits (parity B) and a second set of data bits (data B) representing the set of data. The memory device may then store the first codeword and the second codeword in a memory.

[0107] At 605, the memory device may receive (e.g., from a host device) a read command for the set of data. At 610, the memory device may read a first codeword (e.g., codeword A) and a second codeword (e.g., codeword B) associated with the set of data. The memory device may read the first codeword and the second codeword based on (e.g., in response to) the read command.

[0108] At 615, the memory device may decode the codeword (e.g., via the ECC engine 515). For example, the memory device may decode a first codeword (e.g., codeword A) using the ECC engine 515-a, and may decode a second codeword (e.g., codeword B) using the ECC engine 515-b. At 620, the memory device may determine (e.g., via the ECC engine 515) whether any errors were detected in the codeword during decoding. If any errors are detected at 620, the memory device may correct the errors at 625 (e.g., by the ECC engine 515). For example, if an error is detected in the first codeword (e.g., codeword A), the ECC engine 515-a may correct the error by inverting the bits that are in the error state. If an error is detected in the second codeword (e.g., codeword B), the ECC engine 515-b may correct the error by inverting the bits that are in the error state.

[0109] At 630, the memory device may generate (e.g., via the ECC engine 515) one or more error detection bits. The error detection bits may be generated based on the decoding. For example, the ECC engine 515-a may generate an error detection bit ED_A based on decoding of a first codeword (e.g., codeword A) to indicate whether an error was detected in the first codeword. Similarly, the ECC engine 515-b may generate an error detection bit ED_B based on decoding of a second codeword (e.g., codeword B) to indicate whether an error was detected in the second codeword.

[0110] At 635, the memory device may compare the codewords. For example, the memory device (e.g., via comparison engine 520) compares a first portion of a first codeword (e.g., data A) to a corresponding first portion of a second codeword (e.g., data B). The memory device may additionally or alternatively compare a second portion of the first codeword (e.g., parity A) to a corresponding second portion of the second codeword (e.g., parity B). The comparison of the codewords may occur after decoding the codewords so that the compared codewords include any corrections made during decoding.

[0111] At 640, the memory device (e.g., via comparison engine 520) may generate one or more match bits. For example, the memory device may generate a data match bit indicating whether there is a mismatch between data A and data B. The memory device may additionally or alternatively generate a parity match bit indicating whether there is a mismatch between parity A and parity B.

[0112] At 645, the memory device may communicate the error information bits to the selection component 525. For example, the ECC engine 515 may communicate the error detection bits to the selection component 525, and the comparison engine 520 may communicate the match bits to the selection component 525.

[0113] At 650, the memory device may (e.g., via the selection component 525) use the error information bits to determine an error state of the codeword. For example, the memory device may determine an error state of a first codeword (e.g., codeword A), and may determine an error state of a second codeword (e.g., codeword B). The error state of the first codeword may be determined based on the data match bit M_Data, the parity bit M_Parity, the error detection bit ED_A, or any combination thereof. The error state of the second codeword may be determined based on the data match bit M_Data, the parity match bit M_Parity, the error detection bit ED_B, or any combination thereof. In some examples, the error state may be determined based on Table 2, Table 3, or Table 4.

[0114] At 655, the memory device may (e.g., via selection component 525) select one of the codewords for communication to the host device. For example, the memory device may select codeword A or codeword B for communication to the host device. The memory device may select the codeword for communication based on the error status of the codeword. For example, if one codeword is error-free and the other codeword has an error, the memory device may select the error-free codeword for communication to the host device. At 660, the memory device may provide one or both of the error status of the codewords to the host device. For example, the memory device may transmit an error status or error information bit to the host device. Alternatively, the memory device may write the error status or information bit to one or more registers at the memory device for the host device to read.

[0115] Thus, the memory device may determine an error state for a codeword associated with a set of data requested by a host device. Alternative examples of the foregoing may be implemented, where some operations are performed in a different order than described, in parallel, or not performed at all. In some cases, the operations may include additional features not mentioned herein, or additional operations may be added. In addition, certain operations may be performed multiple times, or certain combinations of operations may be repeated or looped.

[0116] Figure 7 A block diagram 700 is shown of a memory device 720 that supports redundancy-based error detection according to examples as disclosed herein. The memory device 720 may be a memory device as described in reference Figures 1 to 6 Memory device 720 or its various components may be examples of means for performing various aspects of redundancy-based error detection in a memory device as described herein. For example, memory device 720 may include memory array 725, error correction circuitry 730, comparison circuitry 735, controller 740, transmission circuitry 745, registers 750, or any combination thereof. Each of these components may communicate with each other, directly or indirectly (e.g., via one or more buses).

[0117] The memory array 725 may be configured to or otherwise support means for reading from the memory a first codeword comprising a first set of data bits representing a set of data and a second codeword comprising a second set of data bits representing a set of data. The error correction circuitry 730 may be configured to or otherwise support means for generating an error detection bit indicating whether an error has been detected in the first codeword based at least in part on reading the first codeword from the memory. The comparison circuitry 735 may be configured to or otherwise support means for generating a match bit indicating whether a portion of the first codeword matches a corresponding portion of the second codeword based at least in part on reading the first codeword and the second codeword from the memory. The controller 740 may be configured to or otherwise support means for determining an error state of the first codeword based at least in part on the match bit and the error detection bit.

[0118] In some examples, the controller 740 may be configured to or otherwise support means for selecting between the first set of data bits and the second set of data bits for communication to the host device based at least in part on an error state of the first codeword. In some examples, the transmission circuitry 745 may be configured to or otherwise support means for communicating the selected first set of data bits or the second set of data bits to the host device.

[0119] In some examples, the portion of the first codeword includes a first set of data bits and the portion of the second codeword includes a second set of data bits, and the comparison circuitry 735 may be configured to or otherwise support means for generating, based at least in part on reading the first codeword from a memory, a second match bit indicating whether a first set of parity bits in the first codeword matches a second set of parity bits in the second codeword, wherein an error state of the first codeword is determined based at least in part on the second match bit.

[0120] In some examples, a portion of the first codeword includes a first set of parity bits and a portion of the second codeword includes a second set of parity bits, and the comparison circuitry 735 may be configured to or otherwise support means for generating a second match bit indicating whether the first set of data bits matches the second set of data bits based at least in part on reading the first codeword from a memory, wherein an error state of the first codeword is determined based at least in part on the second match bit.

[0121] In some examples, error correction circuitry 730 may be configured or otherwise support means for decoding the first codeword and the second codeword, wherein the error detection bit is based at least in part on the decoding. In some examples, comparison circuitry 735 may be configured or otherwise support means for comparing the first set of data bits to the second set of data bits based at least in part on decoding the first codeword and the second codeword, wherein the match bit is generated based at least in part on the comparison.

[0122] In some examples, error correction circuitry 730 may be configured or otherwise support means for correcting errors in the first set of data bits based at least in part on decoding the first codeword, wherein the first set of data bits are compared to the second set of data bits after correcting the errors.

[0123] In some examples, error correction circuitry 730 may be configured or otherwise support means for decoding the first codeword and the second codeword, wherein the error detection bit is based at least in part on the decoding. In some examples, comparison circuitry 735 may be configured or otherwise support means for comparing the first set of data bits to the second set of data bits in parallel with decoding the first codeword and the second codeword, wherein a match bit is generated based at least in part on the comparison.

[0124] In some examples, the error correction circuitry 730 may be configured to or otherwise support means for generating a second error detection bit indicating whether an error has been detected in the second codeword based at least in part on reading the second codeword from the memory. In some examples, the controller 740 may be configured to or otherwise support means for determining an error state of the second codeword based at least in part on the matching bit and the second error detection bit.

[0125] In some examples, the controller 740 may be configured to or otherwise support means for selecting between the first set of data bits and the second set of data bits for communication to the host device based at least in part on an error state of the first codeword and an error state of the second codeword. In some examples, the transmission circuitry 745 may be configured to or otherwise support means for communicating the selected first set of data bits or the second set of data bits to the host device.

[0126] In some examples, register 750 may be configured as or otherwise support means for providing an indication of an error state of the first codeword to a host device. In some examples, register 750 may be configured as or otherwise support means for providing a match bit and an error detection bit to a host device.

[0127] Figure 8 A block diagram 800 is shown of a host device 820 supporting redundancy-based error detection according to an example as disclosed herein. The host device 820 may be a Figures 1 to 6 820 or its various components may be examples of means for performing various aspects of redundancy-based error detection in a memory device as described herein. For example, host device 820 may include transmission circuitry 825, controller 830, reception circuitry 835, or any combination thereof. Each of these components may communicate with each other, directly or indirectly (e.g., via one or more buses).

[0128] The transmission circuit system 825 may be configured to or otherwise support means for transmitting a read command for a set of data associated with a first codeword and a second codeword, wherein the first codeword includes a first set of data bits representing the set of data, and wherein the second codeword includes a second set of data bits representing the set of data. The controller 830 may be configured to or otherwise support means for determining, based at least in part on the transmission read command, a match bit indicating whether a portion of the first codeword matches a corresponding portion of the second codeword and an error detection bit indicating whether the memory device detected an error in the first codeword. In some examples, the controller 830 may be configured to or otherwise support means for determining an error state of the first codeword based at least in part on the match bit and the error detection bit.

[0129] In some examples, the error status indicates that the first codeword has an uncorrectable error, and controller 830 can be configured to or otherwise support means for entering the secure mode based at least in part on the error status of the first codeword indicating that the first codeword has an uncorrectable error.

[0130] In some examples, the portion of the first codeword includes a first set of data bits and the portion of the second codeword includes a second set of data bits, and the controller 830 may be configured to or otherwise support means for determining, based at least in part on the transfer read command, whether a first set of parity bits in the first codeword matches a second set of parity bits in the second codeword, wherein an error state of the first codeword is determined based at least in part on the second match bits.

[0131] In some examples, a portion of the first codeword includes a first set of parity bits and a portion of the second codeword includes a second set of parity bits, and the controller 830 may be configured to or otherwise support means for determining, based at least in part on the transmit read command, a second match bit indicating whether a first set of data bits in the first codeword matches a second set of data bits in the second codeword, wherein an error state of the first codeword is determined based at least in part on the second match bit.

[0132] In some examples, the receive circuitry 835 may be configured or otherwise support means for receiving the first set of data bits based at least in part on the transmission read command. In some examples, the controller 830 may be configured or otherwise support means for determining that the first set of data bits are error-free based at least in part on the error status.

[0133] In some examples, controller 830 may be configured or otherwise support means for reading one or more mode registers included in a memory device, wherein match bits and error detection bits are determined based at least in part on reading the one or more mode registers.

[0134] In some examples, receive circuitry 835 may be configured or otherwise support means for receiving indications of match bits and error detection bits from a memory device, wherein the match bits and error detection bits are determined based at least in part on receiving the indications.

[0135] Fig. 9 A flowchart illustrating a method 900 for supporting redundancy-based error detection in a memory device according to an example as disclosed herein is shown. The operations of the method 900 may be implemented by a memory device or components thereof as described herein. For example, the operations of the method 900 may be implemented by a memory device or components thereof as described in reference to Figures 1 to 7 The memory device described herein may be used to perform the functions described herein. In some examples, the memory device may execute a set of instructions to control the functional elements of the device to perform the functions described herein. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the functions described herein.

[0136] At 905, the method includes reading from a memory a first codeword including a first set of data bits representing a set of data and a second codeword including a second set of data bits representing the set of data. Operation 905 may be performed according to examples as disclosed herein. In some examples, aspects of operation 905 may be performed as described in reference to Figure 7 The described memory array 725 is implemented.

[0137] At 910, the method may include generating an error detection bit based at least in part on reading the first codeword from the memory, the error detection bit indicating whether an error has been detected in the first codeword. Operation 910 may be performed according to examples as disclosed herein. In some examples, aspects of operation 910 may be performed as described in reference to Figure 7 The error correction circuitry 730 described herein is implemented.

[0138] At 915, the method may include generating a match bit based at least in part on reading the first codeword and the second codeword from the memory, the match bit indicating whether a portion of the first codeword matches a corresponding portion of the second codeword. Operation 915 may be performed according to examples as disclosed herein. In some examples, aspects of operation 915 may be performed as described in reference to Figure 7 The comparison circuitry 735 described above is performed.

[0139] At 920, the method may include determining an error state of the first codeword based at least in part on the matching bits and the error detection bits. Operation 920 may be performed according to examples as disclosed herein. In some examples, aspects of operation 920 may be performed as described in reference to Figure 7 The controller 740 described above is executed.

[0140] In some examples, an apparatus described herein may perform a method such as method 900. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0141] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for: reading from a memory a first codeword comprising a first set of data bits representing a set of data and a second codeword comprising a second set of data bits representing the set of data; generating an error detection bit based at least in part on reading the first codeword from the memory, the error detection bit indicating whether an error has been detected in the first codeword; generating a match bit based at least in part on reading the first codeword and the second codeword from the memory, the match bit indicating whether a portion of the first codeword matches a corresponding portion of the second codeword; and determining an error state of the first codeword based at least in part on the match bit and the error detection bit.

[0142] Aspect 2: The method, apparatus, or non-transitory computer-readable medium of aspect 1, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: selecting between the first set of data bits and the second set of data bits for communication to a host device based at least in part on the error state of the first codeword; and communicating the selected first set of data bits or second set of data bits to the host device.

[0143] Aspect 3: A method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 2, wherein the portion of the first codeword includes the first set of data bits and the portion of the second codeword includes the second set of data bits, and the method, apparatus, and non-transitory computer-readable medium further include operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for generating a second match bit based at least in part on reading the first codeword from a memory, the second match bit indicating whether a first set of parity bits in the first codeword matches a second set of parity bits in the second codeword, wherein the error state of the first codeword is determined at least in part based on the second match bit.

[0144] Aspect 4: A method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 3, wherein the portion of the first codeword includes a first set of parity bits and the portion of the second codeword includes a second set of parity bits, and the method, apparatus, and non-transitory computer-readable medium further include operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for generating a second match bit based at least in part on reading the first codeword from a memory, the second match bit indicating whether the first set of data bits matches the second set of data bits, wherein the error state of the first codeword is determined at least in part based on the second match bit.

[0145] Aspect 5: The method, apparatus, or non-transitory computer-readable medium of any one of aspects 1 to 4, further comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for: decoding the first codeword and the second codeword, wherein the error detection bit is based at least in part on the decoding; and comparing the first set of data bits to the second set of data bits based at least in part on decoding the first codeword and the second codeword, wherein the match bit is generated based at least in part on the comparison.

[0146] Aspect 6: The method, apparatus, or non-transitory computer-readable medium of aspect 5, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for correcting errors in the first set of data bits based at least in part on decoding the first codeword, wherein the first set of data bits are compared to the second set of data bits after correcting the errors.

[0147] Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any one of aspects 1 to 6, further comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for: decoding the first codeword and the second codeword, wherein the error detection bit is based at least in part on the decoding; and comparing the first set of data bits with the second set of data bits in parallel with decoding the first codeword and the second codeword, wherein the match bit is generated based at least in part on the comparison.

[0148] Aspect 8: The method, apparatus, or non-transitory computer-readable medium of any of Aspects 1 to 7, further comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for: generating a second error detection bit based at least in part on reading the second codeword from a memory, the second error detection bit indicating whether an error has been detected in the second codeword; and determining an error state of the second codeword based at least in part on the match bit and the second error detection bit.

[0149] Aspect 9: The method, apparatus, or non-transitory computer-readable medium of Aspect 8, further comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for: selecting between the first set of data bits and the second set of data bits for communication to a host device based at least in part on the error state of the first codeword and the error state of the second codeword; and communicating the selected first set of data bits or second set of data bits to the host device.

[0150] Aspect 10: The method, apparatus, or non-transitory computer-readable medium of any one of aspects 1 to 9, further comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for providing an indication of the error state of the first codeword to a host device.

[0151] Aspect 11: The method, apparatus, or non-transitory computer-readable medium of any one of aspects 1 to 10, further comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for providing the match bits and the error detection bits to a host device.

[0152] Fig.10 A flowchart illustrating a method 1000 for supporting redundancy-based error detection according to an example disclosed herein is shown. The operations of the method 1000 may be implemented by a host device or components thereof as described herein. For example, the operations of the method 1000 may be implemented by a host device or components thereof as described herein. Figures 1 to 6 8 and 8 are performed by a host device. In some examples, the host device may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the host device may use dedicated hardware to perform aspects of the described functions.

[0153] At 1005, the method may include transmitting a read command for a set of data associated with a first codeword and a second codeword, wherein the first codeword includes a first set of data bits representing the set of data, and wherein the second codeword includes a second set of data bits representing the set of data. Operation 1005 may be performed according to examples as disclosed herein. In some examples, aspects of operation 1005 may be implemented as described in reference to Figure 8 The described transmission circuit system 825 is performed.

[0154] At 1010, the method may include determining, based at least in part on transmitting the read command, a match bit indicating whether a portion of the first codeword matches a corresponding portion of the second codeword, and an error detection bit indicating whether a memory device detected an error in the first codeword. Operation 1010 may be performed according to examples as disclosed herein. In some examples, aspects of operation 1010 may be performed as described in reference to Figure 8 The controller 830 described above is executed.

[0155] At 1015, the method may include determining an error state of the first codeword based at least in part on the matching bits and the error detection bits. Operation 1015 may be performed according to examples as disclosed herein. In some examples, aspects of operation 1015 may be performed as described in reference to Figure 8 The controller 830 described above is executed.

[0156] In some examples, an apparatus described herein may perform a method such as method 1000. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0157] Aspect 12: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for: transmitting a read command for a set of data associated with a first codeword and a second codeword, wherein the first codeword comprises a first set of data bits representing the set of data, and wherein the second codeword comprises a second set of data bits representing the set of data; determining, based at least in part on transmitting the read command, a match bit indicating whether a portion of the first codeword matches a corresponding portion of the second codeword, and an error detection bit indicating whether a memory device has detected an error in the first codeword; and determining an error state of the first codeword based at least in part on the match bit and the error detection bit.

[0158] Aspect 13: A method, apparatus, or non-transitory computer-readable medium according to Aspect 12, wherein the error status indicates that the first codeword has an uncorrectable error, and the method, apparatus, and non-transitory computer-readable medium further include operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for entering a secure mode based at least in part on the error status of the first codeword indicating that the first codeword has an uncorrectable error.

[0159] Aspect 14: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 12 to 13, wherein the portion of the first codeword includes the first set of data bits and the portion of the second codeword includes the second set of data bits, and the method, apparatus, and non-transitory computer-readable medium further include operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for determining a second match bit based at least in part on transmitting the read command, the second match bit indicating whether a first set of parity bits in the first codeword matches a second set of parity bits in the second codeword, wherein the error state of the first codeword is determined at least in part based on the second match bit.

[0160] Aspect 15: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 12 to 14, wherein the portion of the first codeword includes a first set of parity bits and the portion of the second codeword includes a second set of parity bits, and the method, apparatus, and non-transitory computer-readable medium further include operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for determining a second match bit based at least in part on transmitting the read command, the second match bit indicating whether the first set of data bits in the first codeword matches the second set of data bits in the second codeword, wherein the error state of the first codeword is determined at least in part based on the second match bit.

[0161] Aspect 16: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 12 to 15, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving the first set of data bits based at least in part on transmitting the read command; and determining that the first set of data bits are error-free based at least in part on the error status.

[0162] Aspect 17: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 12 to 16, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for reading one or more mode registers included in the memory device, wherein the match bits and the error detection bits are determined at least in part based on reading the one or more mode registers.

[0163] Aspect 18: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 12 to 17, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for receiving an indication of the match bit and the error detection bit from the memory device, wherein the match bit and the error detection bit are determined at least in part based on receiving the indication.

[0164] It should be noted that the methods described herein describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0165] A device is described. The following provides an overview of aspects of the device as described herein:

[0166] Aspect 19: An apparatus comprising: a memory; and a controller coupled to the memory and configured to cause the apparatus to: read from the memory a first codeword comprising a first set of data bits representing a set of data and a second codeword comprising a second set of data bits representing the set of data; generate an error detection bit based at least in part on reading the first codeword from the memory, the error detection bit indicating whether an error has been detected in the first codeword; generate a match bit based at least in part on reading the first codeword and the second codeword from the memory, the match bit indicating whether a portion of the first codeword matches a corresponding portion of the second codeword; and determine an error state of the first codeword based at least in part on the match bit and the error detection bit.

[0167] Aspect 20: An apparatus according to Aspect 19, wherein the controller is further configured to cause the apparatus to: select between the first set of data bits and the second set of data bits for communication to a host device based at least in part on the error state of the first codeword; and communicate the selected first set of data bits or second set of data bits to the host device.

[0168] Aspect 21: An apparatus according to any one of Aspects 19 to 20, wherein the portion of the first codeword includes the first set of data bits and the portion of the second codeword includes the second set of data bits, and wherein the controller is further configured to cause the apparatus to: generate a second match bit based at least in part on reading the first codeword from a memory, the second match bit indicating whether a first set of parity bits in the first codeword matches a second set of parity bits in the second codeword, wherein the error state of the first codeword is determined at least in part based on the second match bit.

[0169] Aspect 22: An apparatus according to any one of Aspects 19 to 21, wherein the portion of the first codeword includes a first set of parity bits and the portion of the second codeword includes a second set of parity bits, and wherein the controller is further configured to cause the apparatus to: generate a second match bit based at least in part on reading the first codeword from a memory, the second match bit indicating whether the first set of data bits matches the second set of data bits, wherein the error state of the first codeword is determined at least in part based on the second match bit.

[0170] Aspect 23: An apparatus according to any one of Aspects 19 to 22, wherein the controller is further configured to cause the apparatus to: decode the first codeword and the second codeword, wherein the error detection bit is based at least in part on the decoding; and compare the first set of data bits with the second set of data bits based at least in part on decoding the first codeword and the second codeword, wherein the match bit is generated based at least in part on the comparison.

[0171] Aspect 24: An apparatus according to Aspect 23, wherein the controller is further configured to cause the apparatus to: correct errors in the first set of data bits based at least in part on decoding the first codeword, wherein the first set of data bits are compared with the second set of data bits after correcting the errors.

[0172] Aspect 25: An apparatus according to any one of aspects 19 to 24, wherein the controller is further configured to cause the apparatus to: decode the first codeword and the second codeword, wherein the error detection bit is based at least in part on the decoding; and compare the first set of data bits with the second set of data bits in parallel with decoding the first codeword and the second codeword, wherein the match bit is generated based at least in part on the comparison.

[0173] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a bus of signals, where the bus may have various bit widths.

[0174] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components may be considered to be in electronic communication with (e.g., in conductive contact with, connected to, coupled to) one another if there is any electrical path (e.g., a conductive path) between the components that can support the flow of signals (e.g., charge, current, voltage) between the components at any time. At any given time, the conductive paths between components that are in electronic communication with (e.g., in conductive contact with, connected to, coupled to) one another may be open or closed based on the operation of the device that includes the connected components. The conductive paths between the connected components may be direct conductive paths between the components, or the conductive paths between the connected components may be indirect conductive paths that may include intermediate components (e.g., switches, transistors, or other components). In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0175] The term "coupled" refers to a condition that transitions from an open-circuit relationship between components, where signals are currently unable to communicate between the components (e.g., through conductive paths), to a closed-circuit relationship between the components, where signals are able to communicate between the components (e.g., through conductive paths). When a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components through conductive paths that previously did not allow signals to flow.

[0176] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. If an open circuit exists between components, then they are isolated from each other. For example, when a switch positioned between two components is opened, the components separated by the switch are isolated from each other. When a controller isolates two components, the controller causes a change that prevents a signal from flowing between the components using a conductive path that previously allowed the signal to flow.

[0177] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping method.

[0178] The switching components (e.g., transistors) discussed herein may represent field effect transistors (FETs) and may include a three-terminal component including a source (e.g., a source terminal), a drain (e.g., a drain terminal), and a gate (e.g., a gate terminal). The terminals may be connected to other electronic components by conductive materials (e.g., metals, alloys). The source and drain may be conductive and may include doped (e.g., heavily doped, degenerate) semiconductor regions. The source and drain may be separated by doped (e.g., lightly doped) semiconductor regions or channels. If the channel is n-type (e.g., most carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (e.g., most carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "on" or "activated." A transistor may be "off" or "deactivated" when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

[0179] The description set forth herein in conjunction with the drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" rather than "preferred" or "advantageous over other examples." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0180] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label without regard to the second reference label.

[0181] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions (e.g., code) on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. Features that implement the functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations.

[0182] For example, the various illustrative blocks and modules described in connection with the present disclosure may be implemented or executed with a processor, such as a DSP, an ASIC, an FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof designed to perform the functions described herein. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or any type of processor. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0183] As used herein, "or" as used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of"), including in the claims, indicates an inclusive list such that a list of at least one of (for example) A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be understood as a reference to a closed set of conditions. For example, an example step described as "based on condition A" can be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be understood in the same manner as the phrase "based at least in part on".

[0184] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media may be any available media that can be accessed by a computer. By way of example but not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device, or any other non-transitory media that can be used to carry or store a desired program code device in the form of an instruction or data structure and can be accessed by a computer or processor. In addition, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, optical cable, twisted pair, digital subscriber line (DSL), or wireless technology such as infrared, radio, and microwaves is used to transmit software from a website, server, or other remote source, then coaxial cable, optical cable, twisted pair, digital subscriber line (DSL), or wireless technology such as infrared, radio, and microwaves are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0185] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to one skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is in the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: reading from a memory a first codeword including a first set of data bits representing a set of data and a second codeword including a second set of data bits representing the set of data; generating an error detection bit based at least in part on reading the first codeword from the memory, the error detection bit indicating whether an error has been detected in the first codeword; generating a match bit based at least in part on reading the first codeword and the second codeword from the memory, the match bit indicating whether a portion of the first codeword matches a corresponding portion of the second codeword; and An error state of the first codeword is determined based at least in part on the matching bit and the error detection bit.

2. The method according to claim 1, further comprising: selecting between the first set of data bits and the second set of data bits for communication to a host device based at least in part on the error state of the first codeword; as well as The selected first set of data bits or second set of data bits is communicated to the host device.

3. The method of claim 1 , wherein the portion of the first codeword includes the first set of data bits and the portion of the second codeword includes the second set of data bits, the method further comprising: A second match bit is generated based at least in part on reading the first codeword from the memory, the second match bit indicating whether a first set of parity bits in the first codeword matches a second set of parity bits in the second codeword, wherein the error status of the first codeword is determined based at least in part on the second match bit.

4. The method of claim 1 , wherein the portion of the first codeword comprises a first set of parity bits and the portion of the second codeword comprises a second set of parity bits, the method further comprising: A second match bit is generated based at least in part on reading the first codeword from the memory, the second match bit indicating whether the first set of data bits matches the second set of data bits, wherein the error state of the first codeword is determined based at least in part on the second match bit.

5. The method according to claim 1, further comprising: decoding the first codeword and the second codeword, wherein the error detection bit is based at least in part on the decoding; as well as The first set of data bits is compared to the second set of data bits based at least in part on decoding the first codeword and the second codeword, wherein the matching bits are generated based at least in part on the comparison.

6. The method according to claim 5, further comprising: Errors in the first set of data bits are corrected based at least in part on decoding the first codeword, wherein the first set of data bits are compared to the second set of data bits after correcting the errors.

7. The method according to claim 1, further comprising: decoding the first codeword and the second codeword, wherein the error detection bit is based at least in part on the decoding; as well as The first set of data bits is compared to the second set of data bits in parallel with decoding the first codeword and the second codeword, wherein the matching bits are generated based at least in part on the comparison.

8. The method according to claim 1, further comprising: generating a second error detection bit based at least in part on reading the second codeword from the memory, the second error detection bit indicating whether an error has been detected in the second codeword; as well as An error state of the second codeword is determined based at least in part on the matching bit and the second error detection bit.

9. The method according to claim 8, further comprising: selecting between the first set of data bits and the second set of data bits for communication to a host device based at least in part on the error state of the first codeword and the error state of the second codeword; as well as The selected first set of data bits or second set of data bits is communicated to the host device.

10. The method according to claim 1, further comprising: An indication of the error status of the first codeword is provided to a host device.

11. The method according to claim 1, further comprising: The match bits and the error detection bits are provided to a host device.

12. A method comprising: transmitting a read command for a set of data associated with a first codeword and a second codeword, wherein the first codeword includes a first set of data bits representing the set of data, and wherein the second codeword includes a second set of data bits representing the set of data; determining, based at least in part on transmitting the read command, a match bit indicating whether a portion of the first codeword matches a corresponding portion of the second codeword and an error detection bit indicating whether a memory device detected an error in the first codeword; and An error state of the first codeword is determined based at least in part on the matching bit and the error detection bit.

13. The method of claim 12, wherein the error status indicates that the first codeword has an uncorrectable error, the method further comprising: A secure mode is entered based at least in part on the error status of the first codeword indicating that the first codeword has an uncorrectable error.

14. The method of claim 12, wherein the portion of the first codeword includes the first set of data bits and the portion of the second codeword includes the second set of data bits, the method further comprising: A second match bit is determined based at least in part on transmitting the read command, the second match bit indicating whether a first set of parity bits in the first codeword matches a second set of parity bits in the second codeword, wherein the error status of the first codeword is determined based at least in part on the second match bit.

15. The method of claim 12, wherein the portion of the first codeword includes a first set of parity bits and the portion of the second codeword includes a second set of parity bits, the method further comprising: and determining a second match bit based at least in part on transmitting the read command, the second match bit indicating whether the first set of data bits in the first codeword matches the second set of data bits in the second codeword, wherein the error state of the first codeword is determined based at least in part on the second match bit.

16. The method of claim 12, further comprising: receiving the first set of data bits based at least in part on transmitting the read command; as well as The first set of data bits is determined to be error-free based at least in part on the error status.

17. The method of claim 12, further comprising: One or more mode registers included in the memory device are read, wherein the match bits and the error detection bits are determined based at least in part on reading the one or more mode registers.

18. The method of claim 12, further comprising: An indication of the match bit and the error detection bit is received from the memory device, wherein the match bit and the error detection bit are determined based at least in part on receiving the indication.

19. A memory system comprising: one or more memories; and One or more controllers coupled to the one or more memories and configured to cause the memory system to: reading from the one or more memories a first codeword including a first set of data bits representing a set of data and a second codeword including a second set of data bits representing the set of data; generating an error detection bit based at least in part on reading the first codeword from the one or more memories, the error detection bit indicating whether an error has been detected in the first codeword; generating a match bit based at least in part on reading the first codeword and the second codeword from the one or more memories, the match bit indicating whether a portion of the first codeword matches a corresponding portion of the second codeword; and An error state of the first codeword is determined based at least in part on the matching bit and the error detection bit.

20. The memory system of claim 19, wherein the one or more controllers are further configured to cause the memory system to: selecting between the first set of data bits and the second set of data bits for communication to a host device based at least in part on the error state of the first codeword; and The selected first set of data bits or second set of data bits is communicated to the host device.

21. The memory system of claim 19, wherein the portion of the first codeword includes the first set of data bits and the portion of the second codeword includes the second set of data bits, and wherein the one or more controllers are further configured to cause the memory system to: generating a second match bit based at least in part on reading the first codeword from the one or more memories, the second match bit indicating whether a first set of parity bits in the first codeword matches a second set of parity bits in the second codeword, wherein the error status of the first codeword is determined based at least in part on the second match bit.

22. The memory system of claim 19, wherein the portion of the first codeword includes a first set of parity bits and the portion of the second codeword includes a second set of parity bits, and wherein the one or more controllers are further configured to cause the memory system to: A second match bit is generated based at least in part on reading the first codeword from the one or more memories, the second match bit indicating whether the first set of data bits matches the second set of data bits, wherein the error state of the first codeword is determined based at least in part on the second match bit.

23. The memory system of claim 19, wherein the one or more controllers are further configured to cause the memory system to: decoding the first codeword and the second codeword, wherein the error detection bits are based at least in part on the decoding; and The first set of data bits is compared to the second set of data bits based at least in part on decoding the first codeword and the second codeword, wherein the matching bits are generated based at least in part on the comparison.

24. The memory system of claim 23, wherein the one or more controllers are further configured to cause the memory system to: Errors in the first set of data bits are corrected based at least in part on decoding the first codeword, wherein the first set of data bits are compared to the second set of data bits after correcting the errors.

25. The memory system of claim 19, wherein the one or more controllers are further configured to cause the memory system to: decoding the first codeword and the second codeword, wherein the error detection bits are based at least in part on the decoding; and The first set of data bits is compared to the second set of data bits in parallel with decoding the first codeword and the second codeword, wherein the matching bits are generated based at least in part on the comparison.

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