Integrated high-K dielectric triple-trench silicon carbide vertical power device and preparation method

Abstract

The present invention discloses an integrated high-K dielectric three-trench silicon carbide vertical power device and its preparation method. The device comprises a semiconductor drain region, a semiconductor drift region, and a three-trench structure formed by a high-K dielectric deep trench region, a gate trench region, and a source trench region. The gate trench region is located within the high-K dielectric deep trench region. The source trench region comprises a P-type shielding region and a P-type heavily doped block. The region between the high-K dielectric deep trench region and the source trench region comprises, from top to bottom, a semiconductor source region, a P-type well region, and a current diffusion layer. In the on-state, the high-K dielectric deep trench region can increase the gate oxide capacitance, reduce the threshold voltage, and increase the drift region doping concentration, thereby reducing the specific on-resistance. The current diffusion layer mitigates the JFET effect in the drift region. In the off-state, the high-K dielectric deep trench region modulates the drift region electric field, increasing the breakdown voltage. The source trench region balances the electric field distribution at the top of the drift region, making the gate trench corners less susceptible to breakdown and improving gate oxide stability.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor power devices, in particular to an integrated high-K dielectric three-trench silicon carbide vertical power device and a preparation method thereof. Background Art

[0002] As a representative of the third generation of wide bandgap semiconductor materials, silicon carbide materials have replaced traditional silicon materials due to their advantages such as high bandgap width, critical breakdown electric field and thermal conductivity, and are widely used in charging and discharging equipment, new energy vehicles, satellite communications and other fields. Silicon carbide power semiconductor devices are the core components of the new generation of power integrated circuits. Structurally, they are mainly divided into silicon carbide lateral power devices and silicon carbide vertical power devices. Although silicon carbide lateral power devices have good integration, their lateral voltage resistance method leads to an increase in specific on-resistance, making them unsuitable for high-voltage and low-power applications. Trench-type silicon carbide vertical power devices have become the best choice for replacing planar-gate silicon carbide vertical power devices due to their lower on-resistance and faster switching speed.

[0003] In traditional trench-type silicon carbide vertical power devices, due to the collector effect at the tip of the gate trench corner, a large number of electrons are attracted, and the electric field strength increases sharply, making premature breakdown easy to occur in the device gate trench. In addition, for vertical power devices, increasing the breakdown voltage requires extending the length of the device drift region or reducing the drift region doping concentration, which will lead to an increase in the device's specific on-resistance and a decrease in the conduction capability. In summary, the problem of premature gate trench breakdown and the contradictory relationship between breakdown voltage and specific on-resistance are two major problems that restrict the development of trench-type silicon carbide vertical power devices in the field of high voltage and low power consumption.

[0004] To address premature gate trench breakdown in trench-type silicon carbide vertical power devices and balance the conflicting relationship between breakdown voltage and specific on-resistance, dual-source trench structures, superjunction technology, and high-K gate oxide dielectric technologies have been widely adopted. However, dual-source trench structures and traditional high-K gate oxide dielectric technologies cannot modulate the device's drift region, resulting in limited effectiveness in balancing the conflicting relationship between breakdown voltage and specific on-resistance. Superjunction technology requires maintaining charge balance in the PN junction of the drift region, placing stringent process requirements. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to address the deficiencies of the above-mentioned existing technologies and provide an integrated high-K dielectric three-trench silicon carbide vertical power device. The integrated high-K dielectric three-trench silicon carbide vertical power device is a three-trench structure composed of a source trench region, a gate trench region and a high-K dielectric deep trench region. The device drift region and the channel are modulated at the same time, and the advantages of the traditional source double trench structure and high-K gate oxide dielectric technology are combined to improve device performance without significantly increasing process complexity, balance the contradictory relationship between breakdown voltage and specific on-resistance, and alleviate the collector effect at the tip of the gate trench corner, thereby obtaining a higher quality factor.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] An integrated high-K dielectric three-trench silicon carbide vertical power device comprises a semiconductor drain region, a semiconductor drift region and a three-trench structure.

[0008] The semiconductor drift region is stacked on the top of the semiconductor drain region, and a drain metal electrode is deposited on the bottom of the semiconductor drain region.

[0009] The three-trench structure includes a high-K dielectric deep trench region, a gate trench region and a source trench region.

[0010] The high-K dielectric deep trench region is coaxially opened in the center of the semiconductor drift region, and the top portion thereof extends out from the top surface of the semiconductor drift region; the high-K dielectric deep trench region is filled with a high-K gate dielectric.

[0011] The gate trench region is coaxially opened at the top center of the high-K dielectric deep trench region, and a gate terminal metal electrode is deposited inside;

[0012] The source trench regions are arranged on both sides of the top of the semiconductor drift region, and the tops of the source trench regions extend from the top surface of the semiconductor drift region and are at the same height as the high-K dielectric deep trench region.

[0013] The source trench region includes a P-type shielding region and a P-type heavily doped block; the P-type shielding region is L-shaped, with a source metal electrode deposited on the outside; the P-type heavily doped block is arranged at the outer edge of the P-type shielding region below the source metal electrode.

[0014] On the top surface of the semiconductor drift region between the high-K dielectric deep trench region and the source trench region, a current diffusion layer, a P-type well region and a semiconductor source region are arranged in sequence from bottom to top.

[0015] The source end metal electrode is in an inverted L shape and is in contact with the semiconductor source region, the P-type shielding region and the P-type heavily doped block respectively.

[0016] The dielectric constant of high-K gate dielectric is greater than 20C 2 / (N·M 2 ), the materials used are hafnium dioxide, lanthanum oxide, titanium dioxide or lead zirconate titanate.

[0017] The depth of the high-K dielectric deep trench region in the semiconductor drift region is greater than half of the thickness of the semiconductor drift region, but less than the thickness of the semiconductor drift region.

[0018] The depth of the gate trench region is the same as the L-shaped trench depth of the P-type shielding region in the source trench region.

[0019] The total depth of the semiconductor source region, the P-type well region and the current diffusion layer is shallower than that of the gate trench region and the source trench region.

[0020] The semiconductor drain region, the semiconductor drift region, the current diffusion layer, the P-type well region, the semiconductor source region, the P-type shielding region and the P-type heavily doped block are all made of silicon carbide, and the silicon carbide material is 3C-SiC, 4H-SiC or 6H-SiC.

[0021] A method for preparing an integrated high-K dielectric triple-trench silicon carbide vertical power device comprises the following steps.

[0022] Step 1: Fabricate a semiconductor drift region: epitaxially grow a layer of silicon carbide on the semiconductor drain region to form a semiconductor drift region.

[0023] Step 2: Fabricate a current diffusion layer, a P-type well region, and a semiconductor source region: Using ion implantation and annealing, fabricate a current diffusion layer, a P-type well region, and a semiconductor source region in sequence on top of the semiconductor drift region fabricated in step 1.

[0024] Step 3, etching a high-K dielectric deep trench: using ion etching, a high-K dielectric deep trench is etched vertically downward from the top center of the semiconductor source region; the high-K dielectric deep trench sequentially penetrates the semiconductor source region, the P-type well region and the current diffusion layer, and extends to the semiconductor drift region; wherein, the etching depth of the high-K dielectric deep trench in the semiconductor drift region is greater than half of the thickness of the semiconductor drift region, but less than the thickness of the semiconductor drift region.

[0025] Step 4: Etching source trenches: Using ion etching, source trenches are etched vertically downward on both sides of the top of the semiconductor source region. The source trenches sequentially penetrate the semiconductor source region, the P-type well region, and the current diffusion layer, and extend to the top of the semiconductor drift region.

[0026] Step 5: Making a P-type shielding region: Each source trench etched in step 4 is ion implanted to make an L-shaped P-type shielding region.

[0027] Step 6, making P-type heavily doped blocks: At the top of the outer edge of the bottom of each P-type shielding area made in step 5, ion implantation and annealing are used to make P-type heavily doped blocks; the P-type heavily doped blocks and the P-type shielding area together form the source trench area.

[0028] Step 7, depositing high-K dielectric: using magnetron sputtering deposition, deposit high-K dielectric in the high-K dielectric deep trench etched in step 3, thereby forming a high-K dielectric deep trench region.

[0029] Step 8: Make a gate trench region: Use ion etching to etch vertically downward at the top center of the high-K dielectric deep trench region to form a gate trench region; the etching depth of the gate trench region is greater than the sum of the thicknesses of the semiconductor source region, the P-type well region, and the current diffusion layer.

[0030] Step 9, depositing metal electrodes: The metal electrodes include a gate metal electrode, a source metal electrode and a drain metal electrode; wherein the gate metal electrode is deposited in the gate trench region formed in step 8 by magnetron sputtering; the source metal electrode is deposited in the source trench region formed in step 6 by magnetron sputtering; and the drain metal electrode is deposited at the bottom of the semiconductor drain region by magnetron sputtering.

[0031] In step 1, the doping concentration of the semiconductor drift region is not less than 5×10 15 cm -3 In step 2, the doping concentration of the current diffusion layer is not less than 5×10 16 cm -3 ; In step 6, the doping concentration of the P-type heavily doped block needs to be higher than that of the P-type shielding area.

[0032] The source metal electrode deposited in step 9 is in an inverted L shape, and is in contact with the semiconductor source region, the P-type shielding region and the P-type heavily doped block respectively.

[0033] The present invention has the following beneficial effects:

[0034] 1. The present invention simultaneously modulates the device drift region and channel through a three-trench structure composed of a source trench region, a gate trench region, and a high-K dielectric deep trench region, which can reduce the device's specific on-resistance and threshold voltage, and improve the device's breakdown voltage, gate oxide stability, drift region doping concentration, and quality factor.

[0035] 2. The present invention uses high-K gate dielectric to replace traditional silicon dioxide gate dielectric, which increases the gate oxide capacitance, reduces the threshold voltage and the electric line density at the gate trench; the MIS structure composed of metal gate, high-K dielectric and silicon carbide material increases the electron accumulation layer density and reduces the channel resistance.

[0036] 3. The high-K gate dielectric in this invention modulates the electric field distribution in the device's drift region, increasing the breakdown voltage. A sudden electric field change occurs at the interface between the bottom of the gate dielectric and the drift region, creating a peak that further increases the breakdown voltage. Furthermore, the auxiliary depletion effect of the high-K gate dielectric increases the doping concentration in the device's drift region, thereby reducing the drift region's resistance.

[0037] 4. The highly doped current diffusion layer in the present invention alleviates the JFET effect in the drift region and reduces the resistance of the JFET region.

[0038] 5. The P-type shielding region and the P-type heavily doped block in the source trench region of the present invention play the role of attracting electric lines and balancing the electric field distribution at the top of the drift region, thereby alleviating the collector effect at the corner of the gate trench and improving the gate oxide stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a schematic structural diagram of an integrated high-K dielectric three-trench silicon carbide vertical power device according to the present invention.

[0040] Figure 2 This is a schematic diagram of the structure after the semiconductor drift region is completed in step 1 of the present invention.

[0041] Figure 3 This is a schematic diagram of the structure after the current diffusion layer, P-type well region and semiconductor source region are completed in step 2 of the present invention.

[0042] Figure 4 This is a schematic diagram of the structure after etching of the high-K dielectric deep trench and source trench region in the present invention is completed.

[0043] Figure 5 This is a schematic diagram of the structure after the P-type shielding region and the P-type heavily doped block in the present invention are manufactured.

[0044] Figure 6 This is a schematic diagram of the structure after the high-K dielectric deposition is completed and the gate trench region is fabricated in the present invention.

[0045] Figure 7 This is a comparison diagram of the relationship between the quality factor and the drift region doping concentration of the new structure of the present invention, the traditional source double trench structure and the conventional structure.

[0046] Figure 8 This is a comparison diagram of the transfer characteristic curves of the new structure of the present invention, the traditional source double trench structure and the conventional structure.

[0047] Figure 9 This is a comparison diagram of the output characteristic curves of the new structure of the present invention, the traditional source double trench structure and the conventional structure.

[0048] Figure 10 This is a comparison diagram of the vertical electric field distribution of the new structure of the present invention, the traditional source double trench structure and the conventional structure.

[0049] Figure 11 This is a planar electric field and power line distribution diagram at the gate trench corner of the integrated high-K dielectric three-trench silicon carbide vertical power device provided by the present invention.

[0050] Explanation of the numbers in the figure: 1. Semiconductor drain region, 2. Semiconductor drift region, 3. Current diffusion layer, 4. P-type well region, 5. Semiconductor source region, 6. High-K dielectric deep trench, 7. Source trench, 8. P-type shielding region, 9. P-type heavily doped block, 10. Deep trench high-K dielectric, 11. High-K gate dielectric, 12. Gate trench region, 13. Gate metal electrode, 14. Source metal electrode, 15. Drain metal electrode. DETAILED DESCRIPTION

[0051] The present invention will be further described in detail below with reference to the accompanying drawings and specific preferred embodiments.

[0052] The present invention is described in detail using an N-type drift region SiC vertical power MOSFET as an example. Alternatively, the present invention's integrated high-K dielectric triple-trench SiC vertical power device can also be applied to various types of SiC vertical power devices, such as P-type drift region SiC vertical power MOSFETs and SiC IGBTs.

[0053] like Figure 1 As shown, an integrated high-K dielectric three-trench silicon carbide vertical power device includes a semiconductor drain region 1, a semiconductor drift region 2 and a three-trench structure.

[0054] The semiconductor drift region is stacked on the top of the semiconductor drain region, and a drain metal electrode is deposited on the bottom of the semiconductor drain region.

[0055] The three-trench structure includes a high-K dielectric deep trench region, a gate trench region 12 and a source trench region.

[0056] The high-K dielectric deep trench region is coaxially opened in the center of the semiconductor drift region, and the top portion thereof extends out from the top surface of the semiconductor drift region; the high-K dielectric deep trench region is filled with a high-K gate dielectric 11 .

[0057] Furthermore, the dielectric constant of the high-K gate dielectric is preferably greater than 20C 2 / (N·M 2 ), the preferred materials are hafnium dioxide, lanthanum oxide, titanium dioxide or lead zirconate titanate.

[0058] Furthermore, the depth of the high-K dielectric deep trench region in the semiconductor drift region is greater than half of the thickness of the semiconductor drift region, but less than the thickness of the semiconductor drift region; more preferably, it is two-thirds of the thickness of the semiconductor drift region.

[0059] The gate trench region is coaxially opened at the top center of the high-K dielectric deep trench region, and a gate terminal metal electrode 13 is deposited inside. At this time, the high-K gate dielectric located outside the gate trench region is referred to as the deep trench high-K dielectric 10.

[0060] The source trench regions are opened on both sides of the top of the semiconductor drift region, and the tops of the source trench regions extend from the top surface of the semiconductor drift region and are preferably at the same height as the high-K dielectric deep trench region.

[0061] The source trench region includes a P-type shielding region 8 and a P-type heavily doped block 9; the P-type shielding region is L-shaped, with a source metal electrode 14 deposited on the outside; the P-type heavily doped block is arranged at the outer edge of the P-type shielding region below the source metal electrode.

[0062] On the top surface of the semiconductor drift region between the high-K dielectric deep trench region and the source trench region, a current diffusion layer 3, a P-type well region 4 and a semiconductor source region 5 are arranged in sequence from bottom to top.

[0063] The source-end metal electrode is in an inverted L-shape and is in contact with the semiconductor source region, the P-type shielding region and the P-type heavily doped block respectively.

[0064] Furthermore, the depth of the gate trench region is preferably the same as the L-shaped groove depth of the P-type shielding region in the source trench region; at the same time, the total depth of the semiconductor source region, P-type well region and current diffusion layer is shallower than the gate trench region and the source trench region.

[0065] Furthermore, the materials of the above-mentioned semiconductor drain region, semiconductor drift region, current diffusion layer, P-type well region, semiconductor source region, P-type shielding region and P-type heavily doped block are all silicon carbide, and the silicon carbide material is preferably 3C-SiC, 4H-SiC or 6H-SiC, and further preferably 4H-SiC.

[0066] In this embodiment, the semiconductor drift region is 20 microns thick, so the high-K dielectric deep trench is 13 microns deep and 2.2 microns wide. The high-K dielectric deep trench modulates the drift region and the channel, increasing the breakdown voltage and reducing the specific on-resistance.

[0067] In this embodiment, to ensure optimal device performance, the source trench region is optimized to have a depth of 3 microns and a width of 0.3 microns, which is used to attract electric lines and reduce the collector effect at the corners of the gate trench. The P-type heavily doped block is close to the edge of the source trench region, has a width of 0.2 microns, and has a doping concentration higher than that of the P-type shielding region, which is used to balance the electric field distribution at the top of the drift region.

[0068] In the present invention, when in the on state, the high-K dielectric deep trench region increases the gate oxide capacitance and reduces the threshold voltage, and its auxiliary depletion effect increases the drift region doping concentration, thereby reducing the specific on-resistance; the current diffusion layer reduces the JFET effect in the drift region; the MIS structure composed of the metal gate, high-K dielectric and silicon carbide material increases the electron accumulation layer density, further reducing the specific on-resistance; in the off state, the high-K dielectric deep trench region modulates the drift region electric field and increases the breakdown voltage; the source trench region balances the electric field distribution at the top of the drift region, making the gate trench corner less prone to breakdown and improving the gate oxide stability.

[0069] A method for preparing an integrated high-K dielectric triple-trench silicon carbide vertical power device comprises the following steps.

[0070] Step 1: Make a semiconductor drift region

[0071] like Figure 2 As shown, a layer of P-type doped silicon carbide is epitaxially grown on the N-type doped semiconductor drain region to form a doping concentration of not less than 5×10 15 cm -3 semiconductor drift region.

[0072] Step 2: Make the current diffusion layer, P-type well region and semiconductor source region

[0073] A. Fabrication of current diffusion layer: Use high energy ion implantation to implant nitrogen ions into the top of the semiconductor drift region to form an N-type current diffusion layer 3. Use rapid thermal annealing to activate and promote diffusion to form a fixed impurity distribution. The doping concentration of the current diffusion layer is not less than 5×10 16 cm-3, and the depth of the current diffusion layer is preferably 0.05 to 0.3 microns to alleviate the JFET effect of the device.

[0074] B. Fabrication of a P-type well region: Using the same method, a high dose of aluminum ions is implanted onto the current diffusion layer to form a highly doped P-type well region 4.

[0075] C. Fabrication of semiconductor source region: Using the same method, high-dose nitrogen ions are injected onto the P-type well region to form a highly doped semiconductor source region 5. The completed structure is as follows: Figure 3 shown.

[0076] Step 3, etching a high-K dielectric deep trench: using a photoresist as a mask and adopting an ion etching method, a high-K dielectric deep trench 6 is etched vertically downward at the top center of the semiconductor source region; the high-K dielectric deep trench sequentially penetrates the semiconductor source region, the P-type well region and the current diffusion layer, and extends to the semiconductor drift region; wherein, the etching depth of the high-K dielectric deep trench in the semiconductor drift region is greater than half of the thickness of the semiconductor drift region, but less than the thickness of the semiconductor drift region, preferably two-thirds of the thickness of the semiconductor drift region, and the bottom does not contact the semiconductor drain region; the width of the high-K dielectric deep trench region is wider than the gate trench region.

[0077] Step 4, etching the source trench: using photoresist as a mask, ion etching is used to etch the source trench vertically downward on both sides of the top of the semiconductor source region; the source trench sequentially penetrates the semiconductor source region, the P-type well region and the current diffusion layer, and extends to the top of the semiconductor drift region. Figure 4 shown.

[0078] In this embodiment, the source trench region is preferably 2 to 4 microns in depth and 0.3 microns in width.

[0079] Step 5: Fabricate a P-type shielding region: Use vertical and tilted implantation methods to implant aluminum ions into each source trench etched in step 4 to fabricate an L-shaped P-type shielding region.

[0080] Step 6: Make a P-type heavily doped block: At the top of the outer edge of the bottom of each P-type shielding area made in step 5, ion implantation and annealing are used to implant high-dose aluminum ions to make a P-type heavily doped block. Figure 5 shown.

[0081] The P-type heavily doped block and the P-type shielding region together form the source trench region 7. The doping concentration of the P-type heavily doped block needs to be much higher than that of the P-type shielding region.

[0082] In this embodiment, the P-type heavily doped block is closely attached to the edge of the source trench region, and its width is preferably 0.05 to 0.3 microns.

[0083] Step 7, depositing high-K dielectric: using magnetron sputtering deposition, deposit high-K dielectric in the high-K dielectric deep trench etched in step 3, thereby forming a high-K dielectric deep trench region.

[0084] Step 8: Make the gate trench area: Use photoresist as a mask and ion etching to etch vertically downwards at the top center of the high-K dielectric deep trench area to form a gate trench area. Figure 6 The gate trench region shown; the etching depth of the gate trench region is greater than the sum of the thicknesses of the semiconductor source region, the P-type well region and the current diffusion layer.

[0085] In this embodiment, the gate trench region is preferably made of metal gate material, and the depth is preferably 2 to 4 microns, preferably the same as the depth of the source trench region, to simplify the process steps.

[0086] Step 9, depositing metal electrodes: The metal electrodes include a gate metal electrode, a source metal electrode and a drain metal electrode; wherein the gate metal electrode is deposited in the gate trench region formed in step 8 by magnetron sputtering; the source metal electrode is deposited in the source trench region formed in step 6 by magnetron sputtering, and is preferably in an inverted L shape, contacting the semiconductor source region, the P-type shielding region and the P-type heavily doped block respectively; the drain metal electrode is deposited at the bottom of the semiconductor drain region by magnetron sputtering.

[0087] The gate metal electrode, source metal electrode and drain metal electrode are preferably made of metals such as Ni, Ti or Al, and are deposited by magnetron sputtering and then rapidly thermally annealed to form a metal alloy to achieve good ohmic contact.

[0088] Figure 7The quality factor (Figure of merit, FOM) and drift region doping concentration (N) of a three-trench silicon carbide vertical power device with integrated high-K dielectric, a double-trench source structure without high-K dielectric (traditional double-trench source structure) silicon carbide vertical power device, and a conventional structure silicon carbide vertical power device provided by the present invention are given. D ). The high-K dielectric of the integrated high-K dielectric three-trench silicon carbide vertical power device uses hafnium dioxide, and the other structural parameters of the three devices are consistent. Figure 7 It can be seen that all three devices have the maximum FOM value. Due to the comprehensive modulation effect of the high-K dielectric deep trench region, the FOM value of the integrated high-K dielectric three-trench silicon carbide vertical power device proposed in the present invention reaches 5003MW / cm 2 Compared with the traditional source double trench structure and the conventional structure, the FOM value is increased by 122.8% and 171% respectively. Taking the highest point of the FOM value as the best optimization point, the breakdown voltage (BV) of the invention at the highest FOM value reaches 2611V, which is higher than the on-resistance (R on,sp ) reaches 1.36mΩ, and the breakdown voltage is increased by 13.2% and 20.1% respectively compared with the other two structures, and the on-resistance is reduced by 42.6% and 47.7% respectively, and the drift region doping concentration is more than doubled.

[0089] Figure 8 The present invention provides an integrated high-K dielectric three-trench silicon carbide vertical power device, a traditional source double-trench structure silicon carbide vertical power device, and a conventional structure silicon carbide vertical power device in terms of drain-source voltage V DS The present invention uses high-K gate dielectric instead of traditional silicon dioxide gate dielectric, which greatly improves the gate capacitance and makes the threshold voltage V TH Significantly reduced. Figure 8 It can be seen that the threshold voltage V TH It reaches 2.79V, which is 68.7% and 73.1% lower than the traditional source double trench structure and the conventional structure respectively.

[0090] Figure 9 The present invention provides an integrated high-K dielectric three-trench silicon carbide vertical power device, a traditional source double-trench structure silicon carbide vertical power device, and a conventional structure silicon carbide vertical power device in terms of gate-source voltage V GS The following is a comparison of the output characteristic curves at 10V and 20V. Figure 9 In the figure, the horizontal axis is the drain-source voltage V DS , the vertical axis is the drain-source current I DS .Depend on Figure 9It can be seen that since the high-K dielectric deep trench region, source trench and current diffusion layer of the present invention all have the ability to enhance forward conduction capability and reduce specific on-resistance, compared with the traditional source double trench structure and the conventional structure, it has a larger IV curve slope in the linear region and a larger saturation current in the saturation region.

[0091] Figure 10 A comparison diagram of the vertical electric field distribution of an integrated high-K dielectric triple-trench silicon carbide vertical power device provided by the present invention, a traditional source double-trench structure silicon carbide vertical power device, and a conventional structure silicon carbide vertical power device is given. Figure 10 In the equation, the vertical axis is the electric field strength and the horizontal axis is the vertical position of the device. Figure 10 It can be seen that for conventional structures, the electric field strength at the gate trench corners exceeds 10 MV / cm, making premature breakdown highly likely. With the new structure provided by the present invention, the electric field strength at the gate trench corners is reduced to below 3 MV / cm, significantly improving gate oxide stability. Furthermore, the high-K dielectric deep trench introduces a new electric field peak in the drift region, improving the device's withstand voltage performance.

[0092] Figure 11 The planar electric field and power line distribution diagram at the gate trench corner of the integrated high-K dielectric triple-trench silicon carbide vertical power device. Figure 11 In the figure, the ordinate is the device's longitudinal position, and the abscissa is its lateral position. As can be seen from the figure, the heavily P-type doped block attracts electric lines of force. The high-k dielectric deep trench and P-type shielding region balance the electric field distribution at the top of the drift region, alleviating the collector effect at the gate trench corners. The maximum electric field intensity is only 2.74 MV / cm.

[0093] The preferred embodiments of the present invention are described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the scope of protection of the present invention.

Claims

1. An integrated high-K dielectric triple-trench silicon carbide vertical power device, characterized by: including a semiconductor drain region, a semiconductor drift region and a three-trench structure; The semiconductor drift region is stacked on top of the semiconductor drain region, and a drain metal electrode is deposited on the bottom of the semiconductor drain region; The three-trench structure includes a high-K dielectric deep trench region, a gate trench region and a source trench region; The high-K dielectric deep trench region is coaxially opened in the center of the semiconductor drift region, and the top portion thereof extends out from the top surface of the semiconductor drift region; The high-K dielectric deep trench region is filled with a high-K gate dielectric; The depth of the high-K dielectric deep trench region in the semiconductor drift region is greater than half of the thickness of the semiconductor drift region but less than the thickness of the semiconductor drift region; The gate trench region is coaxially opened at the top center of the high-K dielectric deep trench region, and a gate terminal metal electrode is deposited inside; The source trench regions are provided on both sides of the top of the semiconductor drift region, and the tops thereof extend from the top surface of the semiconductor drift region and are at the same height as the high-K dielectric deep trench region; The total depth of the semiconductor source region, the P-type well region and the current diffusion layer is shallower than the gate trench region and the source trench region; The source trench region includes a P-type shielding region and a P-type heavily doped block; the P-type shielding region is L-shaped, with a source metal electrode deposited on the outside; the P-type heavily doped block is arranged at the outer edge of the P-type shielding region below the source metal electrode; On the top surface of the semiconductor drift region between the high-K dielectric deep trench region and the source trench region, a current diffusion layer, a P-type well region and a semiconductor source region are arranged in sequence from bottom to top; The three-trench structure composed of the source trench region, the gate trench region, and the high-K dielectric deep trench region simultaneously modulates the device drift region and the channel, which can reduce the device's specific on-resistance and threshold voltage, and increase the device breakdown voltage to 2611 V at the highest FOM value. The doping concentration of the semiconductor drift region is not less than 5×10 15 cm -3 , the specific on-resistance reaches 1.36 mΩ.

2. The integrated high-K dielectric triple-trench silicon carbide vertical power device according to claim 1, characterized in that: The source end metal electrode is in an inverted L shape and is in contact with the semiconductor source region, the P-type shielding region and the P-type heavily doped block respectively.

3. The integrated high-K dielectric triple-trench silicon carbide vertical power device according to claim 1, characterized in that: The dielectric constant of high-K gate dielectric is greater than 20C 2 / (N·M 2 ), the materials used are hafnium dioxide, lanthanum oxide, titanium dioxide or lead zirconate titanate.

4. The integrated high-K dielectric triple-trench silicon carbide vertical power device according to claim 1, characterized in that: The semiconductor drain region, the semiconductor drift region, the current diffusion layer, the P-type well region, the semiconductor source region, the P-type shielding region and the P-type heavily doped block are all made of silicon carbide, and the silicon carbide material is 3C-SiC, 4H-SiC or 6H-SiC.

5. A method for preparing an integrated high-K dielectric triple-trench silicon carbide vertical power device, characterized by: The steps include: Step 1: Fabricate a semiconductor drift region: epitaxially grow a layer of silicon carbide on the semiconductor drain region to form a semiconductor drift region; Step 2: Fabricating a current diffusion layer, a P-type well region, and a semiconductor source region: Using ion implantation and annealing, a current diffusion layer, a P-type well region, and a semiconductor source region are fabricated in sequence on top of the semiconductor drift region fabricated in step 1. Step 3, etching a high-K dielectric deep trench: Using an ion etching method, a high-K dielectric deep trench is etched vertically downward from the center of the top of the semiconductor source region; the high-K dielectric deep trench sequentially penetrates the semiconductor source region, the P-type well region, and the current diffusion layer, and extends to the semiconductor drift region; wherein the etching depth of the high-K dielectric deep trench in the semiconductor drift region is greater than half of the thickness of the semiconductor drift region, but less than the thickness of the semiconductor drift region; Step 4: Etching source trenches: Using ion etching, vertically etch source trenches downward on both sides of the top of the semiconductor source region; the source trenches sequentially penetrate the semiconductor source region, the P-type well region, and the current diffusion layer, and extend to the top of the semiconductor drift region; Step 5: Making a P-type shielding region: Each source trench etched in step 4 is ion implanted to make an L-shaped P-type shielding region; Step 6: Fabricate a P-type heavily doped block: Ion implantation and annealing are performed on the top of the outer edge of the bottom of each P-type shielding region fabricated in step 5 to fabricate a P-type heavily doped block; the P-type heavily doped block and the P-type shielding region together form a source trench region; Step 7: Depositing high-K dielectric: Using magnetron sputtering deposition, deposit high-K dielectric in the high-K dielectric deep trench etched in step 3, thereby forming a high-K dielectric deep trench region; Step 8: Forming a gate trench region: Using ion etching, vertically etch downward from the top center of the high-K dielectric deep trench region to form a gate trench region; the etching depth of the gate trench region is greater than the sum of the thicknesses of the semiconductor source region, the P-type well region, and the current diffusion layer; Step 9, depositing metal electrodes: The metal electrodes include a gate metal electrode, a source metal electrode and a drain metal electrode; wherein the gate metal electrode is deposited in the gate trench region formed in step 8 by magnetron sputtering; the source metal electrode is deposited in the source trench region formed in step 6 by magnetron sputtering; and the drain metal electrode is deposited at the bottom of the semiconductor drain region by magnetron sputtering.

6. The method for preparing an integrated high-K dielectric triple-trench silicon carbide vertical power device according to claim 5, characterized in that: In step 1, the doping concentration of the semiconductor drift region is not less than 5×10 15 cm -3 In step 2, the doping concentration of the current diffusion layer is not less than 5×10 16 cm -3 ; In step 6, the doping concentration of the P-type heavily doped block needs to be higher than that of the P-type shielding area.

7. The method for preparing an integrated high-K dielectric triple-trench silicon carbide vertical power device according to claim 5, characterized in that: The source metal electrode deposited in step 9 is in an inverted L shape, and is in contact with the semiconductor source region, the P-type shielding region and the P-type heavily doped block respectively.

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