Predictive Validation of the Cache Subsystem

Abstract

A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in multiple ways. A request circuit generates a request to access a specific cache line in the cache. A prediction circuit is configured to generate a prediction about which of the ways includes the specific cache line. A comparison circuit verifies the prediction by comparing a specific address tag associated with the specific cache line and a cache tag corresponding to the predicted one of the ways. In response to determining that the prediction is correct, a confirmation indication indicating the correct prediction is stored. For subsequent requests for the specific cache line, the cache is configured to abandon verification of the prediction that the specific cache line is included in one of the ways based on the confirmation indication.

Description

Background Art Technical Field

[0002] The present disclosure relates to computer systems, and more particularly to cache subsystems.

[0003] Description of Related Technology

[0004] Computer systems employ various types of memory in a memory hierarchy. This hierarchy may extend from architectural registers in a processor (e.g., to store operands for instructions to be executed) to mass storage such as on a hard drive or solid-state disk. Many computer systems also include multiple levels of cache memory.

[0005] A cache is a type of memory that is below registers in the memory hierarchy but above system memory, such as random access memory (RAM), in the hierarchy. A cache can store information based on principles of locality, including temporal locality (e.g., recently accessed information is likely to be accessed again within a given time) and spatial locality (e.g., recently accessed information is likely to be stored near other information that will be accessed). Based on these principles, information stored in a cache can be accessed faster than if it were stored only in system RAM or mass storage. Thus, a cache can improve the overall performance of a computer system by reducing the access time to at least some information (e.g., data or instructions) to be used by a processor. Summary of the invention

[0006] A device for prediction confirmation in a cache subsystem is disclosed. In one embodiment, the cache subsystem includes a cache configured to store information in cache lines arranged in multiple ways. The request circuit is configured to generate a request to access a specific cache line in the cache. The prediction circuit is configured to generate a prediction about which way of the multiple ways of the cache includes the specific cache line. The comparison circuit is configured to verify the prediction by comparing a specific address tag associated with the specific cache line and a cache tag corresponding to one of the predicted multiple ways. The prediction circuit is also configured to store a confirmation indication indicating that the prediction is correct in response to the comparison circuit determining that the prediction is correct, and wherein for subsequent access requests for the specific cache line, the cache is configured to abandon verification of the prediction that the specific cache line is included in one of the multiple ways based on the confirmation indication indicating that the prediction is correct.

[0007] In one embodiment, verifying the prediction includes reading an address tag from an address tag memory. The address tag is provided to the comparator together with the cache tag. After determining that the address tag and the cache tag match, the prediction is confirmed to be correct, and the prediction circuit makes the same indication, causing the confirmation bit to be set. The confirmation bit is stored in the confirmation bit memory. For subsequent requests for the correctly predicted cache line, the confirmation bit memory is queried. Since it is determined that the confirmation bit is set, the cache subsystem abandons reading the cache tag and the comparison operation from the cache. Therefore, abandoning the tag reading and comparison operation can save non-negligible power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following detailed description refers to the accompanying drawings, which are now briefly described.

[0009] Figure 1 is a block diagram of one embodiment of a cache subsystem.

[0010] Figure 2 is a block diagram of one embodiment of a cache subsystem having an instruction cache.

[0011] Figure 3 is a block diagram of one embodiment of a cache subsystem having a data cache.

[0012] Figure 4 is a block diagram of one embodiment of a confirmation bit memory.

[0013] Figure 5 is a flow chart illustrating one embodiment of a method for operating a cache subsystem.

[0014] Figure 6 is a flow chart illustrating one embodiment of a method for operating a cache subsystem.

[0015] Figure 7 is a block diagram of one embodiment of an exemplary system. DETAILED DESCRIPTION

[0016] The present disclosure is directed to an apparatus and method for confirming way predictions in a cache subsystem. Way predictions are used in cache to reduce power consumption. Instead of searching all ways for a block / page of a requested cache line, a prediction can be made as to which specific way the cache line is stored. If the prediction is correct, less power will be consumed than searching all ways.

[0017] When a prediction is made, the address tag array may be read to obtain the address tag corresponding to the requested cache line. The cache tag corresponding to the predicted way may also be read from the cache. The address tag and the cache tag corresponding to the predicted way are then compared. If the tags match, then the way storing the requested cache line has been correctly predicted. However, even when the prediction is correct, the reading of the cache tag and subsequent comparison operations may still consume a significant amount of power, despite the fact that only a single way is searched rather than all ways of the cache. Furthermore, each subsequent access to the cache line may be predicted, thereby duplicating the work of the original correct prediction.

[0018] The present disclosure is based on the idea that once a cache line is predicted correctly, the prediction will continue to be correct for subsequent accesses to the cache line unless the state of the cache line changes. Possible changes include eviction of the cache line, invalidation of the cache line, context switching, or predicting a different virtual page. However, if the cache line is still validly stored in the predicted way, the prediction may also remain valid.

[0019] Based on the above discussion, a confirmation bit can be added to a particular cache line when it is correctly predicted that the particular cache line is stored in a particular way. When a prediction is made for a particular cache line and it is verified that the particular cache line is stored in the particular way, the confirmation bit is set and remains until a state change occurs, such as one of the examples provided in the previous paragraph. For subsequent access requests to the particular cache line, the confirmation bit is read, and the cache subsystem can abandon reading the cache tag and thereby abandon the comparison operation. This can save more power than if the cache line was correctly predicted for multiple different accesses. In addition, performance gains can be achieved by canceling the steps required to confirm the prediction and therefore not repeating the work of the original prediction. The use of the confirmation bit can be particularly useful in certain situations, such as in a program loop that repeatedly accesses a particular cache line.

[0020] Note that while prediction verification as discussed herein may include tag read and comparison operations, the disclosure is not intended to be limited in this manner. Rather, the disclosure is intended to cover any suitable mechanism for verifying whether a cache line is stored in a predicted way of a cache.

[0021] The present disclosure will now be discussed in more detail. First, a cache subsystem and the operations of the cache subsystem with respect to prediction paths, confirmation of the predictions, and operations following the confirmation are discussed. Then, an example of a cache subsystem utilizing a confirmation bit mechanism is discussed, including an instruction cache subsystem and a data cache subsystem. Subsequently, an embodiment of a memory for storing confirmation bits is described. Next, a flow chart illustrating a method for operating a cache subsystem having a tag confirmation bit is described. The description ends with a discussion of an example system.

[0022] Cache subsystem with predictive acknowledgment:

[0023] Figure 1 is a block diagram of one embodiment of a cache subsystem in which a prediction is made about the way of a requested cache line and if the prediction is correct, a confirmation bit is set. Note that Figure 1 Only a portion of the cache subsystem is shown, and the cache subsystem may include other circuits, such as those described below. Figure 2 and Figure 3 Circuit discussed.

[0024] In the illustrated embodiment, cache subsystem 100 includes prediction circuit 102, cache 104, and comparison circuit 120. Cache 104 in the illustrated embodiment includes N ways and is an N-way set associative cache. Embodiments in which cache 104 is fully associative are also contemplated.

[0025] The cache subsystem 100 is configured to receive a cache access request from a requester 110. The requester 110 can be one of a plurality of different types of functional circuit units that can request access to the cache. In one embodiment, the cache 104 is an instruction cache that is configured to store instructions executed by a processor. Therefore, the requester 110 in this embodiment can be an instruction fetch unit that initiates a cache request to fetch instructions. In another embodiment, the cache 104 is a data cache, and the requester 110 can be a processor core or a portion thereof that initiates a request for data used when executing instructions. In general, the cache 104 can be an instruction cache or a data cache, and the requester 110 can be any type of functional circuit that submits an access request to a corresponding cache type.

[0026] The prediction circuit 102 in the illustrated embodiment is configured to predict the way in which a particular cache line is stored. More specifically, the prediction circuit 102 generates a prediction in response to an incoming access request for a predicted cache line. Upon receiving an indication of the requested cache line, the prediction circuit 102 generates the prediction and provides the prediction to the comparison circuit 120. In the illustrated embodiment, the requested address tag associated with the cache line is accessed by the prediction circuit 102 and provided as part of the prediction process.

[0027] Comparison circuit 120 may also receive a cache tag provided by cache 104 in response to a request to verify the prediction. The cache tag provided by cache 104 may correspond to the predicted cache way. After obtaining the cache tag and the address tag (from prediction circuit 102), comparison circuit 120 performs a comparison operation. If the address tag matches the cache tag, the prediction is considered correct. Otherwise, the prediction is considered incorrect, and if the requested cache line exists in the cache, other ways are searched to find the requested cache line. If the requested cache line is not stored in the cache, the cache line can be accessed from system memory.

[0028] In response to correctly predicting that the requested cache line is stored in a particular way, the prediction circuit 102 is configured to generate and store a confirmation indication. As described below, the confirmation indication or confirmation bit can be stored in a dedicated memory. For subsequent predictions of the particular cache line, the setting of the confirmation bit indicates that the previous prediction about the particular way storing the cache line was correct. Therefore, in response to observing that the confirmation bit is in a set state, if the cache line associated with the correct prediction is requested again, the cache subsystem 100 may abandon certain operations.

[0029] If the cache subsystem 100 determines that the confirmation bit has been set in the illustrated embodiment, the cache tag is not read from the cache 104. In addition, the comparison circuit 120 does not perform a comparison operation because no cache tag is provided. Therefore, for subsequent requests for a cache line that has been correctly predicted to be stored in a particular way, the cache tag read and comparison operations are eliminated. More generally, when the corresponding confirmation bit indicates that the way storing the requested cache line has been correctly predicted in a previous access, no verification is performed. Eliminating the verification operation can significantly save power and improve performance.

[0030] When the confirmation bit is set in response to a correct prediction, the confirmation bit can remain set as long as the prediction itself remains valid. The confirmation bit can be reset in response to various events that affect the cache line associated with the correct prediction. For example, if the cache line fails, the confirmation bit is reset. Similarly, if the cache line is evicted from the cache, the confirmation bit is reset. A context switch can also cause the confirmation bit to reset because the cache can be flushed. However, as long as the cache line associated with the correct prediction remains stored in the predicted cache line and also remains valid, the confirmation bit can remain set.

[0031] Instruction and data cache subsystem:

[0032] Figure 22 is a block diagram of an embodiment of a cache subsystem that implements an instruction cache. In the illustrated embodiment, the cache subsystem 200 includes an N-way set associative cache, namely an instruction cache 204. In this particular embodiment, the number of ways in each group is 2, and way 0 and way 1 constitute group 0. Although not explicitly shown, for this embodiment, group 1 will include way 1 and way 2, and so on. Other embodiments with different arrangements can also be considered. The instruction cache 204 also includes a cache controller 209, which performs various cache control functions. These functions include, but are not limited to, storing cache lines, evicting cache lines, writing cache lines to the instruction cache 204, invalidating cache lines, and reading and providing requested cache lines to the requesting party.

[0033] The instruction cache 204 in the illustrated embodiment is configured to store instructions to be executed by the processor. Thus, the requester in this particular embodiment is the instruction fetch unit 210, which requests access to instructions to be executed as part of a program or instruction thread. The instruction fetch request is provided by the instruction fetch circuit 210 to the prediction circuit 202 and the cache controller 209.

[0034] When an instruction fetch request is issued for a cache line, the request is received by the prediction circuit 202 and the cache controller 209. The prediction circuit 202 in the illustrated embodiment may respond to the request by generating a prediction that the requested cache line is stored in a particular way in the instruction cache 204. After generating the prediction, the prediction circuit 202 may access the address tag memory 206 to obtain an address tag corresponding to the requested cache line. The address tag may then be provided to the comparison circuit 209 for use in a validation operation. The predicted way may also be provided to the cache controller 209, which may use this information to determine whether the requested cache line is the subject of a previous correct prediction that is still valid.

[0035] The address tag memory 206 in the illustrated embodiment may store virtual addresses, although embodiments in which physical addresses are stored in the address tag memory are also contemplated. Embodiments in which the address tag memory 206 stores virtual addresses and the corresponding physical addresses are accessed from a translation lookaside buffer (TLB) and used as a basis for comparisons performed by the comparison circuit 208 are also contemplated. For purposes of this disclosure, the address tag memory 206 may be viewed as storing virtual addresses, physical addresses, and / or may also be viewed as including multiple memories in which virtual addresses are stored in one memory circuit and corresponding physical addresses are stored in another memory circuit (e.g., the TLB mentioned above). Regardless of whether the address tag provided is virtual or physical, the comparison circuit 208 in the illustrated embodiment performs a comparison to determine whether the way prediction for the requested cache line is correct.

[0036] The cache controller 209 in the illustrated embodiment may initially respond to a request for a cache line by querying the confirmation bit memory 212. In the illustrated embodiment, the confirmation bit memory 212 is configured to store confirmation bits corresponding to the cache index and the corresponding ways in which the various cache lines may be stored. Using the information about the predicted way and the information about the requested cache line, the cache controller 209 may query the confirmation bit memory to determine whether the confirmation bit has been set in the particular way for the requested cache line.

[0037] If the confirmation bit is not set (e.g., the confirmation bit is reset), indicating that the previous correct prediction for the requested cache line is currently invalid, the cache controller 209 can respond by providing an instruction cache tag to the comparison circuit 208, the instruction cache tag corresponding to the predicted way. In response, the comparison circuit 208 compares the address tag received from the address tag memory and the instruction tag received from the instruction cache 204. If the tags match (a "hit"), the comparison circuit 208 provides an indication to the prediction circuit 202 that the tags match. In response to receiving the hit indication, the prediction circuit 202 provides an indication to the confirmation bit memory 212 to indicate the correctly predicted way and corresponding index. The confirmation bit is then set in the confirmation bit memory 212 for the predicted way and index. In addition, the indication that the prediction is correct is provided to the cache controller 209, and the cache controller can respond by accessing the requested cache line and providing the requested cache line to the instruction fetch circuit 210.

[0038] It should be noted that embodiments are also contemplated in which the functions of prediction circuit 202 and comparison circuit 208 are combined into a single unit. The comparison circuit implemented in such an embodiment may be a source of indication that the prediction was correct. Figure 2 In the embodiment explicitly shown in FIG. 2 , it is also contemplated that the comparison circuit 208 provides an indication of the correct prediction to the confirmation bit memory 212 .

[0039] If the prediction is incorrect (if the address tag and the instruction tag do not match), the prediction circuit 202 (or the comparison circuit 208) may provide an indication that the prediction is incorrect to the cache controller 209. In response to the incorrect prediction, the cache controller 209 may search other ways in the cache 204 to determine whether the requested cache line is stored in other ways. If the requested cache line is not stored in any way of the instruction cache 204, a search of the main system memory may be performed by the memory controller. If the requested cache line is stored in a different way than the predicted way, the requested cache line is provided to the instruction fetch circuit 210.

[0040] If there is a subsequent access request for the previously correctly predicted object (a particular cache line), the verification process is not performed in the illustrated embodiment. Specifically, the cache controller 209 may query the confirmation bit memory 212 again in response to a request for a particular cache line. Upon receiving an indication from the confirmation bit memory that the confirmation bit is set for the predicted way of the particular cache line, the cache controller 209 in the illustrated embodiment will issue a "disable verification" signal, which is received by the comparison circuit 208. When the comparison circuit 208 receives the signal, the signal indicates that the cache controller 209 will no longer read the instruction tag for comparison, and therefore will not perform a comparison operation on the particular request. By abandoning the reading and comparison operations of the instruction tags, significant power consumption savings can be achieved. Canceling the tag reading and comparison operations can also improve performance. Since the confirmation bit is set, the cache controller 209 also responds by providing the particular cache line to the instruction acquisition circuit 210 from the corresponding way of the instruction cache 204, without the delay caused by waiting to determine that the prediction has been verified.

[0041] The cache controller 209 in the illustrated embodiment is configured to reset the confirmation bits stored in the confirmation bit storage 212 in response to certain conditions. For example, if it is determined that a cache line that was the subject of a previous correct prediction fails at a subsequent time, the cache controller 209 can reset the corresponding confirmation bit. The eviction of a cache line that was previously correctly predicted to be stored in a particular way can also reset the corresponding confirmation bit. Other conditions for resetting the confirmation bit include the failure of the corresponding virtual address to physical address translation, a context switch in which the cache is flushed (thereby resetting all confirmation bits), and the like.

[0042] Figure 3 FIG. 1 is a block diagram of an embodiment of a cache subsystem for implementing data caching. In the illustrated embodiment, the cache subsystem 300 and Figure 2 304 is similar to the cache subsystem 200 shown, with the primary difference being that the cache 304 is a data cache including a cache controller 309. The requestor 310 in the illustrated embodiment may be, for example, one of the one or more processor cores that utilize the data cache 304. More generally, the requestor 310 may be any type of functional circuitry that is capable of accessing and utilizing a data cache. The functions of the prediction circuit 302, the comparison circuit 308, the address tag memory 306, the cache controller 309, and the confirmation bit memory 312 may be similar to those of the embodiment shown. Figure 2. Again, as with the case discussed above with respect to cache subsystem 200, these circuit units may vary from one embodiment to another. In short, cache subsystem 300 and its components in the illustrated embodiment are configured to make and verify a prediction for a particular way of a requested cache line storing data, set a confirmation bit in response to a correct prediction, and abandon a verification process including a tag read and comparison operation when the confirmation bit indicates that the previous prediction of the requested cache line was correct.

[0043] Example of acknowledgement bit memory:

[0044] Figure 4 4 is a block diagram of an embodiment of a confirmation bit memory for storing confirmation bits corresponding to correct predictions according to the present disclosure. In the illustrated embodiment, the confirmation bit memory 412 is arranged to store multiple confirmation bits 411. In the illustrated embodiment, when the confirmation bit is set (e.g., has a logical value of 1), it indicates that the way storing the requested cache line has been correctly predicted before and the prediction is still valid. As long as the corresponding cache line remains effectively stored in the cache, the prediction can remain valid. As described above, if the corresponding cache line has been invalidated, evicted, etc., and in the case where the corresponding way and index are not correctly predicted, the confirmation bit can be placed in a reset state (e.g., a logical value of 0). After the cache is refilled after a context switch, each confirmation bit can remain in a reset state until the cache line stored in the cache is correctly predicted.

[0045] In the illustrated embodiment, the confirmation bit memory 412 is arranged in a way and index manner, with the index being associated with various address tags. Thus, if the cache line associated with the address tag corresponding to the correctly predicted index A is stored in, for example, way 2, then the confirmation bit 411 at the intersection of the index A row and the way 2 column can be set. For subsequent requests for this particular cache line, the cache controller's reading of the confirmation bit can cause the verification of the prediction process (e.g., the cache tag read and comparison operation described above) to be cancelled.

[0046] Methods for manipulating the cache subsystem:

[0047] Figure 5 5 is a flow chart of one embodiment of a method for operating a cache subsystem. As disclosed herein, method 500 may be performed by any of the various hardware implementations described above. Hardware implementations not discussed herein but otherwise capable of performing method 500 are also considered to fall within the scope of the present disclosure.

[0048] Method 500 includes storing a cache line in a multiway of a cache (block 505). The method also includes generating a request using a request circuit to access a particular cache line in the cache (block 510), and then generating a prediction using a prediction circuit as to which way of the multiway of the cache includes the particular cache line (block 515). After generating the prediction, the method continues to verify the prediction using a comparison circuit, wherein the verification includes comparing a particular address tag associated with the particular cache line to a cache tag corresponding to the predicted one way of the multiway (block 520). The method also includes storing a confirmation bit using the prediction circuit in response to the comparison indicating that the prediction is correct (block 525), and for subsequent access requests for the particular cache line, abandoning verification of a subsequent prediction that the particular cache line includes one way of the multiway based on the confirmation bit indicating that the prediction is correct (block 530).

[0049] In various embodiments, abandoning the verification subsequent request includes: abandoning reading the cache tag from the cache; and abandoning comparing the specific address tag with the cache tag. By abandoning these two operations, power saving and performance improvement can be achieved.

[0050] Various embodiments of method 500 include: storing a plurality of address tags including the particular address tag in a tag memory, wherein some of the plurality of address tags correspond to entries stored in the cache. For such embodiments, determining that the prediction is correct is based on the particular address tag matching the cache tag. After confirming that the prediction is correct, the method includes storing the confirmation bit in a confirmation bit memory. For a request to access a cache line, embodiments of the method include: querying the confirmation bit memory to determine whether a previous prediction was correct in response to a subsequent prediction of the particular cache line.

[0051] Sometimes a correctly predicted cache line may be evicted from the cache. Thus, an embodiment of method 500 includes resetting a particular confirmation bit stored in the confirmation bit memory in response to evicting a cache line corresponding to the particular confirmation bit from the cache. Other conditions may also cause the confirmation bit to be reset. For example, an embodiment of method 500 may include resetting a particular confirmation bit stored in the confirmation bit memory in response to an address translation failure associated with the cache line corresponding to the particular confirmation bit.

[0052] Figure 6 is a flow chart of another embodiment of a method for operating a cache subsystem. As with method 500 described above, method 600 may be performed by referring to Figures 1 to 4 Embodiments of cache subsystems capable of performing method 600 but not disclosed herein may also be considered to fall within the scope of the present disclosure.

[0053] Method 600 includes: the cache subsystem receives a request for a cache line (box 605). Subsequently, the method includes: reading a confirmation bit memory and a tag memory for the requested cache line (box 610). In various embodiments, the tag memory includes an address tag, and thus the address tag corresponding to the requested cache line can be retrieved from the tag memory. At the same time, the confirmation bit memory can be read to determine whether the previous prediction about the specific way to store the requested cache line is correct. If it is determined that the corresponding confirmation bit is set (box 615, yes), indicating that the previous prediction about the specific way to store the requested cache line is correct, then the method continues to skip the cache tag read and comparison operations while obtaining the requested cache line from the cache (box 620). Subsequently, method 600 returns to box 605 and waits for the next cache line request.

[0054] If the confirmation bit is not set (block 615, no), the cache tag corresponding to the predicted way is read (block 625). A comparison operation is then performed, comparing the cache tag to the address tag corresponding to the requested cache line (block 630). If the address tag matches the cache tag (block 635, yes), then the prediction is correct, and the method continues to set and store the confirmation bit while accessing the cache line from the predicted way (block 640). The method 600 then returns to block 605 to await the next cache request.

[0055] On the other hand, if the address tag and the cache tag do not match (block 635, no), the requested cache line is searched in other ways of the cache (block 645), and if the requested line exists in the cache, the requested line is provided. Subsequently, method 600 returns to block 605.

[0056] Example systems:

[0057] Next turn Figure 7 , a block diagram of one embodiment of a system 700 is shown, which can incorporate and / or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, the system 700 includes at least one instance of a system on a chip (SoC) 706, which can include multiple types of processing units (such as a central processing unit (CPU), a graphics processing unit (GPU), or others), a communication structure, and interfaces to memory and input / output devices. In some embodiments, one or more processors in the SoC 706 include multiple execution lanes and instruction issue queues. In various embodiments, the SoC 706 is coupled to an external memory 702, peripherals 704, and a power supply 708.

[0058] A power supply 708 is also provided that supplies a supply voltage to the SoC 706 and one or more supply voltages to the memory 702 and / or peripherals 704. In various embodiments, the power supply 708 represents a battery (e.g., a rechargeable battery in a smartphone, laptop or tablet computer, or other device). In some embodiments, more than one instance of the SoC 706 is included (and more than one external memory 702 is also included).

[0059] The memory 702 is any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, etc., and / or low power versions of SDRAM, such as LPDDR2, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled to the circuit board to form a memory module, such as a single inline memory module (SIMM), a dual inline memory module (DIMM), etc. Alternatively, these devices are mounted with the SoC or integrated circuit in a chip stacking configuration, a package stacking configuration, or a multi-chip module configuration.

[0060] The SoC 706 in the illustrated embodiment may include various levels of cache memory, some of which may be shared between various components, while other cache memories may be dedicated caches. Such cache memories may be implemented as part of corresponding cache subsystems. At least some of the cache subsystems on the SoC 706 may be implemented according to the above reference. Figures 1 to 6 The various hardware and method embodiments discussed herein operate. Thus, at least some of the various cache subsystems on the SoC 706 may be arranged to predict the way in which the requested cache line is stored, and further configured to generate and store an indication when the prediction is correct. For subsequent access requests to the currently valid cache line, such cache subsystems may use the indication to confirm that the cache line is stored in the predicted way, and thus cancel the verification operation (e.g., the tag read and compare operation discussed above, although other mechanisms for verification may also be considered). Cancelling the verification operation may reduce power consumption and may also improve the performance of the cache subsystem.

[0061] Peripheral devices 704 include any desired circuitry, depending on the type of system 700. For example, in one embodiment, peripheral devices 704 include devices for various types of wireless communications such as Wi-Fi, Bluetooth, cellular, global positioning systems, etc. In some embodiments, peripheral devices 704 also include additional storage, including RAM storage, solid-state storage, or disk storage. Peripheral devices 704 include user interface devices such as display screens, including touch screens or multi-touch screens, keyboards or other input devices, microphones, speakers, etc.

[0062] As shown, system 700 is shown as having applications in a wide range of fields. For example, system 700 can be used as a part of a chip, circuit, component, etc. of a desktop computer 710, a laptop computer 720, a tablet computer 730, a cellular or mobile phone 740, or a TV 750 (or a set-top box coupled to a TV). A smart watch and a health monitoring device 760 are also shown. In some embodiments, smart watch 760 may include various general computing related functions. For example, smart watch 760 may provide access to email, mobile phone services, user calendars, etc. In various embodiments, the health monitoring device may be a dedicated medical device or otherwise include dedicated health-related functions. For example, a health monitoring device may monitor the vital signs of a user, track the proximity of a user to other users for the purpose of epidemiological social distance, contact tracking, provide communications to emergency services in the event of a health crisis, etc. In various embodiments, the above-mentioned smart watch may include or may not include some or any health monitoring related functions. Other wearable devices are also envisioned, such as devices worn around the neck, devices that can be implanted in the human body, glasses designed to provide enhanced and / or virtual reality experience, and the like.

[0063] The system 700 may also be used as part of a cloud-based service 770. For example, the previously mentioned devices and / or other devices may access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Still further, the system 700 may be used in one or more devices in a home other than those previously mentioned. For example, a home appliance may monitor and detect noteworthy situations. For example, various devices in a home (e.g., a refrigerator, a cooling system, etc.) may monitor the status of the device and provide an alert to the homeowner (or, for example, a maintenance agency) if a particular event is detected. Alternatively, a thermostat may monitor the temperature in a home and may automatically adjust the heating / cooling system based on a history of responses by the homeowner to various situations. Figure 7Applications of the system 700 to various modes of transportation are also illustrated. For example, the system 700 may be used for control and / or entertainment systems for airplanes, trains, buses, taxis, private cars, watercraft ranging from private boats to cruise ships, scooters (for rental or private use), and the like. In various cases, the system 700 may be used to provide automated guidance (e.g., self-driving vehicles), general system control, and the like. Any of these and many other implementations are possible and contemplated. Note that Figure 7 The devices and applications shown are exemplary only and are not intended to be limiting. Other devices are possible and contemplated.

[0064] This disclosure includes references to "an embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). Embodiments are different specific implementations or examples of the disclosed concepts. References to "an embodiment," "one embodiment," "a particular embodiment," etc. do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or substitutions that fall within the spirit or scope of this disclosure.

[0065] The present disclosure may discuss potential advantages that may be generated by the disclosed embodiments. Not all of these implementations will necessarily exhibit any or all of the potential advantages. Whether a particular implementation achieves an advantage depends on many factors, some of which are outside the scope of the present disclosure. In fact, there are many reasons why a particular implementation that falls within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular implementation may include other circuits outside the scope of the present disclosure, which, in combination with one of the disclosed embodiments, negate or weaken one or more of the disclosed advantages. In addition, suboptimal design execution of a particular implementation (e.g., a specific implementation technique or tool) may also negate or weaken the disclosed advantages. Even if a specific implementation of the technology is assumed, the realization of the advantages may still depend on other factors, such as the environmental conditions in which the specific implementation is deployed. For example, the input provided to a particular implementation may prevent one or more problems solved in the present disclosure from occurring in a particular occasion, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors external to the present disclosure, any potential advantages described herein should not be understood as claim limitations that must be met in order to prove infringement. Instead, the identification of such potential advantages is intended to show one or more types of improvements available to designers who benefit from the present disclosure. Permanently describing such advantages (eg, stating that a particular advantage "may occur") is not intended to convey a doubt as to whether such advantage can actually be achieved, but rather to recognize that achievement of such advantage typically depends on technical realities of additional factors.

[0066] Unless otherwise indicated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on the present disclosure, even if only a single example is described for a particular feature. The embodiments disclosed by the present invention are intended to be illustrative and non-restrictive, without any contrary statement in the present disclosure. Therefore, the present application is intended to allow claims covering the disclosed embodiments, as well as such alternatives, modifications and equivalent forms, which will be apparent to those skilled in the art who are aware of the effective effects of the present disclosure.

[0067] For example, features in this application may be combined in any suitable manner. Accordingly, new claims may be made during the prosecution of this patent application (or a patent application claiming priority thereto) for any such combination of features. In particular, with reference to the appended claims, features of dependent claims may be combined, where appropriate, with features of other dependent claims, including claims that are dependent on other independent claims. Similarly, features from corresponding independent claims may be combined, where appropriate.

[0068] Thus, while the appended dependent claims may be drafted such that each dependent claim is dependent upon a single other claim, additional dependencies are also contemplated. Any combination of dependent claims consistent with the present disclosure is contemplated and may be claimed in this or another patent application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0069] It is also contemplated that claims drafted in one format or legal type (eg, apparatus) are intended to support corresponding claims in another format or legal type (eg, method), where appropriate.

[0070] ***

[0071] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout this disclosure will be used to determine how to interpret claims drafted based on this disclosure.

[0072] Unless the context clearly dictates otherwise, reference to an item in the singular (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more." Thus, reference to "an item" in a claim does not exclude additional instances of that item without the accompanying context. A "plurality" item refers to a collection of two or more items.

[0073] The word "may" is used herein in a permissive sense (ie, having the potential to, being able to), rather than the mandatory sense (ie, must).

[0074] The terms "including" and "comprising" and forms thereof are open ended and mean "including, but not limited to."

[0075] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the expression "x or y" is equivalent to "x or y, or both," thus covering 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either x or y, but not both" make it clear that "or" is used in an exclusive sense.

[0076] The expressions "w, x, y, or z, or any combination thereof" or "at least one of w, x, y, and z" are intended to cover all possibilities involving a single element, up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "... at least one of w, x, y, and z" thus refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in the list of elements. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0077] In this disclosure, various "labels" may precede a noun or noun phrase. Unless the context provides otherwise, different labels used for a feature (e.g., "first circuit," "second circuit," "particular circuit," "given circuit," etc.) refer to different instances of the feature. In addition, unless otherwise specified, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0078] The phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude that there may be additional factors that may influence the determination. That is, a decision may be based only on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor such as C. This phrase is also intended to cover embodiments in which A is determined based only on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0079] The phrases "in response to" and "in response to" describe one or more factors that trigger an effect. The phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either in conjunction with the specified factors or independently of the specified factors. That is, the effect may be responsive to these factors alone, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "in response to B, A is performed." The phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. The phrase does not exclude that the execution of A may also be responsive to certain other factors, such as C. The phrase also does not exclude that the execution of A may be performed jointly in response to B and C. This phrase is also intended to cover embodiments in which A is performed only in response to B. As used herein, the phrase "in response to" is synonymous with the phrase "at least partially in response to." Similarly, the phrase "in response to" is synonymous with the phrase "at least partially in response to."

[0080] ***

[0081] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. This expression—[an entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be said to be "configured to" perform certain tasks even if the structure is not currently being operated. Thus, an entity described or stated as "configured to" perform certain tasks refers to a physical thing used to implement the task, such as a device, a circuit, a system with a processor unit, and a memory storing executable program instructions, etc. This phrase is not used herein to refer to an intangible thing.

[0082] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform those tasks / operations, even if not specifically stated.

[0083] The term "configured to" is not intended to mean "configurable to". For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA may be "configurable to" perform that function. After appropriate programming, the FPGA may then be considered "configured to" perform the particular function.

[0084] For purposes of U.S. patent applications based on the present disclosure, stating in a claim that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112(f) for that claim element. If the applicant wishes to invoke section 112(f) during prosecution of a U.S. patent application based on the present disclosure, it would use the “means for [performing the function]” structure to phrase the claim element.

[0085] Different "circuits" may be described in the present disclosure. These circuits or "circuits" constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom designed or taken from standard libraries. In various specific implementations, circuits may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be generally referred to as "units" (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units are also referred to as circuits or circuit systems.

[0086] Thus, the disclosed circuits / units / components and other elements shown in the drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the functionality of that circuit. For example, a particular "decode unit" may be described as performing the function of "processing an opcode for an instruction and routing the instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform that function. For a person skilled in the computer arts, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0087] In various embodiments, as described in the preceding paragraphs, circuits, units, and other elements may be defined by the functions or operations they are configured to implement. The arrangement relative to each other and such circuits / units / components and the way they interact form a microarchitecture definition of hardware, which is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, the microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall into the broader structure described by the microarchitecture definition. That is, a technician with a microarchitecture definition provided in accordance with the present disclosure can implement the structure by coding a description of a circuit / unit / component in a hardware description language (HDL) such as Verilog or VHDL without excessive experimentation and using the application of ordinary technicians. HDL descriptions are often expressed in a way that can be displayed as functional. However, for those skilled in the art, the HDL description is a way to convert the structure of a circuit, unit, or component into the next level of specific implementation details. Such HDL descriptions may take the form of behavioral code (which is generally non-synthesizable), register transfer language (RTL) code (which is generally synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL description may be sequentially synthesized for a library of cells designed for a given integrated circuit manufacturing technology, and may be modified for timing, power, and other reasons to obtain a final design database that is transmitted to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuits or portions thereof may also be custom designed in a schematic editor and captured into an integrated circuit design along with the synthesized circuitry. The integrated circuit may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuit, and / or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized into a programmable logic array such as a field programmable gate array (FPGA), and may be implemented in an FPGA. This decoupling between the design of a set of circuits and the subsequent low-level implementation of those circuits often leads to a situation where a circuit or logic designer never specifies a specific set of structures for the low-level implementation beyond a description of what the circuits are configured to do, because that process is performed at different stages of the circuit implementation process.

[0088] The fact that many different low-level combinations of circuit elements can be used to achieve the same specification of a circuit results in a large number of equivalent structures for that circuit. As noted, these low-level circuit implementations can vary depending on variations in manufacturing technology, the foundry selected to manufacture the integrated circuit, the cell libraries provided for a particular project, etc. In many cases, the selection made by different design tools or methodologies to produce these different implementations can be arbitrary.

[0089] Furthermore, for a given embodiment, a single implementation of a particular functional specification of a circuit typically includes a large number of devices (e.g., millions of transistors). Thus, the shear volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single embodiment, let alone the large number of equivalent possible implementations. For this reason, the present disclosure describes the structure of the circuit using functional shorthand commonly used in the industry.

[0090] Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to encompass all such variations and modifications.

Claims

1. A device comprising: a cache configured to store information in cache lines arranged in multiple ways; a request circuit configured to generate a request to access a specific cache line in the cache; prediction circuitry configured to generate a prediction as to which of the multiple ways of the cache includes the particular cache line; and a comparison circuit configured to verify the prediction by comparing a particular address tag associated with the particular cache line with a cache tag corresponding to a predicted one of the multiple ways; The prediction circuit is further configured to, in response to the comparison circuit determining that the prediction is correct, store a confirmation indication indicating that the prediction is correct, and wherein for a subsequent access request for the specific cache line, the cache is configured to abandon verifying the prediction that the specific cache line is included in the one of the multiple ways based on the confirmation indication indicating that the prediction is correct.

2. The apparatus according to claim 1, further comprising: a tag memory configured to store address tags corresponding to cache lines stored in the cache, wherein the prediction circuit is configured to access the specific address tag corresponding to the specific cache line; Abandoning the verification includes abandoning reading the cache tag and abandoning comparing the specific address tag with the cache tag.

3. The apparatus of claim 2, wherein the comparison circuit is configured to determine that the prediction is correct based on the particular address tag matching the cache tag. 4 . The apparatus of claim 2 , wherein the tag memory is configured to store virtual address tags, wherein some of the virtual address tags correspond to entries stored in the cache.

5. The apparatus of claim 1, further comprising a confirmation bit memory configured to store a plurality of confirmation bits, wherein a confirmation bit of the plurality of confirmation bits, when set, corresponds to a correct prediction made by the prediction circuit.

6. The apparatus of claim 5, wherein for a subsequent prediction of the particular cache line, the cache is configured to query the confirmation bit memory to determine whether a previous prediction was correct. 7 . The apparatus according to claim 5 , wherein the cache is configured to reset a specific confirmation bit stored in the confirmation bit storage in response to evicting a corresponding cache line from the cache.

8. The apparatus of claim 5, wherein the cache is configured to reset a particular confirmation bit stored in the confirmation bit storage in response to an address translation failure associated with a corresponding cache line.

9. The apparatus of claim 1, wherein the cache is an instruction cache configured to store instructions, and wherein the request circuit is an instruction fetch unit.

10. A method comprising: Storing cache lines into multiple ways of the cache; generating, using request circuitry, a request to access a particular cache line in the cache; generating, using prediction circuitry, a prediction as to which of the multiple ways of the cache includes the particular cache line; validating the prediction using a comparison circuit, wherein the validating comprises comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the multiple ways; responsive to the comparing indicating that the prediction is correct, storing a confirmation bit using the prediction circuit; as well as For subsequent access requests for the specific cache line, based on the confirmation bit indicating that the prediction is correct, verifying a subsequent prediction that the specific cache line is included in the one of the multiple ways is abandoned.

11. The method according to claim 10, wherein: Abandoning verification of the subsequent prediction includes: abandoning reading the cache tag from the cache; and Comparing the specific address tag with the cache tag is abandoned.

12. The method according to claim 11, further comprising: storing a plurality of address tags including the particular address tag in a tag memory, wherein some of the plurality of address tags correspond to entries stored in the cache; determining that the prediction is correct based on the specific address tag matching the cache tag; as well as The confirmation bit is stored in a confirmation bit memory.

13. The method according to claim 12, further comprising: In response to a subsequent prediction of the particular cache line, the confirmation bit store is queried to determine whether the previous prediction was correct.

14. The method according to claim 12, further comprising: In response to evicting a cache line corresponding to a specific confirmation bit from the cache, the specific confirmation bit stored in the confirmation bit storage is reset.

15. The method according to claim 12, further comprising: In response to an address translation fail associated with a cache line corresponding to a particular confirm bit, the particular confirm bit stored in the confirm bit storage is reset.

16. A system comprising: an instruction cache configured to store instructions in cache lines arranged in multiple ways; an instruction fetch circuit, the instruction fetch circuit being configured to fetch instructions from the instruction cache; a prediction circuit configured to generate a prediction about a specific way of the multiple ways including the specific cache line in response to a request for the specific cache line by the instruction fetch circuit; and a comparison circuit configured to determine whether the prediction is correct by comparing a cache tag corresponding to the particular one of the multiple ways with an address tag corresponding to the particular cache line; wherein the prediction circuit is further configured to, in response to determining that the prediction is correct, cause a specific confirmation bit to be set; and The instruction cache is configured to, for a subsequent request for the specific cache line, abandon reading the cache tag from the instruction cache and comparing the address tag with the cache tag in response to the specific confirmation bit being set.

17. The system of claim 16, further comprising a confirmation bit memory configured to store a plurality of confirmation bits including the particular confirmation bit, wherein some of the plurality of confirmation bits indicate that the corresponding prediction is correct when set, and wherein the prediction circuit is configured to cause the particular confirmation bit to be stored in the confirmation bit memory in response to determining that the prediction is correct.

18. The system of claim 17, wherein the instruction cache is configured to reset the particular validation bit in response to determining that an address translation associated with the particular cache line has been invalidated.

19. The system of claim 17, wherein the instruction cache is configured to cause the particular validation bit to reset in response to evicting the particular cache line from the instruction cache.

20. The system of claim 16, wherein the address tag is a virtual address tag, and wherein the tag memory is configured to store a plurality of virtual address tags, wherein some of the virtual address tags correspond to some of the plurality of cache lines.

Images