Host system, data computation method, and independent computable memory redundancy system

Abstract

The embodiment of the application relates to the application field of storage devices, and discloses a host system, a data calculation method and an independent computable storage redundancy system. The host system comprises: an application program, which is used for issuing a task request to a multi-storage driver module; and the multi-storage driver module, which is used for: determining a target computable storage device where to-be-calculated data is located according to the task request and an address mapping relationship of each segmented data and the corresponding computable storage device; sending a task execution program and a first calculation request to the target computable storage device, so that the target computable storage device performs data calculation based on the task execution program. The host system in the application can determine the real storage position of the to-be-calculated data, and issue the corresponding calculation request to the correct computable storage device, so that the computable storage device performs data calculation based on the task execution program, thereby realizing the application of the RAID technology to the computable storage device.

Description

Technical Field

[0001] This application relates to the field of storage device applications, and in particular to a host system, a data computing method, and a redundant system of independently computable memory. Background Technology

[0002] Redundant Arrays of Inexpensive Disks (RAID) is a data storage technology that allows multiple data operations to be performed simultaneously by distributing data across multiple disks.

[0003] Latency predictability refers to the predictability and stability of time delays for data transmission, processing, or response in a computer system or network. It means that when a system performs a specific task or operation, it can reliably provide a defined time delay without experiencing unstable or unpredictable delays.

[0004] Currently, RAID technology is applied to storage systems to achieve predictable latency, thereby avoiding the inability of a single device to provide predictable latency to the system when it is overloaded. In developing this application, the inventors discovered at least the following problems in the prior art:

[0005] Computational Storage Drives (CSDs) employ near-data processing technologies, requiring data processing within the device itself. Data layout and management are typically driven by applications on the host machine. RAID technology virtualizes the storage space of multiple devices into a single global space, hiding the true location of the data from the user. This prevents application computation requests from being routed to the correct CSD device; therefore, existing RAID technologies cannot be directly applied to CSDs. Computational storage drives contain various shared hardware resources, including flash memory, RAM, and computing resources. During resource sharing, contention and waiting inevitably occur, making computational and read / write requests in the computational storage drive subject to unpredictable latency due to workload. This poses a risk of request timeouts for latency-sensitive processes on the host machine, degrading the user experience. Summary of the Invention

[0006] This application provides a host system, a data computing method, and an independent computable memory redundancy system to apply RAID technology to computable storage devices.

[0007] The embodiments of this application provide the following technical solutions:

[0008] In a first aspect, embodiments of this application provide a host system that communicatively connects to at least two computeable storage devices. The host system includes an application program and a multi-memory driver module, wherein...

[0009] The application connects to the multi-memory driver module and is used to send task requests to the multi-memory driver module, wherein the task request includes a first computation request;

[0010] Multi-memory driver module, connected to the application, is used for:

[0011] Based on the task request, the address mapping relationship between each segment of data and the corresponding computable storage device is determined to identify the target computable storage device where the data to be computed is located. The data to be computed includes at least one segment of data.

[0012] A task execution program and a first computation request are sent to the target computable storage device so that the target computable storage device performs data computation based on the task execution program.

[0013] In a second aspect, embodiments of this application provide a data calculation method, which is applied to a host system of the first aspect, wherein the host system is communicatively connected to at least two computable storage devices, and the data calculation method includes:

[0014] Determine the target computable storage device where the data to be computed is located;

[0015] Send a task execution program and a computation request to the target computable storage device so that the target computable storage device can perform data computation based on the task execution program.

[0016] Thirdly, embodiments of this application provide an independent computable memory redundancy system, which includes...

[0017] Such as the host system in the first aspect;

[0018] At least two computable storage devices are communicatively connected to the host system for performing data computations based on computation requests sent by the host system.

[0019] Fourthly, embodiments of this application also provide a non-volatile computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, cause the processor to perform the data calculation method as described in the second aspect.

[0020] The beneficial effects of this application embodiment are as follows: Unlike the prior art, this application embodiment provides a host system that communicatively connects to at least two computable storage devices. The host system includes an application program and a multi-memory driver module. The application program, connected to the multi-memory driver module, is used to issue task requests to the multi-memory driver module, wherein the task request includes a first computation request. The multi-memory driver module, connected to the application program, is used to: determine the target computable storage device where the data to be computed is located based on the task request and the address mapping relationship between each segment of data and the corresponding computable storage device, wherein the data to be computed includes at least one segment of data; and send a task execution program and the first computation request to the target computable storage device so that the target computable storage device performs data computation based on the task execution program.

[0021] By using the multi-memory driver module to determine the target computing storage device where the data to be computed is located based on the task request sent by the application and the address mapping relationship between each segment of data and the corresponding computing storage device, the host system in this application can determine the actual storage location of the data to be computed and send the corresponding computing request to the correct computing storage device, so that the computing storage device can perform data computation based on the task execution program, thereby realizing the application of RAID technology to computing storage devices. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0023] Figure 1 This is a schematic diagram of the structure of a host system provided in an embodiment of this application;

[0024] Figure 2 This is a detailed structural diagram of a host system provided in an embodiment of this application;

[0025] Figure 3 This is a schematic diagram of segmented data and verification data provided in an embodiment of this application;

[0026] Figure 4 This is a schematic diagram of the structure of a multi-memory driver module provided in an embodiment of this application;

[0027] Figure 5 This is a schematic diagram illustrating the mapping relationship between virtual computing memory and the functional data memory of a computable storage device, provided in an embodiment of this application.

[0028] Figure 6 This is a schematic diagram of the host system's workflow when multiple memory driver modules are in parallel mode, provided by an embodiment of this application.

[0029] Figure 7 This is a schematic diagram of the architecture of an NVMe computing program command set provided in an embodiment of this application;

[0030] Figure 8 This is a schematic diagram of the structure of a device driver module provided in an embodiment of this application;

[0031] Figure 9 This is a functional schematic diagram of a coordination processing module provided in an embodiment of this application;

[0032] Figure 10 This is a flowchart illustrating a data calculation method provided in an embodiment of this application;

[0033] Figure 11 This is a schematic diagram of the structure of an independent computable memory redundancy system provided in an embodiment of this application;

[0034] Figure 12 This is a detailed structural diagram of an independent computable memory redundancy system provided in an embodiment of this application.

[0035] Explanation of reference numerals in the attached figures:

[0036] Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0038] It should be noted that, unless there is a conflict, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. Moreover, the terms "first," "second," and "third" used in this application do not limit the data or execution order, but only distinguish identical or similar items with essentially the same function and effect.

[0039] Before providing a detailed description of this application, the nouns and terms used in the embodiments of this application are explained, and the nouns and terms used in the embodiments of this application shall be interpreted as follows:

[0040] (1) Independent disk redundant array

[0041] Redundant Array of Independent Disks (RAID) is a data storage technology designed to improve the performance, redundancy, and reliability of data storage systems. RAID uses multiple hard drives simultaneously to form a single logical storage unit, providing higher performance and data protection than a single hard drive. The core idea of ​​RAID technology is to distribute data across multiple disks, allowing multiple data operations to occur concurrently.

[0042] This not only improves data read and write speeds but also increases system fault tolerance. If one hard drive fails, data can still be recovered from the other hard drives, ensuring data reliability and continuity. Common RAID levels include RAID 0, RAID 1, RAID 5, and RAID 6, each with different characteristics and application scenarios.

[0043] (2) Computable memory

[0044] Traditional data processing is computation-centric, involving the massive data transfer between external storage and the computing core through multi-layered redundancy and low-speed I / O hardware and software. This causes two major problems: first, it wastes the high-performance advantage of the internal storage channels; and second, data transfer generates a large amount of additional power consumption.

[0045] Therefore, a widening gap has emerged between the current linearly growing data processing capacity and the exponentially growing data processing demand. In recent years, near-data processing (NDP) technology, centered on data, has been seen as a breakthrough point for bridging this gap. Among these technologies, flash-based computational storage drives (CSDs) are a key direction for NDP development. Near-data processing performs computation closer to the data, offloading typical data-intensive and hardware-accelerated tasks from upper-layer applications to CSDs. The Storage Networking Industry Association (SNIA) has proposed a universal computational storage model, and the terminology defined therein will be referenced in the following text.

[0046] (3) Delay predictability

[0047] Latency predictability refers to the predictability and stability of time delays for data transmission, processing, or response in a computer system or network. It means that when a system performs a specific task or operation, it can reliably provide a defined time delay without unstable or unpredictable latency. Latency predictability is of great significance in the storage field, as it ensures the stability of data operations, allowing users to complete data read and write operations within a specific timeframe.

[0048] In distributed storage systems, data is typically replicated and synchronized across multiple nodes. If the storage system's latency is unpredictable, data replication and synchronization may be delayed, leading to data inconsistency. Furthermore, latency predictability can improve overall system performance. By reducing latency variance, the storage system can allocate resources more efficiently, reduce queuing times, and increase data throughput. Finally, latency predictability also helps accelerate fault recovery. When a storage system fails, latency predictability ensures that failover and data recovery processes can be completed within a finite timeframe, reducing the risk of data loss.

[0049] Latency predictability faces many challenges in the flash memory field. First, common background tasks in flash memory, such as garbage collection and wear leveling, can impact foreground I / O latency. Second, competition for queue resources by concurrent multitasking can lead to unpredictable latency. Furthermore, data layout and read / write amplification can also interfere with latency.

[0050] To address these challenges, NVMe 1.4 introduced I / O Determinism, providing better Quality of Service (QoS) for the host through Non-Volatile Memory Sets (NVM Sets) and Persistent Memory Logical Block Management (PLM). However, the Deterministic Window (DTWIN) and Non-Deterministic Window (NDWIN) proposed in the protocol are merely soft latency guarantee protocols; the device makes its best effort to provide latency guarantees to the host according to the window agreement. If the SSD uses up its over-provisioning (OP) space in DTWIN, the SSD will also proactively enter NDWIN.

[0051] To address this issue, some approaches utilize RAID technology to prevent unpredictable latency from occurring when a single device is overloaded. RAID not only ensures data security, but the redundant data can also provide better QoS. By sending requests to idle devices with redundant data, requests are prevented from queuing on busy devices, thus ensuring latency predictability. Common latency predictability solutions include: request cloning, application hints, coordinated garbage collection (GC), and preemptive GC. Among these, solutions incorporating redundant data often provide stronger latency guarantees.

[0052] However, since compute-enabled storage uses near-data processing technology, data needs to be processed inside the device. The layout and management of data are usually dominated by applications in the host. RAID technology virtualizes the storage space of multiple devices into a global space, hiding the real location of the data from the user. This makes it impossible for application computing requests to be sent to the correct CSD device. Therefore, existing RAID technology cannot be directly applied to CSD devices.

[0053] Based on this, embodiments of this application provide a host system that communicates with at least two computeable storage devices to determine the actual storage location of the data to be computed and to send the corresponding compute request to the correct computeable storage device, thereby realizing the application of RAID technology to computeable storage devices.

[0054] The technical solution of this application will be described in detail below with reference to the accompanying drawings:

[0055] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a host system provided in an embodiment of this application;

[0056] In this embodiment of the application, the host system communicates with at least two computable storage devices.

[0057] like Figure 1 As shown, the host system 100 includes an application program 101 and a multi-memory driver module 102. The application program 101 and the multi-memory driver module 102 are communicatively connected. The host system 100 is connected to at least two computeable storage devices.

[0058] Application 101 connects to the multi-memory driver module 102 and is used to send task requests to the multi-memory driver module 102.

[0059] The multi-memory driver module 102, connected to the application program 101, is used to: determine the target computing storage device where the data to be calculated is located based on the task request and the address mapping relationship between each segment of data and the corresponding computing storage device; send the task execution program and the first calculation request to the target computing storage device so that the target computing storage device performs data calculation based on the task execution program; specifically, the data calculation is completed within a predictable latency range based on the task execution program.

[0060] Please see Figure 2 , Figure 2 This is a detailed structural diagram of a host system provided in an embodiment of this application;

[0061] like Figure 2 As shown, the host system 100 includes an application program 101, a multi-memory driver module 102, and a device driver module 103. The application program 101, the multi-memory driver module 102, and the device driver module 103 are connected in pairs via communication links.

[0062] Application 101, connected to multi-memory driver module 102, is used to send task requests to multi-memory driver module 102. The task request includes at least one of the following: device memory allocation request, flash memory read / write request, task executor registration request, and first computation request.

[0063] Specifically, the device memory allocation request instructs the computable storage device to allocate a portion of its functional data memory (FDM) for data computation; the flash memory read / write request instructs the computable storage device to write data to flash memory or read data stored in flash memory; the task executor registration request instructs the computable storage device to download the corresponding task executor, which is a program in the computable storage device used to execute a single task; and the first computation request instructs the computable storage device to execute a data computation task.

[0064] In this embodiment, the task request issued by the application is used to instruct the computable storage device to perform related operations. The task request is intercepted by the multi-memory driver module 102. After the multi-memory driver module 102 determines the target computable storage device, it issues the task program to the target computable storage device. The target computable storage device is the computable storage device that actually performs the data computation task, and there is at least one target computable storage device.

[0065] The multi-memory driver module 102, connected to the application program 101, is used to: determine the target computing storage device where the data to be computed is located based on the address mapping relationship between each segment of data and the corresponding computing storage device according to the task request; and send a task execution program and a first computation request to the target computing storage device so that the target computing storage device performs data computation based on the task execution program. Each segment of data is a portion of striped data stored in each computing storage device; several segments of data constitute a striped data; the data to be computed is the data for which the computing storage device needs to perform a data computation task; the data to be computed includes at least one segment of data.

[0066] In this embodiment of the application, Linux is used as the example. Based on the original Multi-Disk module of the host kernel, a multi-memory driver module (Multi-CSD module) is implemented. The multi-memory driver module 102 is the main module for managing multiple computeable storage devices. It includes basic RAID functions, mainly including: address mapping from a virtual computeable storage device to multiple real computeable storage devices according to RAID5 technology, generating parity data and reconstructing data, metadata management, disk synchronization, etc.

[0067] Specifically, taking RAID5 technology as a redundancy strategy for multiple computeable storage devices (CSD arrays) as an example, the multi-memory driver module 102 stores the parity information in different computeable storage devices. When a computeable storage device is busy due to GC, it can read data from other idle computeable storage devices through degraded read, thereby reconstructing the target data with the parity data and obtaining deterministic latency.

[0068] Understandably, RAID 5 technology can fully leverage the computing performance of CSD arrays. A single operation on a computeable storage device often involves a large amount of data, and since continuous data is distributed across various computeable storage devices using RAID 5, combining it with RAID technology not only allows for the distributed use of parallel computing power but also ensures data security and predictable latency. Furthermore, RAID 5 is suitable for scenarios where read loads are much higher than write loads, which aligns perfectly with the needs of computeable storage devices. Existing NDP operations such as database lookups, distributed computing models (Big Data MapReduce), and recommendation system acceleration are all read-first-compute operations; compute-first-write operations are only a small portion, such as transparent compression and transparent encryption. Therefore, from an application perspective, computeable storage devices are more often used in scenarios where a large number of read operations follow a write operation.

[0069] In this embodiment, before the application 101 sends a task request to the multi-memory driver module 102, the host system is further configured to: store several segment data corresponding to a stripe of data and the corresponding parity data in different computable storage devices. Specifically, each parity data segment corresponds one-to-one with a computable storage device, and the size of the stripe block in each computable storage device is greater than or equal to a preset stripe depth.

[0070] Specifically, the striped data is the data to be stored. The multi-memory driver module 102 divides the data to be stored into several segments, performs data calculations on these segments to obtain corresponding check data, and then stores the check data and each segment data into different computeable storage devices. At the same time, the multi-memory driver module 102 stores the address mapping relationship between each segment data and the corresponding computeable storage device.

[0071] In this embodiment, a chunk is the basic unit within a stripe, also known as the stripe depth, which is a continuous area of ​​the stripe on a disk. Since the continuous size of data affects the computational process of the computing storage device, to avoid excessive overhead caused by excessively small chunks amplifying the number of computations, the size of the chunks in this application is greater than or equal to a preset stripe depth. For example, the preset stripe depth is 1MB, and the minimum size of a chunk is 1MB. The preset stripe depth can be set by those skilled in the art according to actual conditions and is not limited in this embodiment. Preferably, the chunk size in this application is 1MB.

[0072] Please see Figure 3 , Figure 3 This is a schematic diagram of segmented data and verification data provided in an embodiment of this application;

[0073] like Figure 3 As shown, computeable storage device 1 (CSD 1) stores segmented data A1, segmented data B1, segmented data C1 and parity data Dp; computeable storage device 2 (CSD 2) stores segmented data A2, segmented data B2, parity data Cp and segmented data D1; computeable storage device 3 (CSD 3) stores segmented data A3, parity data Bp, segmented data C2 and segmented data D2; and computeable storage device 4 (CSD 4) stores parity data Ap, segmented data B3, segmented data C3 and segmented data D3.

[0074] Slice 1 includes segmented data A1, segmented data A2, and segmented data A3, with Ap being the checksum of slice 1; slice 2 includes segmented data B1, segmented data B2, and segmented data B3, with Bp being the checksum of slice 2; slice 3 includes segmented data C1, segmented data C2, and segmented data C3, with Cp being the checksum of slice 3; slice 4 includes segmented data D1, segmented data D2, and segmented data D3, with Dp being the checksum of slice 4.

[0075] In this application embodiment, compared to existing solutions where some RAID levels severely reduce the computing power of computable storage (e.g., RAID 2 / 3 / 4 uses dedicated disks to store parity data, completely wasting the computing power of the parity disk; RAID 1 has only 50% disk utilization and 50% computational utilization), this application fully utilizes the computing power of each computable storage device by storing segmented data and parity data corresponding to different stripes of data in each computable storage device, and by enabling each computable storage device to perform data computation tasks.

[0076] After several segments of data and their corresponding verification data are stored in different computeable storage devices, the multi-memory driver module 102 obtains the task request issued by the application 101, and, based on the address mapping relationship between each segment of data and its corresponding computeable storage device, determines the target computeable storage device where the data to be computed is located. It then sends a task execution program and a first computation request to the target computeable storage device, enabling the target computeable storage device to perform data computation based on the task execution program. This data computation includes, but is not limited to, database lookup acceleration, string lookup, recommendation system acceleration, and neural network training.

[0077] It is understood that when the multi-memory driver module 102 receives the task request issued by the application 101, the data to be computed has already been stored internally in the target computeable storage device using RAID technology. By distributing the data across multiple devices from the outset using RAID technology, the computeable storage device in this application can provide transparent parallel computing capabilities to the application, facilitating the development of CSD applications.

[0078] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of a multi-memory driver module provided in an embodiment of this application;

[0079] like Figure 4 As shown, the multi-memory driver module 102 includes a virtual computing memory 121, a global computing storage module 122, a task distribution module 123, a device management module 124, a mapping management module 125, and a data reconstruction module 126.

[0080] Specifically, the multi-memory driver module 102 manages multiple computable storage devices, abstracting them into a single computable storage device. Its main functions are divided into two parts:

[0081] One part is used for the management of computable storage devices: implemented by virtual computing memory 121, global computing storage module 122, and task distribution module 123; the other part is for RAID function: implemented by device management module 124, mapping management module 125, and data reconstruction module 126.

[0082] Virtual computing memory 121 is a virtual functional data memory, a contiguous block of memory on the host system 100 used to store logically contiguous but physically discontinuous data. Virtual computing memory 121 has an address mapping relationship with the functional data memory of each computable storage device. Virtual computing memory 121 allows applications to send device memory allocation requests without specifying the actual computable storage device; they can simply send the request to the / dev / mcsd device file registered with the multi-memory driver module 102. Functional data memory (FDM) is the memory within the computable storage device used to perform data computation tasks. It stores the data to be computed, intermediate variables, and computation results.

[0083] Please see Figure 5 , Figure 5 This is a schematic diagram illustrating the mapping relationship between virtual computing memory and the functional data memory of a computable storage device, provided in an embodiment of this application.

[0084] like Figure 5 As shown, the virtual computing memory 121 in the multi-memory driver module 102 has a one-to-one address mapping relationship with the functional data memory (FDM) of n computable storage devices. Here, CSD 1 represents the first computable storage device that is communicatively connected to the host system 100, and CSD n represents the nth computable storage device that is communicatively connected to the host system 100, where n is a positive integer. Figure 5 The CSD application is a program that calls the computing interface of the computing storage device and uses near-data processing technology. The CSD application is used to send task requests to the multi-memory driver module 102.

[0085] The global computing storage module 122 is a globally registered computing storage function (CSF). A CSF is a program in a computing storage device used to execute a single task, i.e., a task execution program.

[0086] The global computing storage module 122 is used to cache the task execution programs downloaded by the application, establish a mapping relationship between the global identifier (CSF ID) of each task execution program and the program identifier in the corresponding target computing storage device, and send the corresponding task execution program to the target computing storage device.

[0087] The global identifier is the identifier (ID) of a task executor in the global space, and the program identifier is the identifier (ID) of a task executor in the target computable storage device. Each task executor has a unique global identifier, that is, in the global space of the host system 100, one global identifier represents one task executor, and the global identifier is set by the multi-memory driver module 102.

[0088] Each task execution program has a unique program identifier in its corresponding target computeable storage device. Within a single computeable storage device, the program identifier distinguishes different task execution programs, but it is unique only within that device. Program identifiers may be duplicated across different computeable storage devices, therefore a global mapping is required in the multi-memory driver module 102. When a task execution program needs to be deployed to a target computeable storage device, the global compute storage module 122 records the mapping relationship between the global identifier of that task execution program and the program identifier in the corresponding target computeable storage device.

[0089] The task distribution module 123 is used to send the corresponding task execution program and computation request to the target computable storage device. The computation request includes a first computation request or a second computation request. The first computation request is a computation request sent by the application program 101 to the multi-memory driver module 102. It is also a computation request sent by the multi-memory driver module 102 to the target computable storage device when the multi-memory driver module 102 is in transparent mode and the data to be computed corresponds to only one computable storage device.

[0090] The second computation request is a computation request obtained by segmenting the first computation request when the multi-memory driver module 102 is in parallel mode. It is also the computation request actually sent to each target computable storage device in parallel mode.

[0091] The device management module 124 is used to manage the computing storage devices connected to the host system 100, such as monitoring the status and performance indicators of the computing storage devices, diagnosing and handling faults, and managing capacity.

[0092] The mapping management module 125 is used to establish the address mapping relationship between each segment of data and the corresponding computable storage device, and to determine the target computable storage device corresponding to each piece of data to be computed.

[0093] The data reconstruction module 126 is used to read segmented data and verification data from a computing storage device in an idle state, and perform verification calculations on the segmented data and verification data to obtain target data. The target data is the segmented data stored in a computing storage device in a busy state.

[0094] In this embodiment, compared to existing solutions where the application manages the CSD array (i.e., the application divides the data and places it on different devices, then distributes requests to each device for parallel computation during execution), the complexity of programming increases. The application must understand the details of the hardware devices, and the computational logic needs to be specifically adapted, which brings drawbacks to CSD application development. By distributing the first computation request and task execution program to the target computeable storage device through the multi-memory driver module 102, this application can reuse RAID technology to manage multiple computeable storage devices, improving the parallelism of the computeable storage devices. Furthermore, by distributing data across multiple devices from the outset using RAID technology, the computeable storage devices can provide transparent parallel computing capabilities to the application, facilitating the development of CSD applications.

[0095] In this embodiment of the application, the device memory allocation request includes the size of a first memory of a computable storage device, wherein a device memory allocation request corresponds to a target computable storage device, the first memory is the functional data memory in the computable storage device used for data calculation, and the first memory is less than or equal to a preset stripe depth.

[0096] In this embodiment, the multi-memory driver module 102 is specifically used to: obtain the device memory allocation request sent by the application to the device file; cache each task execution program downloaded by the application based on the global computing storage module; obtain the logical address of the data to be computed sent by the application; and, based on the mapping management module, query the address mapping relationship between each segment of data and the corresponding computable storage device to determine the target computable storage device corresponding to the logical address of the data to be computed.

[0097] Specifically, the device file is a file registered by the multi-memory driver module, such as the / dev / mcsd device file. The device file serves as the interface between the multi-memory driver module 102 and the user program 101. The user program 101 determines the size of the first memory based on the size of a single data processing operation, i.e., the size of the segmented data, and calls the device control interface function (IOCTL function) in the system to send a device memory allocation request to the device file. This device memory allocation request includes the size of the first memory of a computable storage device and the total size of the functional data memory used to perform this data computation task. The first memory is the functional data memory in the computable storage device used for data computation, and the first memory is less than or equal to a preset stripe depth; for example, the maximum first memory is 1MB.

[0098] Furthermore, the multi-memory driver module 102 obtains the device memory allocation request sent by the application to the device file, and after determining the target computable storage device, sends the device memory allocation request to the target computable storage device.

[0099] Then, application 101 downloads the task execution programs required for this data computation task. These task execution programs support segmented or out-of-order execution of data computation. Global computing storage module 122 caches each task execution program downloaded by the application and establishes a mapping relationship between the global identifier of each task execution program and the program identifier in the corresponding target computing storage device before distributing the task execution program to the corresponding target computing storage device.

[0100] Application 101 sends the logical address of the data to be computed to the multi-memory driver module 102. Correspondingly, the multi-memory driver module 102 obtains the logical address of the data to be computed, and the mapping management module 125 queries the address mapping relationship between each segment of data and the corresponding computable storage device to determine the target computable storage device corresponding to the logical address of the data to be computed. The target computable storage device is the computable storage device that actually stores the data to be computed.

[0101] Furthermore, based on the current computing mode of the multi-memory driver module 102, the task distribution module 123 sends a task execution program and a first computing request to the target computing storage device so that the same target computing storage device can perform data computing tasks, or it segments the first computing request to obtain several second computing requests, and sends the task execution program and the second computing requests to the target computing storage device so that the several target computing storage devices can perform data computing tasks in parallel.

[0102] In this embodiment, the multi-memory driver module 102 is further configured to: control at least two computable storage devices to perform parallel computing or control the host system to simulate computable storage devices to perform data computing according to different computing modes.

[0103] Specifically, the computing modes include parallel mode or transparent mode. In parallel mode, the multi-memory driver module 102 controls multiple computable storage devices connected to the host system 100 to perform parallel computing; in transparent mode, the multi-memory driver module 102 controls one of the computable storage devices connected to the host system 100 to perform data computing, or controls the host system 100 to simulate a computable storage device to perform data computing.

[0104] In parallel mode, application 101 is unaware of virtual computing memory 121; for application 101, the granularity of computation is a file or address segment. Based on the size of a single data processing operation, application 101 calls the system's device control interface function (IOCTL function) to send a device memory allocation request to the device file. The multi-memory driver module 102 obtains this device memory allocation request.

[0105] Application 101 downloads the task execution programs required for this data computation task, and the global computation storage module 122 caches each downloaded task execution program. Application 101 sends a file identifier or the logical address of the data to be computed to the multi-memory driver module 102, with no size limit. It is understandable that using a file to call the computation interface is more user-friendly, so application 101 only needs to pass the file identifier and does not need to know the file's location in the computational storage device.

[0106] The mapping management module 125 queries the address mapping relationship between each segment of data and the corresponding computable storage device based on the logical address of the data to be computed, and determines the target computable storage device corresponding to the logical address of the data to be computed; or, the mapping management module 125 determines the target computable storage device based on the file identifier. Then, the task distribution module 123 performs data segmentation and transmission operations.

[0107] In parallel mode, the task distribution module 123 is specifically used to: after determining the target computable storage device corresponding to the data to be computed, segment the first computing request sent by the application 101 to obtain several second computing requests; send the corresponding task execution program and device memory allocation request to the several target computable storage devices in parallel, so that each target computable storage device downloads the task execution program and allocates a portion of space in the functional data memory as the first memory; send the corresponding second computing request to the several target computable storage devices in parallel, so that each target computable storage device reads the segmented data from the device memory into the first memory, and performs data computation on the segmented data in the first memory based on the task execution program.

[0108] Specifically, after determining the target computeable storage device corresponding to the data to be computed, the task distribution module 123 segments the first compute request sent by the application 101 to obtain several second compute requests. Each target computeable storage device corresponds to one second compute request. The second compute request instructs the target computeable storage device to perform data computation based on the task execution program. The second compute request includes read requests and task execution requests. It can be understood that the data is distributed across multiple computeable storage devices using RAID technology. Each computeable storage device can only perform computations on its internal data. The significance of data segmentation is to break down the data computation task into multiple parts and distribute them to multiple computeable storage devices. Otherwise, logically continuous large amounts of data cannot be computed on a single computeable storage device.

[0109] The task distribution module 123 sends corresponding task execution programs and device memory allocation requests to several target computeable storage devices in parallel, so that each target computeable storage device downloads the task execution program and allocates a portion of its functional data memory as its first memory. It is understood that in a single computation in parallel mode, all target computeable storage devices should execute the same task execution program. Before distributing the task execution program to the corresponding target computeable storage device, the global compute storage module 122 establishes a mapping relationship between the global identifier of each task execution program and the program identifier in the corresponding target computeable storage device. Depending on the registration order, different target computeable storage devices may receive different program identifiers, but all correspond to the same task execution program.

[0110] Then, the task distribution module 123 sends corresponding second computation requests to several target computable storage devices in parallel, so that each target computable storage device reads segmented data from the device memory into the first memory, and performs data computation on the segmented data in the first memory based on the task execution program within a predictable latency range, and obtains the computation result.

[0111] Each of the computable storage devices 1101 includes a Computational Storage Engine Environment (CSEE), which runs a task execution program in the first memory to perform data computation.

[0112] Understandably, depending on the type of data computation task, the target computable storage device uses functional data memory in different ways. For example, in a target computable storage device, the number of primary memory units can be two: an input FDM and an output FDM. The target computable storage device reads the data to be computed (segmented data) from the device memory into the input FDM, runs the task execution program in the input FDM to perform data computation, obtains the computation result, and then writes the computation result into the output FDM.

[0113] After the target computable storage device writes the calculation result to the output FDM, the multi-memory driver module 102 reads the calculation result from the output FDM back to the virtual computing memory 121 and determines whether all segment data corresponding to the data to be calculated has completed the data calculation. If all segment data corresponding to the data to be calculated has completed the data calculation, the multi-memory driver module 102 sends the calculation result to the application program 101; if at least one segment data has not completed the data calculation, the multi-memory driver module 102 sends the failure reason to the application program 101.

[0114] Understandably, the second computation request is sent non-blockingly to each target computeable storage device. After completing the data computation task, the target computeable storage device replies to the host system 100 with a message. Upon receiving the message, the device driver module 103 notifies the corresponding thread. The multi-memory driver module 102 only needs to communicate with the device driver module 103 to determine whether the target computeable storage device has completed the data computation task. If the target computeable storage device fails to complete the data computation task, it replies to the host system 100 with a failure message. The multi-memory driver module 102 then sends the reason for the failure to the application program 101.

[0115] Please see Figure 6 , Figure 6 This is a schematic diagram of the host system's workflow when multiple memory driver modules are in parallel mode, provided by an embodiment of this application.

[0116] like Figure 6 As shown, the host system's workflow when the multi-memory driver module is in parallel mode includes:

[0117] Step S1: The CSD application starts;

[0118] Specifically, application 101 includes a CSD application, i.e., a compute storage application, which is used to issue task requests to the multi-memory driver module 102.

[0119] Step S2: The application sends a device memory allocation request;

[0120] Step S3: The application downloads the task executor;

[0121] Step S4: The application transmits the file identifier or the logical address of the data to be calculated;

[0122] Step S5: The multi-memory driver module determines the target computable storage device;

[0123] Step S6: The multi-memory driver module segments the first computation request;

[0124] Step S7: The multi-memory driver module sends the task execution program and device memory allocation request;

[0125] Specifically, the multi-memory driver module 102 sends task execution programs and device memory allocation requests to the target computing storage devices in parallel, so that each target computing storage device downloads the task execution program and allocates a portion of the functional data memory as the first memory.

[0126] Step S8: The multi-memory driver module sends a second computation request;

[0127] Specifically, the multi-memory driver module 102 sends corresponding second computation requests to several target computable storage devices in parallel, so that each target computable storage device reads segmented data from the device memory into the first memory, and performs data computation on the segmented data in the first memory based on the task execution program to obtain the computation result.

[0128] Step S9: The multi-memory driver module reads the calculation results;

[0129] Specifically, the multi-memory driver module 102 reads the calculation results from the first memory of the target computable storage device back to the virtual computing memory 121.

[0130] Step S10: The multi-memory driver module sends the calculation results to the application.

[0131] Specifically, if all segments of data corresponding to the data to be calculated have completed the data calculation, the multi-memory driver module 102 sends the calculation result to the application program 101; if at least one segment of data has not completed the data calculation, the multi-memory driver module 102 sends the reason for the failure to the application program 101.

[0132] In transparent mode, the multi-memory driver module 102 is used to: determine, based on the mapping management module, whether several data to be computed correspond to the same target computable storage device; and when several data to be computed correspond to the same target computable storage device, send the first computing request to the target computable storage device.

[0133] Specifically, in transparent mode, the operation of application 101 on multiple computeable storage devices is consistent with the operation on a single computeable storage device. There is no concept of segmentation in transparent mode; application 101 can use the / dev / mcsd device file as a regular computeable storage device. Application 101 issues a device memory allocation request, and the multi-memory driver module 102 obtains this request and allocates a portion of space in virtual compute memory 121 as secondary memory. The size of the secondary memory is the same as the total size of the functional data memory used to perform this data computation task in the device memory allocation request. The size of the secondary memory is not limited by the stripe depth; the upper limit of the secondary memory size is related to the remaining memory of the kernel where the multi-memory driver module 102 resides. The secondary memory is used to store the data to be computed read from the computeable storage devices.

[0134] Furthermore, application 101 downloads the task execution programs required for this data computation task, and global computation storage module 122 caches each task execution program downloaded by the application. Application 101 sends the logical address of the data to be computed to multi-memory driver module 102. Mapping management module 125 queries the address mapping relationship between each segment of data and the corresponding computable storage device based on the logical address of the data to be computed, and determines whether several data segments to be computed correspond to the same target computable storage device.

[0135] When several data sets to be computed correspond to the same target computeable storage device, the task distribution module 123 sends a task execution program and a device memory allocation request to the target computeable storage device, so that the target computeable storage device downloads the task execution program and allocates a portion of the functional data memory as the first memory; then the task distribution module 123 sends the first computing request to the target computeable storage device, so that the target computeable storage device reads the data to be computed from the device memory into the first memory, and performs data computing on the data to be computed in the first memory based on the task execution program within a predictable latency range.

[0136] In this embodiment, compared to existing solutions where multiple RAID levels disperse continuous data across different devices, rendering the logic of processing data on a single device inapplicable and preventing data from being centralized on a single device during computation, thus making existing RAID technology unsuitable for direct application to computeable storage devices, this application addresses this issue. By sending a first computation request to the target computeable storage device when several data points correspond to the same target computeable storage device while the multi-memory driver module is in transparent mode, this application enables data computation to be performed on the same target computeable storage device. Furthermore, by having multiple target computeable storage devices perform parallel computation while the multi-memory driver module is in parallel mode, this application can complete data computation even when continuous data is dispersed across different devices, thereby enabling the application of RAID technology to computeable storage devices.

[0137] The device driver module 103 is used to read data from the computeable storage device and to perform command slicing, flow control, task reconstruction, etc. The device driver module 103 includes an NVMe driver module.

[0138] In the embodiments of this application, the multi-memory driver module 102 and the device driver module 103 can actually be understood as the computable storage management middleware in the kernel of the host system 100, that is, the components between the application 101 and the computable storage device.

[0139] Traditional near-data processing tasks often use custom command formats, requiring the development of task-specific firmware in compute-enabled storage devices. This poses challenges to the unified management of compute-enabled storage devices and makes them difficult to scale. Therefore, the Non-Volatile Memory Express (NVMe) standard introduced a new set of command sets related to compute-enabled storage.

[0140] Please see Figure 7 , Figure 7 This is a schematic diagram of the architecture of an NVMe computing program command set provided in an embodiment of this application;

[0141] Figure 7 This is an example of all namespaces that exist within the same domain of an NVM subsystem. For example... Figure 7 As shown, an NVM subsystem includes different types of namespaces: compute namespace 1, subsystem local memory (SLM) namespace 11, first NVM namespace 1001, and second NVM namespace 1002.

[0142] The operation flow of a compute-enabled storage device in the NVMe standard includes: 1) Downloading the program: The host delivers a binary executable file or eBPF bytecode to the device, depending on the program type supported by the device. 2) Activating the program. 3) Requesting memory for computation. 4) Reading the data to be computed from non-volatile memory (NVM) into subsystem local memory (SLM), or writing it from the host to the SLM. 5) Executing the computation program. 6) The host reads the computation results back from the SLM.

[0143] It is understandable that NVMe is a specific standard protocol proposed for computeable storage devices, with one computeable storage device corresponding to one NVM subsystem. The NVMe compute program command set defines the standard procedures for related operations of computeable storage devices, such as program download and memory allocation, which define standard command formats. This lays the foundation for implementing computeable storage management middleware in the kernel of host system 100.

[0144] After standardization, computable storage management middleware can perform operations such as command redirection, I / O slicing, and command multi-processing, enabling transparent parallel computing, task reconstruction, and other functions. Standardization means that the operation of computable storage devices was previously highly customized, with different devices using different interfaces and computational processes. Now, under the NVMe standard, the relevant operational processes of computable storage devices have become standardized.

[0145] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of a device driver module provided in an embodiment of this application;

[0146] like Figure 8 As shown, the device driver module 103 includes a flow control module 131, a command slicing module 132, a coordination processing module 133, a task reconstruction module 134, and a simulation execution module 135.

[0147] The flow control module 131 is used to allocate different numbers of read / write requests per unit to different processes based on their priorities and latency guarantee levels. The application program can be a group of processes; the multi-memory driver module 102 in this application addresses multiple application scenarios and has multiple processes.

[0148] In this embodiment, the flow control module 134 allocates different IOPS resources according to the priority and latency protection level of the process. This application can avoid ordinary processes from interfering with the latency of latency-sensitive processes and limit the interference of high-load applications with latency-sensitive applications.

[0149] Command slicing module 132 is used to divide read requests from low-priority processes into several sub-requests and add these sub-requests sequentially to a request queue. The read requests include data being read from flash memory to functional data memory by the computeable storage device, and data being read from the functional data memory of the computeable storage device to virtual compute memory 121 by the host system 100.

[0150] A read request contains information such as computable storage device, read type, read length, and address. Therefore, the command slicing module 131 only needs to divide a read request into multiple read requests according to the length and add them to the request queue one by one. Combined with the management of modules such as the flow control module 134, this application can avoid directly issuing large blocks of IO resources.

[0151] Since large read operations are common in the operation of compute-enabled storage devices, large I / O operations have an advantage when competing for flash memory resources. This application uses the command slicing module 131 to divide large requests from low-priority CSD applications into multiple smaller requests, which can avoid interference from low-priority CSD applications to high-priority ordinary applications without significantly sacrificing read performance.

[0152] The coordination processing module 133 is used to set the garbage collection status of one computing storage device to a busy state and set the garbage collection status of other computing storage devices to an idle state at the same time. Specifically, each computing storage device includes a delayed garbage collection function. At the same time, the coordination processing module 133 sets the garbage collection status of only one computing storage device to a busy state and sets the other computing storage devices to perform delayed garbage collection. Thus, the other computing storage devices delay garbage collection based on the delayed garbage collection function. At this time, the garbage collection status of the other computing storage devices 1101 is an idle state.

[0153] Please see Figure 9 , Figure 9 This is a functional schematic diagram of a coordination processing module provided in an embodiment of this application;

[0154] like Figure 9 As shown, at any given time, only one compute storage device is in a busy garbage collection state, while the garbage collection states of the other compute storage devices are in an idle state.

[0155] Furthermore, the coordination processing module 133 will select the computing storage device to perform garbage collection operation at the next moment based on the remaining OP space in each computing storage device, thereby ensuring the latency of normal read and write I / O.

[0156] Specifically, when the host system 100 determines that the computeable storage device that needs to be read is in a busy state, the device driver module 103 submits a degraded read request to the multi-memory driver module 102. The degraded read request is used to instruct the data reconstruction module 126 to read the corresponding data from other computeable storage devices that are in an idle state to the host system 100.

[0157] Furthermore, the data reconstruction module 126 obtains the downgrade read request sent by the device driver module 103, and reads the corresponding segmented data and verification data from other idle computing storage devices according to the downgrade read request. Then, it performs verification calculation on the segmented data and verification data to obtain the target data, and sends the target data to the application 101. The target data is the segmented data stored in the computing storage device that is in a busy state.

[0158] Understandably, at this time, among the computable storage devices connected to the host system 100, only one computable storage device is in a busy state, while the other computable storage devices are in an idle state. Therefore, the downgrade read will not encounter latency fluctuations.

[0159] When updating segmented data stored in a computeable storage device based on RAID technology, the host system 100 performs a three-step write operation: reading the original segmented data from the computeable storage device, calculating the new checksum data, and writing the updated segmented data and the new checksum data into the corresponding computeable storage devices.

[0160] During the write process, the computeable storage device corresponding to the updated segmented data or the new checksum data may be busy. However, the updated segmented data and the new checksum data will definitely be distributed across two computeable storage devices, with at most one computeable storage device being busy. Therefore, once the host system 100 completes the data write on one of the computeable storage devices, it can mark the write operation as complete, and the write of the other data can wait in the background for completion.

[0161] Therefore, the coordination processing module 133 can ensure that there is no situation where two computable storage devices are busy at the same time. In this application, the above-mentioned write operation only needs to complete the writing of one computable storage device before marking the completion of the write operation.

[0162] The task reconstruction module 134 is used to: read the data to be computed from the corresponding target computing storage device and store the data to be computed in the second memory when the multi-memory driver module is in transparent mode, or when the number of computing requests received by a target computing storage device is greater than the preset task queue depth, which may cause the task to time out. The computing requests include a first request or a second request.

[0163] Specifically, in order to avoid interference between data computing tasks in the computable storage device and the unpredictable computing latency caused by waiting when competing for computing resources, this application sets up a task reconstruction module 134. The task reconstruction module 134 not only serves the transparent mode of the multi-memory driver module 102, but also ensures the latency of data computing tasks.

[0164] The following describes one application scenario of the task reconstruction module 134 in conjunction with the transparent mode of the multi-memory driver module 102:

[0165] In transparent mode, the multi-memory driver module 102 is also used to: allocate a portion of space in the virtual computing memory as a second memory based on the device memory allocation request; when several data to be computed correspond to different target computable storage devices, send a task reconstruction request to the device driver module so that the device driver module can read the corresponding data to be computed from different target computable storage devices based on the address mapping relationship between the virtual computing memory and the functional data memory of each computable storage device, and store the several data to be computed in the second memory.

[0166] Specifically, in transparent mode, if the mapping management module 125 determines that several data items to be computed correspond to different target computable storage devices, the mapping management module 125 sends a task reconstruction request to the task reconstruction module 134 by calling the function interface of the task reconstruction module 134. This task reconstruction request is used to instruct the task reconstruction module 134 to migrate the data computing task to the host system 100.

[0167] Specifically, after receiving the task reconstruction request, the task reconstruction module 134 reads the corresponding data to be calculated from different target computing storage devices based on the address mapping relationship between the virtual computing memory 121 and the functional data memory of each computing storage device, and stores several data to be calculated in the second memory so that the simulation execution module 135 can perform data calculation on the data to be calculated in the second memory.

[0168] In this embodiment, during initialization, the device driver module 103 performs a handshake with the computeable storage device. At this time, the device driver module 103 sets the task queue depth within the computeable storage device. The task queue depth is the number of data computation tasks that can wait. When the task queue depth is 1, it indicates that waiting for data computation tasks is not allowed.

[0169] When the number of computing requests received by a target computing storage device exceeds the preset task queue depth, it may cause a task timeout. That is, when the target computing storage device receives data computing tasks that exceed the task queue depth, the target computing storage device immediately returns a failure message to the host system 100. This failure message indicates that the target computing storage device has failed to execute the data computing task.

[0170] Upon receiving the failure information, and finding that the failure was due to insufficient computing resources, the device driver module 103 calls the task reconstruction module 134 to migrate the data computation task to be performed on the target computable storage device to the host system 100. The task reconstruction module 134 then reads the data to be computed from the target computable storage device and stores it in the second memory, enabling the simulation execution module 135 to perform data computation on the data in the second memory.

[0171] The simulation execution module 135 is used to: call the task execution program corresponding to the target computable storage device to perform data calculation on the data to be calculated in the second memory.

[0172] Specifically, the simulation execution module 135 simulates a computeable storage engine environment for the host system 100, that is, it simulates the computing functions of the computeable storage device using the computing power of the host system 100. For example, the simulation execution module 135 is an Extended Berkeley Packet Filter (EBPF) environment. The computeable storage engine environment simulated by the host system 100 is consistent with the computeable storage engine environment in the computeable storage device, thus allowing for seamless migration of data computing tasks.

[0173] After the task reconstruction module 134 stores the data to be calculated from the target computable storage device into the second memory, the simulation execution module 135 calls the task execution program corresponding to the target computable storage device to perform data calculation on the data to be calculated in the second memory, obtains the calculation result, and then returns the calculation result to the process that initiated the call.

[0174] It is understood that task reconstruction refers to the reconstruction of CSFs, and all CSFs that can run in the computeable storage device can run on the host system 100. Through the task reconstruction module 134 and the simulation execution module 135, this application can flexibly utilize the computing power of the host system 100 and quickly trigger the host system 100 to assist in ensuring the latency of data computing tasks when the load on the computeable storage device is high.

[0175] In this embodiment of the application, for the second computation request in the multi-memory driver module 102, when the target computable storage device to which the second computation request is sent is in an idle state, the target computable storage device reads the data to be computed into the input FDM, performs data computation, obtains the computation result, and then the multi-memory driver module 102 reads the computation result. The latency of the whole process is stable.

[0176] However, when the target computable storage device is busy when the second computing request is sent, the read operation will have unstable latency. Therefore, the task reconstruction module 134 stores the data to be computed from the target computable storage device to the second memory, and the simulation execution module 135 calls the task execution program corresponding to the target computable storage device to perform data computation on the data to be computed in the second memory. The obtained computation result can ensure the latency of the data computation task.

[0177] In this embodiment, compared to existing solutions where the computing power of computeable storage devices is limited, tasks may time out due to queuing under high load, making RAID technology unable to guarantee latency for data computation tasks on computeable storage devices. On one hand, by modifying the original NVMe driver module in the host and adding a command slicing module, coordination processing module, simulation execution module, flow control module, and task reconstruction module, this application can provide applications with predictable latency general I / O read / write operations and predictable latency computation operations. On the other hand, by distributing data through RAID technology and utilizing RAID's data reconstruction capabilities, this application can avoid latency fluctuations caused by busy computeable storage devices.

[0178] It is understandable that predictable latency refers to a low-latency concept, not to providing users with an interface to predict latency results. In a system with predictable latency, users should be provided with stable and reliable low-latency requests.

[0179] In this embodiment, a host system is provided that communicatively connects to at least two computeable storage devices. The host system includes an application program and a multi-memory driver module. The application program, connected to the multi-memory driver module, is used to issue task requests to the multi-memory driver module, wherein the task request includes a first computation request. The multi-memory driver module, connected to the application program, is used to: determine the target computeable storage device containing the data to be computed based on the task request and the address mapping relationship between each segment of data and the corresponding computeable storage device, wherein the data to be computed includes at least one segment of data; and send a task execution program and the first computation request to the target computeable storage device, so that the target computeable storage device performs data computation based on the task execution program.

[0180] By using the multi-memory driver module to determine the target computing storage device where the data to be computed is located based on the task request sent by the application and the address mapping relationship between each segment of data and the corresponding computing storage device, the host system in this application can determine the actual storage location of the data to be computed and send the corresponding computing request to the correct computing storage device, so that the computing storage device can perform data computation based on the task execution program, thereby realizing the application of RAID technology to computing storage devices.

[0181] Please see Figure 10 , Figure 10 This is a flowchart illustrating a data calculation method provided in an embodiment of this application;

[0182] This data calculation method is applied to a host system, which has at least two computeable storage devices connected via communication. The host system 100 includes an application program 101 and a multi-memory driver module 102. There are at least two computeable storage devices. Figure 1 Only one multi-memory driver module 102 is provided for reference.

[0183] like Figure 10 As shown, the data calculation method includes:

[0184] Step S1001: Determine the target computable storage device where the data to be computed is located;

[0185] Specifically, the application 101 sends the logical address of the data to be computed to the multi-memory driver module 102. The multi-memory driver module 102 queries the address mapping relationship between each segment of data and the corresponding computable storage device based on the logical address of the data to be computed, and determines the target computable storage device where the data to be computed is located.

[0186] Before determining the target computable storage device where the data to be computed is located, the method further includes: application 101 sending a device memory allocation request to multi-memory driver module 102, multi-memory driver module 102 obtaining the device memory allocation request; application 101 downloading the task execution program required for this data computation task, multi-memory driver module 102 caching each task execution program downloaded by application 101.

[0187] Step S1002: Send a task execution program and a computation request to the target computable storage device so that the target computable storage device performs data computation based on the task execution program.

[0188] Specifically, the computation request includes a first computation request and a second computation request. When the computation mode of the multi-memory driver module 102 is parallel mode, the multi-memory driver module 102 sends a task execution program and a second computation request to the target computable storage device. When the computation mode of the multi-memory driver module 102 is transparent mode, and several pieces of data to be computed correspond to the same target computable storage device, the multi-memory driver module 102 sends a task execution program and a first computation request to the target computable storage device.

[0189] Specifically, in parallel mode, the multi-memory driver module 102 segments the first computation request sent by the application 101 to obtain several second computation requests. Then, it sends corresponding task execution programs and device memory allocation requests to several target computable storage devices, so that each target computable storage device downloads the task execution program and allocates a portion of its functional data memory as first memory. Further, the multi-memory driver module 102 sends corresponding second computation requests in parallel to the several target computable storage devices, so that each target computable storage device reads segmented data from its device memory into its first memory, and performs data computation on the segmented data in the first memory based on the task execution program to obtain the computation result.

[0190] In transparent mode, the multi-memory driver module 102 determines whether several pieces of data to be computed correspond to the same target computeable storage device. If several pieces of data correspond to the same target computeable storage device, the multi-memory driver module 102 sends a task execution program and a device memory allocation request to the target computeable storage device, causing the target computeable storage device to download the task execution program and allocate a portion of its functional data memory as first memory. Then, the multi-memory driver module 102 sends a first computation request to the target computeable storage device, causing the target computeable storage device to read the data to be computed from its device memory into the first memory, and perform computation on the data within the first memory based on the task execution program, within a predictable latency range, to obtain the computation result.

[0191] Furthermore, the multi-memory driver module 102 reads the calculation results and sends them to the corresponding application program 101.

[0192] In this embodiment, the host system 100 further includes a device driver module 103. When several data to be computed correspond to different target computable storage devices, the multi-memory driver module 102 sends a task reconstruction request to the device driver module 103. Based on the task reconstruction request, the device driver module 103 reads the corresponding data to be computed from the different target computable storage devices, stores the data to be computed in the second memory, and then calls the task execution program corresponding to the target computable storage device to perform data computation on the data to be computed in the second memory to obtain the computation result.

[0193] Furthermore, the device driver module 103 sends the calculation results to the corresponding application 101.

[0194] In this embodiment of the application, a data calculation method is provided, which is applied to a host system. The host system is communicatively connected to at least two computable storage devices. The data calculation method includes: determining the target computable storage device where the data to be calculated is located; and sending a task execution program and a calculation request to the target computable storage device so that the target computable storage device performs data calculation based on the task execution program.

[0195] By determining the target computing storage device where the data to be computed is located, and sending the task execution program and computing request to the target computing storage device, this application can send the computing request to the correct computing storage device, so that the computing storage device can perform data computing based on the task execution program, thereby realizing the application of RAID technology to computing storage devices.

[0196] Please see Figure 11 , Figure 11 This is a schematic diagram of the structure of an independent computable memory redundancy system provided in an embodiment of this application;

[0197] like Figure 11 As shown, the independent computable memory redundancy system 110 includes a host system 100 and at least two computable memories 1101. The host system 100 is communicatively connected to the computable storage devices 1101. Figure 11 The example uses two computable memories 1101.

[0198] The host system 100 has communication connections to at least two computable memories 1101, which are used to determine the target computable storage device where the data to be computed is located, and send the task execution program and computation request to the target computable storage device.

[0199] Specifically, the host system 100 includes an application program 101 and a multi-memory driver module 102. The application program 101, connected to the multi-memory driver module 102, is used to send task requests to the multi-memory driver module 102. The multi-memory driver module 102, connected to the application program 101, is used to: determine the target computational storage device where the data to be computed is located based on the task request and the address mapping relationship between each segment of data and the corresponding computational storage device; and send a task execution program and a first computation request to the target computational storage device, so that the target computational storage device can complete the data computation within a predictable latency range based on the task execution program.

[0200] Computable storage device 1101 is communicatively connected to host system 100 and is used to perform data computation based on computation requests sent by host system 100. Each computable storage device 1101 can serve as a target computable storage device, and each computable storage device 1101 includes a computable storage engine environment and delayed garbage collection functionality. The computable storage engine environment in the target computable storage device runs a task execution program to perform data computation.

[0201] At any given time, only one computeable storage device 1101 is in a busy garbage collection state. Other computeable storage devices 1101 perform garbage collection with a delay based on the delayed garbage collection function. At this time, the garbage collection state of the other computeable storage devices 1101 is an idle state.

[0202] Please see Figure 12 , Figure 12 This is a detailed structural diagram of an independent computable memory redundancy system provided in an embodiment of this application;

[0203] like Figure 12 As shown, the independent computable memory redundancy system 110 includes a host system 100 and at least two computable storage devices 1101. Figure 12 (Taking two computable storage devices 1101 as an example). The host system 100 is communicatively connected to each computable storage device 1101. Each computable storage device 1101 includes a computable storage engine environment and delayed garbage collection functionality.

[0204] The host system 100 includes an application 101 and a kernel 11. The kernel 11 includes a virtual file system 111, a general block layer 112, and a driver layer 113.

[0205] Application 101 includes at least one of the following: a normal process, a latency-sensitive process, a CSD application process, and a CSD latency-sensitive process. A normal process refers to a general user process without special requirements or restrictions; a latency-sensitive process refers to a process with high real-time requirements, needing to complete tasks within specific time constraints; a CSD application process refers to a program that calls the computing interface of the CSD device and uses near-data processing technology; and a CSD latency-sensitive process refers to a CSD application process with high real-time requirements.

[0206] The Virtual File Systems (VFS) 111 and the General Block Layer 112 are the software stack in the kernel. Task requests sent from application 101 to driver layer 113 must pass through the Virtual File Systems 111 and the General Block Layer 112.

[0207] The driver layer 113 includes a multi-memory driver module 102 and a device driver module 103. The multi-memory driver module 102 includes a virtual computing memory 121, a global computing storage module 122, a task distribution module 123, a device management module 124, a mapping management module 125, and a data reconstruction module 126. The device driver module 103 includes a flow control module 131, a command slicing module 132, a coordination processing module 133, a task reconstruction module 134, and a simulation execution module 135.

[0208] In this embodiment, an independent computational memory redundancy system is provided. This system includes a host system and at least two computational storage devices communicatively connected to the host system, used to perform data computation based on computation requests sent by the host system. The independent computational memory redundancy system in this application enables the introduction of predictable latency characteristics into the computational storage devices, providing the host system with transparent computational storage parallel computing capabilities.

[0209] This application also provides a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors. For example, the one or more processors can execute the data calculation method in any of the above method embodiments, such as executing the data calculation method in any of the above method embodiments, or executing the steps described above.

[0210] This application also provides a computer program product comprising one or more lines of program code stored in a non-volatile computer-readable storage medium. A processor of a flash memory device reads the program code from the non-volatile computer-readable storage medium and executes the program code to complete the method steps of the data calculation method provided in the above embodiments.

[0211] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware, or by a program or program code related to hardware. The program can be stored in a non-volatile computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0212] The apparatus or device embodiments described above are merely illustrative. The unit modules described as separate components may or may not be physically separate, and the components shown as module units may or may not be physical units; that is, they may be located in one place or distributed across multiple network module units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0213] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions for a computer device (which may be a personal computer, server, or network device, etc.) to execute the various embodiments or some parts of the embodiments.

[0214] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above. For the sake of brevity, they are not provided in detail; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A host system, characterized in that, The host system is communicatively connected to at least two computeable storage devices. The host system includes an application program and a multi-memory driver module. The application connects to the multi-memory driver module and is used to send task requests to the multi-memory driver module, wherein the task request includes a first computation request; The multi-memory driver module, connected to the application program, is used for: Based on the task request, the address mapping relationship between each data segment and the corresponding computable storage device is used to determine the target computable storage device where the data to be computed is located, wherein the data to be computed includes at least one data segment. A task execution program and a first computation request are sent to the target computable storage device so that the target computable storage device performs data computation based on the task execution program; The multi-memory driver module includes a mapping management module; The task request also includes a device memory allocation request, which includes a first memory size of a computable storage device. Wherein, the first memory is the functional data memory in the computable storage device used for data calculation, and the first memory is less than or equal to the preset stripe depth; The multi-memory driver module is specifically used for: Obtain a device memory allocation request sent by the application to a device file, wherein the device file is a file registered by the multi-memory driver module; Based on the global computing storage module, each task execution program downloaded by the application is cached; Get the logical address of the data to be computed sent by the application; Based on the mapping management module, the address mapping relationship between each segment of data and the corresponding computable storage device is queried to determine the target computable storage device corresponding to the logical address of the data to be computed. The multi-memory driver module is also used for: Depending on the computing mode, at least one of the computable storage devices can be controlled to perform parallel computing, or the host system can be controlled to simulate the computable storage device to perform data computing.

2. The system according to claim 1, characterized in that, Before the application sends a task request to the multi-memory driver module, the host system is also configured to: Several segment data corresponding to a stripe of data and the corresponding verification data are stored in different computeable storage devices, wherein each verification data and each segment data corresponds one-to-one with a computeable storage device, and the size of the stripe block in each computeable storage device is greater than or equal to the preset stripe depth.

3. The system according to claim 1, characterized in that, The multi-memory driver module also includes a global computing storage module; The global computing storage module is used to cache the task execution programs downloaded by the application, establish a mapping relationship between the global identifier of each task execution program and the program identifier in the corresponding target computing storage device, and send the corresponding task execution program to the target computing storage device. Each task executor has a unique global identifier, and each task executor also has a unique program identifier in the corresponding target computable storage device.

4. The system according to claim 3, characterized in that, The multi-memory driver module also includes a task distribution module; The mapping management module is used to establish the address mapping relationship between each segment of data and the corresponding computable storage device, and to determine the target computable storage device corresponding to each piece of data to be computed; The task distribution module is used to send the corresponding task execution program and calculation request to the target computable storage device, wherein the calculation request includes a first calculation request or a second calculation request.

5. The system according to claim 4, characterized in that, The computation mode includes a parallel mode; In parallel mode, the task distribution module is used for: After determining the target computable storage device corresponding to the data to be computed, the first computing request sent by the application is segmented to obtain several second computing requests, wherein each target computable storage device corresponds to one second computing request. The corresponding task execution program and device memory allocation request are sent in parallel to several target computable storage devices, so that each target computable storage device downloads the task execution program and allocates a portion of space in the functional data memory as the first memory. The corresponding second computation request is sent in parallel to several target computable storage devices, so that each target computable storage device reads segmented data from device memory into first memory, and performs data computation on the segmented data in first memory based on the task execution program.

6. The system according to claim 1, characterized in that, The computing mode includes a transparent mode; In transparent mode, the multi-memory driver module is used for: Based on the mapping management module, it is determined whether several data to be computed correspond to the same target computable storage device; When several data to be computed correspond to the same target computable storage device, the first computing request is sent to that target computable storage device.

7. The system according to claim 6, characterized in that, The multi-memory driver module also includes virtual computing memory, which has an address mapping relationship with the functional data memory of each computable storage device. The host system also includes a device driver module, which is used to read data from a computable storage device; In transparent mode, the multi-memory driver module is also used for: Based on the device memory allocation request, a portion of the space in the virtual computing memory is allocated as a second memory. When several data to be computed correspond to different target computeable storage devices, a task reconstruction request is sent to the device driver module so that the device driver module can read the corresponding data to be computed from different target computeable storage devices based on the address mapping relationship between the virtual computing memory and the functional data memory of each computeable storage device, and store the data to be computed in the second memory.

8. The system according to claim 7, characterized in that, The device driver module includes a task reconstruction module and a simulation execution module, wherein... The task reconstruction module is used for: When the multi-memory driver module is in transparent mode, or when the number of computing requests received by a certain target computing storage device is greater than the preset task queue depth, the data to be computed is read from the corresponding target computing storage device and the data to be computed is stored in the second memory; The simulation execution module is used for: The task execution program corresponding to the target computable storage device is invoked to perform data calculations on the data to be calculated in the second memory.

9. The system according to claim 1, characterized in that, The host system also includes a device driver module, which includes a coordination processing module. The coordination processing module is used to set the garbage collection status of one computing storage device to a busy state and set the garbage collection status of other computing storage devices to an idle state at the same time. The multi-memory driver module further includes a data reconstruction module, which is used for: When the data to be read is located on a busy computeable storage device, obtain the degraded read request sent by the device driver module; Based on the downgrade read request, the corresponding segmented data and verification data are read from other idle computing storage devices; The segmented data and the verification data are verified to obtain the target data.

10. The system according to claim 1, characterized in that, The host system also includes a device driver module, which includes a flow control module and a command slicing module. The flow control module is used to allocate different unit read / write request quantities to different processes based on their priorities and latency guarantee levels. The command slicing module is used to divide the read requests of low-priority processes into several sub-requests and add the sub-requests to the request queue in sequence.

11. A data calculation method, characterized in that, Applied to a host system according to any one of claims 1-10, the host system communicatively connecting to at least two computeable storage devices, the method comprises: Determine the target computable storage device where the data to be computed is located; A task execution program and a computation request are sent to the target computable storage device so that the target computable storage device performs data computation based on the task execution program.

12. A redundant system of independently computable memory, characterized in that, include The host system as described in any one of claims 1-10; At least two computable storage devices are communicatively connected to the host system for performing data computations based on computation requests sent by the host system.

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