Electronic device, distributed system, and task scheduling method

Abstract

The application provides an electronic device, a distributed system and a task scheduling method. The electronic device comprises: a scheduler, which assigns a first task in a plurality of tasks to a first operator in an execution unit array based on a dependency relationship between the plurality of tasks recorded in a computation graph, and sends first indication information indicating completion of execution of the first task to a second electronic device after completion of execution of the first task, wherein the dependency relationship is used to indicate a sequential execution relationship between the plurality of tasks and an input / output relationship of data variables between the plurality of tasks; a storage unit, which is used to store the computation graph and executable programs of the plurality of tasks, wherein the computation graph and the executable programs of the plurality of tasks are located in different storage spaces; and an execution unit array, which comprises a plurality of operators, and a first operator in the plurality of operators is used to execute the first task. The electronic device can improve the task processing speed and the task processing performance of the distributed computing system.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an electronic device, a distributed system, and a task scheduling method. Background Technology

[0002] With the development of science and technology, computer technology has made rapid progress, and artificial intelligence (AI) has become a mainstream research direction. The computing power required for new applications and algorithms represented by AI is growing exponentially. However, the obstacles to the evolution of semiconductor manufacturing processes are increasing, and the growth rate of transistor density on chips is slowing down. Single chips or integrated chips can hardly support the computing power of AI applications. Exploring parallel opportunities in application algorithms and adopting distributed computing has become a research direction for AI algorithms.

[0003] Traditional distributed computing typically employs a process-thread model, such as the MPI+OpenMP solution used in high-performance computing. This solution uses MPI, based on a process model, to handle task deployment and scheduling across distributed storage, while OpenMP, based on a thread model, handles task deployment and scheduling within shared storage. However, traditional process-thread models often require excessive manual intervention, such as handling data partitioning and load balancing, and customized tuning across distributed clusters with different hardware architectures. Furthermore, traditional process-thread models can only represent a large amount of parallel granularity, and their fixed scheduling strategies lead to low computational utilization for applications with significant runtime dynamics (such as sparse matrix computation, finite element analysis, and molecular dynamics simulations). Therefore, the industry has further proposed distributed computing implementation schemes based on computation graphs, which typically represent the input-output relationships between various task objects. For example, Charm++, developed by the University of Illinois at Urbana-Champaign, is an object-oriented parallel programming framework based on asynchronous message passing. However, in Charm++-based distributed computing, the computation graph representation treats programs and data as a single object for management. This semantic limitation restricts data management efficiency, as the scheduling process cannot process data independently. This results in low storage space utilization for AI applications (involving large data transfers and on-chip memory reuse). Furthermore, these computation graph-based distributed computing implementations are all purely software-based, leading to high costs associated with frequent switching between scheduler threads and computation tasks. This results in issues such as scheduling threads consuming significant computing power and poor task scheduling concurrency. Therefore, when distributed computing systems are applied to the AI ​​field, improving their task processing speed and performance becomes a crucial problem to solve. Summary of the Invention

[0004] The electronic device, distributed system, and task scheduling method provided in this application can improve the task processing speed and performance of distributed computing systems. To achieve the above objectives, this application adopts the following technical solution.

[0005] In a first aspect, embodiments of this application provide an electronic device, which is a first electronic device comprising a scheduler, an execution unit array, and a storage unit. The scheduler, based on dependencies between multiple tasks recorded in a computation graph, assigns a first task among the multiple tasks to a first arithmetic unit in the execution unit array for execution. After the first task is completed, the scheduler sends a first indication message indicating the completion of the first task to a second electronic device. The dependencies are used to indicate the sequential execution relationship between the multiple tasks and the input / output relationship of data variables between the multiple tasks. The storage unit stores the computation graph and executable programs of the multiple tasks, wherein the computation graph and the executable programs of the multiple tasks are located in different storage spaces. The execution unit array includes multiple arithmetic units, and the first arithmetic unit among the multiple arithmetic units is used to execute the first task.

[0006] In this embodiment, the computation graph records the sequential execution relationship between tasks based solely on the input / output relationship of data variables. The computation graph does not store the program executing the tasks; instead, it stores the program in other memory or storage space. Therefore, compared to existing computation graphs that manage functions and data together as task objects, the electronic device provided in this embodiment simplifies the design and generation of the computation graph. This facilitates the realization that each node can store a copy of the computation graph, achieving global consistency of the computation graph in a distributed system. Consequently, the electronic device provided in this embodiment can be applied to distributed systems with larger cluster scales. Furthermore, in existing technologies, task scheduling, message passing between nodes, and task execution are all handled by the processor through software program calls. This leads to frequent switching between the task scheduling thread and computation tasks, increasing processor overhead and resulting in poor task scheduling concurrency. In contrast, in this embodiment, the scheduler for managing the computation graph and performing task scheduling, the processor for executing tasks, and the input / output unit for communicating with other electronic devices are located in different hardware structures. Compared to existing technologies, this reduces the computational overhead of computation graph scheduling and improves task scheduling concurrency. In summary, the electronic device provided in this application embodiment can improve task scheduling and task processing performance.

[0007] In one possible implementation, the scheduler is further configured to: when the first task generates a second task during execution, add the second task to the computation graph based on the dependency relationship between the second task and the tasks in the computation graph; and send the updated computation graph to the second electronic device.

[0008] In one possible implementation, the scheduler is further configured to: periodically receive indication information from the second electronic device indicating the resource utilization rate of the arithmetic unit in the second electronic device; when it is found that the resource utilization rate of the arithmetic unit in the second electronic device is lower than a preset threshold, send second indication information to the second electronic device, the second indication information being used to instruct the second electronic device to process the second task.

[0009] In one possible implementation, the scheduler is further configured to: send the first data variable to the second electronic device when the first data variable output by the first task is an input data variable of the second task executed in the second electronic device.

[0010] In one possible implementation, the scheduler is further configured to: when the second data variable input by the first task is a data variable output by the third task executed in the second electronic device, after the first task is completed, send third indication information to the second electronic device, the third indication information being used to indicate the release of the second data variable.

[0011] In one possible implementation, the computation graph also records indication information indicating whether a data variable is an input data variable or an output data variable; the scheduler is further configured to: when the first data variable is an input data variable of the fourth task, modify the indication information indicating that the first data variable is an output data variable to an indication information indicating that the first data variable is an input data variable, wherein the fourth task is assigned by the scheduler to the second arithmetic unit among the plurality of arithmetic units for execution.

[0012] In one possible implementation, the computation graph also records the number of times a data variable is referenced, the reference indicating that the data variable is at least one of an input data variable and an output data variable; the scheduler is further configured to: decrement the number of times the second data variable is referenced by one when the second data variable is an output data variable of the fifth task, wherein the fifth task is assigned by the scheduler to the third of the plurality of arithmetic units for execution.

[0013] In one possible implementation, the electronic device further includes an input / output unit, which includes a notification cache input, a notification cache output, a network interface controller, and a tag matching engine. The notification cache output is used to cache indication information to be sent by the scheduler to the second device. The notification cache input is used to cache information received from the second electronic device. The network interface controller is used to send the indication information cached in the notification cache output to the second device and to cache the information received from the second electronic device into the notification cache input. The tag matching engine is used to read the information in the notification cache input and update the computation graph based on the information in the notification cache input.

[0014] In one possible implementation, the information in the notification cache input includes at least one of the following: a fourth instruction indicating the completion of processing of the sixth task, a fifth instruction indicating the first electronic device to perform the seventh task, and a sixth instruction indicating the release of a third data variable in the first electronic device.

[0015] In one possible implementation, the tag matching engine is specifically used to: based on the fourth indication information, remove the dependency relationship between the sixth task recorded in the computation graph and other tasks; based on the fifth indication information, add the seventh task to the computation graph; and based on the sixth indication information, decrement the number of times the third data variable recorded in the computation graph is referenced by one.

[0016] In one possible implementation, the storage unit includes a plurality of memories, a first memory of which is used to store the computation graph; a second memory of which is used to store executable programs for the plurality of tasks; and a third memory of which is used to store data.

[0017] Secondly, embodiments of this application provide a distributed system comprising multiple nodes, each of which stores a computation graph, the computation graph recording dependencies between multiple tasks, the dependencies indicating the sequential execution relationship between the multiple tasks and the input-output relationship of data variables between the multiple tasks, the tasks in the computation graph being executed by at least some of the multiple nodes; wherein each of the multiple nodes is the electronic device described in the first aspect.

[0018] Thirdly, embodiments of this application provide a task scheduling method, which includes: assigning a first task among the multiple tasks to a first arithmetic unit for execution based on the dependency relationship between multiple tasks recorded in a computation graph; and sending first indication information indicating the completion of the first task to a second node after the first task is executed, wherein the dependency relationship is used to indicate the sequential execution relationship between multiple tasks and the input-output relationship of data variables between multiple tasks.

[0019] In one possible implementation, after the first task is completed, the method further includes: when the first task generates a second task during execution, adding the second task to the computation graph based on the dependency relationship between the second task and the tasks in the computation graph; and sending the updated computation graph to the second node.

[0020] In one possible implementation, the task scheduling method further includes: periodically receiving indication information from the second node indicating the resource utilization rate of the arithmetic unit in the second node; when it is found that the resource utilization rate of the arithmetic unit in the second node is lower than a preset threshold, sending second indication information to the second node, the second indication information being used to instruct the second node to process the second task.

[0021] In one possible implementation, the task scheduling method further includes: when the first data variable output by the first task is the input data variable of the second task executed in the second node, sending the first data variable to the second node.

[0022] In one possible implementation, the task scheduling method is further configured to: when the second data variable input by the first task is the data variable output by the third task executed in the second node, after the first task is completed, send third indication information to the second node, the third indication information being used to indicate the release of the second data variable.

[0023] In one possible implementation, the computation graph also records indication information indicating whether the data variable is an input data variable or an output data variable; the task scheduling method further includes: when the first data variable is an input data variable of the fourth task, modifying the indication information indicating that the first data variable is an output data variable to an indication information indicating that the first data variable is an input data variable, wherein the fourth task is assigned by the scheduler to the second arithmetic unit among the plurality of arithmetic units for execution.

[0024] In one possible implementation, the computation graph also records the number of times a data variable is referenced, the reference indicating that the data variable is at least one of an input data variable and an output data variable; the task scheduling method further includes: when the second data variable is the output data variable of the fifth task, decrementing the number of times the second data variable is referenced by one, wherein the fifth task is assigned by the scheduler to the third arithmetic unit among the plurality of arithmetic units for execution.

[0025] Fourthly, embodiments of this application provide an apparatus comprising a memory and a controller, the memory being used to store a computer program, and the controller being configured to invoke all or part of the computer program stored in the memory to execute the method described in the second aspect above.

[0026] Fifthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a controller, is used to implement the method described in the second aspect.

[0027] In a sixth aspect, embodiments of this application provide a computer program product that, when executed by a controller, is used to implement the method described in the second aspect above.

[0028] It should be understood that the second to sixth aspects of this application are consistent with the technical solutions of the first aspect of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation are similar, so they will not be described again. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figures 1A-1B This is a schematic diagram of the structure of a distributed system in the prior art provided in the embodiments of this application;

[0031] Figure 2 This is a schematic diagram of the architecture of the distributed system 100 provided in an embodiment of this application;

[0032] Figure 3A The embodiments provided in this application are as follows Figure 2 The diagram shows the hardware structure of each node in the distributed system 100.

[0033] Figure 3B The embodiments provided in this application are as follows Figure 3AThe diagram shows the interactions between the components within a node and with other nodes.

[0034] Figure 4 This is a schematic diagram of the computation graph provided in an embodiment of this application;

[0035] Figure 5 This is yet another structural schematic diagram of the computation graph provided in the embodiments of this application;

[0036] Figure 6 The embodiments provided in this application are as follows Figure 3A The diagram shows a flowchart of task scheduling performed by the scheduler.

[0037] Figure 7A The embodiments provided in this application are as follows Figure 4 The diagram shown illustrates a scenario where tasks are executed at various nodes within the computation graph.

[0038] Figure 7B The embodiments provided in this application are as follows Figure 5 The diagram shown illustrates a scenario where tasks are executed at various nodes within the computation graph.

[0039] Figure 8 The embodiments provided in this application are as follows Figures 7A-7B The diagram shows the interaction flow between the nodes in the scenario shown.

[0040] Figure 9 This is a flowchart of a task scheduling method provided in an embodiment of this application;

[0041] Figure 10 This is a flowchart of an apparatus provided in an embodiment of this application. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0043] The terms "first," "second," and similar terms used in this article do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "one" or similar terms do not indicate a quantity limitation, but rather indicate the existence of at least one.

[0044] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner. In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0045] In existing distributed computing technologies, computation graph-based distributed computing implementations have become the mainstream approach, such as... Figure 1A As shown, Figure 1A The distributed computing system implementation shown is Charm++, developed by the University of Illinois at Urbana-Champaign. Charm++ is an object-oriented parallel programming framework based on asynchronous message passing. Figure 1B This refers to the computational graph formed within this programming framework. For example... Figure 1A In the distributed computing system shown, programmers can create a series of asynchronous, concurrently executing task objects in Charm++. These task objects contain data and functions, and different task objects can cooperate to complete tasks through a message-passing mechanism. The message-passing relationships between task objects form a computation graph, such as... Figure 1B As shown. Figure 1B The diagram schematically illustrates objects C[0], C[1], C[2], C[3], C[4], C[5], and D, as well as the input-output relationships between these task objects, which can also be called dependencies. For example, the output of object C[2] is the input of both object C[0] and object C[1]. Furthermore, Charm++ includes a runtime software, Charm++RT, which runs on multiple distributed processors. Figure 1A The diagram shows processor 0, processor 1, and processor N-1. Based on the aforementioned computation graph composed of task objects, the runtime software Charm++RT can schedule concurrent task objects in the computation graph to run on various processors. Figure 1A In the processor, processor 0 is used to process objects D, C[0], A, and C[3]; processor 1 is used to process objects B, C[1], and C[4]; and processor N-1 is used to process objects C[2] and C[5]. Furthermore, Charm++RT maintains a message queue on each processor to manage message passing between processors. The scheduler software within Charm++RT can monitor the execution status of each concurrent object online and dynamically migrate objects between processors to achieve task load balancing.

[0046] In summary, it can be seen that the distributed computing systems shown in the prior art combine functions and data in the computation graph representation, managing them as task objects. The semantics of the computation graph limit the efficiency of data management, and the scheduling process cannot process data independently. Therefore, the storage space utilization is low for AI applications (involving large-scale data movement and on-chip storage reuse). Furthermore, the runtime software Charm++RT is a pure software implementation, meaning the scheduler is also a pure software implementation. Frequent switching between scheduler threads and computation tasks is costly, and managing message queues consumes CPU computing power, leading to poor task scheduling concurrency. The distributed computing system provided in this application embodiment records the sequential execution relationships between tasks based solely on data input / output relationships in the computation graph. The computation graph does not store the programs that execute tasks; instead, these programs are stored in other memory or storage spaces. Therefore, compared to existing technologies where computation graphs manage functions and data together as task objects, the electronic device, distributed system, and task scheduling method provided in this application embodiment simplify the design and generation of the computation graph. This facilitates the realization that each node can maintain a copy of the computation graph, achieving global consistency of the computation graph in the distributed system. Consequently, the distributed system provided in this application embodiment can cover a larger cluster scale. Furthermore, in existing technologies, task scheduling, inter-node message passing, and task execution are all handled by the processor through software program calls. This leads to frequent switching between task scheduling threads and computation tasks, increasing processor overhead and resulting in poor task scheduling concurrency. In contrast, in this application embodiment, the scheduler for managing the computation graph and performing task scheduling, the processor for executing tasks, and the input / output units for communicating with other nodes are located in different hardware structures in each node. Compared to existing technologies, this reduces the computational overhead of computation graph scheduling and improves task scheduling concurrency. In summary, the electronic device, distributed system, and task scheduling method provided in the embodiments of this application can improve task scheduling and task processing performance.

[0047] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the architecture of the distributed system 100 provided in an embodiment of this application. For example... Figure 2 As shown, the distributed system 100 may include multiple layers. Figure 2 The diagram schematically illustrates a distributed system 100 comprising four levels: LV0, LV1, LV2, and LV3. LV0 can be the lowest level, and LV3 can be the highest level. Figure 2As can be seen, one node at a higher level is connected to multiple nodes at a lower level to manage those nodes. This management may include, but is not limited to, recording the interconnection relationships between nodes at the lower level, recording the communication between nodes at the lower level, and assigning tasks to nodes at the lower level. For example, Figure 2 The diagram schematically shows that level LV3 includes node C1, level LV2 includes nodes R1 and R2, level LV1 includes nodes N1 to N4, and level LV0 includes nodes A1 to A8. Node C1 is connected to nodes R1 and R2, node R1 is connected to nodes N1 and N2, node R2 is connected to nodes N3 and N4, node N1 is connected to nodes A1 and A2, node N2 is connected to nodes A3 and A4, node N3 is connected to nodes A5 and A6, and node N4 is connected to nodes A7 and A8.

[0048] like Figure 2 The distributed system 100 shown can be applied to various scenarios. For example, the distributed system 100 can be applied to large-scale cluster architectures (such as cloud servers). In this scenario, each node at level LV3 is interconnected via routing chips or network interfaces to form a computer cabinet, which is controlled by a node at level LV2. Each node at level LV2 is interconnected via routing chips or network interfaces to form a backbone network constituting a computing cluster, which is controlled by a node at level LV1. Nodes at level LV1 are interconnected via routing chips, network interfaces, or communication protocols to form a higher-level computing cluster, which is controlled by a central control node at level LV0. It should be noted that... Figure 2 The number of levels and the number of nodes included in each level shown are exemplary and not intended to limit the solution. In other scenarios or examples, more or fewer levels may be included, and the number of nodes included in each level may also be more or fewer. For example, distributed system 100 can also be applied to artificial intelligence scenarios such as autonomous vehicles. In this scenario, distributed system 100 may only include node N1 in level LV1 and nodes A1 and A2 in level LV0.

[0049] like Figure 2 In the distributed system 100 shown, the hardware structure of each node can be as follows: Figure 3A As shown. Figure 3A This is a schematic diagram of the hardware structure of a node provided in an embodiment of this application. The node can be a node at any level of the distributed system 100, for example... Figure 2 The nodes shown are C1, R1, N1, or A1. Figure 3AThe hardware structure of the nodes shown can also be referred to as electronic devices. In practical applications, each node of the distributed system 100 can be any type of device or apparatus, such as a chip, chipset, or circuit board with a chip or chipset mounted on it; this embodiment is not limited to this. The chip, chipset, or circuit board with a chip or chipset mounted on it can operate under suitable software drivers. The node includes a scheduler 101, an execution element array 102 (Processing Element Array, PE array), a storage unit 103, and an input / output unit 104.

[0050] The scheduler 101 can be a dedicated processor for task scheduling. As long as the scheduler 101 can manage the computation graph, issue tasks to the execution unit array 102 based on the computation graph, and transmit (or receive) data or computation graphs to other nodes through the input / output unit 104, its implementation form is not limited in this embodiment. For example, the scheduler 101 can be software-driven or hardware-implemented using discrete devices. In its specific operation, the scheduler 101 can obtain the computation graph from other nodes or a compiler independent of the distributed system 100, or it can generate the computation graph itself. This computation graph is used to indicate the dependencies between tasks and the input / output relationships between data. A detailed description of the computation graph is provided below. Figure 4 , Figure 5 The relevant description is provided. Furthermore, the scheduler 101 is also used to, based on the computation graph, assign the current task to the arithmetic unit in the execution unit array 102 for execution after all previous tasks on which certain tasks depend have been completed. Further, the scheduler 101 can also add new tasks generated by the current node to the computation graph based on the data input / output relationship between the new task and previous tasks, and broadcast the computation graph to other nodes.

[0051] The execution unit array 102 contains multiple arithmetic units for performing tasks. Figure 2The diagram schematically illustrates an execution unit array 102 including arithmetic logic units (ALUs) 1021, 1022, and 1023. It is understood that the execution unit array 102 may include more or fewer ALUs, depending on the application scenario. The execution unit array 102 and the scheduler 101 may be integrated within one or more chips, which can be considered a chipset. Optionally, the scheduler 101 and the execution unit array 102 may be integrated into the same chip. ALUs 1021, 1022, and 1023 may include components such as logic computing units for loading programs and executing instructions. ALUs 1021, 1022, and 1023 may include, for example, various arithmetic units, central processing units (CPUs), or dedicated processors, such as artificial intelligence processors, neural network processors, digital signal processors, or image processing processors. The ALUs execute tasks assigned by the scheduler 101 by running or executing software programs stored in the storage unit 103 and by calling instruction programs stored in the storage unit 103.

[0052] Storage unit 103 may include one or more memories, which may be implemented by any type of volatile or non-volatile memory or a combination thereof, such as one or more of static random access memory (SRAM), dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR), erasable programmable read-only memory (EPROM), and read-only memory (ROM). In one possible implementation, storage unit 103 includes a memory that can be divided into multiple storage spaces. A portion of the storage space is used to store instruction programs corresponding to each task, which are invoked by the arithmetic logic unit (ALU) in execution unit array 102 to execute tasks assigned by scheduler 101. Another portion of the storage space is used to store a computation graph. Yet another portion of the storage space is used to store data that needs to be output to or input from other nodes. In another possible implementation, storage unit 103 includes multiple memories, which may be program memory, computation graph memory, and input / output data memory. The program memory stores the instruction programs corresponding to each task, the computation graph memory stores the computation graph, and the input / output data memory stores data that needs to be output to other nodes or input from other nodes. In this embodiment, the storage unit 103 can be selectively integrated into the same chip as the scheduler 101 and multiple arithmetic units, or it can be located outside the chip. Optionally, when the storage unit 103 includes multiple memories, these memories can be integrated into the same memory chip or located in separate chips.

[0053] The input / output unit 104 is used to enable communication between nodes, to obtain data or computational graphs from other nodes, or to output data or computational graphs to other nodes. Nodes can communicate wirelessly or via electronic circuitry. This wireless communication can include, but is not limited to, Bluetooth, Wi-Fi, or cellular networks. When nodes communicate wirelessly, the input / output unit 104 can be configured with radio frequency hardware modules based on standard wireless communication protocols, which will not be elaborated further. When nodes communicate via electronic circuitry, the input / output unit 104 includes a network interface controller (NIC) 1041 and a notification buffer for caching external information. Figure 3A As can be seen, two lines, one input and one output, are set between NIC1041 and scheduler 101. The output line includes a notification buffer out (1042), and the input line includes a notification buffer in (1043) and a tag-matching engine (1044). The network interface controller, notification buffer, and tag-matching engine cooperate to enable information exchange between nodes. Figure 3A The diagram illustrates a scenario where nodes communicate via electronic circuitry.

[0054] based on Figure 3A The hardware structure diagram shown below illustrates information from node A1 to node A2 as an example. Figure 3A The interaction flow between the various hardware components, and between node A1 and node A2, is shown below. Figure 3B As shown. The interaction flow 300 includes the following steps:

[0055] Step 301: The scheduler 101 in node A1 stores the computation graph and the executable programs of the tasks in the computation graph into the storage unit 103. Step 302: Based on the dependencies between the tasks recorded in the computation graph, the scheduler 101 in node A1 assigns task F to the arithmetic unit 1021 for execution.

[0056] Step 303: The arithmetic unit 1021 in node A1 executes task F.

[0057] Step 304: After task F is completed, scheduler 101 in node A1 transmits the indication information indicating that task F has been completed to node A2.

[0058] Please continue to refer to this. Figure 4 , Figure 4 An example of a computational graph provided for an embodiment of this application. For example... Figure 4As shown, the computation graph includes multiple nodes and directed lines connecting them. It should be noted that each node in the computation graph represents a task, and the meaning of this node differs from... Figure 2 The diagram illustrates the meaning of each node in the distributed system 100. The directed line segments connecting the nodes in the computation graph represent the order of task execution and the input / output relationships between the data used by each task. Specifically... Figure 4 The diagram illustrates tasks A, B, C, and D. Task A is connected to tasks B, C, and D by directed line segments, with the arrows of these lines pointing to tasks B, C, and D, respectively. This means that tasks B, C, and D must be executed after task A has finished, and the data generated by task A is the input data required by tasks B, C, and D. Similarly, Figure 4 Task B is connected to Task C by directed line segments, with the arrows of these segments pointing towards Task C; that is, the data generated by Task B is the data that Task C needs to input. Furthermore, Figure 4 The computation graph shown also records task information for each task. This information includes the number of previous tasks that the current task depends on, and the identifiers of the tasks that depend on the current task. Here, dependency refers to the order in which tasks are executed and the input / output relationships between the data used by each task. Figure 4 As can be seen from the data, task A depends on 0 previous tasks, while tasks B, C, and D depend on task A; task B depends on 1 previous task, while task D depends on task B; task C depends on 1 previous task; and task D depends on 1 previous task. Figure 4 The computation graph shown records not only task information but also data variable information. Assuming that data variable 'a', the output of task A, is the input of tasks B and C, and the input of task D, and data variable 'b', the output of task B, is the input of task D, then the data variable information recorded in the computation graph is as follows: Figure 4 As shown in the diagram, four tasks require the use of data variable 'a', so the task count for data variable 'a' is 4; two tasks require the use of data variable 'b', so the task count for data variable 'b' is 2.

[0059] In this embodiment, each node can also generate new tasks during runtime, and add the new tasks to the computation graph based on the data input / output relationship between the new tasks and previous tasks. Assuming a node generates task E during runtime, and the data inputs of task E are the data outputs of task C and task D, then in... Figure 4 Add task E, and add directed line segments pointing to task E from task C and task D respectively, such as... Figure 5As shown in the diagram. Specifically, the task information for task C needs to include task E, which depends on task C; the task information for task D also needs to include task E, which depends on task D. The task information for task E records the number of tasks it depends on as 2. Furthermore, assuming that data variable c, the output of task C, and data variable d, the output of task D, are both inputs to task E, then data variables c and d also need to be added to the data variable information. The task count for data variable c is 2, and the task count for data variable d is 2.

[0060] It should be noted that, Figure 4 and Figure 5 The computation graphs shown are all implemented in the form of nodes and directed line segments. Computation graphs can also be implemented in other ways, such as lists, but this embodiment does not specifically limit them.

[0061] based on Figure 2 The distributed system 100 shown Figure 3A The hardware structure of each node is shown below, in conjunction with... Figure 3A The hardware structure shown describes the flow of the task scheduling method executed by the scheduler in each node. Please refer to [reference needed]. Figure 6 , Figure 6 This is a process 600 of the task scheduling method provided in this application embodiment, which includes:

[0062] Step 601: Receive the initialized computation graph and save the computation graph to the storage unit 103.

[0063] Step 602: Select task T1 in the computation graph that depends on the previous task number 0, and allocate storage space for task T1. This storage space is used to store the input data variables, output data variables, and temporary data of task T1.

[0064] Step 603: Select a locally idle arithmetic unit P1 and send an instruction message to execute task T1 to task P1. This instruction message includes the address space information of the memory unit 103 used to store the instruction program for task T1, and the address space information of the data variables to be input. Thus, task P1 can obtain the stored instruction program for task T1 from the memory unit 103 to execute task T1. Additionally, during the execution of task T1, task P1 can also obtain the address space information of the data variables to be input from the memory unit 103.

[0065] Step 604: After task T1 is completed, write an indication message indicating that task T1 has been completed to the notification cache output 1042.

[0066] Step 605: Based on the previous tasks that task T1 depends on, as indicated in the computation graph, determine whether the input data variable of task T1 comes from the local node. If it is detected that the input data variable of task T1 comes from the local node, proceed to step 606; if it is detected that the input data variable of task T1 comes from another node, proceed to step 607. In this step, since the computation graph records which previous task each task's input data variable comes from, the scheduler can determine whether the input data variable of task T1 comes from the local node or another node based on whether the task from which the input data variable of task T1 comes is executed locally or on another node. For example, if the input data variable of task T1 is the output data variable of task T11, when task T11 is executed locally, the input data variable of task T1 comes from the local node; when task T11 is executed on another node, the input data variable of task T1 comes from another node.

[0067] Step 606: Decrement the reference count of the data variables recorded in the computation graph by one.

[0068] Step 607: Write the instruction information of the input data variable of the release task T1 into the notification cache output 1042.

[0069] Step 608: Based on the tasks dependent on task T1 indicated in the computation graph, determine whether the output data variable of task T1 is consumed only locally. If it is detected that the output data variable of task T1 is consumed only locally, proceed to step 609; if it is detected that the output data variable of task T1 is also consumed by other nodes, proceed to step 610. In this embodiment, "consumption" refers to the output data variable of one task serving as the input data variable of another task. In this step, since the computation graph records which tasks' output data variables serve as their input data variables, the scheduler can determine whether the output data variable of task T1 is consumed only locally or by other nodes based on whether the task using the output data variable of task T1 as its input data variable is executed locally or on other nodes.

[0070] Step 609: Update the output data variable corresponding to task T1 recorded in the computation graph to the input data variable.

[0071] Step 610: Write the indication information of the value of the output data variable of task T1 to the notification cache output 1042.

[0072] Step 611: Check whether all tasks in the computation graph have been completed. If any unexecuted tasks are detected in the computation graph, proceed to step 612.

[0073] Step 612: Detect whether there is a task in the computation graph that depends on the previous task with a number of zeros. When a task in the computation graph that depends on the previous task with a number of zeros is detected, the task is designated as task T1, and steps 602 to 612 are continued.

[0074] In this embodiment, NIC 1041 can periodically send the information stored in the notification cache output 1042 to other nodes. For example, NIC 1041 can broadcast the indication information indicating that task T1 has been completed to all nodes in the distributed system 100; NIC 1041 can transmit the indication information indicating the release of the input data variables of task T1 to the node used to generate the input data variables of task T1; NIC 1041 can transmit the indication information indicating the value of the output data variables of task T1 to the node that uses the output data variables of task T1 as input data variables.

[0075] In this embodiment, NIC 1041 can also receive information and store the received information in notification cache input 1043. The scheduler can also periodically call tag matching engine 1044 to read information from notification cache input 1042 and update the computation graph based on the read information. Specifically, the information cached in notification cache input 1042 may include, but is not limited to: indication information I1 instructing other nodes to complete processing of task T12, indication information I2 instructing task T13 to be scheduled for execution by this node, indication information I3 instructing data variable V1 to be the input data variable of the local task, and indication information I4 instructing the release of local data variable V2. Specifically, tag matching engine 1044 can, based on indication information I1, remove the dependency relationship between tasks that execute after task T12 and depend on task T12 and task T12. Tag matching engine 1044 can, based on indication information I2, add task T13 to the computation graph. The tag matching engine 1044 can store the data variable V1 in the storage unit 104 based on the instruction information I3, as an input data variable for the local task. The tag matching engine 1044 can decrement the reference count of the data variable V2 recorded in the computation graph based on the instruction information I4.

[0076] In this embodiment of the application, the scheduler can also detect whether a new task T2 has been created during task execution. When the scheduler detects that a new task T2 has been created, it can also execute the following process steps for creating a new task T2:

[0077] First, based on the data variables input by task T2 and the previous tasks that task T2 depends on, task T2 is added to the computation graph, and the updated computation graph is broadcast to the remaining nodes.

[0078] Secondly, it is determined whether task T2 is executed locally. If task T2 is executed locally, storage space is allocated for task T2 in storage unit 103. This storage space is used to store the input data variables, output data variables, and temporary data of task T2. Instructions for executing task T2 are sent to the arithmetic unit P2, and then... Figure 6 Steps 603 to 610, similar to those shown, schedule task T2 and the data variables involved in task T2. When task T2 is not executed locally, an instruction to schedule task T2 to another idle node is written to the notification cache output 1042. In this step, the scheduler can periodically obtain the processor resource utilization rate of other nodes. Based on the local processor resource utilization rate, the processor resource utilization rate of other nodes, and whether input data is stored locally, the scheduler determines whether task T2 should be executed locally or scheduled to another node. For example, when the local processor resource utilization rate is lower than a preset threshold and the input data variables are stored locally, task T2 can be executed locally; conversely, when the local processor resource utilization rate is higher than a preset threshold and the processor resource utilization rate of other nodes is lower than a preset threshold, task T2 can be scheduled to another node.

[0079] pass Figure 3A The structural diagrams of each node shown are as follows: Figure 4 and Figure 5 The calculation diagram shown and Figure 6As can be seen from the task scheduling process executed by the scheduler shown, in the distributed system 100 provided in this application embodiment, the computation graph only records the data input / output relationship and the sequential execution relationship between tasks. The computation graph does not store the program that executes the task, but stores the program that executes the task in other memory or storage space. Therefore, compared with the computation graph in the prior art that manages functions and data together as task objects, the distributed system 100 provided in this application embodiment can simplify the design and generation of the computation graph, which is conducive to realizing that each node can save a copy of the computation graph and realize the global consistency of the computation graph on the distributed system. Thus, the distributed system 100 provided in this application embodiment can cover a larger cluster scale. Furthermore, in existing technologies, task scheduling, inter-node message passing, and task execution are all handled by the processor through software program calls. This leads to frequent switching between task scheduling threads and computational tasks, resulting in increased processor overhead and poor task scheduling concurrency. In contrast, in this embodiment, the scheduler for managing the computation graph and performing task scheduling, the processor for executing tasks, and the input / output units for communicating with other nodes are located in different hardware structures within each node. Compared to existing technologies, this reduces the computational overhead of computation graph scheduling and improves task scheduling concurrency. In summary, the distributed system 100 provided in this embodiment can improve task scheduling and task processing performance.

[0080] based on Figure 2 The architecture of the distributed system 100 shown Figure 3A The hardware structure of each node in the distributed system 100 shown below is illustrated in the following section. Figure 4 and Figure 5 The calculation graph shown is an example, and... Figure 4 and Figure 5 Taking the example of tasks distributed across nodes A1, A2, and A3, combined with... Figure 7A The application scenario shown provides a more detailed description of the execution of each task on each node in this embodiment. First, the computation graph can be generated by a compiler independent of the distributed system 100. Figure 4 The computation graph and the programs corresponding to each task in the computation graph shown can be broadcast by the compiler to nodes A1, A2, and A3 via the distributed system 100. In another possible implementation, the task compiler can be set in nodes at other levels, such as node C1. Node C1 can then generate the computation graph and the programs corresponding to each task in the computation graph. Node C1 then broadcasts the computation graph and the programs corresponding to each task in the computation graph to nodes A1, A2, and A3 through the connected nodes. Nodes A1, A2, and A3 have all pre-obtained... Figure 4The calculation diagram is shown. Assume... Figure 4 If tasks A and B are assigned to node A1 for execution, task C is assigned to node A2 for execution, and task D is assigned to node A3 for execution, then the steps executed by nodes A1, A2, and A3, and the interaction flow 800 between nodes A1, A2, and A3, include the following steps:

[0081] Step 801: In node A1, scheduler A1101 provides the program for task A stored in the program memory to the arithmetic unit. Step 802: After task A completes execution, scheduler A1101 provides the program for task B stored in the program memory to the arithmetic unit. Step 803: Scheduler A1101, through input / output unit A1104, provides the data variable 'a' generated after task A completes execution to nodes A2 and A3 respectively.

[0082] In step 804, in node A2, the scheduler A1102 provides the data variable a cached in the input / output unit A2104 to the arithmetic unit, and provides the program of task C stored in the program memory to the arithmetic unit.

[0083] Step 805: After task B is completed, scheduler A1101 provides the data variable b generated after task B is completed to node A3 through input / output unit A1104.

[0084] In step 806, in node A3, the scheduler A1103 provides the data variable a and data variable b cached in the input / output unit A3104 to the arithmetic unit, and provides the program of task D stored in the program memory to the arithmetic unit.

[0085] The above has been approved. Figure 8 The interactive flow shown is for Figure 4 The computational graph shown illustrates the execution status of each task on each node and the interactions between nodes. Furthermore, in... Figure 4 Based on the computational graph shown, it is assumed that during the execution of tasks A through D, additional computational tasks are generated. Figure 5 As shown, task E, based on its data dependencies on previous tasks, will generate nodes for task E. Figure 4 The computation graph shown has been updated to Figure 5 The calculation graph shown is then used to calculate the graph. Figure 5The computation graph shown is broadcast to each node in the distributed system 100. It should be noted that in this embodiment, the nodes used to generate new tasks and update the computation graph may not necessarily execute the newly generated task. In one possible implementation, each node periodically broadcasts its local compute unit resource utilization rate to all nodes. Each node can query the compute unit resource utilization rates of other nodes. If the node generating the new task currently has a high compute unit resource utilization rate (i.e., the compute unit is overloaded), it can schedule the new task to a node with a lower compute unit resource utilization rate. For example, if node A2 generates a new task E during task processing, and node A2 has a high compute unit resource utilization rate while node A3 has a low compute unit resource utilization rate, then node A2 will schedule task E to node A3 for processing. Of course, if the node generating the new task has a low compute unit resource utilization rate or the data used to process the new task is stored locally, the node generating the new task can also process the newly generated task locally. Assuming task E runs on node A3, such as... Figure 7B As shown, the computational graph memories in nodes A1, A2, and A3 respectively store... Figure 5 The calculation diagram is shown. Since the data variable c output by task C and the data variable d output by task D are both inputs to task E, then in Figure 8 Following step 806, the following steps are also included: Step 807, after task C is completed, the scheduler A2101 in node A2 calls the input / output unit A2104 to provide the data variable c to node A3; Step 808, in node A3, after task D is completed, the scheduler A1103 provides the cached data variable c and the generated data variable d in the input / output unit A3104 to the arithmetic unit, and provides the program of task E stored in the program memory to the arithmetic unit.

[0086] exist Figure 2In the distributed system 100 shown, the computation graph of each node may change over time as tasks are completed and the number of tasks increases. If an error occurs in the operation of a node, the error may be due to a problem with its own program or an error in the information transmitted between nodes. If an error in the information transmitted between nodes causes an error in the operation of one or more nodes, it is impossible to trace the error information between those nodes when the computation graph changes. Therefore, to improve the error correction capability and reliability of the distributed system 100, in this embodiment, higher-level nodes can periodically save the local computation graph and the next lower level computation graph locally. That is, the higher the level of the node, the more detailed the computation graph it saves, and the more tasks and input-output relationships between tasks it saves. For example, node N1 can periodically save its current computation graph, node A1's current computation graph, and node A2's current computation graph to its own memory; node A1 can periodically save node N1's computation graph to its own memory; and node A2 can periodically save node N1's computation graph to its own memory. It should be noted that in this embodiment, the period for higher-level nodes to save their computation graphs is longer than the period for lower-level nodes. Since higher-level nodes save their computation graphs for longer periods, setting the period for higher-level nodes to save their computation graphs longer than that for lower-level nodes ensures that small-scale, low-cost computation graph saving occurs frequently, while large-scale, high-cost computation graph saving occurs less frequently, thereby controlling the computing power and storage resources consumed in computation graph saving. Furthermore, when an error occurs on a node in the distributed system 100, the system first checks whether the error can be recovered from the computation graph previously saved by the node. If it cannot be recovered from the computation graph, the system notifies the parent node to recover from the computation graph saved by the parent node. If it can be recovered from the computation graph saved by the node, the node continues to operate normally after successfully recovering from the computation graph previously saved by the node. If recovery from the computation graph previously saved by the node fails, the system further checks whether the failed recovery can be recovered from the computation graph saved by the node. If the failed recovery cannot be recovered from the computation graph saved by the node, the system notifies the parent node to recover from the computation graph saved by the parent node.

[0087] Based on the same inventive concept, embodiments of this application also provide a task scheduling method, which is applied to tasks such as... Figure 3A The nodes shown are shown. Please continue reading. Figure 9This illustrates a flowchart 900 of a task scheduling method provided in an embodiment of this application. The flowchart 900 can be executed by a scheduler 101 in a node, and includes the following steps: Step 901, based on the dependencies between multiple tasks recorded in the computation graph, assigning a first task among the multiple tasks to a first arithmetic unit for execution; Step 902, after the first task is completed, sending first indication information indicating the completion of the first task to a second node, wherein the dependencies are used to indicate the sequential execution relationship between multiple tasks and the input / output relationship of data variables between multiple tasks.

[0088] In one possible implementation, after the first task is completed, the task scheduling method further includes: when the first task generates a second task during execution, adding the second task to the computation graph based on the dependency relationship between the second task and the tasks in the computation graph; and sending the updated computation graph to the second node.

[0089] In one possible implementation, the task scheduling method further includes: periodically receiving indication information from the second node indicating the resource utilization rate of the arithmetic unit in the second node; when it is found that the resource utilization rate of the arithmetic unit in the second node is lower than a preset threshold, sending second indication information to the second node, the second indication information being used to instruct the second node to process the second task.

[0090] In one possible implementation, the task scheduling method further includes: when the first data variable output by the first task is the input data variable of the second task executed in the second node, sending the first data variable to the second node.

[0091] In one possible implementation, the task scheduling method further includes: when the second data variable input by the first task is the data variable output by the third task executed in the second node, after the first task is completed, sending third indication information to the second node, the third indication information being used to indicate the release of the second data variable.

[0092] In one possible implementation, the computation graph also records indication information indicating whether the data variable is an input data variable or an output data variable; the task scheduling method further includes: when the first data variable is an input data variable of the fourth task, modifying the indication information indicating that the first data variable is an output data variable to an indication information indicating that the first data variable is an input data variable, wherein the fourth task is assigned by the scheduler to the second arithmetic unit among the plurality of arithmetic units for execution.

[0093] In one possible implementation, the computation graph also records the number of times a data variable is referenced, the reference indicating that the data variable is at least one of an input data variable and an output data variable; the task scheduling method further includes: when the second data variable is the output data variable of the fifth task, decrementing the number of times the second data variable is referenced by one, wherein the fifth task is assigned by the scheduler to the third arithmetic unit among the plurality of arithmetic units for execution.

[0094] It is understood that, in order to achieve the above-mentioned functions, the scheduler 101 includes hardware and / or software modules corresponding to the execution of each function. Based on the steps of the various examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in a manner that drives hardware or computer software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in conjunction with the embodiments, but such implementation should not be considered beyond the scope of this application.

[0095] This embodiment can divide the scheduler 101 into functional modules according to the above method example. For example, different functional modules can be divided for each function, or two or more functions can be integrated into one processing module. The integrated modules can be implemented in hardware. It should be noted that the module division in this embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0096] When dividing each function into modules according to its corresponding function. Figure 10 This diagram illustrates one possible embodiment of the apparatus 1000 described above. Further extensions of the aforementioned apparatus are possible, for example... Figure 10 The corresponding device 1000 can be a software device running on the scheduler 101, or the device 1000 can be a combination of software and hardware, embedded in the scheduler 101. For example... Figure 10 As shown, the device 1000 may include: an allocation module 1001, configured to allocate a first task among the multiple tasks to a first arithmetic unit for execution based on the dependency relationship between multiple tasks recorded in the computation graph; and a first sending module 1002, configured to send a first indication information indicating the completion of the first task to a second node after the first task has been executed, wherein the dependency relationship is used to indicate the sequential execution relationship between multiple tasks and the input-output relationship of data variables between multiple tasks.

[0097] In one possible implementation, after the first task is completed, the device 1000 further includes: an adding module (not shown in the figure), used to add the second task to the computation graph based on the dependency relationship between the second task and the tasks in the computation graph when the first task generates the second task during the execution of the first task; and a second sending module (not shown in the figure), used to send the updated computation graph to the second node.

[0098] In one possible implementation, the device 1000 further includes: a receiving module (not shown in the figure), configured to periodically receive indication information from the second node indicating the resource utilization rate of the arithmetic unit in the second node; and a third sending module (not shown in the figure), configured to send second indication information to the second node when it is found that the resource utilization rate of the arithmetic unit in the second node is lower than a preset threshold, wherein the second indication information is used to instruct the second node to process the second task.

[0099] In one possible implementation, the device 1000 further includes: a fourth sending module (not shown in the figure), used to send the first data variable to the second node when the first data variable output by the first task is the input data variable of the second task executed in the second node.

[0100] In one possible implementation, the device 1000 further includes: a fifth sending module (not shown in the figure), configured to send third indication information to the second node after the first task is completed when the second data variable input by the first task is the data variable output by the third task executed in the second node, the third indication information being used to indicate the release of the second data variable.

[0101] In one possible implementation, the computation graph also records indication information indicating whether the data variable is an input data variable or an output data variable; the device 1000 further includes: a modification module (not shown in the figure), used to modify the indication information indicating that the first data variable is an output data variable to the indication information indicating that the first data variable is an input data variable when the first data variable is an input data variable for the fourth task, wherein the fourth task is assigned by the scheduler to the second arithmetic unit among the plurality of arithmetic units for execution.

[0102] In one possible implementation, the computation graph also records the number of times a data variable is referenced, the reference indicating that the data variable is at least one of an input data variable and an output data variable; the device 1000 further includes: a count change module (not shown in the figure), used to decrement the number of times the second data variable is referenced by one when the second data variable is an output data variable of the fifth task, wherein the fifth task is assigned by the scheduler to the third of the plurality of arithmetic units for execution.

[0103] The apparatus 1000 provided in this embodiment is used to execute the task scheduling method executed by the scheduler 101, and can achieve the same effect as the above-described implementation method or apparatus. Specifically, the above... Figure 10 Each module can be implemented in software, hardware, or a combination of both. For example, each module can be implemented in software to drive the scheduler 101. Alternatively, each module can include a corresponding processor and corresponding driver software, i.e., implemented in software or hardware in combination.

[0104] Exemplarily, the scheduler 101 may further include at least one processor and a memory. The at least one processor can invoke all or part of the computer program stored in the memory to control and manage the operations of the scheduler 101, for example, it can be used to support the scheduler 101 in executing the steps performed by the various modules described above. The memory can be used to support the scheduler 101 in executing stored program code and data, and the memory includes, but is not limited to, at least a portion of the storage space, cache, or registers of the storage unit 103 described above. The at least one processor can implement or execute various exemplary multiple logic modules described in conjunction with the disclosure of this application, which may be a combination of one or more microprocessors implementing computing functions. Furthermore, the at least one processor may also include other programmable logic devices, transistor logic devices, or discrete hardware components, etc.

[0105] This embodiment also provides a computer-readable storage medium storing computer instructions. When the computer instructions are executed on a computer, the computer performs the aforementioned method steps to implement the method for securely accessing software described in the above embodiment.

[0106] This embodiment also provides a computer program product that, when run on a computer, causes the computer to perform the aforementioned related steps to implement the method for securely accessing software described in the above embodiment.

[0107] In this embodiment, the computer-readable storage medium or computer program product is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects of the corresponding method provided above, and will not be repeated here.

[0108] Through the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0109] Furthermore, the functional units in the various embodiments of this application can be integrated into a single product, or each unit can exist physically separately, or two or more units can be integrated into a single product. Corresponding to Figure 9 If the aforementioned modules are implemented as software functional units and sold or used as independent products, they can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, essentially or in other words, the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0110] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An electronic device, wherein the electronic device is a first electronic device, characterized in that, The electronic device includes a scheduler, an array of execution units, and a storage unit; The scheduler is configured to assign a first task among the multiple tasks to a first arithmetic unit in the execution unit array for execution based on the dependency relationships between multiple tasks recorded in the computation graph, and to send a first indication message indicating the completion of the first task to a second electronic device after the first task has been executed. The dependency relationships are used to indicate the sequential execution relationship between the multiple tasks and the input-output relationship of data variables between the multiple tasks. The second electronic device is configured to execute one or more tasks among the multiple tasks other than the first task. The storage unit is used to store the computation graph and the executable programs of the plurality of tasks, wherein the computation graph and the executable programs of the plurality of tasks are located in different storage spaces. The execution unit array includes multiple arithmetic units, and the first arithmetic unit among the multiple arithmetic units is used to execute the first task; The scheduler is further configured to add the second task to the computation graph based on the dependency relationship between the second task and the tasks in the computation graph when the first task generates the second task during execution; The updated computational graph is sent to the second electronic device.

2. The electronic device according to claim 1, characterized in that, The scheduler is also used for: Periodically receive indication information from the second electronic device indicating the resource utilization rate of the arithmetic unit in the second electronic device; When it is found that the resource utilization rate of the arithmetic unit in the second electronic device is lower than a preset threshold, a second instruction message is sent to the second electronic device. The second instruction message is used to instruct the second electronic device to process the second task.

3. The electronic device according to claim 1, characterized in that, The scheduler is also used for: When the first data variable output by the first task is the input data variable of the second task executed in the second electronic device, the first data variable is sent to the second electronic device.

4. The electronic device according to any one of claims 1-3, characterized in that, The scheduler is also used for: When the second data variable input by the first task is the data variable output by the third task executed in the second electronic device, after the first task is completed, a third instruction message is sent to the second electronic device, and the third instruction message is used to indicate the release of the second data variable.

5. The electronic device according to claim 3, characterized in that, The computation graph also records indication information indicating whether the data variable is an input data variable or an output data variable; The scheduler is further configured to: when the first data variable is an input data variable for the fourth task, modify the indication information indicating that the first data variable is an output data variable to an indication information indicating that the first data variable is an input data variable, wherein the fourth task is assigned by the scheduler to the second arithmetic unit among the plurality of arithmetic units for execution.

6. The electronic device according to claim 4, characterized in that, The computation graph also records the number of times a data variable is referenced, wherein the reference indicates that the data variable is at least one of input data variable and output data variable; The scheduler is further configured to: decrement the number of times the second data variable is referenced by one when the second data variable is the output data variable of the fifth task, wherein the fifth task is assigned by the scheduler to the third arithmetic unit among the plurality of arithmetic units for execution.

7. The electronic device according to any one of claims 1-3 and 5-6, characterized in that, The electronic device also includes an input / output unit, which includes a notification buffer input, a notification buffer output, a network interface controller, and a tag matching engine. The notification cache output is used to cache the instruction information that the scheduler is about to send to the second electronic device; The notification cache input is used to cache information received from the second electronic device; The network interface controller is configured to send the cached indication information in the notification cache output to the second electronic device, and to cache the information received from the second electronic device to the notification cache input; The tag matching engine is used to read information from the notification cache input and update the computation graph based on the information from the notification cache input.

8. The electronic device according to claim 7, characterized in that, The information in the notification cache input includes at least one of the following: The system includes a fourth instruction message indicating the completion of processing the sixth task, a fifth instruction message indicating the first electronic device to perform the seventh task, and a sixth instruction message indicating the release of the third data variable in the first electronic device.

9. The electronic device according to claim 8, characterized in that, The tag matching engine is specifically used for: Based on the fourth instruction information, the dependency relationship between the sixth task and other tasks recorded in the computation graph is removed; Based on the fifth instruction information, the seventh task is added to the computation graph; Based on the sixth indication information, the number of times the third data variable recorded in the computation graph is referenced is reduced by one.

10. The electronic device according to any one of claims 1-3, 5-6, and 8-9, characterized in that, The storage unit includes multiple memories, a first memory for storing the computation graph, a second memory for storing the executable programs of the multiple tasks, and a third memory for storing data.

11. A distributed system, characterized in that, It includes multiple nodes, each of which stores a computation graph. The computation graph records the dependencies between multiple tasks. The dependencies are used to indicate the sequential execution relationship between the multiple tasks and the input-output relationship of data variables between the multiple tasks. The tasks in the computation graph are executed by at least some of the nodes. Each of the plurality of nodes is an electronic device as described in any one of claims 1 to 10.

12. A task scheduling method, applied to a first node, characterized in that, The first node is a first electronic device, comprising an execution unit array and a storage unit. The execution unit array includes multiple arithmetic units, with the first arithmetic unit being one of the multiple arithmetic units. The storage unit stores a computation graph and executable programs for multiple tasks, wherein the computation graph and the executable programs for the multiple tasks are located in different storage spaces. Based on the dependencies between multiple tasks recorded in the computation graph, the first task among the multiple tasks is assigned to the first arithmetic unit for execution; After the first task is completed, a first indication message indicating the completion of the first task is sent to the second node. The dependency relationship is used to indicate the sequential execution relationship between the multiple tasks and the input-output relationship of data variables between the multiple tasks. The second node is a second electronic device, which is used to execute one or more of the multiple tasks other than the first task. Wherein, after the first task is completed, the method further includes: When the first task generates the second task during execution, the second task is added to the computation graph based on the dependency relationship between the second task and the tasks in the computation graph; The updated computation graph is sent to the second node.

13. The task scheduling method according to claim 12, characterized in that, The task scheduling method further includes: Periodically receive indication information from the second node indicating the resource utilization rate of the arithmetic unit in the second node; When the resource utilization rate of the arithmetic unit in the second node is found to be lower than a preset threshold, a second indication message is sent to the second node. The second indication message is used to instruct the second node to process the second task.

14. The task scheduling method according to claim 12, characterized in that, The task scheduling method further includes: When the first data variable output by the first task is the input data variable of the second task executed in the second node, the first data variable is sent to the second node.

15. The task scheduling method according to any one of claims 12-14, characterized in that, The task scheduling method further includes: When the second data variable input by the first task is the data variable output by the third task executed in the second node, after the first task is completed, a third instruction message is sent to the second node, and the third instruction message is used to indicate the release of the second data variable.

16. The task scheduling method according to claim 15, characterized in that, The computation graph also records indication information indicating whether the data variable is an input data variable or an output data variable; The task scheduling method further includes: When the first data variable is the input data variable of the fourth task, the indication information indicating that the first data variable is the output data variable will be modified to the indication information indicating that the first data variable is the input data variable, wherein the fourth task is assigned by the scheduler to the second arithmetic unit among the plurality of arithmetic units for execution.

17. The task scheduling method according to claim 15, characterized in that, The computation graph also records the number of times a data variable is referenced, wherein the reference indicates that the data variable is at least one of input data variable and output data variable; The task scheduling method further includes: When the second data variable is the output data variable of the fifth task, the number of times the second data variable is referenced is decremented by one, wherein the fifth task is assigned by the scheduler to the third arithmetic unit among the plurality of arithmetic units for execution.

18. An electronic device, characterized in that, The electronic device includes a memory and a task scheduler, the memory being used to store computer programs, and the task scheduler being configured to invoke all or part of the computer programs stored in the memory to execute the task scheduling method as described in any one of claims 12 to 17.

19. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a task scheduler, is used to implement the task scheduling method as described in any one of claims 12 to 17.

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