A display panel and display device

Abstract

This invention discloses a display panel and a display device. In one specific embodiment, the display panel includes a display area and a border area surrounding the display area. A common voltage feedback line and N clock signal lines, where N>1, are disposed in the border area. The distance between the (n+1)th clock signal line and the common voltage feedback line is greater than the distance between the nth clock signal line and the common voltage feedback line, where n∈[1,N]. The clock signal of the mth clock signal line has an opposite waveform to that of the (m+N / 2)th clock signal line, where m∈[1,N / 2]. A compensation capacitor is disposed between the (m+N / 2)th clock signal line and the common voltage feedback line. This embodiment can effectively improve the horizontal stripe defect in display products, especially large-size display products, while ensuring the improvement of the greenish display effect, thus contributing to the improvement of the image quality of the display products.

Description

Technical Field

[0001] This invention relates to the field of display technology. More specifically, it relates to a display panel and a display device. Background Technology

[0002] Horizontal stripe defects are common in display products using related technologies, especially for large-size display products, which seriously affects the image quality of the display products. Summary of the Invention

[0003] The purpose of this invention is to provide a display panel and display device to solve at least one of the problems existing in the prior art.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] The first aspect of the present invention provides a display panel, including a display area and a border area surrounding the display area, wherein a common voltage feedback line and N clock signal lines are disposed in the border area, where N>1;

[0006] The distance between the (n+1)th clock signal line and the common voltage feedback line is greater than the distance between the nth clock signal line and the common voltage feedback line, where n∈[1,N];

[0007] The clock signal of the m-th clock signal line is opposite to the waveform of the (m+N / 2)-th clock signal line, where m ∈ [1, N / 2]. A compensation capacitor is provided between the (m+N / 2)-th clock signal line and the common voltage feedback line.

[0008] Optionally, the sum of the capacitance value of the compensation capacitor and the coupling capacitance value between the (m+N / 2)th clock signal line and the common voltage feedback line is the first capacitance value, and the coupling capacitance value between the clock signal of the mth clock signal line and the common voltage feedback line is the second capacitance value, wherein the first capacitance value and the second capacitance value are equal.

[0009] Optionally, the display panel includes a substrate, and the bezel area includes a wiring layer on the substrate and an insulating layer covering the wiring layer. The wiring layer includes the common voltage feedback line and the N clock signal lines. The insulating layer has a first opening and a second opening. The orthographic projection of the first opening on the substrate overlaps with the orthographic projection of the common voltage feedback line on the substrate, and the first opening does not expose the common voltage feedback line. The orthographic projection of the second opening on the substrate overlaps with the orth projection of the (m+N / 2)th clock signal line on the substrate, and the second opening exposes the (m+N / 2)th clock signal line. The bezel area also includes a first electrode layer located in the first opening and a first connection line covering the insulating layer and connecting the first electrode layer and the (m+N / 2)th clock signal line through the first opening and the second opening. The first electrode layer and the common voltage feedback line constitute the compensation capacitor.

[0010] Optionally, the display panel includes a substrate, and the bezel area includes a wiring layer on the substrate and an insulating layer covering the wiring layer. The wiring layer includes the common voltage feedback line and the N clock signal lines. The insulating layer has a first opening and a second opening. The orthographic projection of the first opening on the substrate overlaps with the orthographic projection of the common voltage feedback line on the substrate, and the first opening exposes the common voltage feedback line. The orthographic projection of the second opening on the substrate overlaps with the orth projection of the (m+N / 2)th clock signal line on the substrate, and the second opening does not expose the (m+N / 2)th clock signal line. The bezel area also includes a second electrode layer located in the second opening and a second connection line covering the insulating layer and connecting the second electrode layer and the common voltage feedback line through the first opening and the second opening. The second electrode layer and the (m+N / 2)th clock signal line constitute the compensation capacitor.

[0011] Optionally, the material of the first connecting wire is indium tin oxide, or the material of the second connecting wire is indium tin oxide.

[0012] Optionally, the width of the first connecting line is smaller than the width of the clock signal line, or the width of the second connecting line is smaller than the width of the clock signal line.

[0013] Optionally, the display area includes a plurality of sub-pixels arranged in an array, each sub-pixel including a thin-film transistor, wherein the first electrode layer is disposed in the same layer as the source-drain metal layers forming the source and drain of the thin-film transistor, or the second electrode layer is disposed in the same layer as the source-drain metal layers forming the source and drain of the thin-film transistor.

[0014] Optionally, the display panel further includes a printed circuit board, and the compensation capacitor is disposed on the printed circuit board.

[0015] Optionally, the display panel is a liquid crystal display panel.

[0016] A second aspect of the present invention provides a display device including the aforementioned display panel.

[0017] The beneficial effects of this invention are as follows:

[0018] This invention provides a display panel that can effectively improve the horizontal stripe defect in display products, especially large-size display products, while ensuring the improvement of the greenish phenomenon, thereby enhancing the picture quality of display products. Attached Figure Description

[0019] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0020] Figure 1 The diagram shows the wiring schematic of the clock signal line, common voltage feedback line, and common voltage line in the related technology.

[0021] Figure 2a The diagram shows the common voltage feedback and measured common voltage waveform of large-size products in related technologies.

[0022] Figure 2b This illustrates a pair of solutions utilized in the relevant technology. Figure 2a A schematic diagram of common voltage sampling and compensation for the product shown.

[0023] Figure 3a The measured waveform of the clock signal duty cycle adjustment scheme in the relevant technology is shown.

[0024] Figure 3b This demonstrates the use of Scheme 2 in the related technology. Figure 3a The waveform diagram of the adjustment scheme for the product shown is illustrated.

[0025] Figure 4 A circuit diagram of a display panel provided in the first embodiment of the present invention is shown.

[0026] Figure 5a The diagram shows a measured waveform of the mutual cancellation of the pull of the first clock signal and the fourth clock signal on the common voltage signal in the related technology.

[0027] Figure 5b In the related technologies shown Figure 5a A magnified view of a portion of the measured image shown.

[0028] Figure 6 The diagram shows the waveform of the display panel circuit after adding a 280pF capacitor for adjustment, according to the first embodiment of the present invention.

[0029] Figure 7 The diagram shows the waveform of the display panel circuit after adding a 360pF capacitor for adjustment, according to the first embodiment of the present invention.

[0030] Figure 8 A schematic diagram of the structure of a display panel provided in the second embodiment of the present invention is shown.

[0031] Figure 9 A schematic diagram of the structure of a display panel provided in the third embodiment of the present invention is shown.

[0032] Figure 10 This diagram illustrates the wiring layer of a display panel provided in a second embodiment of the present invention.

[0033] Figure 11 A schematic diagram of the wiring layer of a display panel provided in the third embodiment of the present invention is shown. Detailed Implementation

[0034] The terms “on”, “formed on”, and “set on” used in this disclosure can indicate that one layer is directly formed or set on another layer, or that one layer is indirectly formed or set on another layer, meaning that there are other layers between the two layers.

[0035] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0036] In this disclosure, unless otherwise stated, the term "co-layer arrangement" means that two layers, components, members, elements, or portions can be formed by the same fabrication process (e.g., patterning process), and that the two layers, components, members, elements, or portions are generally formed of the same material. For example, co-layer arrangement of two or more functional layers means that these co-layer functional layers can be formed using the same material layers and the same fabrication process, thereby simplifying the fabrication process of the display substrate.

[0037] In this disclosure, unless otherwise stated, the term "patterning process" generally includes steps such as photoresist coating, exposure, development, etching, and photoresist stripping. The term "one-step patterning process" refers to a process that uses a photomask to form patterned layers, components, or parts.

[0038] Display products, especially large-size products, often suffer from horizontal stripe defects. The inventors have discovered that during the adjustment of greenish, the higher the compensation factor of the common electrode signal (VCOM), the better the greenish adjustment result, but the horizontal stripe phenomenon in grayscale will be more severe. The two effects are contradictory, making it impossible to ensure that both horizontal stripe and greenish are optimal, which seriously affects product quality.

[0039] In related technologies, Greenish is caused by the inconsistent pull of different source traces on the common electrode voltage under certain screen conditions. As a result, the common electrode voltage does not recover to the center value during the charging time, causing green pixels to be brighter and the overall screen to appear green.

[0040] Regarding the horizontal stripe problem, the inventors analyzed and confirmed that it was caused by the coupling between the clock signal line of the parallel-line gate driver on array (GOA) and the signal of the common voltage feedback line (VCOM Feedback). The horizontal stripe disappeared when the Feedback input was disconnected.

[0041] There are two solutions in the relevant technologies. Solution one is to reduce the VCOM compensation factor; solution two is to adjust the duty cycle (CLK Duty) of the clock signal so that the rising and falling edges of the GOA signals cancel each other out. However, both solutions can only alleviate the problem to a certain extent. For example, reducing the VCOM compensation factor in solution one may worsen the greenish effect; solution two may still result in poor improvement of the horizontal stripe effect because the rise time (Tr) and fall time (Tf) of different clock signals (CLK) may differ, or the pull degree between different CLKs may be different.

[0042] like Figure 1 As shown, the array substrate is divided into display areas and non-display areas. The display area is the pixel area on the array substrate, which is used to display images when the display device is working, including the AA area 101; the non-display area is the area that does not have display function, including the GOA area 102 and the dummy area. Figure 1 The wiring is symmetrical from left to right, including multiple clock signal lines (e.g., 6 clock signal lines, namely the first clock signal line 1031 (CLK1) to the sixth clock signal line 1036 (CLK6)) located on one side of the GOA area, a common voltage feedback line 104 adjacent to the clock signal lines, and a first common voltage line 105, a second common voltage line 106 and a third common voltage line 107.

[0043] The capacitance value between parallel traces can be approximately determined using the capacitance formula, which is:

[0044] 8A / D

[0045] In the formula, ε is the dielectric constant between traces; A is the effective area between traces; and D is the distance between traces.

[0046] Based on the routing information within the corresponding plane, it can be seen that the closer the CLK trace is to the Feedback trace (i.e., the smaller the distance D), the larger the coupling capacitance C between the two traces according to the capacitance formula. Therefore, the CLK trace is more strongly coupled to the Feedback waveform. For example... Figure 1 In the GOA area, the wiring from the outside to the AA area is Feedback, CLK1, CLK2, CLK3, CLK4, CLK5 and CLK6 respectively. CLK1 is closest to Feedback, that is, the distance to D is the smallest. The larger the coupling capacitance C, the more severe the voltage change of the rising and falling edges of the CLK1 waveform will be for Feedback.

[0047] Therefore, the distance between different CLKs and Feedback traces varies, which in turn leads to different degrees of coupling pull on Feedback by different CLK traces.

[0048] like Figure 2a The image shows the measured common voltage feedback and common voltage waveform of a large-size product in related technologies. For example... Figure 2b The image shows a pair of schemes used in related technologies. Figure 2a A schematic diagram of the common voltage sampling and compensation for the product shown. Figure 2b The signal includes a first clock signal 201 (CLK1), a second clock signal 202 (CLK2), a third clock signal 203 (CLK3), a fourth clock signal 204 (CLK4), a fifth clock signal 205 (CLK5), a sixth clock signal 206 (CLK6), a common voltage feedback signal 207 (Feedback), a common voltage signal 208 (VCOM), a pull-up waveform 2071 coupled with the rising edge of the first to sixth clock signals, and a pull-down waveform 2072 coupled with the falling edge of the first to sixth clock signals.

[0049] exist Figure 2bIn this circuit, both the rising and falling edges of the clock signal are coupled to the common voltage (VCOM) to varying degrees. After compensation by the reference voltage comparator amplifier (VCOM OP), the VCOM output will be further amplified by reverse compensation. That is, the larger the amplification factor of VCOM OP, the more severe the ripple. Furthermore, when the gate is turned off (falling edge of CLK), the VCOM ripple cannot quickly recover to the center value, resulting in inconsistent VCOM values ​​for different rows. Moreover, it changes periodically with CLK, forming horizontal stripe defects.

[0050] like Figure 3a The image shows a measured waveform of a clock signal duty cycle adjustment scheme in a related technology. (Example:) Figure 3b The image shows the application of Scheme 2 in related technologies. Figure 3a The waveform diagram of the adjustment scheme for the product shown is illustrated. Figure 3b The diagram includes waveforms of the first clock signal 301 (CLK1), the second clock signal 302 (CLK2), the third clock signal 303 (CLK3), the fourth clock signal 304 (CLK4), the fifth clock signal 305 (CLK5), the sixth clock signal 306 (CLK6), the common voltage feedback signal 308 (Feedback), the common voltage signal 309 (VCOM), the pull-up signals 3071 of the first to third clock signals to the common voltage feedback signal, and the pull-down signals 3072 of the fourth to sixth clock signals to the common voltage feedback signal.

[0051] Depend on Figure 3b It can be seen that by canceling out the rising and falling edges of different clock signals (CLK), the coupling pull of CLK's rising and falling edges on VCOM is further reduced. When different CLKs (e.g. Figure 3b When the rising and falling edges of CLK1 and CLK4 shown are completely aligned, they do have a certain offsetting effect on the Ripple. However, the degree of pull on VCOM by the falling edge of CLK1 and the rising edge of CLK4 is inconsistent, so there will still be a pull on VCOM in the end, and the problem cannot be completely avoided.

[0052] In view of this, one embodiment of the present invention provides a display panel, including a display area and a border area surrounding the display area. A common voltage feedback line and N clock signal lines are disposed in the border area, where N>1; the distance between the (n+1)th clock signal line and the common voltage feedback line is greater than the distance between the nth clock signal line and the common voltage feedback line, where n∈[1,N]; the clock signal of the mth clock signal line has the opposite waveform to that of the (m+N / 2)th clock signal line, where m∈[1,N / 2]; and a compensation capacitor is disposed between the (m+N / 2)th clock signal line and the common voltage feedback line.

[0053] In a specific example, by increasing the capacitance between the clock signal line and the common voltage feedback line, and by adjusting the compensation capacitor values ​​of different clock signal lines and the common voltage feedback line, the consistency of the coupling degree of the rising and falling edges of different clock signals to the common voltage feedback signal within the display panel can be achieved. This allows the rising and falling coupling of different clock signals to cancel each other out, enabling the common voltage to quickly recover to the center value when the gate is turned off. This improves the grayscale horizontal stripe problem caused by increasing the compensation factor of the Greenish degree in the heavy-duty surface, greatly enhances the picture quality, and increases product competitiveness.

[0054] This embodiment can effectively improve the horizontal stripe defect of display products, especially large-size display products, while ensuring the improvement of the greenish phenomenon of display products, which is conducive to improving the picture quality of display products.

[0055] In one possible implementation, the sum of the capacitance value of the compensation capacitor and the coupling capacitance value between the (m+N / 2)th clock signal line and the common voltage feedback line is a first capacitance value, and the coupling capacitance value between the clock signal of the mth clock signal line and the common voltage feedback line is a second capacitance value, wherein the first capacitance value and the second capacitance value are equal.

[0056] This embodiment effectively improves large-size horizontal stripe defects. By setting variable capacitor compensation on the printed circuit board assembly (PCBA), it solves the problem of conflict between Greenish debugging and grayscale horizontal stripe solutions, greatly improving the product image quality.

[0057] In one possible implementation, the display panel further includes a printed circuit board on which the compensation capacitor is disposed.

[0058] In a specific example, such as Figure 4 As shown, the printed circuit board includes a level shift unit 407, a compensation factor adjustment unit 409, and a reference voltage comparison and amplification unit 408.

[0059] Furthermore, the level offset unit 407 is used to receive the clock signal, amplify it to obtain the amplified clock signal, and output the amplified clock signal through multiple clock signal lines, including a first clock signal line 401 (CLK1), a second clock signal line 402 (CLK2), a third clock signal line 403 (CLK3), a fourth clock signal line 404 (CLK4), a fifth clock signal line 405 (CLK5), and a sixth clock signal line 406 (CLK6).

[0060] Furthermore, the compensation factor adjustment unit 409 is used to receive the common voltage feedback signal, the common voltage signal and the amplified clock signal, and perform compensation factor adjustment to obtain the adjusted common voltage feedback signal and the adjusted common voltage signal, wherein the compensation factor adjustment unit 409 receives the common voltage signal via the common voltage line 4002.

[0061] Furthermore, the compensation factor adjustment unit 409 includes a first capacitor 4094, a first resistor 4091, a second resistor, and a third resistor; wherein the first terminal of the first capacitor 4094 receives the common voltage feedback signal and the clock signal after passing through the compensation capacitor, and the second terminal of the first capacitor 4094 is connected to the first terminal of the first resistor 4091; the first terminal of the second resistor 4092 is connected to the second terminal of the first resistor 4091 and the first input terminal of the reference voltage comparison amplification unit 408; the first terminal of the third resistor 4093 receives the common voltage feedback signal, and the second terminal of the third resistor 4093 is connected to the second terminal of the second resistor 4092 and the second input terminal of the reference voltage comparison amplification unit 408.

[0062] Furthermore, the reference voltage comparison amplification unit 408 is used to receive the adjusted common voltage feedback signal and the adjusted common voltage signal after compensation.

[0063] In a specific example, such as Figure 4 As shown, the PCBA has a reserved mounting point 400 between the clock signal and the common voltage feedback signal. Figure 4 The schematic diagram of the debugged upper part shows that capacitors are added between the clock signal line and the common voltage feedback line. Specifically, a second capacitor 4041 is added between the fourth clock signal line 404 and the common voltage feedback line 4001, a third capacitor 4051 is added between the fifth clock signal line 405 and the common voltage feedback line 4001, and a fourth capacitor 4061 is added between the sixth clock signal line 406 and the common voltage feedback line 4001. The capacitance values ​​can be customized to compensate for the capacitance differences between the traces of different clock signals and the common voltage signal on the display panel. Ultimately, the coupling state of each clock signal with respect to the common voltage is made consistent. This achieves complete cancellation of the ripple, based on the original mutual cancellation of clock signals to reduce ripple. Finally, under the premise of a large VCOM compensation factor, the horizontal stripe problem is effectively improved.

[0064] In a specific example, such as Figure 4As shown, when the distance between the first clock signal line 401 (CLK1) to the sixth clock signal line 406 (CLK6) and the common voltage feedback line 4001 gradually increases, according to the capacitance formula, the coupling capacitance C of the GOA signal to the Feedback is... clk1 >C clk2 >C clk3 >C clk4 >C clk5 >C clk6 To ensure that the coupling of the rising and falling edges of the clock signal waveform to the common voltage feedback signal can cancel each other out—for example, the rising (falling) edge of CLK1 cancels out the falling (rising) edge of CLK4—the coupling of CLK1 and CLK4 to the feedback needs to be approximately equal. This can be approximated by considering that C... clk1 With C clk4 Consistent, as can be seen from the wiring, C clk1 >C clk4 Therefore, by routing on the PCBA, an additional compensation capacitor, namely the second capacitor 4041 (C1), can be added between the fourth clock signal line 404 (CLK4) and the common voltage feedback line 4001 (Feedback), so that C clk4 Parallel with C1 and C clk1 The pulls are equal, thus achieving a similar degree of pull on the Feedback signal waveform, and the pulls cancel each other out.

[0065] In related technologies, Figure 5a The diagram shows a measured waveform of the mutual cancellation of the pull of the first clock signal and the fourth clock signal on the common voltage signal in the related technology. Figure 5b In the related technologies shown Figure 5a A magnified view of a portion of the measured image shown. (See attached image.) Figure 5a In the waveform measurement diagram of the product containing the first to sixth clock signals shown, when the CLK Duty is adjusted to 50%, the rising and falling edges of CLK1 and CLK4 coincide, and they can cancel each other out to some extent, but there is a certain difference in the rise time (Tr) and fall time (Tf). The thin-film transistor (TFT) can be completely turned off when the gate voltage drops to -4V. Figure 5b It can be seen that when CLK1 drops to -4V, the common voltage feedback signal still has a negative level of 940mV relative to the center value. After being amplified by the VCOM OP inverting amplifier, the deviation of VCOM relative to the center value is about 3.5V, which is a very large deviation.

[0066] In a specific example, such as Figure 6As shown in the diagram, the waveform after adding a 280pF capacitor between CLK4 and the common voltage feedback line shows that both the feedback and VCOM rise are reduced to some extent after adjustment. When CLK1 drops to -4V, the VCOM level deviates from the center value by approximately 860mV, which is relatively... Figure 5b The Ripple scheme in the example has a significant reduction.

[0067] In a specific example, such as Figure 7 As shown in the diagram, after adding a 360pF capacitor between CLK4 and the common voltage feedback line, the waveform diagram shows that when CLK1 drops to -4V, the VCOM level deviates from the center value by about 5mV, which has basically recovered to the center value, and the horizontal stripes in the grayscale image are basically invisible.

[0068] This embodiment, by selecting appropriate matching capacitor values ​​for different products, can eliminate the coupling ripple of different CLKs to VCOM, provided that the CLK Duty is adjustable, without affecting the adjustment multiple of VCOM OP. It can also achieve optimal Greenish adjustment, and the added capacitor is in the pF level, which has a relatively small impact on the PCBA circuit.

[0069] In one possible implementation, such as Figure 8 As shown, the display panel includes a substrate 801, and the bezel area includes a wiring layer on the substrate 801 and an insulating layer 802 covering the wiring layer. The wiring layer includes the common voltage feedback line 803 and the N clock signal lines (e.g., 8041, 8042, and 8043). The insulating layer 802 has a first opening 8051 and a second opening 8052. The orthographic projection of the first opening 8051 on the substrate 801 overlaps with the orthographic projection of the common voltage feedback line 803 on the substrate 801, and the first opening 8051 does not expose the common voltage feedback line 803. The second opening 8052 is located in the... The orthographic projection on the substrate 801 overlaps with the orthographic projection on the substrate 801 of the (m+N / 2)th clock signal line (e.g., 8041), and the second opening 8052 exposes the (m+N / 2)th clock signal line (e.g., 8041). The border area also includes a first electrode layer 806 located in the first opening 8051 and a first connection line 807 covering the insulating layer 801 and connecting the first electrode layer 806 and the (m+N / 2)th clock signal line (e.g., 8041) through the first opening 8051 and the second opening 8052. The first electrode layer 806 and the common voltage feedback line 803 constitute the compensation capacitor.

[0070] This embodiment effectively improves large-size horizontal stripe defects. By setting a variable capacitor compensation on the display panel, it solves the problem of the contradiction between Greenish debugging and grayscale horizontal stripe solutions, and greatly improves the product's picture quality.

[0071] In a specific example, such as Figure 10 As shown, when the distances between the first clock signal line 1041 (CLK11), the second clock signal line 1042 (CLK12), the third clock signal line 1043 (CLK13), the fourth clock signal line 1044 (CLK14), the fifth clock signal line 1045 (CLK15), and the sixth clock signal line 1046 (CLK16) and the common voltage feedback line 1003 gradually increase, according to the capacitance formula, the coupling capacitance C of the GOA signal to the Feedback is... clk11 >C clk12 >C clk13 >C clk14 >C clk15 >C clk16 To ensure that the coupling of the rising and falling edges of the clock signal waveform to the common voltage feedback signal can cancel each other out—for example, to ensure that the rising (falling) edge of CLK11 cancels out the falling (rising) edge of CLK14—the coupling of CLK11 and CLK14 to the feedback signal needs to be approximately equal. This can be approximated by considering that C... clk11 With C clk14 Therefore, to ensure consistency, a first connection line 1071 is added between the fourth clock signal line 1044 (CLK14) and the common voltage feedback line 1003 (Feedback) to form the compensation capacitor (C2), so that C clk14 Parallel with C2 and C clk11 Equal; a first connection line 1072 is added between the fifth clock signal line 1045 (CLK15) and the common voltage feedback line 1003 (Feedback) to form the compensation capacitor (C3), such that C clk15 Parallel with C3 and C clk12 Equal; a first connection line 1073 is added between the sixth clock signal line 1046 (CLK6) and the common voltage feedback line 1003 (Feedback) to form the compensation capacitor (C4), such that C clk16 Parallel with C4 and C clk13 Equal; thus achieving a similar degree of pulling on the Feedback signal waveform, achieving mutual cancellation of the up and down pulling.

[0072] In a specific example, according to the capacitance formula, given a fixed dielectric constant and distance, the additional compensation capacitance can be adjusted by adjusting the effective area between traces (e.g., the product of trace length and width).

[0073] This embodiment eliminates the need for component placement on the PCBA; signal coupling can be achieved simply by routing within the panel.

[0074] In a specific example, the capacitor dielectric of the compensation capacitor is a gate insulating layer and a passivation layer.

[0075] In one possible implementation, such as Figure 9 As shown, the display panel includes a substrate 901. The bezel area includes a wiring layer on the substrate 901 and an insulating layer 902 covering the wiring layer. The wiring layer includes a common voltage feedback line 903 and N clock signal lines (e.g., 9041, 9042, and 9043). The insulating layer has a first opening 9051 and a second opening 9052. The orthographic projection of the first opening 9051 on the substrate 901 overlaps with the orthographic projection of the common voltage feedback line 903 on the substrate 901, and the first opening 9051 exposes the common voltage feedback line 903. The second opening 9052 is located on the substrate. The orthographic projection on 901 overlaps with the orthographic projection of the (m+N / 2)th clock signal line (e.g., 9041) on the substrate 901, and the second opening 9052 does not expose the (m+N / 2)th clock signal line (e.g., 9041). The border area also includes a second electrode layer 906 located in the second opening 9052 and a second connection line 907 covering the insulating layer 902 and connecting the second electrode layer 906 and the common voltage feedback line 903 through the first opening 9051 and the second opening 9052. The second electrode layer 907 and the (m+N / 2)th clock signal line (e.g., 9041) constitute the compensation capacitor.

[0076] In a specific example, such as Figure 11 As shown, when the distances between the first clock signal line 1141 (CLK21), the second clock signal line 1142 (CLK22), the third clock signal line 1143 (CLK23), the fourth clock signal line 1144 (CLK24), the fifth clock signal line 1145 (CLK25), and the sixth clock signal line 1146 (CLK26) and the common voltage feedback line 1103 gradually increase, according to the capacitance formula, the coupling capacitance C of the GOA signal to the Feedback is... clk21 >C clk22 >C clk23 >C clk24 >C clk25 >C clk26To ensure that the coupling of the rising and falling edges of the clock signal waveform to the common voltage feedback signal cancels out, such as the rising (falling) edge of CLK21 canceling out the falling (rising) edge of CLK24, the coupling of CLK21 and CLK24 to the feedback needs to be roughly equal. This can be approximated by considering that C... clk21 With C clk24 Therefore, to ensure consistency, a first connection line 1171 is added between the fourth clock signal line 1144 (CLK24) and the common voltage feedback line 1103 (Feedback) to form the compensation capacitor (C5), so that C clk24 Parallel with C5 and C clk21 Equal; a first connection line 1172 is added between the fifth clock signal line 1145 (CLK25) and the common voltage feedback line 1103 (Feedback) to form the compensation capacitor (C6), such that C clk25 Parallel with C6 and C clk22 Equal; a first connection line 1173 is added between the sixth clock signal line 1146 (CLK26) and the common voltage feedback line 1103 (Feedback) to form the compensation capacitor (C7), such that C clk26 Parallel with C7 and C clk23 Equal; thus achieving a similar degree of pulling on the Feedback signal waveform, achieving mutual cancellation of the up and down pulling.

[0077] In a specific example, according to the capacitance formula, given a fixed dielectric constant and distance, the additional compensation capacitance can be adjusted by adjusting the effective area between traces (e.g., the product of trace length and width).

[0078] This embodiment eliminates the need for component placement on the PCBA; signal coupling can be achieved simply by routing within the panel.

[0079] In a specific example, the capacitor dielectric of the compensation capacitor is a gate insulating layer and a passivation layer.

[0080] In one possible implementation, the display area includes a plurality of sub-pixels arranged in an array, each sub-pixel including a thin-film transistor, wherein the first electrode layer is disposed in the same layer as the source-drain metal layers forming the source and drain of the thin-film transistor, or the second electrode layer is disposed in the same layer as the source-drain metal layers forming the source and drain of the thin-film transistor.

[0081] In a specific example, routing is performed on the common voltage feedback line and the (m+N / 2)th clock signal line. A source-drain metal line (i.e., the first connection line or the second connection line) is designed on the common voltage feedback line or the corresponding (m+N / 2)th clock signal line and overlaps with it in parallel with the common voltage feedback line or the corresponding (m+N / 2)th clock signal line. The drain-source metal line is connected through a via in the second electrode layer, so that the gate metal line of the common voltage feedback line and the (m+N / 2)th clock signal metal line form a compensation capacitor.

[0082] In a specific example, an additional compensation capacitor is formed by routing the common voltage feedback line and the m+N / 2th clock signal line (i.e., the first connection line or the second connection line) and connected in parallel with the original capacitor. This ensures that the required clock signal has the same coupling degree to the common voltage feedback signal, thereby achieving mutual cancellation of the coupling degree of the corresponding signal rising and falling edges to the Feedback signal.

[0083] In one possible implementation, the material of the first connecting wire is indium tin oxide, or the material of the second connecting wire is indium tin oxide.

[0084] In one possible implementation, the width of the first connection line is smaller than the width of the clock signal line, or the width of the second connection line is smaller than the width of the clock signal line.

[0085] In a specific example, the trace at the crossover position in the middle of the first or second connecting line can be made thinner. The two poles of the capacitor are the common voltage feedback signal and the clock signal of the m+N / 2th line, respectively. The capacitor dielectric is the gate insulating layer (GI). The area can be adjusted by adjusting the length and / or width of the first or second connecting line, thereby further adjusting the size of the capacitor.

[0086] In one possible implementation, the display panel is a liquid crystal display panel.

[0087] Another embodiment of the present invention provides a display device, including the display module provided in the above embodiments. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator; this embodiment does not limit this.

[0088] Obviously, the above embodiments of this disclosure are merely examples for clearly illustrating this disclosure, and are not intended to limit the implementation of this disclosure. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. Any obvious variations or modifications derived from the technical solutions of this disclosure are still within the protection scope of this disclosure.

Claims

1. A display panel, characterized in that, It includes a display area and a border area surrounding the display area, wherein a common voltage feedback line and N clock signal lines are provided in the border area, where N>1; The distance between the (n+1)th clock signal line and the common voltage feedback line is greater than the distance between the nth clock signal line and the common voltage feedback line, where n∈[1,N]; The clock signal of the m-th clock signal line is opposite to the waveform of the (m+N / 2)-th clock signal line, where m∈[1,N / 2]. A compensation capacitor is provided between the (m+N / 2)-th clock signal line and the common voltage feedback line. The display panel includes a substrate. The bezel area includes a wiring layer on the substrate and an insulating layer covering the wiring layer. The wiring layer includes the common voltage feedback line and the N clock signal lines. The insulating layer has a first opening and a second opening. The orthographic projection of the first opening on the substrate overlaps with the orthographic projection of the common voltage feedback line on the substrate, and the first opening does not expose the common voltage feedback line. The orthographic projection of the second opening on the substrate overlaps with the orth projection of the (m+N / 2)th clock signal line on the substrate, and the second opening exposes the (m+N / 2)th clock signal line. The bezel area also includes a first electrode layer located in the first opening and a layer covering the insulating layer and connecting the first electrode layer to the (m+N / 2)th clock signal line through the first opening and the second opening. The first connecting line of N / 2 clock signal lines, the first electrode layer and the common voltage feedback line constitute the compensation capacitor; or, the orthographic projection of the first opening on the substrate overlaps with the orthographic projection of the common voltage feedback line on the substrate and the first opening exposes the common voltage feedback line, the orthographic projection of the second opening on the substrate overlaps with the orth projection of the (m+N / 2)th clock signal line on the substrate and the second opening does not expose the (m+N / 2)th clock signal line, the border area also includes a second electrode layer located in the second opening and a second connecting line covering the insulating layer and connecting the second electrode layer and the common voltage feedback line through the first opening and the second opening, the second electrode layer and the (m+N / 2)th clock signal line constitute the compensation capacitor.

2. The display panel according to claim 1, characterized in that, The sum of the capacitance value of the compensation capacitor and the coupling capacitance value between the (m+N / 2)th clock signal line and the common voltage feedback line is the first capacitance value, and the coupling capacitance value between the clock signal of the mth clock signal line and the common voltage feedback line is the second capacitance value. The first capacitance value and the second capacitance value are equal.

3. The display panel according to claim 1, characterized in that, The material of the first connecting wire is indium tin oxide, or the material of the second connecting wire is indium tin oxide.

4. The display panel according to claim 1, characterized in that, The width of the first connecting line is less than the width of the clock signal line, or the width of the second connecting line is less than the width of the clock signal line.

5. The display panel according to claim 1, characterized in that, The display area includes a plurality of sub-pixels arranged in an array. Each sub-pixel includes a thin-film transistor. The first electrode layer is disposed in the same layer as the source-drain metal layers forming the source and drain of the thin-film transistor, or the second electrode layer is disposed in the same layer as the source-drain metal layers forming the source and drain of the thin-film transistor.

6. The display panel according to claim 1, characterized in that, The display panel also includes a printed circuit board, and the compensation capacitor is disposed on the printed circuit board.

7. The display panel according to claim 1, characterized in that, The display panel is a liquid crystal display panel.

8. A display device, characterized in that, The display panel includes any one of claims 1-7.

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