A method for implementing a new three-dimensional chip

Abstract

The application belongs to the field of computing architecture and chip design, and discloses a new three-dimensional chip implementation method. According to the method, different functional three-dimensional chips can be manufactured by the lowest flow sheet, and the manufacturing cost of the different functional three-dimensional chips can be effectively reduced. In addition, the method can improve the density of transistors under a unit projection area, and can effectively reduce the energy loss caused by signal transmission between chips.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of reconfigurable processor design, and particularly relates to a new three-dimensional chip implementation method. BACKGROUND

[0002] With the continuous development of artificial intelligence technology, the demand for chip computing power is getting higher and higher. On the one hand, the computing power of a single chip is limited by the slow evolution of Moore's law and is difficult to improve quickly. On the other hand, the power consumption problem of the chip has become a problem to be solved. Generally, the lower the power consumption of the chip, the more conducive to the miniaturization of the device, and the economic cost caused by chip computing heat dissipation can be reduced.

[0003] The three-dimensional chip can greatly improve the transistor density per unit projection area by vertically stacking multiple chips into one chip. At the same time, compared with the plane interconnection between chips in the traditional chip, the vertical interconnection is adopted between chips in the three-dimensional chip. This connection can effectively reduce the energy loss caused by signal transmission. Therefore, the three-dimensional chip has become an important technical choice to improve the integration of the chip and reduce the power consumption of the chip.

[0004] However, although the three-dimensional chip can improve the integration of the chip and reduce the power consumption, because the three-dimensional chip needs to flow multiple times for the stacked chips, the cost of the three-dimensional chip is high, which seriously limits the development and wide application of the three-dimensional chip. SUMMARY

[0005] In order to solve at least one problem mentioned in the background art, the present application proposes a new three-dimensional chip implementation method.

[0006] A new three-dimensional chip implementation method, comprising the steps of:

[0007] Step S1, performing a flow design step to obtain two round crystals, the front surface of one side of the round crystal, and the back surface after the round crystal is flipped 180 degrees along the diameter plane, wherein the flow design step is specifically performed, and the steps include:

[0008] Step S101, designing two kinds of chips with the same size and area, marked as functional chip A and functional chip B, the functions of the functional chip A and the functional chip B can be the same or different;

[0009] Step S102, arranging the functional chip A and the functional chip B according to the arrangement rule within the limit range of the mask, and the arrangement rule specifically includes:

[0010] Arrangement rule one, in the horizontal direction, the functional chip A and the functional chip B are placed according to the interval rule, and arranged in a row matrix;

[0011] The second arrangement rule is that the functional chip A and the functional chip B are arranged according to a spacing rule in the vertical direction, and are arranged in a column matrix;

[0012] The third arrangement rule is that the number of chips between two adjacent row matrices is equal, and the functional chips between the two adjacent row matrices are different;

[0013] The fourth arrangement rule is that the chips between the row matrices are scribe lanes, and the chips between the column matrices are scribe lanes, and the function of the scribe lane is to place a mark circuit for wafer bonding alignment and a test circuit for the chip manufacturing process;

[0014] In step S2, the first wafer is placed with the front face upward, and the second wafer is placed with the back face upward.

[0015] In the traditional chip, the chips are distributed in a plane, and this connection relationship leads to a too long connection distance between the chips.

[0016] In step S3, the two wafers after being stacked are bonded with the front faces aligned, and the bonding is specifically to form a vertical corresponding relationship between the A chip in the first wafer and the B chip in the second wafer, and then the top metal of the corresponding A chip and B chip is electrically connected through a hole.

[0017] In step S4, the wafer after being bonded is cut along the scribe lane to obtain a stacked three-dimensional die.

[0018] In step S5, the obtained three-dimensional die is packaged to obtain a three-dimensional chip.

[0019] Generally, to realize three-dimensional chips with different functions, two different functional wafers are stacked, and because the two wafers involve different manufacturing processes, this method needs to bear the cost of two wafer flow sheets. The present application proposes to place different logic chips on one wafer, and then stack the same two wafers to obtain a three-dimensional die with different functions. The method proposed in the present application only needs to be masked once, and therefore the method proposed in the present application can significantly reduce the manufacturing cost of three-dimensional chips with different functions.

[0020] The present application proposes a new three-dimensional chip implementation method, which has the following advantages compared with the existing technology:

[0021] The present application provides a novel three-dimensional chip implementation technology, according to the method, different functional three-dimensional chips can be manufactured by the lowest flow sheet, and the manufacturing cost of different functional three-dimensional chips can be effectively reduced.

[0022] The method can improve the density of transistors per unit projection area, and effectively reduce the energy loss caused by signal transmission between chips. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is a flowchart of the present application;

[0024] Figure 2 is an arrangement diagram of two functional chips in the embodiment of the present application;

[0025] Figure 3 is a front surface diagram of a wafer obtained after flow sheeting in the embodiment of the present application;

[0026] Figure 4 is a back surface diagram of a wafer obtained after flow sheeting in the embodiment of the present application;

[0027] Figure 5 is a three-dimensional grain diagram obtained by cutting the stacked wafer in the embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to make the purpose and features of the present application more obvious and easy to understand, the technical solution will be described in detail below by examples and in combination with the drawings.

[0029] As shown in Figure 1 A novel three-dimensional chip implementation method comprises the following steps:

[0030] Step S1, a flow sheet design step is performed to obtain two wafers, the front surface of one side of the wafer is the front surface, and the back surface is obtained after the wafer is flipped by 180 degrees along the diameter plane; wherein the flow sheet design step specifically comprises the following steps:

[0031] Step S101, design two chips with the same size and area, marked as functional chip A and functional chip B, the functions of the functional chip A and the functional chip B can be the same or different.

[0032] In the actual implementation process, optionally, A is a calculation circuit chip, and B is a memory circuit chip.

[0033] Step S102, arrange the functional chip A and the functional chip B according to the arrangement rule within the limit range of a mask, and the arrangement rule specifically comprises:

[0034] The arrangement rule one is that the functional chips A and the functional chips B are arranged in a horizontal direction according to a spacing rule, and are arranged in a row matrix.

[0035] The arrangement of the functional chips A and the functional chips B is shown in the figure. Figure 2

[0036] The arrangement rule two is that the functional chips A and the functional chips B are arranged in a vertical direction according to a spacing rule, and are arranged in a column matrix.

[0037] The arrangement rule three is that the number of chips between two adjacent row matrices is equal, and the functional chips between the two adjacent row matrices are different.

[0038] The arrangement rule four is that the chips between the row matrices are scribe lanes, and the chips between the column matrices are scribe lanes, and the function of the scribe lanes is to place a mark circuit for wafer bonding alignment and a test circuit for the chip manufacturing process.

[0039] According to the above arrangement rules, the functional chips A and the functional chips B are arranged within the wafer mask limit, and the front surface of the wafer obtained after the wafer is processed is shown in the figure. Figure 3 The back surface of the wafer obtained after the wafer is processed is shown in the figure. Figure 4

[0040] Step S2, stack the first wafer with the front surface upward and the second wafer with the back surface upward, the front surface of the wafer is the top metal surface, and the back surface is the silicon substrate.

[0041] In the traditional chip, the chips are distributed in a plane, and this connection relationship leads to a too long connection distance between the chips. The chip stacking method in the three-dimensional space is adopted in the present application, so that the chips become vertically interconnected. The size of the transistor in this connection relationship is smaller than that in the traditional planar interconnection. Therefore, compared with the traditional method, the method proposed in the present application can improve the density of transistors per unit projection area and effectively reduce the energy loss caused by signal transmission between chips.

[0042] Step S3, bond the two stacked wafers with the front surfaces facing each other. The bonding is specifically to form a vertical corresponding relationship between the A chip in the first wafer and the B chip in the second wafer, and then electrically connect the top metal of the corresponding A chip and B chip through a hole.

[0043] In the actual implementation process, the wafer bonding method is optional, and common methods include hybrid bonding.

[0044] Step S4, cut the bonded wafer along the scribe lane to obtain a stacked three-dimensional die, as shown in the figure. Figure 5

[0045] ​​​Step S5, the obtained three-dimensional crystal grain is packaged to obtain a three-dimensional chip. In the actual manufacturing process, the form of packaging is not limited.

[0046] Generally, to realize three-dimensional chips with different functions, two different functional wafers are stacked. Because the two wafers involve different manufacturing processes, the method needs to bear the cost of two wafer flow sheets. The present application proposes to place different logic chips on one wafer, and then stack the same two wafers to obtain three-dimensional crystal grains with different functions. The method proposed by the present application only needs to perform a mask for different functional chips. Therefore, the method proposed by the present application can significantly reduce the manufacturing cost of three-dimensional chips with different functions.

[0047] At this point, according to the method disclosed in the present application, the working process of the present application has been completed.

[0048] Although the present application has been fully described in the specification by general description and specific embodiments, some modifications or improvements can be made on the basis of the present application, which is obvious to those skilled in the art. Therefore, these modifications or improvements made on the basis of not deviating from the spirit of the present application, all belong to the scope of protection required by the present application.

Claims

1. A novel method for implementing a three-dimensional chip, comprising the following steps: Step S1: Perform the wafer fabrication design steps to obtain two wafers. One side of the wafer is the front side, and the wafer is flipped 180 degrees along any diameter plane to become the back side. The two wafers are identical, and different logic chips are placed on them. in, The chip design process described in step S1 specifically includes the following steps: Step S101: Design two chips with the same side length and area, labeled as functional chip A and functional chip B. Step S102: Within a photomask limit, arrange functional chip A and functional chip B according to the arrangement rules; Step S2: Stack the first wafer with the front side facing up and the second wafer with the back side facing up. Step S3: Bond the two stacked wafers face to face. Step S4: The bonded wafer is cut along the dicing path to obtain stacked three-dimensional grains. Step S5: The obtained three-dimensional die is packaged to obtain a three-dimensional chip; The arrangement rules specifically include: Arrangement rule one: In the horizontal direction, functional chip A and functional chip B are placed according to an interval pattern, arranged in a row matrix. Arrangement rule two: In the vertical direction, functional chip A and functional chip B are placed according to an interval pattern, arranged in a column matrix; Rule 3: The number of chips in two adjacent rows of matrices is equal, and the functional chips in two adjacent rows of matrices are different. Rule 4: The chips between rows of a matrix are scribe lines, and the chips between columns of a matrix are scribe lines.

2. The method for implementing a novel three-dimensional chip according to claim 1, characterized in that, The functional chip A and functional chip B mentioned in step S101 may have the same function.

3. The method for implementing a novel three-dimensional chip according to claim 1, characterized in that, The functional chips A and B mentioned in step S101 may have different functions.

4. A method for implementing a novel three-dimensional chip according to claim 2 or 3, characterized in that, The dicing channels between the row matrix and the column matrix chips serve to house marking circuits for wafer bonding alignment and test circuits for the chip manufacturing process.

5. The method for implementing a novel three-dimensional chip according to claim 1, characterized in that, In step S3, bonding the two stacked wafers face to face involves first establishing a vertical correspondence between the functional chip A in the first wafer and the functional chip B in the second wafer, and then electrically connecting the top metal of the corresponding functional chip A and functional chip B through holes.

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