Scan driving circuit, array substrate, display panel and display device

Abstract

The application relates to a scanning driving circuit, an array substrate, a display panel and a display device. The circuit comprises a preset high potential signal line, N clock signal lines and M scanning driving units in cascade. Each scanning driving unit comprises N adjusting circuits and 2N GDL circuits in cascade. The i-th GDL circuit in the 2N GDL circuits is connected with the i-th clock signal line in the N clock signal lines, and i [1, N]. The j-th GDL circuit in the 2N GDL circuits is connected with the preset high potential signal line and the i-th clock signal line in the N clock signal lines through the i-th adjusting circuit in the N adjusting circuits. The i-th adjusting circuit is used for adjusting the clock signal provided by the i-th clock signal line according to the high level signal provided by the preset high potential signal line, obtaining an adjusted clock signal, and j = i + N. In this way, the number of clock signal lines can be reduced to half of the original number, and the narrow frame design of the display panel can be better realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a scan driving circuit, an array substrate, a display panel and a display device. BACKGROUND

[0002] With the continuous maturity of liquid crystal display technology, liquid crystal display (LCD) has many advantages such as thin body, power saving, no radiation, etc., and thus has been widely applied. For example, it is widely applied in liquid crystal televisions, mobile phones, personal digital assistants, digital cameras, computers or notebook computers and other devices.

[0003] At present, the Gate Driver Less (GDL) technology is generally used in LCD, that is, the gate driving circuit (GDL circuit) of the horizontal scan line is made on the substrate around the display area, so that it can replace the external integrated circuit board (IC) to complete the driving of the horizontal scan line, so as to save space and reduce production cost.

[0004] However, with the increasing performance requirements of the size, refresh rate and resolution of the display panel, the number of clock signal lines (CLK signal lines) of the display panel is also increasing, which will increase the overall space occupied by the CLK signal lines, resulting in that it is difficult for the display panel to realize narrow frame design. Therefore, how to reduce the number of CLK signal lines while meeting the performance requirements of the display panel has become a technical problem to be solved. SUMMARY

[0005] The present application provides a scan driving circuit, an array substrate, a display panel and a display device to solve the problem that the existing display panel is difficult to realize narrow frame design due to the limitation of the number of CLK signal lines.

[0006] In a first aspect, an embodiment of the present application provides a scan driving circuit, comprising: a preset high potential signal line, N clock signal lines and M cascade scan driving units, the preset high potential signal line is used to provide a high level signal, the N clock signal lines are used to provide N different clock signals, each of the scan driving units comprises N adjusting circuits and 2N cascade gate driving circuits, and N and M are both integers greater than or equal to 1.

[0007] Among the 2N gate driving circuits, the i-th gate driving circuit is connected with the i-th clock signal line among the N clock signal lines, and the i-th gate driving circuit is used to output the i-th scan signal according to the clock signal provided by the i-th clock signal line, i∈[1,N];

[0008] The jth gate drive circuit in the 2N gate drive circuits is connected with the preset high potential signal line and the ith clock signal line in the N clock signal lines through the ith adjusting circuit in the N adjusting circuits, the ith adjusting circuit is used for adjusting the clock signal provided by the ith clock signal line according to the high level signal provided by the preset high potential signal line to obtain an adjusted clock signal, the jth gate drive circuit is used for outputting a jth scanning signal according to the adjusted clock signal provided by the ith adjusting circuit, the adjusted clock signal provided by the ith adjusting circuit is opposite to the potential of the clock signal provided by the ith clock signal line, j = i + N, j ∈ [N, 2N].

[0009] Optionally, the ith adjusting circuit comprises a first switch tube and a second switch tube.

[0010] The first end and the second end of the first switch tube are connected with the preset high potential signal line, the third end of the first switch tube is connected with the first end of the jth gate drive circuit and the first end of the second switch tube respectively, the second end of the second switch tube is connected with the ith clock signal line, and the third end of the second switch tube is connected with a first low potential signal line.

[0011] Optionally, the ratio of the current value of the second switch tube in the on state to the current value of the first switch tube in the on state is greater than a preset threshold value, and the preset threshold value is greater than or equal to 5.

[0012] Optionally, each of the 2N gate drive circuits comprises a first node, and a pull-up control module, an output module and a first pull-down control module connected with the first node.

[0013] The pull-up control module is used for pulling up the potential of the first node to a high potential according to the received first level signal.

[0014] The output module is used for outputting a corresponding scanning signal according to the received clock signal in the case that the potential of the first node is pulled up to a high potential.

[0015] The first pull-down control module is used for pulling down the potential of the first node to a low potential according to the received second level signal.

[0016] Optionally, the output module comprises a third switch tube and a fourth switch tube.

[0017] In the jth gate drive circuit, the first end of the third switch tube and the first end of the fourth switch tube are connected with the first node, the second end of the third switch tube and the second end of the fourth switch tube are connected with the first end of the jth gate drive circuit as a first end of the jth gate drive circuit, the first end of the second switch tube and the third end of the first switch tube are connected, the third end of the third switch tube is connected with the level transmission signal input end of other gate drive circuits, and the third end of the fourth switch tube is connected with the scan line of the corresponding pixel row.

[0018] In the ith gate drive circuit, the first end of the third switch tube and the first end of the fourth switch tube are connected with the first node, the second end of the third switch tube and the second end of the fourth switch tube are connected with the ith clock signal line, the third end of the third switch tube is connected with the level transmission signal input end of other gate drive circuits, and the third end of the fourth switch tube is connected with the scan line of the corresponding pixel row.

[0019] Optionally, each of the 2N gate drive circuits further comprises a second node, and a pull-down module and a second pull-down control module connected with the second node.

[0020] The second pull-down control module is configured to pull up the potential of the second node to a high potential according to the received power voltage signal.

[0021] The pull-down module is configured to pull down the potentials of the level transmission signal and the scan signal output by the output module in the case that the potential of the second node is pulled up to a high potential.

[0022] Optionally, each of the 2N gate drive circuits further comprises a pull-down maintenance module.

[0023] The pull-down maintenance module is connected with the second node, and the pull-down maintenance module is configured to maintain the potential of the second node according to the received first level transmission signal.

[0024] In a second aspect, the embodiments of the present application further provide an array substrate, comprising the scan drive circuit and 2N*M scan lines, the 2N*M gate drive circuits in the scan drive circuit are connected with the 2N*M scan lines one by one, and each scan line is connected with a plurality of pixel units.

[0025] In a third aspect, the embodiments of the present application further provide a display panel, comprising a counter substrate, a liquid crystal layer, and the array substrate as described in the second aspect, wherein the liquid crystal layer is located between the counter substrate and the array substrate.

[0026] In a fourth aspect, the embodiments of the present application further provide a display device, comprising a housing and the display panel as described in the third aspect, wherein the display panel is arranged on the housing.

[0027] The above technical solution provided by the embodiments of the present application has the following advantages compared with the prior art: the scanning driving circuit provided by the embodiments of the present application comprises a preset high potential signal line, N clock signal lines and M scanning driving units connected in cascade, the preset high potential signal line is used to provide a high level signal, the N clock signal lines are used to provide N different clock signals, each scanning driving unit comprises N adjusting circuits and 2N gate driving circuits connected in cascade, N and M are integers greater than or equal to 1; wherein the i-th gate driving circuit in the 2N gate driving circuits is connected with the i-th clock signal line in the N clock signal lines, the i-th gate driving circuit is used to output an i-th scanning signal according to the clock signal provided by the i-th clock signal line, i∈[1,N]; the j-th gate driving circuit in the 2N gate driving circuits is connected with the preset high potential signal line and the i-th clock signal line in the N clock signal lines through the i-th adjusting circuit in the N adjusting circuits, the i-th adjusting circuit is used to adjust the clock signal provided by the i-th clock signal line according to the high level signal provided by the preset high potential signal line to obtain an adjusted clock signal, the j-th gate driving circuit is used to output a j-th scanning signal according to the adjusted clock signal provided by the i-th adjusting circuit, the adjusted clock signal provided by the i-th adjusting circuit is opposite to the potential of the clock signal provided by the i-th clock signal line, j=i+N, j∈[N,2N]. In this way, for each scanning driving unit, the N adjusting circuits can be used to adjust the clock signals provided by the N clock signal lines to obtain N adjusted clock signals for the latter N gate driving circuits in the scanning driving unit, so that the number of clock signal lines can be reduced to half of the original, and the overall space occupied by the clock signal lines is reduced, which can better realize the narrow frame design of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0028] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles behind the application.

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0030] One or more embodiments are illustrated by way of example with reference to the drawings, which are schematic and not intended to be limiting of the present application, and in which like reference numerals refer to like elements in the various figures of the drawings. The drawings are not necessarily to scale, the emphasis instead being placed upon illustrating the principles of the embodiments.

[0031] Figure 1 A structural schematic diagram of a scan driving circuit provided by an embodiment of the present application is shown in FIG. 1.

[0032] Figure 2 A structural schematic diagram of a scan driving circuit provided by the prior art is shown in FIG. 2.

[0033] Figure 3 A timing sequence diagram of a clock signal line CLK provided by the prior art is shown in FIG. 3.

[0034] Figure 4 A structural schematic diagram of another scan driving circuit provided by an embodiment of the present application is shown in FIG. 4.

[0035] Figure 5 A connection schematic diagram of a 5th and 6th GDL circuit and a regulating circuit in a scan driving unit provided by an embodiment of the present application is shown in FIG. 5.

[0036] Figure 6 A connection schematic diagram of a 1st and 2nd GDL circuit in a scan driving unit provided by an embodiment of the present application is shown in FIG. 6.

[0037] Figure 7 A structural schematic diagram of an array substrate provided by an embodiment of the present application is shown in FIG. 7.

[0038] Figure 8 A structural schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 8.

[0039] Figure 9 A structural schematic diagram of a display device provided by an embodiment of the present application is shown in FIG. 9.

[0040] Wherein, 100, scan driving unit; 110, adjusting circuit; 120, GDL circuit; 1201, pull-up control module; 1202, output module; 1203, first pull-down control module; 1204, pull-down module; 1205, second pull-down control module; 1206, pull-down maintenance module; 710, scan driving circuit; 720, scan line; 810, opposite substrate; 820, liquid crystal layer; 830, array substrate; 910, shell; 920, display panel. DETAILED DESCRIPTION

[0041] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the following will be combined with the drawings in the embodiments of the present application to make a clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments are a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work belong to the scope of protection of the present application.

[0042] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeatedly refer to numbers and / or letters in different examples. Such repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or settings discussed.

[0043] Reference Figure 1 , Figure 1 A structure schematic diagram of a scan driving circuit provided by the embodiments of the present application is provided. As shown in Figure 1 , the scan driving circuit comprises a preset high potential signal line VGH, N clock signal lines CLK and M scan driving units 100 connected in cascade, the preset high potential signal line VGH is used to provide a high level signal, the N clock signal lines CLK are used to provide N different clock signals, each scan driving unit 100 comprises N adjusting circuits 110 and 2N GDL circuits 120 connected in cascade, N and M are both integers greater than or equal to 1.

[0044] Wherein, the i-th GDL circuit 120 in the 2N GDL circuits 120 is connected with the i-th clock signal line CLK in the N clock signal lines CLK, the i-th GDL circuit 120 is used to output the i-th scan signal according to the clock signal provided by the i-th clock signal line CLK, i∈[1,N];

[0045] The jth GDL circuit 120 of the 2N GDL circuits 120 is connected with the ith adjusting circuit 110 of the N adjusting circuits 110 and the preset high potential signal line VGH and the ith clock signal line CLK of the N clock signal lines CLK, the ith adjusting circuit 110 is configured to adjust the clock signal provided by the ith clock signal line CLK according to the high level signal provided by the preset high potential signal line VGH, to obtain an adjusted clock signal, and the jth GDL circuit 120 is configured to output a jth scanning signal according to the adjusted clock signal provided by the ith adjusting circuit 110, the adjusted clock signal provided by the ith adjusting circuit 110 is opposite to the potential of the clock signal provided by the ith clock signal line CLK, j = i + N, j ∈ [N, 2N].

[0046] Specifically, the preset high potential signal line VGH is configured to provide a constant high level signal for the adjusting circuit 110. The preset high potential signal line VGH can be a newly added signal line, or can be the VDD_e signal line or the VDD_o signal line in the original signal line by multiplexing.

[0047] The numbers of M and N can be set according to actual needs, which are not limited in the application. In the embodiment of the application, one GDL circuit 120 corresponds to one pixel row, so the total number of GDL circuits 120 can be determined according to the resolution of the display, and the number of scanning driving units 100 required can be further determined according to the number of GDL circuits 120 in each scanning driving unit 100. For example, taking the 2160th row of pixel units P in the display panel as an example, 2160 GDL circuits 120 are required to cascade to output 2160 scanning signals, and assuming that there are 8 GDL circuits 120 in each scanning driving unit 100, a total of 270 scanning driving units 100 are required.

[0048] It should be noted that the number of GDL circuits 120 in each scan driving unit 100 can be determined based on the number of clock signal lines CLK, because the number of GDL circuits 120 in each scan driving unit 100 is twice the number of clock signal lines CLK. That is, when there are four clock signal lines CLK, the number of GDL circuits 120 in each scan driving unit 100 is eight; when there are five clock signal lines CLK, the number of GDL circuits 120 in each scan driving unit 100 is ten; when there are six clock signal lines CLK, the number of GDL circuits 120 in each scan driving unit 100 is twelve; when there are eight clock signal lines CLK, the number of GDL circuits 120 in each scan driving unit 100 is sixteen, and so on.

[0049] In the prior art, each GDL circuit 120 in the scan driver unit 100 usually needs to be set in correspondence with a clock signal line CLK, which results in a large demand for clock signal lines CLK. However, in the embodiment of the present application, since only half of the GDL circuits 120 in the scan driver unit 100 need to be set in a one-to-one correspondence with a corresponding number of clock signal lines CLK, the other half of the GDL circuits 120 obtain the clock signals required by their respective GDL circuits 120 through a corresponding number of adjustment circuits 110. Therefore, in the embodiment of the present application, the number of clock signal lines CLK can be halved. For example, when there are 8 GDL circuits 120 in the scan driver unit 100, the prior art requires 8 clock signal lines CLK to correspond thereto, such as Figure 2 As shown. Among them, the timing relationship of these 8 clock signal lines CLK is as follows Figure 3 As shown, when CLK1 is high, CLK5 is low at the corresponding time; when CLK1 is low, CLK5 is high at the corresponding time. In other words, the potential of CLK1 is exactly opposite to that of CLK5. Similarly, the potential of CLK2 is exactly opposite to that of CLK6, the potential of CLK3 is exactly opposite to that of CLK7, and the potential of CLK4 is exactly opposite to that of CLK8.

[0050] In the embodiment of the present application, only four clock signal lines CLK need to be set to correspond thereto. By setting the first four GDL circuits 120 in the scan driving unit 100 to correspond to the four clock signal lines CLK one by one, and setting the last four GDL circuits 120 to correspond to the four adjustment circuits 110 one by one, the potentials of CLK1 to CLK4 can be adjusted by the four adjustment circuits 110 to obtain CLK5 to CLK8 respectively, and then CLK5 to CLK8 are respectively given to the last four GDL circuits 120 in the scan driving unit 100 for use, as shown in FIG. Figure 4 As shown. Although Figure 4The preset high potential signal line VGH and the plurality of adjusting circuits 110 are added, but the actual occupied space is far less than the occupied space of the clock signal line CLK removed, so that the scan driving circuit provided by the embodiment of the present application can better realize the narrow frame design of the display panel.

[0051] Further, referring to Figure 5 , the i-th adjusting circuit 110 includes a first switch tube TA and a second switch tube TB;

[0052] The first end and the second end of the first switch tube TA are connected with the preset high potential signal line VGH, the third end of the first switch tube TA is connected with the first end of the j-th GDL circuit 120 and the first end of the second switch tube TB respectively, the second end of the second switch tube TB is connected with the i-th clock signal line CLK, and the third end of the second switch tube TB is connected with the first low potential signal line.

[0053] Specifically, the first switch tube TA and the second switch tube TB can both be thin film transistors (TFTs). The first low potential signal line can be used to output a VSSQ signal, i.e., a constant low potential signal.

[0054] In an embodiment, since the signal output by the preset high potential signal line VGH is a constant high potential signal VGH, when the i-th clock signal CLK(i) is low, the first switch tube TA is opened, the second switch tube TB is closed, and the third end (i.e., the N point) of the first switch tube TA is high. When the i-th clock signal CLK(i) is high, the second switch tube TB is opened, and the third end (i.e., the N point) of the first switch tube TA is pulled low to low. In this way, the third end (i.e., the N point) of the first switch tube TA obtains a clock signal opposite to the i-th clock signal CLK(i) in potential, and the clock signal opposite in potential is given to the j-th GDL circuit 120 to output the j-th scan signal. For example, assuming that N is 4, the first adjusting circuit 110 can output a clock signal CLK5 opposite to CLK1 in potential, the second adjusting circuit 110 can output a clock signal CLK6 opposite to CLK2 in potential, the third adjusting circuit 110 can output a clock signal CLK7 opposite to CLK3 in potential, and the fourth adjusting circuit 110 can output a clock signal CLK8 opposite to CLK4 in potential.

[0055] In the above manner, the original clock signal and the adjusting circuit 110 can be used to generate a new clock signal, so that the number of clock signal lines CLK required on the display panel can be reduced, and the narrow frame design of the display panel can be better realized.

[0056] Further, a ratio of a current value of the second switch tube TB in an on state to a current value of the first switch tube TA in an on state is greater than a preset threshold, and the preset threshold is greater than or equal to 5.

[0057] In an embodiment, since the signal output by the preset high potential signal line VGH is a constant high potential signal VGH, the first switch tube TA is turned on, and the N point is at a high potential. When the second switch tube TB needs to be turned on to pull down the potential of the N point, the current value of the second switch tube TB in an on state needs to be greater than the current value of the first switch tube TA in an on state, so that the N point can be pulled down from a high potential to a low level more quickly when the second switch tube TB is turned on. As an optional implementation, a switch tube with a ratio of a current value in an on state to a current value of the first switch tube TA in an on state greater than a preset threshold can be selected as the second switch tube TB. That is, the ratio of the size of the second switch tube TB to the size of the first switch tube TA needs to be greater than the preset threshold (such as 5, 6, 7, etc.), so that the high potential of the N point can be pulled down more quickly when the second switch tube TB is turned on.

[0058] Further, continuing to refer to Figure 5 , each of the 2N GDL circuits 120 includes a first node Q(n), and a pull-up control module 1201, an output module 1202, and a first pull-down control module 1203 connected to the first node Q(n);

[0059] The pull-up control module 1201 is configured to pull up the potential of the first node Q(n) to a high potential according to a received first-level carry signal.

[0060] The output module 1202 is configured to output a corresponding scan signal according to a received clock signal in a case where the potential of the first node Q(n) is pulled up to a high potential.

[0061] The first pull-down control module 1203 is configured to pull down the potential of the first node Q(n) to a low potential according to a received second-level carry signal.

[0062] In an embodiment, the pull-up control module 1201 is connected to the first node Q(n) and accesses a first-level carry signal, which can be an (n-4)th-level carry signal Carry(n-4). The pull-up control module 1201 is configured to pull up the potential of the first node Q(n) to a high potential according to the received (n-4)th-level carry signal Carry(n-4). It can be understood that for the first four GDL circuits 120, the first-level carry signal can be a start signal STV.

[0063] The first pull-down control module 1203 is also connected with the first node Q(n) and accesses a second stage transmission signal, which is an (n+4)th stage transmission signal Carry(n+4), the start signal STV and the first low potential signal VSSQ. The first pull-down control module 1203 is configured to pull down the potential of the first node Q(n) to the low potential by the first low potential signal VSSQ according to the received (n+4)th stage transmission signal Carry(n+4). The first pull-down control module 1203 is also configured to pull down the potential of the first node Q(n) according to the (n+4)th stage transmission signal Carry(n+4).

[0064] The output module 1202 is also connected with the first node Q(n). The output module 1202 can output a corresponding scan signal according to the received clock signal in the case that the potential of the first node Q(n) is pulled up to the high potential.

[0065] In this way, the output of the scan signal and the driving of the corresponding horizontal scan line can be implemented by using the pull-up control module 1201, the output module 1202 and the first pull-down control module 1203 in the GDL circuit 120.

[0066] Further, continuing to refer to Figure 5 and Figure 6 The output module 1202 includes a third switch tube T6N and a fourth switch tube T6.

[0067] In the jth GDL circuit 120, the first end of the third switch tube T6N and the first end of the fourth switch tube T6 are connected with the first node Q(n). The second end of the third switch tube T6N and the second end of the fourth switch tube T6 are commonly used as the first end of the jth GDL circuit 120 and are connected with the first end of the second switch tube TB and the third end of the first switch tube TA. The third end of the third switch tube T6N is connected with the transmission signal input end of other GDL circuits 120, for outputting the transmission signal to the transmission signal input end of other GDL circuits 120. The third end of the fourth switch tube T6 is connected with the scan line of the corresponding pixel row, for outputting the scan signal to the scan line of the corresponding pixel row.

[0068] In the i-th GDL circuit 120, the first end of the third switch tube T6N and the first end of the fourth switch tube T6 are connected with the first node Q(n), the second end of the third switch tube T6N and the second end of the fourth switch tube T6 are connected with the i-th clock signal line CLK, the third end of the third switch tube T6N is connected with the stage transmission signal input end of other GDL circuit 120, for outputting the stage transmission signal to the stage transmission signal input end of other GDL circuit 120, and the third end of the fourth switch tube T6 is connected with the scan line of the corresponding pixel row, for outputting the scan signal to the scan line of the corresponding pixel row.

[0069] It should be noted that for the first N GDL circuits 120 in the scan driving unit 100, the second end of the third switch tube T6N and the second end of the fourth switch tube T6 in the output unit as the clock signal input end are directly connected with the corresponding clock signal line CLK; and for the last N GDL circuits 120 in the scan driving unit 100, the second end of the third switch tube T6N and the second end of the fourth switch tube T6 in the output unit as the clock signal input end are connected with the N point in the corresponding adjusting circuit 110. For example, in the scan driving circuit of 8 clock signals shown in Figure 4 The first 4 GDL circuits 120 in each scan driving unit 100 are connected with 4 clock signal lines CLK one by one, for receiving clock signals CLK1 to CLK4. Figure 6 That is, the connection diagram of the first and second GDL circuits in each scan driving unit. The last 4 GDL circuits in each scan driving unit are connected with 4 clock signal lines CLK one by one through the adjusting circuit, for receiving clock signals CLK5 to CLK6. Figure 5 That is, the connection diagram of the fifth and sixth GDL circuits in each scan driving unit and the adjusting circuit.

[0070] Further, continuing to refer to Figure 5 and Figure 6 Each GDL circuit 120 of the 2N GDL circuits 120 further comprises a second node Qb(n), and a pull-down module 1204 and a second pull-down control module 1205 connected with the second node Qb(n).

[0071] The second pull-down control module 1205 is configured to pull up the potential of the second node Qb(n) to a high potential according to the received power voltage signal.

[0072] The pull-down module 1204 is configured to pull down the potential of the stage transmission signal and the scan signal output by the output module 1202 in the case that the potential of the second node Qb(n) is pulled up to a high potential.

[0073] In an embodiment, the second pull-down control module 1205 is connected with the second node Qb(n) and accesses the power voltage signal VDD_o, and the second pull-down control module 1205 is configured to pull up the potential of the second node Qb(n) to the high potential. The pull-down module 1204 is also connected with the second node Qb(n) and accesses the first low potential signal VSSQ and the second low potential signal VSSG, and is configured to pull down the potential of the output end of the output module 1202 according to the first low potential signal VSSQ and the second low potential signal VSSG when the potential of the second node Qb(n) is the high potential, that is, to pull down the stage transmission signal and the scan signal output by the output module 1202, so as to control the potential of the stage transmission signal and the scan signal output by the output module 1202.

[0074] Further, each GDL circuit 120 of the 2N GDL circuits 120 further comprises a pull-down maintenance module 1206.

[0075] The pull-down maintenance module 1206 is connected with the second node Qb(n), and the pull-down maintenance module 1206 is configured to maintain the potential of the second node Qb(n) according to the received first stage transmission signal.

[0076] In an embodiment, the GDL circuit 120 can further comprise a pull-down maintenance module 1206, and the pull-down maintenance module 1206 can maintain the potential of the second node Qb(n) according to the received first stage transmission signal (that is, the n-4 stage transmission signal Carry(n-4)) and the first low potential signal VSSQ, so as to control the potential of the stage transmission signal and the scan signal output by the output module 1202.

[0077] Referring to Figure 7 , Figure 7 A structure schematic diagram of an array substrate is provided for an embodiment of the present application. As shown in the figure, the array substrate comprises the aforementioned scan driving circuit 710 and 2N*M scan lines 720, the 2N*M GDL circuits in the scan driving circuit 710 are connected with the 2N*M scan lines 720 in one-to-one correspondence, and each scan line 720 is connected with a plurality of pixel units P. Figure 7

[0078] Referring to Figure 8 , Figure 8 A structure schematic diagram of a display panel is provided for an embodiment of the present application. As shown in the figure, the display panel comprises an opposite substrate 810, a liquid crystal layer 820, and the aforementioned array substrate 830, and the liquid crystal layer 820 is located between the opposite substrate 810 and the array substrate 830. Figure 8

[0079] ​​The array substrate 830 can be the array substrate in the above embodiments, and the opposite substrate 810 can be a color film substrate. Since the display panel includes the array substrate described above, and the array substrate includes the scan driving circuit in the above embodiments, the display panel can better achieve a narrow frame design.

[0080] In addition, referring to Figure 9 , Figure 9 A structural schematic diagram of a display device provided by an embodiment of the present application is shown in FIG. 9. As shown in FIG. 9, the display device includes a housing 910 and the aforementioned display panel 920, and the display panel 920 is arranged on the housing 910. Figure 9

[0081] It should be noted that the display device can be a display screen, or a mobile phone, computer, television, wearable device, etc. provided with a display screen, and the present application is not limited in this regard.

[0082] The device embodiments described above are merely schematic, wherein the units illustrated as separate components can or can not be physically separated, and the components illustrated as units can or can not be physical units, i.e., they can be located in one place, or distributed on multiple network units. According to actual needs, some or all of the modules can be selected to achieve the purpose of the present embodiment.

[0083] From the above description of the embodiments, those skilled in the art can clearly understand that the embodiments can be implemented by means of software plus a general hardware platform, and of course, can also be implemented by hardware. Based on such understanding, the above technical solutions, essentially or in terms of related art, can be embodied in the form of a software product, and the computer software product can be stored in a computer readable storage medium, such as a ROM / RAM, magnetic disk, optical disk, etc., and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0084] ​It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises", "comprising", "includes", "including" and "has" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order

[0085] The above description is merely that of the specific embodiments of the application and as such is not to be taken in a limiting sense. Various modifications and alterations of the embodiments described herein will become apparent to those skilled in the art from the foregoing description, which does not limit the generality presented. It is the intention that all such modifications and alterations be considered equaliy by the spirit and scope of this application. It is therefore intended to cover in the appended claims all such changes and alterations that come within the scope of this application.

Claims

1. A scan driving circuit, characterized in that: The scan driving circuit includes: a preset high-potential signal line, N clock signal lines, and M cascaded scan driving units, wherein the preset high-potential signal line is used to provide a high-level signal, and the N clock signal lines are used to provide N different clock signals. Each of the scan driving units includes N adjustment circuits and 2N cascaded gate driving circuits, where N and M are both integers greater than or equal to 1; The i-th gate driving circuit among the 2N gate driving circuits is connected to the i-th clock signal line among the N clock signal lines, and the i-th gate driving circuit is used to output the i-th scanning signal according to the clock signal provided by the i-th clock signal line, i∈[1,N ]; The j-th gate driving circuit among the 2N gate driving circuits is connected to the preset high-potential signal line and the i-th clock signal line among the N clock signal lines through the i-th regulating circuit among the N regulating circuits, the i-th regulating circuit is used to adjust the clock signal provided by the i-th clock signal line according to the high-level signal provided by the preset high-potential signal line to obtain an adjusted clock signal, and the j-th gate driving circuit is used to output the j-th scanning signal according to the adjusted clock signal provided by the i-th regulating circuit, the adjusted clock signal provided by the i-th regulating circuit having a potential opposite to that of the clock signal provided by the i-th clock signal line, j=i+N, j∈[N,2N]; Wherein, the i-th regulating circuit includes a first switching tube and a second switching tube; Among them, the first end and the second end of the first switching tube are both connected to the preset high-potential signal line, the third end of the first switching tube is respectively connected to the first end of the j-th gate drive circuit and the first end of the second switching tube, the second end of the second switching tube is connected to the i-th clock signal line, and the third end of the second switching tube is connected to the first low-potential signal line.

2. The scan driving circuit according to claim 1, wherein: A ratio of a current value of the second switch tube in the on state to a current value of the first switch tube in the on state is greater than a preset threshold, and the preset threshold is greater than or equal to 5.

3. The scanning driving circuit according to claim 1, wherein: Each gate driving circuit of the 2N gate driving circuits includes a first node, and a pull-up control module, an output module and a first pull-down control module connected to the first node; The pull-up control module is configured to pull up the potential of the first node to a high potential according to the received first-level transmission signal; The output module is configured to output a corresponding scanning signal according to the received clock signal when the potential of the first node is pulled up to a high potential; The first pull-down control module is configured to pull down the potential of the first node to a low potential according to the received second-stage transmission signal.

4. The scanning driving circuit according to claim 3, wherein: The output module includes a third switching tube and a fourth switching tube; In the j-th gate driving circuit, the first end of the third switching transistor and the first end of the fourth switching transistor are both connected to the first node; the second end of the third switching transistor and the second end of the fourth switching transistor jointly serve as the first end of the j-th gate driving circuit, and are connected to the first end of the second switching transistor and the third end of the first switching transistor; the third end of the third switching transistor is connected to the level transmission signal input end of other gate driving circuits, and is used to output the level transmission signal to the level transmission signal input end of the other gate driving circuits; the third end of the fourth switching transistor is connected to the scan line of the corresponding pixel row, and is used to output the scan signal to the scan line of the corresponding pixel row; In the i-th gate drive circuit, the first end of the third switch tube and the first end of the fourth switch tube are both connected to the first node, the second end of the third switch tube and the second end of the fourth switch tube are both connected to the i-th clock signal line, the third end of the third switch tube is connected to the level transmission signal input end of other gate drive circuits, and is used to output the level transmission signal to the level transmission signal input end of other gate drive circuits, and the third end of the fourth switch tube is connected to the scan line of the corresponding pixel row, and is used to output the scan signal to the scan line of the corresponding pixel row.

5. The scan driving circuit according to claim 3, wherein: Each gate driving circuit of the 2N gate driving circuits further includes: a second node, and a pull-down module and a second pull-down control module connected to the second node; The second pull-down control module is configured to pull up the potential of the second node to a high potential according to the received power supply voltage signal; The pull-down module is used to pull down the potentials of the stage transfer signal and the scan signal output by the output module when the potential of the second node is pulled up to a high potential.

6. The scan driving circuit according to claim 5, wherein: Each gate driving circuit of the 2N gate driving circuits further includes: a pull-down maintaining module; The pull-down maintaining module is connected to the second node, and is used to maintain the potential of the second node according to the received first-level transmission signal.

7. An array substrate, characterized in that: The array substrate comprises: a scan driving circuit according to any one of claims 1 to 6 and 2N*M scan lines, wherein the 2N*M gate driving circuits in the scan driving circuit are connected to the 2N*M scan lines in a one-to-one correspondence, and each scan line is connected to a plurality of pixel units.

8. A display panel, characterized in that: The display panel includes an opposing substrate, a liquid crystal layer, and the array substrate according to claim 7 , wherein the liquid crystal layer is located between the opposing substrate and the array substrate.

9. A display device, characterized in that: The display device includes a housing and the display panel according to claim 8, wherein the display panel is disposed on the housing.

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