A missile-borne solid-state power conversion module and a method of operating the same

Abstract

The application discloses a missile-borne solid-state power conversion module and a running method thereof, and uses solid-state power devices and ideal diodes to realize power conversion control, and simultaneously adopts hardware logic circuit and processor control output to realize redundant processing of power conversion control instructions, so that the reliability of power conversion control is ensured. In addition, the processor circuit cooperates with sufficient current and voltage detection and conditioning circuits, realizes comprehensive and effective monitoring of power conversion states, and realizes timely reporting of power conversion monitoring states through a high-speed RS422 communication network.

Description

Technical Field

[0001] This invention relates to the field of missile-borne equipment technology, specifically to a missile-borne solid-state power conversion module and its operation method. Background Technology

[0002] Because the airborne power source (such as a thermal battery) on the missile-borne equipment is a one-time power source, it will continuously release the energy it stores after activation. Therefore, during the production and testing process before takeoff from the ground, the airborne power source on the missile-borne equipment will not be activated, and the missile-borne equipment will be powered by ground power. However, after preparation for takeoff or ignition, the airborne power source on the missile-borne equipment will be activated, and the missile-borne equipment will use a power conversion module to convert the ground power supply to the airborne power supply.

[0003] For the power transfer control of missile-borne equipment, the power transfer module of traditional missile-borne equipment generally uses electromechanical switches such as relays and contactors in conjunction with power anti-reverse diodes. In addition, the necessary functional modules for power transfer status monitoring inevitably lead to inherent defects such as excessive size, excessive weight, low resistance to vibration and shock, and low overall reliability. Summary of the Invention

[0004] The present invention aims to solve the problems of large size and poor reliability of existing airborne power transfer modules, and provides an airborne solid-state power transfer module and its operation method.

[0005] To solve the above problems, the present invention is achieved through the following technical solution:

[0006] A missile-borne solid-state power conversion module comprises a VH solid-state power circuit, a VH voltage and current detection and conditioning circuit, a VH anti-reverse circuit, a VL solid-state power circuit, a VL voltage and current detection and conditioning circuit, a VL anti-reverse circuit, a servo motor voltage and current detection and conditioning circuit, an ignition voltage and current detection and conditioning circuit, a power conversion signal isolation detection circuit, a power conversion feedback signal conditioning circuit, a control logic processing circuit, an isolation drive circuit, a processor circuit, an RS422 isolation interface circuit, and a filter isolation power supply circuit.

[0007] The positive terminal of the high-voltage battery is connected to the VHIN input terminal of the VH solid-state power circuit. The S-VH output terminal of the VH solid-state power circuit is connected to the S-VH input terminal of the VH voltage and current detection and conditioning circuit, and the high-voltage power supply ground is connected to the VHGND input terminal of the VH voltage and current detection and conditioning circuit. The S'-VH output terminal of the VH voltage and current detection and conditioning circuit is connected to the S'-VH input terminal of the VH reverse protection circuit, and the VHOUT output terminal of the VH reverse protection circuit is connected to the positive terminal of the ground high-voltage power supply. The ADV-VH and ADI-VH output terminals of the VH solid-state power circuit are connected to the two AD ports of the processor circuit, respectively.

[0008] The positive terminal of the low-voltage battery is connected to the VLIN input of the VL solid-state power circuit. The S-VL output of the VL solid-state power circuit is connected to the S-VL input of the VL voltage and current detection and conditioning circuit, and the low-voltage power supply ground is connected to the VLGND input of the VL voltage and current detection and conditioning circuit. The S'-VL output of the VL voltage and current detection and conditioning circuit is connected to the S'-VL input of the VL reverse protection circuit, and the VLOUT output of the VL reverse protection circuit is connected to the positive terminal of the ground low-voltage power supply. The ADV-VL and ADI-VL outputs of the VL solid-state power circuit are connected to the two AD ports of the processor circuit, respectively.

[0009] The positive terminal of the first servo power supply is connected to the VDJ1IN input of the servo voltage and current detection and conditioning circuit. The positive terminal of the second servo power supply is connected to the VDJ2IN input of the servo voltage and current detection and conditioning circuit. The servo power ground is connected to the VDJGND input of the servo voltage and current detection and conditioning circuit. The VDJ1OUT output of the servo voltage and current detection and conditioning circuit is connected to the positive terminal of the first servo load. The VDJ2OUT output of the servo voltage and current detection and conditioning circuit is connected to the positive terminal of the second servo load. The ADV-DJ1, ADV-DJ2, ADI-DJ1, and ADI-DJ2 outputs of the servo voltage and current detection and conditioning circuit are respectively connected to the four AD ports of the processor circuit.

[0010] The ignition current input terminal is connected to the VDHIN input terminal of the ignition voltage and current detection and conditioning circuit, and the ignition power ground is connected to the VDHGND input terminal of the ignition voltage and current detection and conditioning circuit. The VDHOUT output terminal of the ignition voltage and current detection and conditioning circuit is connected to the ignition current output terminal. The ADV-DH and ADI-DH output terminals of the ignition voltage and current detection and conditioning circuit are respectively connected to the two AD ports of the processor circuit.

[0011] The power transfer control signal is connected to the XZD input of the power transfer signal isolation detection circuit, the power transfer release signal is connected to the XJC input of the power transfer signal isolation detection circuit, and the low-voltage power ground is connected to the VLGND input of the power transfer signal isolation detection circuit. The OD-ZD and OD-JC outputs of the power transfer signal isolation detection circuit are respectively connected to two I / O ports of the processor circuit.

[0012] The S-VL output of the VL solid-state power circuit is connected to the S-VL input of the power feedback signal conditioning circuit, and the low-voltage power ground is connected to the VLGND input of the power feedback signal conditioning circuit. The A output of the power feedback signal conditioning circuit is connected to the A input of the external monitoring center, the B output of the power feedback signal conditioning circuit is connected to the B input of the external monitoring center, and the OD-FK output of the power feedback signal conditioning circuit is connected to an I / O port of the processor circuit.

[0013] The ZD1, ZD2, JC1, and JC2 inputs of the control logic processing circuit are connected to the four I / O ports of the processor circuit, respectively. The OD-ZD and OD-JC outputs of the electrical signal isolation detection circuit are connected to the OD-ZD and OD-JC inputs of the control logic processing circuit, respectively. The DRI output of the control logic processing circuit is connected to the DRI input of the isolation drive circuit.

[0014] The S-VH and DRI-VH outputs of the isolation drive circuit are connected to the S-VH and DRI-VH inputs of the VH solid-state power circuit, respectively. The S-VL and DRI-VL outputs of the isolation drive circuit are connected to the S-VL and DRI-VL inputs of the VL solid-state power circuit, respectively.

[0015] The SCI port of the processor circuit is connected to the TXD and RXD communication terminals of the RS422 isolation interface. The 422-A and 422-B receive signal terminals, the 422-Y and 422-Z transmit signal terminals, and the 422-GND shielding ground terminal of the RS422 isolation interface are connected to an external RS422 bus network.

[0016] The positive terminal of the low-voltage ground power supply is connected to the VLOUT input terminal of the filter isolation power supply circuit, and the low-voltage ground is connected to the VLGND input terminal of the filter isolation power supply circuit. The output terminal of the filter isolation power supply circuit is connected to the internal operating power supply.

[0017] The aforementioned control logic processing circuit consists of a first processor control signal confirmation circuit, a first delay filter circuit, a first hysteresis comparator circuit, a second processor control signal confirmation circuit, a second delay filter circuit, a comparator circuit with a second hysteresis, a reference voltage circuit, common cathode diodes D1 to D2, a reset priority RS flip-flop circuit, and a control signal power amplifier circuit.

[0018] The input terminals of the first processor control signal confirmation circuit form the ZD1 and ZD2 input terminals of the control logic processing circuit. The input terminal of the first delay filter circuit forms the OD-ZD input terminal of the control logic processing circuit. The output terminal of the first delay filter circuit is connected to one input terminal of the first hysteresis comparator circuit. The input terminals of the second processor control signal confirmation circuit form the JC1 and JC2 input terminals of the control logic processing circuit. The input terminal of the second delay filter circuit forms the OD-JC input terminal of the control logic processing circuit. The output terminal of the second delay filter circuit is connected to one input terminal of the second hysteresis comparator circuit. The output terminal of the reference voltage circuit is connected to the other input terminal of the first and second hysteresis comparators circuits. The output terminals of the first processor control signal confirmation circuit and the first hysteresis comparator circuit are respectively connected to the two anodes of a common cathode diode D1, and the cathode of the common cathode diode D1 is connected to one input terminal of a reset-priority RS flip-flop circuit. The output terminals of the second processor control signal confirmation circuit and the second hysteresis comparator circuit are respectively connected to the two anodes of a common cathode diode D2, and the cathode of the common cathode diode D2 is connected to the other input terminal of a reset-priority RS flip-flop circuit. The output of the reset priority RS flip-flop circuit is connected to the input of the control signal power amplifier circuit, and the output of the control signal power amplifier circuit forms the DRI output of the control logic processing circuit.

[0019] The aforementioned isolation drive circuit consists of a high-voltage high-frequency oscillation circuit, a high-voltage transformer, a high-voltage rectifier, filter, limiting and release circuit, a high-voltage drive signal distribution circuit, a low-voltage high-frequency oscillation circuit, a low-voltage transformer, a low-voltage rectifier, filter, limiting and release circuit, and a low-voltage drive signal distribution circuit.

[0020] The input terminals of the high-voltage high-frequency oscillation circuit and the low-voltage high-frequency oscillation circuit together form the DRI input terminal of the isolated drive circuit. The output terminal of the high-voltage high-frequency oscillation circuit is connected to the primary winding of the high-voltage transformer. The secondary winding of the high-voltage transformer is connected to the input terminal of the high-voltage rectification, filtering, limiting, and release circuit. The output terminal of the high-voltage rectification, filtering, limiting, and release circuit is connected to the input terminal of the high-voltage drive signal distribution circuit. The output terminal of the high-voltage drive signal distribution circuit forms the S-VH output terminal and the DRI-VH output terminal of the isolated drive circuit. The output terminal of the low-voltage high-frequency oscillation circuit is connected to the primary winding of the low-voltage transformer. The secondary winding of the low-voltage transformer is connected to the input terminal of the low-voltage rectification, filtering, limiting, and release circuit. The output terminal of the low-voltage rectification, filtering, limiting, and release circuit is connected to the input terminal of the low-voltage drive signal distribution circuit. The output terminal of the low-voltage drive signal distribution circuit forms the S-VL output terminal and the DRI-VL output terminal of the isolated drive circuit.

[0021] Both the high-voltage and low-voltage transformers mentioned above are on-board transformers. These on-board transformers adopt a multi-layer printed circuit board format, in which coils with fewer turns are placed in the middle layer, and coils with more turns are arranged in adjacent layers above and below.

[0022] The operation method of the aforementioned missile-borne solid-state power conversion module is characterized by the following steps:

[0023] Step 1: The power transfer signal isolation detection circuit obtains the corresponding power transfer control isolation detection signal OD-ZD and power transfer release isolation detection signal OD-JC based on the power transfer control signal XZD and power transfer release signal XJC sent from the external monitoring center, and sends them to the processor circuit and control logic processing circuit.

[0024] Step 2: The processor circuit detects the validity of the power transfer control signal XZD based on the power transfer control isolation detection signal OD-ZD, and obtains the first power transfer control signal ZD1 and the second power transfer control signal ZD2 according to the detection result. The processor circuit detects the validity of the power transfer release signal XJC based on the power transfer release isolation detection signal OD-JC, and obtains the first power transfer release signal JC1 and the second power transfer release signal JC2 according to the detection result, and sends them to the control logic processing circuit.

[0025] Step 3: The control logic processing circuit first performs a logical XOR operation on the first power transfer control signal ZD1 and the second power transfer control signal ZD2 to obtain the power transfer control XOR result. Then, it performs a logical OR operation on the power transfer control XOR result and the power transfer control isolation detection signal OD-ZD to obtain the power transfer control drive signal DRI. The control logic processing circuit first performs a logical XOR operation on the first power transfer release signal JC1 and the second power transfer release signal JC2 to obtain the power transfer release XOR result. Then, it performs a logical OR operation on the power transfer release isolation detection signal OD-JC to obtain the power transfer release drive signal DRI.

[0026] Step 4: The isolation drive circuit first processes the drive signal DRI to obtain the high-voltage solid-state power transistor drive signal DRI-VH and its reference signal S-VH, as well as the low-voltage solid-state power transistor drive signal DRI-VL and its reference signal S-VL. Then, based on the number of high-voltage solid-state power transistors in the VH solid-state power circuit, the high-voltage solid-state power transistor drive signal DRI-VH is allocated and sent to the VH solid-state power circuit along with its reference signal S-VH. Simultaneously, based on the number of low-voltage solid-state power transistors in the VL solid-state power circuit, the low-voltage solid-state power transistor drive signal DRI-VL is allocated and sent to the VL solid-state power circuit along with its reference signal S-VL.

[0027] Step 5: The operating processes of the VH solid-state power circuit and the VL solid-state power circuit are as follows:

[0028] The VH solid-state power circuit turns on when the voltage of the high-voltage solid-state power transistor drive signal DRI-VH relative to its reference signal S-VH exceeds the gate threshold voltage of the high-voltage solid-state power transistor in the VH solid-state power circuit. The VH solid-state power circuit turns off when the voltage of the high-voltage solid-state power transistor drive signal DRI-VH relative to its reference signal S-VH is 0V.

[0029] The VL solid-state power circuit turns on when the voltage of the low-voltage solid-state power transistor drive signal DRI-VL relative to its reference signal S-VL exceeds the gate threshold voltage of the low-voltage solid-state power transistor in the VL solid-state power circuit. The VL solid-state power circuit turns off when the voltage of the low-voltage solid-state power transistor drive signal DRI-VL relative to its reference signal S-VL is 0V.

[0030] Step 6: The working processes of the VH voltage and current detection and conditioning circuit and the VL voltage and current detection and conditioning circuit are as follows:

[0031] When the VH solid-state power circuit is turned on, the VH voltage and current detection and conditioning circuit conditions the signal output by the VH solid-state power circuit before sending it to the VH reverse protection circuit. Simultaneously, the VH voltage and current detection and conditioning circuit acquires the high-voltage signal ADV-VH and the high-voltage current signal ADI-VH, and sends them to the processor circuit. The processor circuit then samples the high-voltage signal ADV-VH and the high-voltage current signal ADI-VH, and calculates the VH voltage and current values.

[0032] When the VL solid-state power circuit is turned on, the VL voltage and current detection and conditioning circuit conditions the signal output by the VL solid-state power circuit before sending it to the VL reverse protection circuit. Simultaneously, the VL voltage and current detection and conditioning circuit acquires the low-voltage signal ADV-VL and the low-voltage current signal ADI-VL, and sends them to the processor circuit. The processor circuit completes the sampling of the low-voltage signal ADV-VL and the low-voltage current signal ADI-VL, as well as the calculation of the VL voltage and current values.

[0033] Step 7: The working processes of the VH anti-reverse circuit and the VL anti-reverse circuit are as follows:

[0034] The VH anti-reverse circuit prevents current backflow when the high-voltage battery voltage is lower than the ground high-voltage power supply voltage, and seamlessly switches the downstream high-voltage power supply to the high-voltage battery when the high-voltage battery voltage is higher than the ground high-voltage power supply voltage.

[0035] The VL anti-reverse circuit prevents current backflow when the low-voltage battery voltage is lower than the ground low-voltage power supply voltage, and seamlessly switches the subsequent low-voltage power supply to the low-voltage battery when the low-voltage battery voltage is higher than the ground low-voltage power supply voltage.

[0036] Step 8: The power transfer feedback signal conditioning circuit detects the actual on / off state of the VL solid-state power circuit, sends power transfer feedback signals A and B to the external monitoring center, and sends a feedback signal OD-FK to the processor circuit. The processor circuit detects the feedback signal OD-FK and updates the corresponding status bit in memory with the detection result.

[0037] Step 9: The filter isolation power supply circuit is powered by a ground low-voltage power supply. After the low-voltage power conversion is completed, the internal working power supply of the missile equipment is switched to low-voltage battery power supply.

[0038] Step 10: The servo voltage and current detection and conditioning circuit conditions the power supply of the first servo and sends it to the load of the first servo in the missile-borne equipment. It also conditions the power supply of the second servo and sends it to the load of the second servo in the missile-borne equipment. Simultaneously, the servo voltage and current detection and conditioning circuit collects the voltage signal ADV-DJ1 of the first servo, the voltage signal ADV-DJ2 of the second servo, the current signal ADI-DJ1 of the first servo, and the current signal ADI-DJ2 of the second servo, and sends them to the processor circuit. The processor circuit completes the sampling of the voltage signal ADV-DJ1 of the first servo, the voltage signal ADV-DJ2 of the second servo, the current signal ADI-DJ1 of the first servo, and the current signal ADI-DJ2 of the second servo, as well as the calculation of the voltage and current values ​​of DJ1 and DJ2.

[0039] Step 11: The ignition voltage and current detection and conditioning circuit conditions the ignition power supply and sends it to the ignition timing control device of the onboard equipment. Simultaneously, the ignition voltage and current detection and conditioning circuit acquires the ignition voltage signal ADV-DH and the ignition current signal ADI-DH and sends them to the processor circuit. The processor circuit completes the sampling of the ignition voltage signal ADV-DH and the ignition current signal ADI-DH, as well as the calculation of the DH voltage and current values.

[0040] Step 12: The RS422 isolation interface circuit connects the processor circuit's SCI port to the external RS422 network and enables communication with the external monitoring center according to the communication protocol.

[0041] The specific process of step 2 is as follows:

[0042] Step 2.1: The processor circuit periodically scans the power transfer control isolation detection signal OD-ZD to obtain its level status. If OD-ZD is high, the high-level count value is incremented by 1. Otherwise, the high-level count value is decremented by 2.

[0043] Step 2.2: The processor circuit judges the high-level count value of the power transfer control isolation detection signal OD-ZD. If it exceeds the set threshold, it is considered that a power transfer control command needs to be executed, and the processor circuit outputs the first power transfer control signal ZD1 as high and the second power transfer control signal ZD2 as low. Otherwise, the processor circuit outputs both the first power transfer control signal ZD1 and the second power transfer control signal ZD2 as low.

[0044] Step 2.3: The processor circuit periodically scans the power-off isolation release detection signal OD-JC to obtain its level status. If OD-JC is high, the high-level count is incremented by 1. Otherwise, the high-level count is decremented by 2.

[0045] Step 2.4: The processor circuit judges the high-level count value of the power-off isolation detection signal OD-JC. If it exceeds the set threshold, it is considered that the power-off release command needs to be executed, and the processor circuit outputs the first power-off release signal JC1 as high and the second power-off release signal JC2 as low. Otherwise, the processor circuit outputs both the first power-off release signal JC1 and the second power-off release signal JC2 as low.

[0046] The processor circuit adopts an embedded foreground and background program architecture, where the foreground consists of a timer interrupt program and an SCI receive interrupt program, and the background is the main program.

[0047] After a normal processor circuit reset, its program pointer points to the main program. The main program consists of a system initialization section and a loop section. The system initialization section runs only once, mainly completing the hardware self-test of the onboard solid-state power conversion module and the initialization of various peripherals of the processor circuit, including timer initialization and SCI communication initialization. The loop section loops infinitely before the processor circuit resets, polling and processing system tasks.

[0048] When the main program initializes the system, it sets a timer to trigger a timer interrupt at a set time T. The interrupt handling system of the processor circuit responds to the timer interrupt and enters the timer interrupt routine.

[0049] When the main program initializes the system, it performs SCI communication according to the communication protocol requirements and enables the receive interrupt. After receiving data, the processor circuit interrupts the system response to the receive interrupt and enters the SCI receive interrupt routine.

[0050] The main program processes system tasks through polling as follows:

[0051] Step 1: The processor circuit scans the power transfer control isolation detection signal OD-ZD output from the power transfer signal isolation detection circuit, the power transfer release isolation detection signal OD-JC output from the OD-JC output, and the feedback signal OD-FK output from the OD-FK output of the power transfer feedback signal conditioning circuit. After a specified duration, it confirms the validity of the corresponding instruction or state and stores it in memory for later use. Simultaneously, it reads memory data according to the reporting data frame format required by the missile host instruction, organizes it into a complete data frame for later use, and accumulates the communication duration.

[0052] Step 2: The processor circuit sets a counter for the reported bytes of a data frame. The counter increments by 1 for each reported byte. After the entire data frame is reported successfully (i.e., the checksum byte at the end of the frame is sent), the counter reaches its maximum value and is reset to zero when the onboard host command is successfully received again after an SCI receive interrupt. If a reporting failure occurs during the data frame reporting process, the communication duration is incremented.

[0053] Step 3: The processor circuit determines whether SCI communication is abnormal based on the accumulated communication duration: if it exceeds the set threshold, it is considered to be in a communication abnormal state and set to a communication abnormal state. Otherwise, the communication abnormal state is cleared.

[0054] The process of the timer interrupt routine is as follows:

[0055] Step 1: The processor circuit clears the interrupt flag and enables the next timer interrupt.

[0056] Step 2: The processor circuit samples the ignition current signal ADI-DH and calculates the DH current value.

[0057] Step 3: The processor circuit increments the processing stage identifier "step" and performs overflow prevention.

[0058] Step 4: The processor circuit performs task processing for each stage according to the step identifier value, including sampling and calculating the VL voltage value of the low voltage signal ADV-VL, sampling and calculating the VL current value of the low voltage signal ADI-VL, sampling and calculating the VH voltage value of the high voltage signal ADV-VH, sampling and calculating the VH current value of the high voltage signal ADI-VH, sampling and calculating the DJ1 voltage value of the first servo's voltage signal ADV-DJ1, sampling and calculating the DJ2 voltage value of the second servo's voltage signal ADV-DJ2, sampling and calculating the DJ2 current value of the second servo's current signal ADI-DJ2, sampling and calculating the DH voltage value of the ignition voltage signal ADV-DH, and main program time base processing.

[0059] The SCI receive interrupt procedure is as follows:

[0060] Step 1: The processor circuit clears the interrupt flag to enable the next SCI receive interrupt.

[0061] Step 2: The processor circuit determines the meaning of the received characters according to the communication protocol and processes them accordingly. All communication is initiated by the onboard host or the debugging host, and responded by the onboard solid-state power converter module. The onboard host instruction initiated by the onboard host is the query instruction during normal operation, and the debugging host instruction initiated by the debugging host is the debugging instruction during the production testing process.

[0062] Compared with the prior art, the present invention has the following characteristics:

[0063] 1. Using solid-state power switches for power switching control effectively reduces the product's size and weight, while improving the system's resistance to vibration and shock. Simultaneously, the use of ideal diodes for reverse polarity protection significantly reduces power consumption, further reducing product size, weight, and temperature rise, while also improving the system's resistance to vibration and shock and its reliability.

[0064] 2. The power supply after the low-voltage battery is converted directly drives the power conversion feedback signal circuit, and at the same time provides processor recognition and execution of power conversion control instructions and hardware logic circuit recognition and execution, ensuring that the core power conversion control and status feedback functions of the product work normally when the processor fails, thus improving the reliability of power conversion control.

[0065] 3. Voltage and current isolation sampling is achieved by using various voltage and current detection and conditioning circuits (including Hall sensors), command isolation is achieved by using power conversion signal isolation detection circuits (including opto-MOS relays) and power conversion feedback signal conditioning circuits (including optocouplers), and solid-state switch drive signal isolation is achieved by using isolation drive circuits (including transformers). This effectively realizes the isolation between the internal and external parts of the product, and between the control circuit and the power circuit, and effectively reduces the size and weight of the product, and improves the reliability of the product.

[0066] 4. Using high-speed RS422 point-to-point communication and a high-speed voltage and current sampling system, along with a set communication protocol, it comprehensively meets the requirements for voltage and current status acquisition and monitoring of the missile's low-voltage power supply, high-voltage power supply, servo power supply, and ignition power supply. In particular, it can fully realize the effective monitoring of the current status of short-term (millisecond-level) ignition operations. Attached Figure Description

[0067] Figure 1 This is a schematic diagram of the principle of the missile-borne solid-state power conversion module of the present invention;

[0068] Figure 2 This is a block diagram of the switching feedback signal conditioning circuit of the present invention;

[0069] Figure 3 This is an example of an implementation of the current feedback signal conditioning circuit of the present invention;

[0070] Figure 4 This is a block diagram of the control logic processing circuit of the present invention;

[0071] Figure 5 This is an implementation example of the control logic processing circuit of the present invention;

[0072] Figure 6 This is a block diagram of the isolation drive circuit of the present invention;

[0073] Figure 7 This is an example of an implementation of the isolation drive circuit of the present invention;

[0074] Figure 8 The recommended shape for the onboard transformer coil in this invention;

[0075] Figure 9 This is the main program flowchart of the processor circuit of the present invention;

[0076] Figure 10 This is a flowchart of the timer interrupt handling procedure of the present invention;

[0077] Figure 11 This is a flowchart of the SCI receive interrupt handling procedure of the present invention. Detailed Implementation

[0078] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0079] See Figure 1 A missile-borne solid-state power conversion module comprises a VH solid-state power circuit, a VH voltage and current detection and conditioning circuit, a VH anti-reverse circuit, a VL solid-state power circuit, a VL voltage and current detection and conditioning circuit, a VL anti-reverse circuit, a servo motor voltage and current detection and conditioning circuit, an ignition voltage and current detection and conditioning circuit, a power conversion signal isolation detection circuit, a power conversion feedback signal conditioning circuit, a control logic processing circuit, an isolation drive circuit, a processor circuit, an RS422 isolation interface circuit, and a filter isolation power supply circuit.

[0080] The VH solid-state power circuit, VH voltage and current detection and conditioning circuit, and VH anti-reverse circuit are connected in series to form the VH power conversion circuit, used for power conversion control between the high-voltage battery and the ground high-voltage power supply, enabling power supply to the missile's onboard high-voltage equipment, and simultaneously monitoring the voltage and current of the high-voltage battery. The VL solid-state power circuit, VL voltage and current detection and conditioning circuit, and VL anti-reverse circuit are connected in series to form the VL power conversion circuit, used for power conversion control between the low-voltage battery and the ground low-voltage power supply, enabling power supply to the missile's onboard low-voltage equipment, and simultaneously monitoring the voltage and current of the low-voltage battery. The servo motor voltage and current detection and conditioning circuit is used to monitor the operating voltage and current of two servo motors. The ignition voltage and current detection and conditioning circuit is used to monitor the voltage and current of the ignition circuit. The power conversion signal isolation detection circuit, control logic processing circuit, and isolation drive circuit are used to isolate and detect power conversion control and power conversion release signals, and output corresponding drive signals DRI-VH and DRI-VL to control the on / off state of the VH and VL power conversion circuits. The power conversion feedback signal conditioning circuit conditions the low-voltage power conversion result and outputs it to notify the monitoring center of the conversion result. The RS422 isolation interface circuit is used to connect the processor circuit to the external RS422 network, providing an external communication interface. The filter isolation power supply circuit is used to stably convert the low-voltage power supply into the operating power supply for the various internal modules.

[0081] The positive terminal of the high-voltage battery is connected to the VHIN input terminal of the VH solid-state power circuit. The S-VH output terminal of the VH solid-state power circuit is connected to the S-VH input terminal of the VH voltage and current detection and conditioning circuit, and the high-voltage power supply ground is connected to the VHGND input terminal of the VH voltage and current detection and conditioning circuit. The S'-VH output terminal of the VH voltage and current detection and conditioning circuit is connected to the S'-VH input terminal of the VH reverse protection circuit, and the VHOUT output terminal of the VH reverse protection circuit is connected to the positive terminal of the ground high-voltage power supply. The high-voltage detection output signal from the ADV-VH output terminal of the VH solid-state power circuit and the high-voltage current detection output signal from the ADI-VH output terminal are respectively connected to the two AD ports of the processor circuit.

[0082] The positive terminal of the low-voltage battery is connected to the VLIN input terminal of the VL solid-state power circuit. The S-VL output terminal of the VL solid-state power circuit is connected to the S-VL input terminal of the VL voltage and current detection and conditioning circuit, and the low-voltage power supply ground is connected to the VLGND input terminal of the VL voltage and current detection and conditioning circuit. The S'-VL output terminal of the VL voltage and current detection and conditioning circuit is connected to the S'-VL input terminal of the VL reverse protection circuit, and the VLOUT output terminal of the VL reverse protection circuit is connected to the positive terminal of the ground low-voltage power supply. The low-voltage detection output signal from the ADV-VL output terminal and the low-voltage current detection output signal from the ADI-VL output terminal of the VL solid-state power circuit are respectively connected to the two AD ports of the processor circuit.

[0083] The positive terminal of the first servo power supply is connected to the VDJ1IN input of the servo voltage and current detection and conditioning circuit. The positive terminal of the second servo power supply is connected to the VDJ2IN input of the servo voltage and current detection and conditioning circuit. The servo power ground is connected to the VDJGND input of the servo voltage and current detection and conditioning circuit. The VDJ1OUT output of the servo voltage and current detection and conditioning circuit is connected to the positive terminal of the first servo load. The VDJ2OUT output of the servo voltage and current detection and conditioning circuit is connected to the positive terminal of the second servo load. The ADV-DJ1, ADV-DJ2, ADI-DJ1, and ADI-DJ2 outputs of the servo voltage and current detection and conditioning circuit are respectively connected to the four AD ports of the processor circuit.

[0084] The ignition current input terminal is connected to the VDHIN input terminal of the ignition voltage and current detection and conditioning circuit, and the ignition power ground is connected to the VDHGND input terminal of the ignition voltage and current detection and conditioning circuit. The VDHOUT output terminal of the ignition voltage and current detection and conditioning circuit is connected to the ignition current output terminal. The ADV-DH and ADI-DH output terminals of the ignition voltage and current detection and conditioning circuit are respectively connected to the two AD ports of the processor circuit.

[0085] The power transfer control signal is connected to the XZD input of the power transfer signal isolation detection circuit, the power transfer release signal is connected to the XJC input of the power transfer signal isolation detection circuit, and the low-voltage power ground is connected to the VLGND input of the power transfer signal isolation detection circuit. The OD-ZD and OD-JC outputs of the power transfer signal isolation detection circuit are respectively connected to two I / O ports of the processor circuit.

[0086] The S-VL output of the VL solid-state power circuit is connected to the S-VL input of the power feedback signal conditioning circuit, and the low-voltage power ground is connected to the VLGND input of the power feedback signal conditioning circuit. The A output of the power feedback signal conditioning circuit is connected to the A input of the external monitoring center, the B output of the power feedback signal conditioning circuit is connected to the B input of the external monitoring center, and the OD-FK output of the power feedback signal conditioning circuit is connected to an I / O port of the processor circuit.

[0087] The ZD1, ZD2, JC1, and JC2 inputs of the control logic processing circuit are connected to the four I / O ports of the processor circuit, respectively. The OD-ZD and OD-JC outputs of the electrical signal isolation detection circuit are connected to the OD-ZD and OD-JC inputs of the control logic processing circuit, respectively. The DRI output of the control logic processing circuit is connected to the DRI input of the isolation drive circuit.

[0088] The S-VH and DRI-VH outputs of the isolation drive circuit are connected to the S-VH and DRI-VH inputs of the VH solid-state power circuit, respectively. The S-VL and DRI-VL outputs of the isolation drive circuit are connected to the S-VL and DRI-VL inputs of the VL solid-state power circuit, respectively.

[0089] The SCI port of the processor circuit is connected to the TXD and RXD communication terminals of the RS422 isolation interface. The 422-A and 422-B receive signal terminals, the 422-Y and 422-Z transmit signal terminals, and the 422-GND shielding ground terminal of the RS422 isolation interface are connected to an external RS422 bus network.

[0090] The positive terminal of the low-voltage ground power supply is connected to the VLOUT input terminal of the filter isolation power supply circuit, and the low-voltage ground is connected to the VLGND input terminal of the filter isolation power supply circuit. The output terminal of the filter isolation power supply circuit is connected to the operating power supply of the internal module.

[0091] The above connection relationships indicate that: the reference signal for VH voltage and the transfer feedback signal S-VH is the high-voltage power supply ground VHGND; the reference signal for VL voltage, the transfer control signal XZD, the transfer release signal XJC, and the transfer feedback signal S-VL is the low-voltage power supply ground VLGND; the reference signal for the servo voltage is the servo power supply ground VDJGND; the reference signal for the ignition voltage is the ignition power supply ground VDHGND; the reference signal for the drive signal DRI-VH is S-VH; and the reference signal for the drive signal DRI-VL is S-VL. The internal control and detection signals of ADV-VH, ADV-VL, ADV-DJ1, ADV-DJ2, ADV-DH, ADI-VH, ADI-VL, ADI-DJ1, ADI-DJ2, ADI-DH, OD-ZD, OD-JC, ZD1, ZD2, JC1, JC2, DRI, TXD, RXD, etc., as well as the reference signals of each working power rail, are all internal working power ground GND. This is an industry default rule and is not explicitly stated in the text or the attached diagrams, but it is explained here.

[0092] The VH solid-state power circuit uses two high-voltage power MOSFETs connected in parallel, with an RC snubber circuit consisting of a thick-film power resistor and a metal-film capacitor connected in series next to each MOSFET. The high-voltage power MOSFETs are turned off when the voltage of the drive signal DRI-VH relative to S-VH is approximately 0V, and turned off when the voltage of the drive signal DRI-VH relative to S-VH exceeds the gate threshold voltage V of the high-voltage power MOSFET. GS(TH) The switching on and off states are described below. The following descriptions will use the switching on and off states of a high-voltage power MOSFET as an example to illustrate these two operating states.

[0093] The VL solid-state power circuit uses two low-voltage power MOSFETs connected in parallel, with an RC snubber circuit consisting of a thick-film power resistor and a metal-film capacitor connected in series next to each low-voltage power MOSFET. The low-voltage power MOSFETs are turned off when the voltage of the drive signal DRI-VL relative to S-VL is approximately 0V, and turned off when the voltage of the drive signal DRI-VL relative to S-VL exceeds the gate threshold voltage V of the low-voltage power MOSFET. GS(TH) The MOSFET is turned on at a certain time. The following descriptions will use the on / off states of a low-voltage power MOSFET to illustrate these two operating states.

[0094] The VH and VL anti-reverse circuits use ideal diodes for current reverse protection. For details, please refer to another patent application of the inventor, "Diode for Aircraft Power Transfer Reverse Protection and its Operation Method", which will not be repeated here.

[0095] The VH, VL, servo, and ignition voltage and current sensing and conditioning circuits all use the same core circuitry. Current detection utilizes a Hall effect current sensor for isolated sampling, which is then filtered by an RC network to obtain the current detection signal. Voltage sampling first uses a resistor divider to obtain a signal that meets the input range of the isolated op-amp, then the isolated op-amp performs a linear conversion and is filtered by an RC network to obtain the voltage detection signal. The voltage divider resistors in the VL voltage and current sensing and conditioning circuit use power resistors to ensure sufficient leakage current discharge capability across the entire temperature range. In actual testing at room temperature, no cumulative voltage exceeding 1V is generated, thus eliminating the impact of solid-state power switch leakage current on the current feedback signal conditioning circuit. The voltage and current sensing and conditioning circuits utilizing Hall effect current sensors for current detection, isolated op-amps with resistor dividers for voltage detection, and RC network filtering are all mature technologies.

[0096] After optocoupler isolation is adopted, the output signals OD-ZD and OD-JC are high when the XZD and XJC signals are valid (i.e., connected to the low-voltage power supply VL), and low when the XZD and XJC signals are invalid (i.e., disconnected from the low-voltage power supply VL). This circuit can be designed by industry professionals; the technical details are not the focus of this invention and will not be elaborated further.

[0097] The feedback signal conditioning circuit consists of a threshold and protection circuit, a signal isolation circuit, and a signal output circuit, such as... Figure 2As shown. The input terminals of the threshold and protection circuit form the S-VL input terminal and VLGND input terminal of the switching feedback signal conditioning circuit. The output terminal of the threshold and protection circuit is connected to the input terminal of the signal isolation circuit. The output terminal of the signal isolation circuit forms the A output terminal, B output terminal, and OD-FK output terminal of the switching feedback signal conditioning circuit. The switching feedback signal conditioning circuit of this invention can be implemented using a dual-output miniature relay or an opto-MOS relay as the core signal isolation circuit. The function of the threshold and protection circuit is to ensure that the cumulative voltage of the leakage current of the solid-state power switch within the entire operating temperature range does not cause false detections where the switching feedback state differs from the actual switching state, thereby eliminating the influence of the solid-state power switch leakage current. When using an opto-MOS relay as the core, a Zener diode is generally used in conjunction with a current-limiting resistor to construct the threshold circuit, while the function of the protection circuit is to provide reverse connection protection, overvoltage protection, and overcurrent protection for the light-emitting diode of the opto-MOS device.

[0098] In a preferred embodiment of the present invention, the switching feedback signal conditioning circuit is composed of a dual-channel optical MOS relay Q6, a Zener diode D11, a diode D12, resistors R31 to R33, and a capacitor C12. Figure 3 As shown. One end of resistor R31 forms the S-VL input terminal of the feedback signal conditioning circuit, and the other end of resistor R31 is connected to the cathode of Zener diode D11; the anode of Zener diode D11, the cathode of diode D12, one end of resistor R33, and one end of capacitor C12 are simultaneously connected to the first input terminal of dual-channel opto-MOS relay Q6; the second and third input terminals of dual-channel opto-MOS relay Q6 are connected; the anode of diode D12, the other end of resistor R33, and the other end of capacitor C12 are simultaneously connected to the fourth output terminal of dual-channel opto-MOS relay Q6, forming a feedback signal conditioning circuit. The VLGND input terminal of the electrical feedback signal conditioning circuit; the first output terminal of the dual-channel optical MOS relay Q6 forms the A output terminal of the electrical feedback signal conditioning circuit; the second output terminal of the dual-channel optical MOS relay Q6 forms the B output terminal of the electrical feedback signal conditioning circuit; the third output terminal of the dual-channel optical MOS relay Q6 forms the OD-FK output terminal of the electrical feedback signal conditioning circuit; one end of resistor R32 is connected to the power supply VCC, the other end of resistor R32 is connected to the third output terminal of the dual-channel optical MOS relay Q6, and the fourth output terminal of the dual-channel optical MOS relay Q6 is connected to the power supply GND.

[0099] The control logic processing circuit consists of a first processor control signal confirmation circuit, a first delay filter circuit, a first hysteresis comparator circuit, a second processor control signal confirmation circuit, a second delay filter circuit, a comparator circuit with a second hysteresis, a reference voltage circuit, common cathode diodes D1-D2, a reset priority RS flip-flop circuit, and a control signal power amplifier circuit. Figure 4As shown. The input terminals of the first processor control signal confirmation circuit form the ZD1 and ZD2 input terminals of the control logic processing circuit. The input terminal of the first delay filter circuit forms the OD-ZD input terminal of the control logic processing circuit. The output terminal of the first delay filter circuit is connected to one input terminal (generally called the comparator terminal) of the first hysteresis comparator circuit. The input terminals of the second processor control signal confirmation circuit form the JC1 and JC2 input terminals of the control logic processing circuit. The input terminal of the second delay filter circuit forms the OD-JC input terminal of the control logic processing circuit. The output terminal of the second delay filter circuit is connected to one input terminal (generally called the comparator terminal) of the second hysteresis comparator circuit. The output terminal of the reference voltage circuit is connected to the other input terminal (generally called the reference terminal) of the first and second hysteresis comparator circuits. The output terminals of the first processor control signal confirmation circuit and the first hysteresis comparator circuit are respectively connected to the two anodes of the common cathode diode D1, and the cathode of the common cathode diode D1 is connected to one input terminal of the reset priority RS flip-flop circuit. The outputs of the second processor control signal confirmation circuit and the second hysteresis comparator circuit are respectively connected to the two anodes of the common cathode diode D2. The cathode of the common cathode diode D2 is connected to the other input of the reset priority RS flip-flop circuit. The output of the reset priority RS flip-flop circuit is connected to the input of the control signal power amplifier circuit, and the output of the control signal power amplifier circuit forms the DRI output of the control logic processing circuit.

[0100] The processor control signal confirmation circuit in the control logic processing circuit ensures that a high level is output only when the processor control signal is valid. A valid processor control signal means that the signal is highly unlikely to be generated by abnormal conditions such as system reset or system interference, but rather is a control signal output according to the agreed-upon protocol after processor signal processing. In practical use, it is recommended that the I / O ports for the processor control signal output use registers in the same group, employ external pull-down resistors, and that the signal be valid when one I / O port outputs a high signal and the other a low signal; in this case, a high level is obtained after processing by the processor control signal confirmation circuit. In other cases, the output of the processor control signal confirmation circuit is low. Considering the relationship between OD_ZD and ZD1, ZD2, and OD_JC and JC1, JC2 signals, the specific relationships are as follows:

[0101] When the processor circuit detects that OD_ZD is valid, it performs signal width detection according to the power-on control signal characteristics specified in the task requirements. Once it confirms that the power-on control signal meets the task requirements, the processor outputs ZD1 as high and ZD2 as low. At this time, the output of the first processor control signal confirmation circuit is high (this state is defined as valid processor power-on control output). In all other cases, ZD1 and ZD2 output low, and the output of the first processor control signal confirmation circuit is also low (this state is defined as invalid processor power-on control output).

[0102] When the processor circuit detects that OD_JC is valid, it performs signal width detection according to the power-off control signal characteristics specified in the task requirements. Once the power-off release signal is confirmed to meet the task requirements, the processor outputs JC1 high and JC2 low. At this time, the output of the second processor control signal confirmation circuit is high (this state is defined as the processor power-off release output being valid). In all other cases, JC1 and JC2 output low, and the output of the second processor control signal confirmation circuit is also low (this state is defined as the processor power-off release output being invalid).

[0103] The control implemented by the processor circuit described above through the output of IO ports after detecting OD_ZD and OD_JC is called software control.

[0104] The delay filter circuit and hysteresis comparator circuit of the control logic processing circuit, together with the reference voltage provided by the reference voltage circuit, realize the validity judgment and control of the transfer signal and the release signal in hardware logic. The delay filter circuit, by configuring the RC circuit parameters, detects the signal width, ensuring that the transfer control signal and transfer release signal meeting the task requirements can be transmitted to the comparator input of the hysteresis comparator circuit. When the signal is greater than the reference voltage, the hysteresis comparator circuit outputs a high level; otherwise, it outputs a low level. If the transfer control signal meets the task requirements, the signal voltage at the comparison terminal of the first hysteresis comparator circuit will exceed the reference voltage, and the output of the first hysteresis comparator circuit will become high (this state is defined as the hardware logic transfer control output being valid); otherwise, the output of the first hysteresis comparator circuit will always be low (this state is defined as the hardware logic transfer control output being invalid). If the power-off signal meets the task requirements, the voltage of the comparison terminal signal of the second hysteresis comparator circuit will exceed the reference voltage, and the output of the second hysteresis comparator circuit will become high (this state is defined as the hardware logic power-off output being valid); otherwise, the output of the second hysteresis comparator circuit will be low (this state is defined as the hardware logic power-off output being invalid).

[0105] The above-mentioned method of judging the validity of the power transfer control signal and the power transfer release signal and controlling the output through pure hardware circuits is called hardware control method.

[0106] The software control output and hardware control output of the power conversion control signal are connected through a common cathode diode D1 to achieve a logical OR relationship. That is, if either the software control output or the hardware control output is valid, the control effect of the power conversion control signal is valid.

[0107] The software control output and hardware control output of the power-off release signal are connected through a common cathode diode D2 to achieve a logical OR relationship. That is, if either the software control output or the hardware control output is valid, the control effect of the power-off release signal is valid.

[0108] The reset-priority RS flip-flop circuit of the control logic processing circuit satisfies the logical relationship specified in the following truth table to ensure that the power-switching module does not perform a power-switching operation when the XZD and XJC signals are unexpectedly valid simultaneously (corresponding to R and S being 1 simultaneously). The reset-priority RS flip-flop circuit ensures that the power-switching release command is executed when both the power-switching control signal and the power-switching release signal are present. This is mandated by the task's requirement for priority power-switching release. When the task requires priority for power-switching control, simply swap the RS terminal wiring in the above scheme.

[0109] The control signal power amplifier circuit of the control logic processing circuit is used to amplify the control signal Q output by the reset priority RS flip-flop circuit to obtain the power control signal DRI of the isolation drive circuit, so as to drive the drive signal of the solid-state power circuit output by the isolation drive circuit.

[0110] In a preferred embodiment of the present invention, the control logic processing circuit comprises a dual-channel hysteresis comparator circuit K3, common cathode diodes D1 and D2, XOR gates K1 and K5, NOR gates K2 and K4, an NPN transistor Q1, resistors R1 to R14, Rzd, Rjc and Rrs, and capacitors C1, Czd, Cjc and Crs. Figure 5As shown. One end of resistor R1 and one input of XOR gate K1 form the ZD1 input of the control logic processing circuit. One end of resistor R2 and the other input of XOR gate K1 form the ZD2 input of the control logic processing circuit. The other ends of resistors R1 and R2 are grounded. The output of XOR gate K1 is connected to one anode of common cathode diode D1. One end of resistor Rzd and one end of resistor R5 together form the OD-ZD input of the control logic processing circuit. The other end of resistor Rzd, one end of resistor R4, and one end of capacitor Czd are simultaneously connected to the INA+ terminal of the dual-channel hysteresis comparator circuit K3. The other end of resistor R5 and the other end of capacitor Czd are connected to the GND terminal of the dual-channel hysteresis comparator circuit K3 and connected to the power supply GND. The other end of resistor R4 and the other anode of common cathode diode D1 are jointly connected to the OUTA terminal of the dual-channel hysteresis comparator circuit K3. One end of resistor R13 and one input of XOR gate K5 form the JC1 input of the control logic processing circuit. One end of resistor R14 and the other input of XOR gate K5 form the JC2 input of the control logic processing circuit. The other ends of resistors R13 and R14 are grounded. The output of XOR gate K5 is connected to one anode of common cathode diode D2. One end of resistor Rjc and one end of resistor R10 together form the OD-JC input of the control logic processing circuit. The other end of resistor Rjc, one end of resistor R9, and one end of capacitor Cjc are simultaneously connected to the INB+ terminal of the dual-channel hysteresis comparator circuit K3. The other end of resistor R10 and the other end of capacitor Cjc are connected to the power supply GND. The other end of resistor R9 and the other anode of common cathode diode D2 are simultaneously connected to the OUTB terminal of the dual-channel hysteresis comparator circuit K3. One end of resistor R6 and one end of resistor R7 are simultaneously connected to the INA- and INB- terminals of the dual-channel hysteresis comparator circuit K3. The other end of resistor R6 is connected to the power supply VCC, and the other end of resistor R7 is connected to the power supply GND. One end of capacitor C1 is connected to the VCC terminal of the dual-channel hysteresis comparator circuit K3 and is also connected to the power supply VCC. The other end of capacitor C1 is connected to the power supply GND. The anode of common-cathode diode D1 and one end of resistor R3 are connected to one input terminal of NOR gate K2. The other end of resistor R3 is connected to the power supply GND. The anode of common-cathode diode D2, one end of resistor Rrs, and one end of capacitor Crs are connected to one input terminal of NOR gate K4. The other end of capacitor Crs is connected to the power supply VCC, and the other end of resistor Rrs is connected to the power supply GND. The other input terminal of NOR gate K4 is connected to the output terminal of NOR gate K2 via resistor R8. The other input terminal of NOR gate K2 is directly connected to the output terminal of NOR gate K4. One end of resistor R11 is connected to the output terminal of NOR gate K4, and the other end of resistor R11 and one end of resistor R12 are connected to the base of NPN transistor Q1. The other end of resistor R12 and the emitter of NPN transistor Q1 are connected to the power supply GND. The collector of NPN transistor Q1 forms the DRI output of the control logic processing circuit.

[0111] By configuring the parameters of Rzd and Czd, and Rjc and Cjc, the width requirements of the XZD and XJC signals can be met for different tasks. Let the unit of resistance values ​​of Rzd and Rjc be Ω, and the unit of capacitance values ​​of Czd and Cjc be F. Their product is the time constant τ (in seconds), then (4-5)*τ is the width of the XZD and XJC signals. The parameters of Rrs and Crs are used to ensure that the output of the reset-priority RS flip-flop circuit is low during the power-on period of the power-on module. Generally, Rrs is in the 10kΩ range, while Crs should be above 10uF.

[0112] The isolated drive circuit consists of a high-voltage high-frequency oscillation circuit, a high-voltage transformer, a high-voltage rectifier, filter, limiting, and release circuit, a high-voltage drive signal distribution circuit, a low-voltage high-frequency oscillation circuit, a low-voltage transformer, a low-voltage rectifier, filter, limiting, and release circuit, and a low-voltage drive signal distribution circuit. Figure 6 As shown. The input terminals of the high-voltage high-frequency oscillation circuit and the low-voltage high-frequency oscillation circuit together form the DRI input terminal of the isolated drive circuit. The output terminal of the high-voltage high-frequency oscillation circuit is connected to the primary winding of the high-voltage transformer. The secondary winding of the high-voltage transformer is connected to the input terminal of the high-voltage rectification, filtering, limiting, and release circuit. The output terminal of the high-voltage rectification, filtering, limiting, and release circuit is connected to the input terminal of the high-voltage drive signal distribution circuit. The output terminal of the high-voltage drive signal distribution circuit forms the S-VH output terminal and the DRI-VH output terminal of the isolated drive circuit. The output terminal of the low-voltage high-frequency oscillation circuit is connected to the primary winding of the low-voltage transformer. The secondary winding of the low-voltage transformer is connected to the input terminal of the low-voltage rectification, filtering, limiting, and release circuit. The output terminal of the low-voltage rectification, filtering, limiting, and release circuit is connected to the input terminal of the low-voltage drive signal distribution circuit. The output terminal of the low-voltage drive signal distribution circuit forms the S-VL output terminal and the DRI-VL output terminal of the isolated drive circuit.

[0113] This invention provides two isolated implementations, each with two drive signal outputs, for controlling low-voltage and high-voltage power transfer lines respectively. The low-voltage and high-voltage power transfer lines use the same power transfer control command; therefore, their respective high-frequency oscillation circuits use the same power control signal (DRI). The high-frequency oscillation circuit receives the power input and the power control signal (DRI) as inputs, working in conjunction with the primary winding of the transformer to achieve high-frequency oscillation and output an alternating signal, which is proportionally transmitted to the secondary winding of the transformer. The alternating signal from the secondary winding of the transformer is processed by a rectification, filtering, limiting, and release circuit to obtain the drive signal. Each set of drive signals can be divided into two drive signals by a drive signal distribution circuit for controlling the on / off state of the solid-state power circuit.

[0114] In a preferred embodiment of the present invention, the isolation drive circuit comprises a low-voltage transformer T1, a high-voltage transformer T2, NPN transistors Q3 and Q5, PNP transistors Q2 and Q4, diodes D4 to D9, Zener diodes D10 and D11, resistors R15 to R30, and capacitors C2 to C11. Figure 7As shown. One end of resistor R19, one end of resistor R22, one end of resistor R27, and one end of resistor R30 together form the DRI input terminal of the isolated drive circuit. The other end of resistor R19 and one end of resistor R18 are connected to the base of NPN transistor Q3. The other end of resistor R22, one end of capacitor C4, and one end of capacitor C6 are connected to the emitter of NPN transistor Q3. The other end of resistor R18 and one end of capacitor C2 are connected to the positive terminal of the primary winding of low-voltage transformer T1, and connected to power supply VCC. The other end of capacitor C2 is connected to the other end of capacitor C4. The collector of NPN transistor Q3 and the other end of capacitor C6 are connected to the negative terminal of the primary winding of low-voltage transformer T1. The other end of resistor R27 and one end of resistor R26 are connected to the base of NPN transistor Q5. The other end of resistor R30, one end of capacitor C9, and one end of capacitor C11 are connected to the emitter of NPN transistor Q5. The other end of resistor R26 and one end of capacitor C7 are connected to the positive terminal of the primary winding of high-voltage transformer T2, and then to power supply VCC. The other end of capacitor C7 is connected to the other end of capacitor C9. The collector of NPN transistor Q5 and the other end of capacitor C11 are connected to the negative terminal of the primary winding of high-voltage transformer T2. The positive terminal of the secondary winding of low-voltage transformer T1 is connected to one end of capacitor C3, and the other end of capacitor C3 is connected to the cathode of diode D4 and the anode of diode D5. The cathode of diode D5, the anode of diode D6, and one end of resistor R20 are connected to the base of PNP transistor Q2. The collector of PNP transistor Q2 is connected to one end of resistor R21. The cathode of diode D6 and one end of resistor R15 are connected to the emitter of PNP transistor Q2. The other end of resistor R15, one end of resistor R16, one end of resistor R17, the cathode of Zener diode D10, and one end of capacitor C5 are connected. The other end of resistor R16 forms the DRI-VL1 output of the isolated drive circuit, and the other end of resistor R17 forms the DRI-VL2 output of the isolated drive circuit. Since the VL solid-state power circuit uses two low-voltage power MOSFETs in parallel, two isolated drive circuits, DRI-VL1 and DRI-VL2, are required. The negative terminal of the secondary winding of low-voltage transformer T1, the anode of diode D4, the other end of resistor R20, the other end of resistor R21, the anode of Zener diode D10, and the other end of capacitor C5 together form the S-VL output of the isolated drive circuit. The positive terminal of the secondary winding of high-voltage transformer T2 is connected to one end of capacitor C8, and the other end of capacitor C8 is connected to the cathode of diode D7 and the anode of diode D8. The cathode of diode D8, the anode of diode D9, and one end of resistor R28 are connected to the base of PNP transistor Q4. The collector of PNP transistor Q4 is connected to one end of resistor R29. The cathode of diode D9 and one end of resistor R23 are connected to the emitter of PNP transistor Q4. The other end of resistor R23, one end of resistor R24 ​​and one end of resistor R25, the cathode of Zener diode D11, and one end of capacitor C10 are connected.The other end of resistor R24 ​​forms the DRI-VH1 output terminal of the isolated drive circuit, and the other end of resistor R25 forms the DRI-VH2 output terminal of the isolated drive circuit. Since the VH solid-state power circuit uses two high-voltage power MOSFETs connected in parallel, two isolated drive circuits, DRI-VL1 and DRI-VL2, are required. The negative terminal of the secondary coil of high-voltage transformer T2, the anode of diode D7, the other end of resistor R28, the other end of resistor R29, the anode of Zener diode D11, and the other end of capacitor C10 together form the S-VH output terminal of the isolated drive circuit.

[0115] To effectively reduce product size and weight while improving reliability, high-voltage and low-voltage transformers are implemented as on-board transformers using printed circuit boards (PCBs). During the design of on-board transformers, the number of turns is configured according to the power input voltage and the drive voltage requirements of the solid-state power circuit. A multi-layer PCB is used, placing coils with fewer turns in the middle layer and coils with more turns on adjacent layers above and below to improve coupling. The conductive strips used for the coils should be arranged in a spiral shape, such as... Figure 8 As shown.

[0116] The RS422 isolation interface circuit is based on a high-speed RS422 isolation interface chip, which realizes the connection between the processor circuit's SCI port and the external RS422 network. The specific circuit is designed with reference to the application manual of the high-speed RS422 isolation interface chip. The technical details are not the focus of this invention and will not be elaborated here.

[0117] The filtered and isolated power supply circuit is powered by a low-voltage ground power source and can smoothly transition to low-voltage battery power after the low-voltage power conversion is completed. The filtered and isolated power supply circuit utilizes components such as TVS diodes, resettable fuses, EMI filters, DC / DC modules, LDO modules, inductors, and capacitors, taking into account factors such as supply voltage, load power, load voltage, power adaptability requirements, electromagnetic compatibility requirements, size, ambient temperature, and reliability requirements. Industry professionals can design such circuits; however, the technical details are not the focus of this invention and will not be elaborated further.

[0118] The operation method of the aforementioned missile-borne solid-state power conversion module includes the following specific steps:

[0119] Step 1: The power transfer signal isolation detection circuit obtains the corresponding power transfer control isolation detection signal OD-ZD and power transfer release isolation detection signal OD-JC based on the power transfer control signal XZD and power transfer release signal XJC sent from the external monitoring center, and sends them to the processor circuit and control logic processing circuit.

[0120] Step 2: The processor circuit detects the validity of the power transfer control signal XZD and the power transfer release signal XJC based on the power transfer control isolation detection signal OD-ZD and the power transfer release isolation detection signal OD-JC. Based on the detection results, the processor circuit obtains the first power transfer control signal ZD1, the second power transfer control signal ZD2, the first power transfer release signal JC1, and the second power transfer release signal JC2, and sends them to the control logic processing circuit.

[0121] 1) The process by which the processor circuit obtains the first power transfer control signal ZD1 and the second power transfer control signal ZD2 based on the power transfer control isolation detection signal OD-ZD is as follows:

[0122] First, the OD-ZD signal is periodically scanned with the main program's time base width. Each scan performs necessary filtering processes, such as "two out of three" or "three out of five", to obtain the level state of the OD-ZD signal. If the result of the OD-ZD signal is high (as mentioned above, the XZD signal is valid at this time), the OD-ZD high-level count value is incremented by 1; otherwise, the OD-ZD high-level count value is decremented by 2, and necessary overflow prevention processing is performed.

[0123] Next, the high-level count value of OD-ZD is judged: if it exceeds the set threshold, the XZD signal is considered to meet the width requirement specified by the task and belongs to the power-off control command that needs to be executed. At this time, it is output in the form of ZD1 signal being high and ZD2 signal being low; otherwise, it is considered that no power-off control command that needs to be executed has been detected. At this time, both ZD1 signal and ZD2 signal are kept low and the above scanning and counting operation of OD-ZD signal is repeated periodically.

[0124] 2) The process by which the processor circuit obtains the first power-off signal JC1 and the second power-off signal JC2 based on the power-off isolation detection signal OD-JC is as follows:

[0125] First, the OD-JC signal is periodically scanned with the main program's time base width. Each scan performs necessary filtering processes, such as "two out of three" or "three out of five", to obtain the level state of the OD-JC signal. If the result of the OD-JC signal is high (as mentioned above, the XJC signal is valid at this time), the OD-JC high-level count value is incremented by 1; otherwise, the OD-JC high-level count value is decremented by 2, and necessary overflow prevention processing is performed.

[0126] Next, the high-level count value of OD-JC is judged. If it exceeds the set threshold, the XJC signal is considered to meet the width requirement specified by the task, and it belongs to the power-off release command that needs to be executed. At this time, it is output in the form of JC1 signal high level and JC2 signal low level. Otherwise, it is considered that no power-off control command to be executed has been detected. At this time, both JC1 signal and JC2 signal are kept at low level output, and the above scanning and count value addition and subtraction operation of OD-JC signal is repeated periodically.

[0127] The aforementioned OD-ZD high-level counting threshold and OD-JC high-level counting threshold can be embedded in the processor during program design according to task requirements, or they can be stored in the processor after being debugged and confirmed through an RS422 communication network.

[0128] Step 3: The control logic processing circuit performs logical operations on the power transfer control isolation detection signal OD-ZD, the first power transfer control signal ZD1, the second power transfer control signal ZD2, the power transfer release isolation detection signal OD-JC, the first power transfer release signal JC1, and the second power transfer release signal JC2 to obtain the drive signal DRI, which is then sent to the isolation drive circuit.

[0129] The logic operation process of the control logic processing circuit is as follows:

[0130] When the processor detects a power-off control instruction to be executed, it outputs ZD1 high and ZD2 low. At this time, the output of the first processor control signal confirmation circuit is high (this state is defined as the processor power-off control output being valid). In all other cases, ZD1 and ZD2 are both low, and the output of the first processor control signal confirmation circuit is also low (this state is defined as the processor power-off control output being invalid). When the processor detects a power-off release instruction to be executed, it outputs JC1 high and JC2 low. At this time, the output of the second processor control signal confirmation circuit is high (this state is defined as the processor power-off release output being valid). In all other cases, JC1 and JC2 are both low, and the output of the second processor control signal confirmation circuit is also low (this state is defined as the processor power-off release output being invalid). The control implemented by the processor of this invention through the I / O port output after detecting OD_ZD and OD_JC is called software control.

[0131] When the first delay filter circuit detects a power-off control command to be executed, the output of the first hysteresis comparator circuit goes high (this state is defined as valid hardware logic power-off control output); otherwise, the output of the first hysteresis comparator circuit goes low (this state is defined as invalid hardware logic power-off control output). When the second delay filter circuit detects a power-off release command to be executed, the voltage of the comparison terminal signal of the second hysteresis comparator circuit exceeds the reference voltage, and the output of the second hysteresis comparator circuit goes high (this state is defined as valid hardware logic power-off release output); otherwise, the output of the second hysteresis comparator circuit goes low (this state is defined as invalid hardware logic power-off release output). This invention's method of judging the validity of power-off control signals and power-off release signals and controlling the output through pure hardware circuitry is called hardware control.

[0132] The software control output and hardware control output of the power conversion control signal are connected through a common cathode diode D1 to achieve a logical OR relationship. That is, if either the software control output or the hardware control output is valid, the control effect of the power conversion control signal is valid.

[0133] The software control output and hardware control output of the power-off release signal are connected through a common cathode diode D2 to achieve a logical OR relationship. That is, if either the software control output or the hardware control output is valid, the control effect of the power-off release signal is valid.

[0134] The relationship between the set terminal S, the reset terminal R, and the output terminal Q of the reset priority RS flip-flop circuit satisfies the logical relationship specified in the following truth table (Table 1) to ensure that the power transfer module does not perform a power transfer operation when the XZD and XJC signals are unexpectedly valid at the same time (corresponding to R and S being 1 at the same time).

[0135] Serial Number S R Q Remark 1 0 0 0 System Reset 2 0 1 0 XJC signal is valid. 3 1 0 1 XZD signal is valid. 4 1 1 0 Both XZD and XJC signals are valid.

[0136] Table 1

[0137] Step 4: The isolation drive circuit first performs high-frequency oscillation, transformer isolation, rectification, filtering, and limiting on the drive signal DRI to obtain the high-voltage solid-state power transistor drive signal DRI-VH and its reference signal S-VH, and the low-voltage solid-state power transistor drive signal DRI-VL and its reference signal S-VL. The isolation drive circuit then allocates the high-voltage solid-state power transistor drive signal DRI-VH as DRI-VH1 and DRI-VH2 according to the number of high-voltage solid-state power transistors in the VH solid-state power circuit, and sends it along with its reference signal S-VH into the VH solid-state power circuit. Simultaneously, based on the number of low-voltage solid-state power transistors in the VL solid-state power circuit, the low-voltage solid-state power transistor drive signal DRI-VL is allocated as DRI-VL1 and DRI-VL2, and then sent along with its reference signal S-VL into the VL solid-state power circuit.

[0138] Step 5: The operating processes of the VH solid-state power circuit and the VL solid-state power circuit are as follows:

[0139] The VH solid-state power circuit is controlled by the high-voltage solid-state power transistor drive signal voltage. When the voltage of the high-voltage solid-state power transistor drive signal DRI-VH relative to its reference signal S-VH exceeds the high-voltage MOSFET gate threshold voltage V... GS(TH) It is turned on when the voltage of the high-voltage solid-state power transistor drive signal DRI-VH relative to its reference signal S-VH is approximately 0V, thereby connecting or disconnecting the positive terminal VHIN of the high-voltage battery from S-VH.

[0140] The VL solid-state power circuit is controlled by the low-voltage solid-state power transistor drive signal voltage. When the voltage of the low-voltage solid-state power transistor drive signal DRI-VL relative to its reference signal S-VL exceeds the low-voltage MOSFET gate threshold voltage V... GS(TH) It is turned on when the voltage of the low-voltage solid-state power transistor drive signal DRI-VL relative to its reference signal S-VL is approximately 0V, thereby connecting or disconnecting the positive terminal VLIN of the low-voltage battery from S-VL.

[0141] Step 6: The working processes of the VH voltage and current detection and conditioning circuit and the VL voltage and current detection and conditioning circuit are as follows:

[0142] When the VH solid-state power circuit is turned on, the VH voltage and current detection and conditioning circuit conditions the signal output by the VH solid-state power and sends it to the VH anti-reverse circuit; at the same time, it collects the high voltage signal ADV-VH and the high voltage current signal ADI-VH and sends them to the processor circuit. The processor circuit completes the sampling of the high voltage signal ADV-VH and the high voltage current signal ADI-VH and the calculation of the VH voltage and current values ​​by the timer interrupt program.

[0143] When the VL solid-state power circuit is turned on, the VL voltage and current detection and conditioning circuit conditions the signal output by the VL solid-state power and sends it to the VL anti-reverse circuit. At the same time, it collects the low-voltage signal ADV-VL and the low-voltage current signal ADI-VL and sends them to the processor circuit. The processor circuit completes the sampling of the low-voltage signal ADV-VL and the low-voltage current signal ADI-VL and the calculation of the VL voltage and current values ​​by a timer interrupt program.

[0144] Step 7: The working processes of the VH anti-reverse circuit and the VL anti-reverse circuit are as follows:

[0145] The VH anti-reverse circuit prevents current backflow when the high-voltage battery voltage is lower than the ground high-voltage power supply voltage, and seamlessly switches the downstream high-voltage power supply to the high-voltage battery when the high-voltage battery voltage is higher than the ground high-voltage power supply voltage.

[0146] The VL anti-reverse circuit prevents current backflow when the low-voltage battery voltage is lower than the ground low-voltage power supply voltage, and seamlessly switches the subsequent low-voltage power supply to the low-voltage battery when the low-voltage battery voltage is higher than the ground low-voltage power supply voltage.

[0147] Step 8: The power transfer feedback signal conditioning circuit detects the actual on / off state of the VL solid-state power circuit, sends power transfer feedback signals A and B to the external monitoring center, and sends feedback signal OD-FK to the processor circuit; the processor circuit detects the feedback signal OD-FK and updates the detection result to the corresponding status bit in memory.

[0148] When the VL solid-state power circuit is turned on (i.e., the positive terminal VLIN of the low-voltage battery is connected to S-VL), the power transfer feedback signal A and the power transfer feedback signal B are on, and the feedback signal OD-FK is low. When the VL solid-state power circuit is turned off (i.e., the positive terminal VLIN of the low-voltage battery is disconnected from S-VL), the power transfer feedback signal A and the power transfer feedback signal B are in a high-impedance state, and the feedback signal OD-FK is high.

[0149] Step 9: The filter isolation power supply circuit is powered by a ground low-voltage power supply. After the low-voltage power conversion is completed, the internal working power supply of the missile equipment is switched to low-voltage battery power supply.

[0150] Step 10: The servo voltage and current detection and conditioning circuit conditions the power supply of the first servo and sends it to the load of the first servo in the missile-borne equipment, and conditions the power supply of the second servo and sends it to the load of the second servo in the missile-borne equipment; at the same time, it collects the voltage signal ADV-DJ1 of the first servo, the voltage signal ADV-DJ2 of the second servo, the current signal ADI-DJ1 of the first servo and the current signal ADI-DJ2 of the second servo, and sends them to the processor circuit; the processor circuit uses a timer interrupt program to sample the voltage signal ADV-DJ1 of the first servo, the voltage signal ADV-DJ2 of the second servo, the current signal ADI-DJ1 of the first servo and the current signal ADI-DJ2 of the second servo, and calculates the voltage and current values ​​of DJ1 and DJ2.

[0151] Step 11: The ignition voltage and current detection and conditioning circuit conditions the ignition power supply and sends it to the ignition timing control device of the missile equipment; at the same time, it collects the ignition voltage signal ADV-DH and the ignition current signal ADI-DH and sends them to the processor circuit; the processor circuit completes the sampling of the ignition voltage signal ADV-DH and the ignition current signal ADI-DH and the calculation of the DH voltage and current values ​​by the timer interrupt program.

[0152] Step 12: The RS422 isolation interface circuit connects the processor circuit's SCI port to the external RS422 network, enabling communication with the external monitoring center according to the communication protocol.

[0153] The processor circuit of the missile-borne solid-state power conversion module adopts an embedded foreground and background program architecture, in which the foreground consists of a timer interrupt program and an SCI receive interrupt program, and the background is the main program.

[0154] 1) Main program, such as Figure 9 As shown.

[0155] After a normal processor circuit reset, its program pointer will point to the main program. The main program consists of a system initialization section and a loop section. The system initialization section runs only once, mainly completing the self-test of the power-on module's hardware and the initialization of the processor's peripherals, including the aforementioned timer initialization and SCI initialization; the loop section of the main program loops infinitely before the processor circuit resets, polling and processing system tasks.

[0156] The main program processes system tasks through polling as follows:

[0157] Step 1: Determine whether the main program's time base has been accumulated.

[0158] On one hand, the processor circuit scans the OD-ZD signal output from the OD-ZD output terminal of the power conversion signal isolation detection circuit, the OD-JC signal output from the OD-JC output terminal, and the OD-FK signal output from the OD-FK output terminal of the power conversion feedback signal conditioning circuit. After a specified duration, it confirms that the corresponding instruction or status of the above signals is valid and stores it in memory for later use. On the other hand, it reads the memory data according to the reporting data frame format required by the missile host instruction and organizes it into a complete data frame for later use, and performs an accumulation operation on the communication duration.

[0159] The power transfer signal isolation detection circuit obtains the OD-ZD signal based on the power transfer control signal XZD and the OD-JC signal based on the power transfer release signal XJC. The processor circuit determines whether the duration of the OD-ZD signal corresponding to the power transfer control signal XZD and the OD-JC signal corresponding to the power transfer release signal XJC reaches a preset value: if the duration reaches the preset value, the power transfer control signal XZD or the power transfer release signal XJC is considered valid, and the circuit controls the connection or disconnection of the VH solid-state power circuit and the VL solid-state power circuit accordingly. Otherwise, the power transfer control signal XZD or the power transfer release signal XJC is considered invalid.

[0160] The preset duration is set in hardware by the first and second delay filter circuits of the control logic circuit, and in software by the program of the processor circuit. The time set by both should generally be within an acceptable range of accuracy.

[0161] To eliminate the influence of leakage current from solid-state power switches, the software considers the actual power transfer control output factor when calculating VL and VH voltages. When the power transfer control signal XZD is invalid, the zero-voltage threshold for VL and VH voltages is increased; that is, when the voltage detection result is lower than a certain threshold, the software sets the reported voltage detection value to 0V.

[0162] Step 2: Determine whether the reported data frames have been completely reported.

[0163] The processor circuit sets a counter for the data frame reporting bytes. The counter increments by 1 for each reported byte. After the entire frame data reporting is completed, i.e., the check byte at the end of the frame is successfully sent, the counter reaches its maximum value. The counter is reset to zero when the onboard host instruction is successfully received again after the SCI receive interrupt. If a reporting failure occurs during the reporting of the data frame, the communication duration is incremented.

[0164] Step 3: Determine if there is a communication problem.

[0165] The processor circuit determines whether communication is abnormal based on the cumulative communication duration: if the duration exceeds the set threshold, it is considered to be abnormal and set to a communication abnormal state; otherwise, the communication abnormal state is cleared.

[0166] The communication duration is driven by the main program time base and the number of reported data failures, and can only be cleared when the SCI successfully receives the instructions from the onboard host.

[0167] 2) Timer interrupt program, such as Figure 10 As shown.

[0168] When the main program initializes the system, it sets a timer to trigger a timer interrupt at time T. The interrupt handling system of the processor circuit responds to the timer interrupt and enters the timer interrupt routine. The timer interrupt routine processes fixed periodic tasks according to the set time T.

[0169] The process of a timer interrupt routine handling fixed-periodic tasks is as follows:

[0170] Step 1: The processor circuit clears the interrupt flag and enables the next timer interrupt.

[0171] Step 2: The processor circuit samples the ADI-DH and calculates the DH current value;

[0172] ADI-DH sampling is specifically implemented by the processor's ADC module. Generally, under the set ADC operating mode, the process follows the sequence of starting ADC conversion → waiting for ADC conversion to complete → reading the ADC conversion result → storing the result in a buffer → filtering the data in the buffer to obtain the analog-to-digital conversion value that can be used to calculate the ignition current value. Then, based on the coefficient relationship between the analog-to-digital conversion value and the actual physical quantity, the actual ignition current of this sampling is calculated.

[0173] Step 3: The processor circuit increments the processing stage identifier "step" and performs overflow prevention.

[0174] The processing stage identifier `step` is used to control processing tasks with different timing periods. This invention specifies that the value range of the processing stage identifier `step` is 0 to 9, meaning there are 10 processing stages. Each time a timer interrupt occurs, the processing stage identifier `step` is incremented by 1, and when the value of `step` is greater than 9, it is set to 0. This is a process for incrementing the processing stage identifier `step` and preventing overflow.

[0175] Step 4: The processor circuit processes the tasks of each stage according to the step identifier value.

[0176] The specific tasks of the 10 processing stages of this invention are shown in Table 2:

[0177] step value Tasks in this phase 0 ADV-VL sampling and calculation of VL voltage value 1 ADI-VL samples and calculates the VL current value. 2 ADV-VH sampling and calculation of VH voltage value 3 ADI-VH samples and calculates the VH current value. 4 ADV-DJ1 samples and calculates DJ1 voltage values. 5 ADV-DJ2 samples and calculates DJ2 voltage values. 6 ADI-DJ1 samples and calculates DJ1 current value. 7 ADI-DJ2 samples and calculates DJ2 current values. 8 ADV-DH sampling and calculation of DH voltage value 9 Main program time base processing

[0178] Table 2

[0179] The processing task descriptions for the nine stages, with step values ​​ranging from 0 to 8, can be found in the description of ADI-DH sampling and ignition current calculation mentioned above.

[0180] In the processing stage where the step value is 9, the main program performs time base processing. Specifically, a flag is set to notify the main program that approximately 10 times the duration T has elapsed, requiring the execution of power transfer commands, status processing, and data reporting. The sampling frequency of the ignition current is 10 times that of other physical quantities such as voltage and current, ensuring a sufficient sampling rate for the ignition current and effectively monitoring the details of ignition current fluctuations.

[0181] 3) SCI receive interrupt routine, such as Figure 11 As shown.

[0182] When the main program initializes the system, it requests SCI according to the communication protocol and enables the receive interrupt. After receiving data, the processor circuit interrupts the system to respond to the receive interrupt and enters the SCI receive interrupt routine.

[0183] The SCI receive interrupt procedure is as follows:

[0184] Step 1: The processor circuit clears the interrupt flag to enable the next SCI receive interrupt.

[0185] Step 2: The processor circuit determines the meaning of the received characters according to the communication protocol and performs corresponding processing.

[0186] The communication method is determined by the hardware circuit to be RS422, the processor cycle is approximately 12 times T, the baud rate is approximately 1 Mbps, and the communication error rate does not exceed 1 × 10⁻⁶. -6 The byte check uses odd parity, and the data frame check uses cumulative checksum. Each byte of data has a format of 1 start bit, 8 data bits, 1 odd parity bit, and 1 stop bit, for a total of 11 bits. When multiple bytes need to be transmitted, the high byte comes first, followed by the low byte.

[0187] All communication is conducted via a host-initiated, power-transfer module-responded approach. Host commands are divided into two categories: onboard host commands, which are query commands during normal operation; and debug host commands, which are debug commands during production testing.

[0188] The missile-borne host instruction is set to one, consisting of two bytes. The first byte is the frame header, tentatively set to 0xAA; the second byte is the checksum byte, which, when summed, also results in 0xAA. That is, after the transfer module receives consecutive "0xAA, 0xAA", it considers that the missile-borne host has issued a query instruction and needs to report data as required. Specific data reporting rules are shown in Table 3.

[0189]

[0190]

[0191] Table 3

[0192] Multiple debugging host commands are set, and to distinguish them from onboard host commands, each command consists of at least four bytes. The first byte is fixed at 0x55, the second byte is the number of data bytes in the current frame, the third byte is the command type, and the last byte is a checksum byte. Specific data reporting requirements are shown in Table 4.

[0193]

[0194] Table 4

[0195] The specific content of the missile-borne host command and the debugging host command, as well as the corresponding command response requirements, can be easily expanded and improved based on the above description, and will not be repeated here.

[0196] This invention utilizes solid-state power devices and ideal diodes to achieve power transfer control. Simultaneously, it employs hardware logic circuitry and processor control output to implement redundant processing of power transfer control commands, ensuring the reliability of power transfer control. Furthermore, the processor circuitry, in conjunction with sufficient current and voltage detection and conditioning circuitry, achieves comprehensive and effective monitoring of the power transfer status, and timely reporting of the power transfer monitoring status is realized through a high-speed RS422 communication network.

[0197] It should be noted that although the embodiments described above are illustrative, they are not intended to limit the invention. Therefore, the invention is not limited to the specific embodiments described above. Any other embodiments obtained by those skilled in the art under the guidance of this invention without departing from its principles are considered to be within the protection scope of this invention.

Claims

1. A missile-borne solid-state power conversion module, characterized in that, It consists of a VH solid-state power circuit, a VH voltage and current detection and conditioning circuit, a VH anti-reverse circuit, a VL solid-state power circuit, a VL voltage and current detection and conditioning circuit, a VL anti-reverse circuit, a servo voltage and current detection and conditioning circuit, an ignition voltage and current detection and conditioning circuit, a transfer signal isolation detection circuit, a transfer feedback signal conditioning circuit, a control logic processing circuit, an isolation drive circuit, a processor circuit, an RS422 isolation interface circuit, and a filter isolation power supply circuit. The positive terminal of the high-voltage battery is connected to the VHIN input terminal of the VH solid-state power circuit; the S-VH output terminal of the VH solid-state power circuit is connected to the S-VH input terminal of the VH voltage and current detection and conditioning circuit, and the high-voltage power supply ground is connected to the VHGND input terminal of the VH voltage and current detection and conditioning circuit; the S'-VH output terminal of the VH voltage and current detection and conditioning circuit is connected to the S'-VH input terminal of the VH reverse protection circuit, and the VHOUT output terminal of the VH reverse protection circuit is connected to the positive terminal of the ground high-voltage power supply; the ADV-VH output terminal and ADI-VH output terminal of the VH voltage and current detection and conditioning circuit are respectively connected to the two AD ports of the processor circuit. The positive terminal of the low-voltage battery is connected to the VLIN input terminal of the VL solid-state power circuit; the S-VL output terminal of the VL solid-state power circuit is connected to the S-VL input terminal of the VL voltage and current detection and conditioning circuit, and the low-voltage power supply ground is connected to the VLGND input terminal of the VL voltage and current detection and conditioning circuit; the S'-VL output terminal of the VL voltage and current detection and conditioning circuit is connected to the S'-VL input terminal of the VL reverse protection circuit, and the VLOUT output terminal of the VL reverse protection circuit is connected to the positive terminal of the ground low-voltage power supply; the ADV-VL output terminal and ADI-VL output terminal of the VL voltage and current detection and conditioning circuit are respectively connected to the two AD ports of the processor circuit. The positive terminal of the first servo power supply is connected to the VDJ1IN input terminal of the servo voltage and current detection and conditioning circuit; the positive terminal of the second servo power supply is connected to the VDJ2IN input terminal of the servo voltage and current detection and conditioning circuit; the servo power ground is connected to the VDJGND input terminal of the servo voltage and current detection and conditioning circuit; the VDJ1OUT output terminal of the servo voltage and current detection and conditioning circuit is connected to the positive terminal of the first servo load; the VDJ2OUT output terminal of the servo voltage and current detection and conditioning circuit is connected to the positive terminal of the second servo load; the ADV-DJ1, ADV-DJ2, ADI-DJ1, and ADI-DJ2 output terminals of the servo voltage and current detection and conditioning circuit are respectively connected to the four AD ports of the processor circuit. The ignition current input terminal is connected to the VDHIN input terminal of the ignition voltage and current detection and conditioning circuit; the ignition power ground is connected to the VDHGND input terminal of the ignition voltage and current detection and conditioning circuit; the VDHOUT output terminal of the ignition voltage and current detection and conditioning circuit is connected to the ignition current output terminal; the ADV-DH output terminal and ADI-DH output terminal of the ignition voltage and current detection and conditioning circuit are respectively connected to the two AD ports of the processor circuit. The power transfer control signal is connected to the XZD input terminal of the power transfer signal isolation detection circuit, the power transfer release signal is connected to the XJC input terminal of the power transfer signal isolation detection circuit, and the low-voltage power supply ground is connected to the VLGND input terminal of the power transfer signal isolation detection circuit. The OD-ZD and OD-JC output terminals of the electrical signal isolation detection circuit are respectively connected to two I / O ports of the processor circuit; The S-VL output terminal of the VL solid-state power circuit is connected to the S-VL input terminal of the power conversion feedback signal conditioning circuit, and the low-voltage power supply ground is connected to the VLGND input terminal of the power conversion feedback signal conditioning circuit. The A output terminal of the power feedback signal conditioning circuit is connected to the A input terminal of the external monitoring center, the B output terminal of the power feedback signal conditioning circuit is connected to the B input terminal of the external monitoring center, and the OD-FK output terminal of the power feedback signal conditioning circuit is connected to an I / O port of the processor circuit. The ZD1, ZD2, JC1, and JC2 input terminals of the control logic processing circuit are connected to the four I / O ports of the processor circuit, respectively. The OD-ZD and OD-JC output terminals of the electrical signal isolation detection circuit are connected to the OD-ZD and OD-JC input terminals of the control logic processing circuit, respectively. The DRI output terminal of the control logic processing circuit is connected to the DRI input terminal of the isolation drive circuit. The S-VH output and DRI-VH output of the isolation drive circuit are connected to the S-VH input and DRI-VH input of the VH solid-state power circuit, respectively; the S-VL output and DRI-VL output of the isolation drive circuit are connected to the S-VL input and DRI-VL input of the VL solid-state power circuit, respectively. The SCI port of the processor circuit is connected to the TXD and RXD communication terminals of the RS422 isolation interface circuit; the 422-A and 422-B receive signal terminals, the 422-Y and 422-Z transmit signal terminals, and the 422-GND shielding ground terminal of the RS422 isolation interface circuit are connected to the external RS422 bus network. The positive terminal of the low-voltage power supply is connected to the VLOUT input terminal of the filter isolation power supply circuit, and the low-voltage power supply ground is connected to the VLGND input terminal of the filter isolation power supply circuit; the output terminal of the filter isolation power supply circuit is connected to the internal working power supply.

2. The missile-borne solid-state power conversion module according to claim 1, characterized in that, The control logic processing circuit consists of a first processor control signal confirmation circuit, a first delay filter circuit, a first hysteresis comparator circuit, a second processor control signal confirmation circuit, a second delay filter circuit, a second hysteresis comparator circuit, a reference voltage circuit, common cathode diodes D1 to D2, a reset priority RS flip-flop circuit, and a control signal power amplifier circuit. The input terminals of the first processor control signal confirmation circuit form the ZD1 and ZD2 input terminals of the control logic processing circuit; the input terminal of the first delay filter circuit forms the OD-ZD input terminal of the control logic processing circuit; the output terminal of the first delay filter circuit is connected to one input terminal of the first hysteresis comparator circuit; the input terminals of the second processor control signal confirmation circuit form the JC1 and JC2 input terminals of the control logic processing circuit; the input terminal of the second delay filter circuit forms the OD-ZD input terminal of the control logic processing circuit. The JC input terminal; the output terminal of the second delay filter circuit is connected to one input terminal of the second hysteresis comparator circuit; the output terminal of the reference voltage circuit is connected to the other input terminal of the first hysteresis comparator circuit and the second hysteresis comparator circuit; the output terminals of the first processor control signal confirmation circuit and the first hysteresis comparator circuit are respectively connected to the two anodes of the common cathode diode D1, and the cathode of the common cathode diode D1 is connected to one input terminal of the reset priority RS flip-flop circuit; the output terminals of the second processor control signal confirmation circuit and the second hysteresis comparator circuit are respectively connected to the two anodes of the common cathode diode D2, and the cathode of the common cathode diode D2 is connected to the other input terminal of the reset priority RS flip-flop circuit; the output terminal of the reset priority RS flip-flop circuit is connected to the input terminal of the control signal power amplifier circuit, and the output terminal of the control signal power amplifier circuit forms the DRI output terminal of the control logic processing circuit.

3. The missile-borne solid-state power conversion module according to claim 1, characterized in that, The isolated drive circuit consists of a high-voltage high-frequency oscillation circuit, a high-voltage transformer, a high-voltage rectifier, filter, limiter and release circuit, a high-voltage drive signal distribution circuit, a low-voltage high-frequency oscillation circuit, a low-voltage transformer, a low-voltage rectifier, filter, limiter and release circuit, and a low-voltage drive signal distribution circuit. The input terminals of the high-voltage high-frequency oscillation circuit and the low-voltage high-frequency oscillation circuit together form the DRI input terminal of the isolated drive circuit. The output terminal of the high-voltage high-frequency oscillation circuit is connected to the primary winding of the high-voltage transformer. The secondary winding of the high-voltage transformer is connected to the input terminal of the high-voltage rectifier, filter, limiting, and release circuit. The output terminal of the high-voltage rectifier, filter, limiting, and release circuit is connected to the input terminal of the high-voltage drive signal distribution circuit. The output terminal of the high-voltage drive signal distribution circuit forms the S-VH output terminal and the DRI-VH output terminal of the isolated drive circuit. The output terminal of the low-voltage high-frequency oscillation circuit is connected to the primary winding of the low-voltage transformer. The secondary winding of the low-voltage transformer is connected to the input terminal of the low-voltage rectifier, filter, limiting, and release circuit. The output terminal of the low-voltage rectifier, filter, limiting, and release circuit is connected to the input terminal of the low-voltage drive signal distribution circuit. The output terminal of the low-voltage drive signal distribution circuit forms the S-VL output terminal and the DRI-VL output terminal of the isolated drive circuit.

4. The missile-borne solid-state power conversion module according to claim 3, characterized in that, Both the high-voltage and low-voltage transformers are on-board transformers. These on-board transformers use a multi-layer printed circuit board design, where coils with fewer turns are placed in the middle layer, and coils with more turns are arranged in adjacent layers above and below.

5. The method for operating a missile-borne solid-state power conversion module as described in claim 1, characterized in that, The steps include the following: Step 1: The power transfer signal isolation detection circuit obtains the corresponding power transfer control isolation detection signal OD-ZD and power transfer release isolation detection signal OD-JC based on the power transfer control signal XZD and power transfer release signal XJC sent from the external monitoring center, and sends them to the processor circuit and control logic processing circuit. Step 2: The processor circuit detects the validity of the power transfer control signal XZD based on the power transfer control isolation detection signal OD-ZD, and obtains the first power transfer control signal ZD1 and the second power transfer control signal ZD2 according to the detection result; The processor circuit detects the validity of the power transfer release signal XJC based on the power transfer release isolation detection signal OD-JC, and obtains the first power transfer release signal JC1 and the second power transfer release signal JC2 according to the detection result, and sends them to the control logic processing circuit. Step 3: The control logic processing circuit first performs a logical XOR operation on the first power transfer control signal ZD1 and the second power transfer control signal ZD2 to obtain the power transfer control XOR result. Then, it performs a logical OR operation on the power transfer control XOR result and the power transfer control isolation detection signal OD-ZD to obtain the power transfer control drive signal DRI. The control logic processing circuit first performs a logical XOR operation on the first power transfer release signal JC1 and the second power transfer release signal JC2 to obtain the power transfer release XOR result. Then, it performs a logical OR operation on the power transfer release isolation detection signal OD-JC to obtain the power transfer release drive signal DRI. Step 4: The isolation drive circuit first processes the drive signal DRI to obtain the high-voltage solid-state power transistor drive signal DRI-VH and its reference signal S-VH, as well as the low-voltage solid-state power transistor drive signal DRI-VL and its reference signal S-VL. Then, according to the number of high-voltage solid-state power transistors in the VH solid-state power circuit, the high-voltage solid-state power transistor drive signal DRI-VH is allocated and sent to the VH solid-state power circuit together with its reference signal S-VH. At the same time, according to the number of low-voltage solid-state power transistors in the VL solid-state power circuit, the low-voltage solid-state power transistor drive signal DRI-VL is allocated and sent to the VL solid-state power circuit together with its reference signal S-VL. Step 5: The working processes of the VH solid-state power circuit and the VL solid-state power circuit are as follows: When the voltage of the high-voltage solid-state power transistor drive signal DRI-VH relative to its reference signal S-VH exceeds the gate threshold voltage of the high-voltage solid-state power transistor in the VH solid-state power circuit, the VH solid-state power circuit is turned on; when the voltage of the high-voltage solid-state power transistor drive signal DRI-VH relative to its reference signal S-VH is 0V, the VH solid-state power circuit is turned off. When the voltage of the low-voltage solid-state power transistor drive signal DRI-VL relative to its reference signal S-VL exceeds the gate threshold voltage of the low-voltage solid-state power transistor in the VL solid-state power circuit, the VL solid-state power circuit is turned on; when the voltage of the low-voltage solid-state power transistor drive signal DRI-VL relative to its reference signal S-VL is 0V, the VL solid-state power circuit is turned off. Step 6: The working processes of the VH voltage and current detection and conditioning circuit and the VL voltage and current detection and conditioning circuit are as follows: When the VH solid-state power circuit is turned on, the VH voltage and current detection and conditioning circuit conditions the signal output by the VH solid-state power circuit and sends it to the VH anti-reverse circuit; at the same time, the VH voltage and current detection and conditioning circuit acquires the high voltage signal ADV-VH and the high voltage current signal ADI-VH and sends them to the processor circuit; the processor circuit completes the sampling of the high voltage signal ADV-VH and the high voltage current signal ADI-VH, as well as the calculation of the VH voltage and current values; When the VL solid-state power circuit is turned on, the VL voltage and current detection and conditioning circuit conditions the signal output by the VL solid-state power circuit and sends it to the VL anti-reverse circuit; at the same time, the VL voltage and current detection and conditioning circuit acquires the low-voltage signal ADV-VL and the low-voltage current signal ADI-VL and sends them to the processor circuit; the processor circuit completes the sampling of the low-voltage signal ADV-VL and the low-voltage current signal ADI-VL, as well as the calculation of the VL voltage and current values; Step 7: The working processes of the VH anti-reverse circuit and the VL anti-reverse circuit are as follows: The VH anti-reverse circuit prevents current backflow when the high-voltage battery voltage is lower than the ground high-voltage power supply voltage, and seamlessly switches the downstream high-voltage power supply to the high-voltage battery when the high-voltage battery voltage is higher than the ground high-voltage power supply voltage. The VL anti-reverse circuit prevents current backflow when the low-voltage battery voltage is lower than the ground low-voltage power supply voltage, and seamlessly switches the downstream low-voltage power supply to the low-voltage battery when the low-voltage battery voltage is higher than the ground low-voltage power supply voltage. Step 8: The power transfer feedback signal conditioning circuit detects the actual on / off state of the VL solid-state power circuit, sends power transfer feedback signal A and power transfer feedback signal B to the external monitoring center, and sends feedback signal OD-FK to the processor circuit; the processor circuit detects the feedback signal OD-FK and updates the detection result to the corresponding status bit in memory. Step 9: The filter isolation power supply circuit is powered by the ground low-voltage power supply. After the low-voltage power conversion is completed, the internal working power supply of the missile equipment is switched to low-voltage battery power supply. Step 10: The servo voltage and current detection and conditioning circuit conditions the power supply of the first servo and sends it to the load of the first servo in the missile-borne equipment, and conditions the power supply of the second servo and sends it to the load of the second servo in the missile-borne equipment; at the same time, the servo voltage and current detection and conditioning circuit collects the voltage signal ADV-DJ1 of the first servo, the voltage signal ADV-DJ2 of the second servo, the current signal ADI-DJ1 of the first servo and the current signal ADI-DJ2 of the second servo, and sends them to the processor circuit; the processor circuit completes the sampling of the voltage signal ADV-DJ1 of the first servo, the voltage signal ADV-DJ2 of the second servo, the current signal ADI-DJ1 of the first servo and the current signal ADI-DJ2 of the second servo, and calculates the voltage and current values ​​of DJ1 and DJ2; Step 11: The ignition voltage and current detection and conditioning circuit conditions the ignition power supply and sends it to the ignition timing control device of the onboard equipment; at the same time, the ignition voltage and current detection and conditioning circuit collects the ignition voltage signal ADV-DH and the ignition current signal ADI-DH and sends them to the processor circuit; the processor circuit completes the sampling of the ignition voltage signal ADV-DH and the ignition current signal ADI-DH, as well as the calculation of the DH voltage and current values; Step 12: The RS422 isolation interface circuit connects the processor circuit's SCI port to the external RS422 network and enables communication with the external monitoring center according to the communication protocol.

6. The method for operating a missile-borne solid-state power conversion module as described in claim 5, characterized in that, The specific process of step 2 is as follows: Step 2.1: The processor circuit performs a periodic scan of the power transfer control isolation detection signal OD-ZD to obtain the level state of the power transfer control isolation detection signal OD-ZD: if the power transfer control isolation detection signal OD-ZD is high, then the high level count value of the power transfer control isolation detection signal OD-ZD is incremented by 1; otherwise, the high level count value of the power transfer control isolation detection signal OD-ZD is decremented by 2. Step 2.2: The processor circuit judges the high-level count value of the power transfer control isolation detection signal OD-ZD: if it exceeds the set threshold, it is considered that the power transfer control command needs to be executed, and the first power transfer control signal ZD1 output by the processor circuit is high level and the second power transfer control signal ZD2 is low level; otherwise, the first power transfer control signal ZD1 and the second power transfer control signal ZD2 output by the processor circuit are both low level. Step 2.3: The processor circuit performs a periodic scan of the power-off isolation release detection signal OD-JC to obtain the level state of the power-off isolation release detection signal OD-JC: if the power-off isolation release detection signal OD-JC is high, then the high-level count value of the power-off isolation release detection signal OD-JC is incremented by 1; otherwise, the high-level count value of the power-off isolation release detection signal OD-JC is decremented by 2. Step 2.4: The processor circuit judges the high-level count value of the power-off isolation detection signal OD-JC: if it exceeds the set threshold, it is considered that the power-off release command needs to be executed, and the first power-off release signal JC1 output by the processor circuit is high level and the second power-off release signal JC2 is low level; otherwise, the first power-off release signal JC1 and the second power-off release signal JC2 output by the processor circuit are both low level.

7. The method for operating a missile-borne solid-state power conversion module as described in claim 5, characterized in that, The processor circuit adopts an embedded foreground and background program architecture, where the foreground consists of a timer interrupt program and an SCI receive interrupt program, and the background is the main program. After the processor circuit is reset normally, its program pointer points to the main program; the main program consists of a system initialization part and a loop part; the system initialization part runs only once, mainly to complete the self-test of the hardware part of the missile-borne solid-state power conversion module and the initialization of each peripheral of the processor circuit, as well as the timing initialization and SCI communication initialization; the loop part loops infinitely before the processor circuit is reset, polling and processing system tasks. When the main program initializes the system, it sets a timer to trigger a timer interrupt at a set time T. The interrupt handling system of the processor circuit responds to the timer interrupt and enters the timer interrupt routine. When the main program initializes the system, it performs SCI communication according to the communication protocol requirements and enables the receive interrupt. After receiving data, the processor circuit interrupts the system response to the receive interrupt and enters the SCI receive interrupt routine.

8. The method for operating a missile-borne solid-state power conversion module as described in claim 7, characterized in that, The main program processes system tasks through polling as follows: Step 1: The processor circuit scans the power transfer control isolation detection signal OD-ZD output from the power transfer signal isolation detection circuit, the power transfer release isolation detection signal OD-JC output from the OD-ZD output from the OD-JC output from the OD-JC output from the OD-JC output from the power transfer signal isolation detection circuit, and the feedback signal OD-FK output from the OD-FK output from the power transfer feedback signal conditioning circuit. After a specified duration, it confirms that the corresponding instruction or state of the above signals is valid and stores it in memory for later use. On the other hand, it reads the memory data according to the reporting data frame format required by the missile host instruction and organizes it into a complete data frame for later use, and performs an accumulation operation on the communication duration. Step 2: The processor circuit sets a counter for the data frame reporting bytes. The counter increments by 1 for each reported byte. After the entire frame data reporting is completed and the check byte at the end of the frame is successfully sent, the counter reaches its maximum value. The counter is reset to zero when the onboard host command is successfully received again after the SCI receive interrupt. If a reporting failure occurs during the data frame reporting process, the communication duration is incremented. Step 3: The processor circuit determines whether SCI communication is abnormal based on the cumulative communication duration: if it exceeds the set threshold, it is considered to be abnormal and set to the abnormal communication state; otherwise, the abnormal communication state is cleared.

9. The method for operating a missile-borne solid-state power conversion module as described in claim 7, characterized in that, The process of the timer interrupt routine is as follows: Step 1: The processor circuit clears the interrupt flag and enables the next timer interrupt; Step 2: The processor circuit samples the ignition current signal ADI-DH and calculates the DH current value; Step 3: The processor circuit increments the processing stage identifier "step" and performs overflow prevention processing. Step 4: The processor circuit performs task processing for each stage according to the step identifier value, including sampling and calculating the VL voltage value of the low voltage signal ADV-VL, sampling and calculating the VL current value of the low voltage signal ADI-VL, sampling and calculating the VH voltage value of the high voltage signal ADV-VH, sampling and calculating the VH current value of the high voltage signal ADI-VH, sampling and calculating the DJ1 voltage value of the first servo's voltage signal ADV-DJ1, sampling and calculating the DJ2 voltage value of the second servo's voltage signal ADV-DJ2, sampling and calculating the DJ2 current value of the second servo's current signal ADI-DJ2, sampling and calculating the DH voltage value of the ignition voltage signal ADV-DH, and main program time base processing.

10. The method for operating a missile-borne solid-state power conversion module as described in claim 7, characterized in that, The SCI receive interrupt procedure is as follows: Step 1: The processor circuit clears the interrupt flag to enable the next SCI receive interrupt; Step 2: The processor circuit determines the meaning of the received characters according to the communication protocol and performs corresponding processing; All communication is initiated by the onboard host or the debugging host, and responded by the onboard solid-state power conversion module. The onboard host commands initiated by the onboard host are query commands during normal operation, while the debugging host commands initiated by the debugging host are debugging commands during production testing.

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