Driving method of liquid crystal display panel and liquid crystal display panel

Abstract

A liquid crystal display panel and a driving method of the liquid crystal display panel. The liquid crystal display panel comprises a pixel array, each sub-pixel is connected to a corresponding gate line and a corresponding data line, and the driving method comprises: providing a first gate signal to a first gate line corresponding to a first row of sub-pixels in the plurality of rows of sub-pixels, the first gate signal comprising an opening period and a closing period, for controlling the first row of sub-pixels to be opened and closed respectively (S10); in the opening period of the first gate signal, a plurality of first data signals are written to a plurality of sub-pixels of the first row of sub-pixels through a plurality of data lines respectively, wherein the plurality of first data signals comprise positive polarity data signals and negative polarity data signals, and the first writing time length of the negative polarity data signals is less than the second writing time length of the positive polarity data signals in the opening period of the first gate signal (S20). The driving method can improve the picture quality and the quality of the liquid crystal display panel.

Description

LCD panel driving method and LCD panel Technical Field

[0001] The embodiments of this disclosure relate to a driving method for a liquid crystal display panel and a liquid crystal display panel. Background Technology

[0002] With the rapid development of display technology, display panels are increasingly moving towards higher integration and lower cost. Liquid Crystal Display (LCD) panels are a high-tech field that has developed rapidly in the last two decades. Due to their advantages such as being thinner and lighter, having low radiation, high contrast, fast response speed, and low power consumption, they have been widely used in flat panel display devices. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a driving method for a liquid crystal display panel, wherein the liquid crystal display panel includes a pixel array, the pixel array includes multiple gate lines, multiple data lines, and multiple sub-pixels, the multiple sub-pixels are arranged in multiple rows and multiple columns, each gate line provides a gate signal for at least one row of sub-pixels, each data line provides a data signal for at least one column of sub-pixels, and each sub-pixel is connected to a corresponding gate line and a corresponding data line. The driving method includes: providing a first gate signal to a first gate line corresponding to a first row of sub-pixels in the multiple rows of sub-pixels, wherein the first gate signal includes an on period and an off period, used to control the first row of sub-pixels to be turned on and off respectively; during the on period of the first gate signal, writing multiple first data signals to the multiple sub-pixels of the first row of sub-pixels respectively through the multiple data lines, wherein the multiple first data signals include positive polarity data signals and negative polarity data signals, and during the on period of the first gate signal, the first writing time length of the negative polarity data signal is less than the second writing time length of the positive polarity data signal.

[0004] For example, in a driving method provided in an embodiment of this disclosure, the delay time of the negative polarity data signal relative to the start time point of the turn-on period corresponding to the first gate signal is a first time length, and the delay time of the positive polarity data signal relative to the start time point of the turn-on period corresponding to the first gate signal is a second time length. The first time length is greater than the second time length, such that when the first gate signal is in the turn-on period, the first write time length of the negative polarity data signal is less than the second write time length of the positive polarity data signal.

[0005] For example, in a driving method provided in one embodiment of this disclosure, the start time point of the turn-on period corresponding to the negative polarity data signal relative to the first gate signal is the same as or different from the start time point of the turn-on period corresponding to the positive polarity data signal relative to the first gate signal.

[0006] For example, in a driving method provided in an embodiment of this disclosure, the first gate signal further includes a transition period located between adjacent on and off periods, the first time length being longer than the second time length by a preset time length, the preset time length being the difference between the write time length of the negative polarity data signal and the write time length of the positive polarity data signal during the transition period of the first gate signal.

[0007] For example, in a driving method provided in an embodiment of this disclosure, each data line provides a data signal to two adjacent columns of sub-pixels. During the on period of the first gate signal, each data line provides a positive polarity data signal and a negative polarity data signal to a first sub-pixel and a second sub-pixel located in two adjacent columns of the same row, respectively. The on period of the first gate signal includes a first sub-on period and a second sub-on period. The positive polarity data signal is applied to the first sub-pixel during the first sub-on period, and the negative polarity data signal is applied to the second sub-pixel during the second sub-on period. The duration of the first sub-on period is greater than the duration of the second sub-on period.

[0008] For example, in a driving method provided in an embodiment of this disclosure, each sub-pixel further includes a pixel electrode, and each data line provides the positive polarity data signal to the pixel electrode of the first sub-pixel through a first multiplexing switching element, and provides the negative polarity data signal to the pixel electrode of the second sub-pixel through a second multiplexing switching element.

[0009] For example, in a driving method provided in an embodiment of this disclosure, the first multiplexing switching element is connected to a first control line to receive a first control signal provided by the first control line, and the first multiplexing switching element is configured to turn on and off in response to the control of the first control signal. The second multiplexing switching element is connected to a second control line to receive a second control signal provided by the second control line, and the second multiplexing switching element is configured to turn on and off in response to the control of the second control signal.

[0010] For example, in a driving method provided in an embodiment of this disclosure, the first sub-on period and the second sub-on period are the same as the on-time period of the first multiplexing switching element and the on-time period of the second multiplexing switching element, respectively.

[0011] For example, in a driving method provided in an embodiment of this disclosure, a first multiplexing switching element and a second multiplexing switching element are disposed around the periphery of the liquid crystal display panel, a column of sub-pixels containing the first sub-pixel shares the first multiplexing switching element, and a column of sub-pixels containing the second sub-pixel shares the second multiplexing switching element.

[0012] For example, in a driving method provided in one embodiment of this disclosure, the first multiplexing switching element is disposed in the first sub-pixel, and the second multiplexing switching element is disposed in the second sub-pixel.

[0013] For example, in a driving method provided in an embodiment of this disclosure, each sub-pixel further includes a pixel switching element connected to a corresponding gate line to receive a gate signal provided by the corresponding gate line. The pixel switching element in the first sub-pixel is connected in series with the first multiplexing switching element between the data line and the pixel electrode. The pixel switching element in the second sub-pixel is connected in series with the second multiplexing switching element between the data line and the pixel electrode.

[0014] At least one embodiment of this disclosure provides a liquid crystal display panel, including a pixel array. The pixel array includes multiple gate lines, multiple data lines, and multiple sub-pixels. The multiple sub-pixels are arranged in multiple rows and columns. Each gate line provides a gate signal to a row of sub-pixels, and each data line provides a data signal to two adjacent columns of sub-pixels. Each sub-pixel is connected to a corresponding gate line and a corresponding data line. A first gate line corresponding to a first row of sub-pixels is configured to provide a first gate signal to the first row of sub-pixels. The first gate signal includes an on period and an off period, used to control the first row of sub-pixels to be turned on and off respectively. Each data line is configured to provide a positive polarity data signal to a first sub-pixel in two adjacent columns and a positive polarity data signal to a second sub-pixel in two adjacent columns respectively during the on period of the first gate signal. A sub-pixel provides a negative polarity data signal. During the on period of the first gate signal, each data line is configured such that the first write time length of the negative polarity data signal is less than the second write time length of the positive polarity data signal. The on period of the first gate signal includes a first sub-on period and a second sub-on period. During the on period of the first gate signal, each data line is configured such that the first write time length of the negative polarity data signal is less than the second write time length of the positive polarity data signal, including: the positive polarity data signal is applied to the first sub-pixel during the first sub-on period, and the negative polarity data signal is applied to the second sub-pixel during the second sub-on period, wherein the duration of the first sub-on period is greater than the duration of the second sub-on period.

[0015] For example, in a liquid crystal display panel provided in an embodiment of this disclosure, each sub-pixel further includes a pixel electrode, and each data line is electrically connected to the pixel electrode of the first sub-pixel through a first multiplexing switching element, and electrically connected to the pixel electrode of the second sub-pixel through a second multiplexing switching element.

[0016] For example, in a liquid crystal display panel provided in an embodiment of this disclosure, the first multiplexing switching element is connected to a first control line to receive a first control signal provided by the first control line. The first multiplexing switching element is configured to turn on and off in response to the control of the first control signal. The second multiplexing switching element is connected to a second control line to receive a second control signal provided by the second control line. The second multiplexing switching element is configured to turn on and off in response to the control of the second control signal.

[0017] For example, in a liquid crystal display panel provided in an embodiment of this disclosure, the first multiplexing switching element and the second multiplexing switching element are disposed around the periphery of the liquid crystal display panel, a column of sub-pixels containing the first sub-pixel shares the first multiplexing switching element, and a column of sub-pixels containing the second sub-pixel shares the second multiplexing switching element.

[0018] For example, in a liquid crystal display panel provided in an embodiment of this disclosure, the first multiplexing switching element is disposed in the first sub-pixel, and the second multiplexing switching element is disposed in the second sub-pixel.

[0019] For example, in a liquid crystal display panel provided in an embodiment of this disclosure, each sub-pixel further includes a pixel switching element. The pixel switching element is connected to a corresponding gate line to receive a gate signal provided by the corresponding gate line. The pixel switching element in the first sub-pixel is connected in series with the first multiplexing switching element between the data line and the pixel electrode. The pixel switching element in the second sub-pixel is connected in series with the second multiplexing switching element between the data line and the pixel electrode. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0021] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0022] Figure 1A shows the equivalent circuit of a sub-pixel in a liquid crystal display panel;

[0023] Figure 1B shows the equivalent circuit of a sub-pixel in another liquid crystal display panel;

[0024] Figure 1C shows a voltage waveform diagram driven by a common electrode DC voltage;

[0025] Figure 1D shows a partial timing diagram of gate signals and data signals;

[0026] Figure 1E shows a partial timing diagram of another gate signal and data signal;

[0027] Figure 2A shows a flowchart of a driving method provided by at least one embodiment of the present disclosure;

[0028] Figure 2B shows a schematic diagram of a pixel driving architecture for a liquid crystal display panel provided in at least one embodiment of the present disclosure;

[0029] Figures 2C and 2D illustrate a schematic diagram of a polarity reversal driving method provided by at least one embodiment of the present disclosure;

[0030] Figure 2E shows a timing diagram of a gate signal and a data signal provided in at least one embodiment of the present disclosure;

[0031] Figure 3A shows a schematic diagram of another pixel driving architecture of a liquid crystal display panel for an application driving method provided in at least one embodiment of the present disclosure;

[0032] Figures 3B and 3C illustrate a timing signal diagram provided by at least one embodiment of the present disclosure;

[0033] Figure 4 shows a partial schematic diagram of another pixel driving architecture of a liquid crystal display panel for an application driving method provided in at least one embodiment of the present disclosure;

[0034] Figure 5A shows a timing signal diagram of the Nth image frame provided in at least one embodiment of the present disclosure;

[0035] Figure 5B shows a timing signal diagram of the N+1th image frame provided in at least one embodiment of the present disclosure;

[0036] Figure 6 shows a schematic diagram of another pixel driving architecture of a liquid crystal display panel for an application driving method provided in at least one embodiment of the present disclosure;

[0037] Figure 7 illustrates another pixel driving architecture of a liquid crystal display panel for an application driving method provided in at least one embodiment of this disclosure; and

[0038] Figures 8A to 8D illustrate some other pixel driving architectures for a liquid crystal display panel applied to a driving method according to at least one embodiment of the present disclosure. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0040] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0041] In a liquid crystal display (LCD) panel, liquid crystal is a non-conductive dielectric layer, for example, sandwiched between pixel electrodes disposed on an array substrate and a common electrode disposed on a color filter substrate, or for example, covering pixel electrodes and a common electrode disposed on the array substrate and insulated from each other. The LCD panel includes a pixel array comprising multiple rows and columns of pixels. Each pixel, used to display a single pixel point in an image, includes multiple sub-pixels, each controlling the display of a specific primary color (e.g., red, green, blue). Figure 1A shows an equivalent circuit of a sub-pixel in one LCD panel. Figure 1B shows an equivalent circuit of a sub-pixel in another LCD panel.

[0042] As shown in Figures 1A and 1B, a sub-pixel includes a pixel switching element T0 and a liquid crystal capacitor C. LC and storage capacitor C ST The pixel switching element T0 can be, for example, a thin-film transistor, whose first electrode (e.g., drain) is electrically connected to the pixel electrode, its second electrode (e.g., source) is electrically connected to the data line corresponding to the pixel column where the sub-pixel is located, and its control electrode (e.g., gate) is electrically connected to the gate line corresponding to the pixel row where the sub-pixel is located. Liquid crystal molecules are located between the pixel electrode and the common electrode, forming a liquid crystal capacitor C. LCIt is used to store the data signal written through the pixel switching element T0. Storage capacitor C ST It is formed by the overlap between a pixel electrode and a potential reference electrode. For example, depending on the potential reference electrode, the storage capacitor has two structural forms. One is to use a common electrode as the potential reference electrode, called C. ST -on-COM, as shown in Figure 1A. Another approach uses the gate line above (or below) the pixel as the potential reference electrode, called C. sT -on-Gate, as shown in Figure 1B.

[0043] During the operation of a liquid crystal display panel, in order to avoid polarization of the liquid crystal molecules, a voltage signal with alternating positive and negative polarities needs to be applied to the liquid crystal molecules to achieve AC driving of the liquid crystal molecules.

[0044] As shown in Figures 1A and 1B, if the potential of the common electrode remains constant, AC driving of the liquid crystal molecules is achieved by causing the potential of the other electrode of the liquid crystal capacitor (i.e., the pixel electrode) to fluctuate relative to the common electrode potential. This AC driving method is called common electrode DC voltage driving. In some other embodiments of this disclosure, if the AC driving of the liquid crystal molecules is achieved by the potential of the common electrode switching between image frames, this AC driving method is called common electrode voltage switching driving.

[0045] Figure 1C shows a voltage waveform diagram driven by a common electrode DC voltage.

[0046] As shown in Figure 1C, the voltage of the common electrode remains constant, while the voltage of the pixel electrode varies according to the different gray levels. Figure 1C illustrates the voltage waveform changes of the pixel electrode for 256 gray levels. For example, in the Nth image frame, the voltage of the common electrode is higher than the voltage of the pixel electrode, and the liquid crystal molecules are negatively polarized; in the (N+1)th image frame, the voltage of the common electrode is lower than the voltage of the pixel electrode, and the liquid crystal molecules are positively polarized. Whether positively or negatively polarized, the liquid crystal molecules can achieve different gray levels.

[0047] As shown in Figures 1A and 1B, the gate of pixel switching element T0 is connected to the gate line to receive the gate signal, and the source of pixel switching element T0 is connected to the data line to receive the data signal (also known as the "source signal"). The drain of pixel switching element T0 is connected to the pixel electrode. When the gate-source voltage Vgs of pixel switching element T0 is less than the threshold voltage Vth, pixel switching element T0 is turned off; when the gate-source voltage Vgs of pixel switching element T0 is greater than the threshold voltage Vth, pixel switching element T0 is turned on. Vgs = Vg - Vs, where Vg represents the gate voltage of pixel switching element T0 and Vs represents the source voltage of pixel switching element T0.

[0048] During the process of displaying images on a liquid crystal display panel, a voltage signal with alternating positive and negative polarity needs to be applied to the liquid crystal molecules to achieve AC driving of the liquid crystal molecules. However, this can easily lead to problems such as uneven display, image retention, and even negative polarity data misalignment on the liquid crystal display panel.

[0049] One or more embodiments of this disclosure provide a driving method to solve problems such as uneven display, image retention, and even negative polarity data misalignment that easily occur in liquid crystal display panels. After studying and analyzing liquid crystal display panels, the inventors of this disclosure discovered that the timing of the gate signal and data signal causes problems such as uneven display, image retention, and even negative polarity data misalignment in liquid crystal display panels, and therefore proposed this invention to solve these problems.

[0050] Figure 1D shows a partial timing diagram of the gate signal and data signal.

[0051] For example, when the gate signal is high (VGH = 36V) and low (VGL = -6V), the gate voltage of pixel switching element T0 is VGH = 36V and VGL = -6V. The gamma voltage Vs+ of positive liquid crystal molecules is between 8.8V and 16.3V, and the gamma voltage Vs- of negative liquid crystal molecules is between 0.3V and 7.8V. The gamma voltage is the source voltage of pixel switching element T0. Therefore, when the Nth image frame is negative, Vgs = 36 - (Vs-), and when the (N+1)th image frame is positive, Vgs' = 36 - (Vs+). Since Vs- is less than Vs+, at the falling edge of the gate signal (during the process of the gate voltage changing from VGH to VGL), the Vgs of the pixel switching element T0 (hereinafter referred to as "negative sub-pixel") when the liquid crystal molecule is negative polarity is greater than the Vgs' of the pixel switching element T0 (hereinafter referred to as "positive sub-pixel") when the liquid crystal molecule is positive polarity. That is, the turn-off voltage position of the positive sub-pixel is earlier than that of the negative sub-pixel, resulting in the charging time of the negative sub-pixel being longer than that of the positive sub-pixel at the falling edge.

[0052] In this disclosure, a positive polarity data signal is a signal that causes the voltage of the pixel electrode of a sub-pixel to be higher than the voltage of the common electrode, and a negative polarity data signal is a signal that causes the voltage of the pixel electrode of a sub-pixel to be lower than the voltage of the common electrode.

[0053] As shown in Figure 1D, for example, when the threshold voltage Vth = 0, during the falling edge of the gate signal, i.e., when the gate voltage changes from VGH to VGL, if the data signal provides a positive data signal to the pixel switching element T0, then at time t1, Vgs' = Vth = 0 for the pixel switching element T0. If the data line provides a negative data signal to the pixel switching element T0, then at time t2, Vgs = Vth = 0 for the pixel switching element T0. Therefore, the positive sub-pixel turns off earlier than the negative sub-pixel by a delay time Td.

[0054] It should be noted that, in the above, Figure 1D illustrates the difference in charging time between positive and negative polarities using the falling edge of the gate signal as an example, but this is not intended to limit the embodiments described below. For example, the driving method provided in the embodiments of this disclosure can also be applied at the rising edge of the gate signal. Hereinafter, the falling and rising edges of the gate signal will be collectively referred to as the transition period. Furthermore, the threshold voltage Vth = 0 is merely an example; in practical applications, the threshold voltage can be any value.

[0055] The charging time of negative polarity subpixels during the transition period is longer than that of positive polarity subpixels. This will cause differences in charging time between positive and negative polarities, resulting in problems such as poor display (e.g., uneven display, image retention) and even data misalignment of negative polarity.

[0056] Figure 1E shows a partial timing diagram of another gate signal and data signal.

[0057] As shown in Figure 1E, the ideal positive data signal, the ideal negative data signal, and the ideal gate signal are all square wave signals (i.e., signals represented by dashed lines). However, in practical applications, whether it is the positive data signal, the negative data signal, or the gate signal, there is a delay in the voltage change at the rising and falling edges. That is, it takes a certain amount of time for the signal value to change from the first value to the second value. In Figure 1E, the actual signals are represented by solid lines.

[0058] As shown in Figure 1E, the actual positive polarity data signals include data signal 1 and data signal 2. Data signal 1 represents the positive polarity data signal received by the sub-pixel closer to the source driver chip; data signal 2 represents the positive polarity data signal received by the sub-pixel farther from the source driver chip. As shown in Figure 1E, the positive polarity data signal received by the sub-pixel farther from the source driver chip has a larger delay compared to the positive polarity data signal received by the sub-pixel closer to the source driver chip. Similarly, the actual negative polarity data signals include data signal 3 and data signal 4. Data signal 3 represents the negative polarity data signal received by the sub-pixel closer to the source driver chip; data signal 4 represents the negative polarity data signal received by the sub-pixel farther from the source driver chip. As shown in Figure 1E, the negative polarity data signal received by the sub-pixel farther from the source driver chip has a larger delay compared to the negative polarity data signal received by the sub-pixel closer to the source driver chip.

[0059] For example, the falling edge of the actual gate signal is a ramp. Due to the existence of the ramp, the actual positive data signal turns off earlier than the actual negative data signal. There is a time delay ΔT between the actual negative data signal turning off and the actual positive data signal turning off.

[0060] For example, a 16K LCD panel has a resolution of 15360*RGB*8640, with 15360*3 = 46080 sub-pixels. The driver chip requires too many source channels (i.e., 46080 channels), and the size of chip-on-flex (COF) films is trending towards smaller designs. Module bonding processes limit the development of COF size. For instance, if the COF size at the LCD panel end is too small, it easily exceeds the minimum bonding capacity. That is, when adjusting the position after pre-alignment, the minimum step displacement distance exceeds the COF size, making bonding and alignment impossible. Taking a COF for 960 display modules as an example, a single display module requires 46080 / 960 = 48 COFs. The large number of required COFs leads to a decrease in bonding yield and an increase in cost.

[0061] Therefore, how to improve the image quality and yield of display panels, and further reduce costs while ensuring quality, is a technical problem that urgently needs to be solved by those skilled in the art.

[0062] At least one embodiment of this disclosure provides a driving method for a liquid crystal display panel and a liquid crystal display panel. The liquid crystal display panel includes a pixel array, which includes multiple gate lines, multiple data lines, and multiple sub-pixels. The multiple sub-pixels are arranged in multiple rows and columns. Each gate line provides a gate signal to at least one row of sub-pixels, and each data line provides a data signal to at least one column of sub-pixels. Each sub-pixel is connected to a corresponding gate line and a corresponding data line. The driving method includes: providing a first gate signal to a first gate line corresponding to a first row of sub-pixels in the multiple rows of sub-pixels. The first gate signal includes an on period and an off period, used to control the first row of sub-pixels to be turned on and off respectively; during the on period of the first gate signal, writing multiple first data signals to the multiple sub-pixels of the first row of sub-pixels respectively through the multiple data lines. The multiple first data signals include positive polarity data signals and negative polarity data signals. During the on period of the first gate signal, the first writing time of the negative polarity data signal is less than the second writing time of the positive polarity data signal. This driving method can improve the image quality and yield of the liquid crystal display panel and alleviate problems such as uneven display, image retention, and even negative polarity data misalignment that easily occur in liquid crystal display panels.

[0063] Figure 2A shows a flowchart of a driving method provided by at least one embodiment of the present disclosure. Figure 2B shows a schematic diagram of a pixel driving architecture for a liquid crystal display panel provided by at least one embodiment of the present disclosure. This pixel driving architecture can be applied to the driving method shown in Figure 2A.

[0064] As shown in Figure 2A, the driving method may include steps S10 to S20.

[0065] Step S10: Provide a first gate signal to the first gate line corresponding to the first row of sub-pixels in the multi-row sub-pixels. The first gate signal includes an on period and an off period, which are used to control the first row of sub-pixels to be turned on and off respectively.

[0066] Step S20: During the period when the first gate signal is turned on, multiple first data signals are written to multiple sub-pixels of the first row of sub-pixels through multiple data lines. The multiple first data signals include positive polarity data signals and negative polarity data signals. During the period when the first gate signal is turned on, the first writing time length of the negative polarity data signal is less than the second writing time length of the positive polarity data signal.

[0067] As shown in Figure 2B, the liquid crystal display panel includes a pixel array, which comprises multiple gate lines (gate lines G1 to Gn), multiple data lines (data lines Data1 to Data(m)), and multiple sub-pixels (sub-pixels P11 to P(nm)). The sub-pixels are arranged in multiple rows and columns; for example, sub-pixels P11 to P(nm) are arranged in n rows and m columns, where n and m are integers greater than or equal to 1. Each sub-pixel can have the structure shown in Figure 1A or Figure 1B. For example, each sub-pixel includes a pixel switching element and an equivalent capacitance C, which may include, for example, the liquid crystal capacitor and storage capacitor shown in Figure 1A or Figure 1B.

[0068] Each gate line provides a gate signal for at least one row of sub-pixels, each data line provides a data signal for at least one column of sub-pixels, and each sub-pixel is connected to the corresponding gate line and the corresponding data line.

[0069] For step S10, the first row of sub-pixels refers to any randomly selected row of sub-pixels in the pixel array; that is, in this disclosure, "first" does not indicate a specific order. Similarly, the first gate line refers to a gate line among multiple gate lines that connects to the first row of sub-pixels, and the first gate line signal refers to a signal provided by the gate line connected to the first row of sub-pixels. For example, the first row of sub-pixels is the sub-pixel in the i-th row of the pixel array, and the first gate line is the gate line connected to the sub-pixel in the i-th row of the pixel array, where i is an integer greater than or equal to 1.

[0070] The first gate signal's on period is used to control the first row of sub-pixels to turn on, and the first gate signal's off period is used to control the first row of sub-pixels to turn off. For example, the first gate signal's on period can be when the first gate signal is at a high level VGH, and the first gate signal's on period can be when the first gate signal is at a high level VGL.

[0071] For example, a gate signal is provided to multiple sub-pixels P(n1) to P(nm) arranged in the nth row of the pixel array through the gate line Gn.

[0072] For step S20, for example, during the activation of the gate signal in the nth row, multiple data lines write multiple first data signals to multiple sub-pixels Pn1 to P(nm), respectively. The multiple first data signals include positive and negative data signals. The multiple sub-pixels Pn1 to P(nm) in the nth row are examples of the first row of sub-pixels.

[0073] Figures 2C and 2D illustrate a polarity reversal driving method provided by at least one embodiment of the present disclosure.

[0074] Figure 2C is a schematic diagram of the polarity of the data signal in the Nth image frame, and Figure 2D is a schematic diagram of the polarity of the data signal in the (N+1)th image frame.

[0075] As shown in Figures 2C and 2D, this polarity reversal driving method is a column reversal driving method, that is, the polarity of the data signals in the same column is consistent, while the polarity of the data signals in adjacent columns is opposite.

[0076] For the same sub-pixel, the polarity changes between two adjacent frames.

[0077] As shown in Figure 2C, for any row of sub-pixels in the Nth image frame, during the activation period of that row of sub-pixels, multiple data lines write data signals to that row of sub-pixels respectively. For example, negative polarity data signals are written to sub-pixels in odd-numbered columns, and positive polarity data signals are written to sub-pixels in even-numbered columns.

[0078] As shown in Figure 2D, for any row of sub-pixels in the (N+1)th image frame, during the activation period of that row of sub-pixels, multiple data lines write data signals to that row of sub-pixels respectively. For example, positive polarity data signals are written to sub-pixels in odd-numbered columns, and negative polarity data signals are written to sub-pixels in even-numbered columns.

[0079] It should be noted that Figures 2C and 2D are merely examples of one polarity inversion driving method and do not imply that the embodiments of this disclosure are only applicable to the polarity inversion driving methods shown in Figures 2C and 2D. For example, embodiments of this disclosure are also applicable to a row inversion driving method, that is, the data signal polarity in the same row is consistent, while the data signal polarity in adjacent rows is opposite. As another example, embodiments of this disclosure are also applicable to a dot inversion driving method, that is, the data signal polarity of each adjacent sub-pixel is opposite.

[0080] For example, during the period when the first gate signal is on, the writing time of the negative data signal is T-, and the writing time of the positive data signal is T+, where 0 < T- < T+. T- is an example of the first writing time length, and T+ is an example of the second writing time length. This embodiment compensates for the impact caused by the longer charging time of the negative data signal than the positive data signal during the transition period by adjusting the writing time of the negative data signal to be shorter than that of the positive data signal during the period when the first gate signal is on. This alleviates problems such as uneven display, image retention, and even negative data misalignment. This embodiment only requires adjusting the timing relationship between the negative or positive data signal and the first gate signal, without requiring any modification to the hardware circuitry of the liquid crystal display panel. It is easy to implement and has good compatibility.

[0081] In some embodiments of this disclosure, the delay time of the negative data signal relative to the start time point of the turn-on period corresponding to the first gate signal is a first time length, and the delay time of the positive data signal relative to the start time point of the turn-on period corresponding to the first gate signal is a second time length. The first time length is greater than the second time length, such that when the first gate signal is in the turn-on period, the first write time length of the negative data signal is less than the second write time length of the positive data signal.

[0082] Figure 2E shows a timing diagram of a gate signal and a data signal provided in at least one embodiment of the present disclosure.

[0083] In some embodiments of this disclosure, the turn-on period corresponding to the first gate signal may refer to, for example, the period when the gate voltage of the first gate signal is VGH, and the start time point of the turn-on period corresponding to the first gate signal refers to the moment when the gate voltage begins to be VGH. As shown in FIG2E, the turn-on period corresponding to the first gate signal may be Tkq, and the start time point of the turn-on period corresponding to the first gate signal may be time Tq.

[0084] In other embodiments of this disclosure, for example, the moment when the gate-source voltage Vgs' equals the threshold voltage Vth when the first data line provides a positive data signal is taken as the start time point of the turn-on period corresponding to the first gate signal. For example, in this embodiment, the start time point of the turn-on period corresponding to the first gate signal is slightly earlier than time Tq.

[0085] Unless otherwise specified, at least some embodiments of this disclosure will be described below with the starting time point being time Tq.

[0086] As shown in Figure 2E, the delay time of the negative polarity data signal relative to the starting time point Tq is a first time length T1, and the delay time of the positive polarity data signal relative to the starting time point Tq is a second time length T2. The first time length T1 is greater than the second time length T2. This embodiment compensates for the impact caused by the longer charging time of the negative polarity data signal compared to the positive polarity data signal by providing the negative polarity data signal later than the positive polarity data signal, thereby alleviating problems such as uneven display, image retention, and even negative polarity data misalignment.

[0087] In some embodiments of this disclosure, the second time length T2 may be approximately equal to 0, for example. The first time length can be determined based on the difference between the charging time of the negative polarity data signal and the charging time of the positive polarity data signal, and the second time length T2.

[0088] In some embodiments of this disclosure, the first gate signal includes a transition period between adjacent on and off periods. The first time length is longer than the second time length by a preset time length, the preset time length being the difference between the write time length of the negative data signal and the write time length of the positive data signal during the transition period of the first gate signal.

[0089] For example, the transition period is the falling edge of the first gate signal, and in Figure 2E, the transition period Tgd is the falling edge located between adjacent turn-on and turn-off periods.

[0090] As shown in Figure 2E, for example, when the threshold voltage Vth = 0, during the transition period Tgd, for a negative data signal, at time t4, the thin-film transistor's Vgs = Vth = 0, at which point the writing of the negative data signal stops. For a positive data signal, at time t3, the thin-film transistor's Vgs' = Vth = 0, at which point the writing of the positive data signal stops. Therefore, the writing time length for the negative data signal is Treg, and the writing time length for the positive data signal is Tpos. The preset time length T = Treg - Tpos, therefore the first time length T1 is longer than the second time length T2 by the preset time length T.

[0091] In some other embodiments of this disclosure, considering that the first gate signal also includes a rising edge, since the rising edge causes the negative polarity data signal to be written to the sub-pixel earlier than the positive polarity data signal to be written to the sub-pixel, the preset time length can be slightly greater than T. For example, if the negative polarity data signal is written to the sub-pixel t earlier than the positive polarity data signal at the rising edge, then the preset time length can be T+t.

[0092] For example, in an embodiment where the moment when the gate-source voltage Vgs' = threshold voltage Vth is used as the start time of the turn-on period corresponding to the first gate signal when the data line provides a positive polarity data signal, the first time length T1 is longer than the second time length T2 by a preset time length T.

[0093] In some embodiments of this disclosure, the start time point of the turn-on period corresponding to the negative polarity data signal relative to the first gate signal is the same as or different from the start time point of the turn-on period corresponding to the positive polarity data signal relative to the first gate signal.

[0094] For example, in the example of Figure 2E, the start time point of the turn-on period corresponding to the negative polarity data signal relative to the first gate signal and the start time point of the turn-on period corresponding to the positive polarity data signal relative to the first gate signal are both time Tq.

[0095] For example, the start time of the turn-on period for the negative data signal relative to the first gate signal is the moment when the gate voltage begins to be VGH in the k-th cycle of the first gate signal, and the start time of the turn-on period for the positive data signal relative to the first gate signal is the moment when the gate voltage begins to be VGH in the r-th cycle, where k and r are different integers. For example, the k-th cycle and the r-th cycle are adjacent cycles, that is, in the k-th cycle of the first gate signal, a negative data signal is provided to the odd-numbered rows in Figure 2C, and in the r-th cycle of the first gate signal, a positive data signal is provided to the even-numbered rows in Figure 2C.

[0096] Figure 3A illustrates another pixel driving architecture of a liquid crystal display panel according to an application driving method provided in at least one embodiment of the present disclosure. Figures 3B and 3C illustrate a timing signal diagram provided in at least one embodiment of the present disclosure.

[0097] As shown in Figure 3A, in this driving architecture, each data line provides a data signal to two adjacent columns of sub-pixels. For example, data line S1 provides a data signal to the first and second adjacent columns of sub-pixels in the pixel array. In this driving architecture, apart from each data line providing a data signal to two adjacent columns of sub-pixels, the other structures are similar to those in Figure 2B; please refer to the description in Figure 2B.

[0098] In one example of this driving architecture, each data line provides a positive and a negative data signal to the first and second sub-pixels located in adjacent columns of the same row. For example, at a first moment during the first gate signal's on period, each data line provides a positive and a negative data signal to the first and second sub-pixels located in adjacent columns of the first row of sub-pixels. The on period of the first gate signal includes a first sub-on period and a second sub-on period. A positive data signal is applied to the first sub-pixel during the first sub-on period, and a negative data signal is applied to the second sub-pixel during the second sub-on period, with the first sub-on period being longer than the second sub-on period. As another example, at a second moment during the first gate signal's on period, each data line provides a negative and a positive data signal to the first and second sub-pixels located in adjacent columns of the first row of sub-pixels.

[0099] In the example of Figure 3B, the polarity distribution of the liquid crystal molecules in the Nth image frame is, for example, the example of Figure 2C. For a sub-pixel in the i-th row of the pixel array (an example of a first row of sub-pixels), during the on-time of the first gate signal G(i) provided to the first row of sub-pixels (i.e., when the gate signal G(i) is high), each data line sequentially provides a negative polarity data signal to the first sub-pixel and a positive polarity data signal to the second sub-pixel of the adjacent column in the first row, respectively. For example, multiple data lines first provide negative polarity data signals to the sub-pixels in odd-numbered rows, then provide positive polarity data signals to the sub-pixels in even-numbered rows, and the time for providing negative polarity data signals to the sub-pixels in odd-numbered rows is shorter than the time for providing positive polarity data signals to the sub-pixels in even-numbered rows.

[0100] As shown in Figure 3B, the turn-on period of the first gate signal G(i) includes a first sub-turn-on period Tkq1 and a second sub-turn-on period Tkq2. The duration of the first sub-turn-on period Tkq1 is longer than the duration of the second sub-turn-on period Tkq2. During the second sub-turn-on period Tkq2, multiple data lines provide negative polarity data signals to the sub-pixels in odd-numbered rows, and during the first sub-turn-on period Tkq1, multiple data lines provide positive polarity data signals to the sub-pixels in even-numbered rows. In the example of Figure 3B, for example, the second sub-turn-on period Tkq2 is earlier than the first sub-turn-on period Tkq1. In other embodiments, the second sub-turn-on period Tkq2 may also be later than the first sub-turn-on period Tkq1.

[0101] After the first row of sub-pixels is turned off, the second row of sub-pixels is turned on. The second row of sub-pixels can be, for example, sub-pixels in a row adjacent to or not adjacent to the first row of sub-pixels. For example, when the second gate signal G(i+1) of the second row of sub-pixels is on, the second row of sub-pixels is turned on, thereby allowing multiple data lines to provide negative and positive data signals to the second row of sub-pixels respectively. The manner in which multiple data lines provide negative and positive data signals to the second row of sub-pixels is the same as the manner in which negative and positive data signals are provided to the first row of sub-pixels respectively, and will not be described again here.

[0102] For example, Figure 3C is a timing signal diagram of the (N+1)th image frame. For example, the polarity distribution of the liquid crystal molecules in the (N+1)th image frame is as shown in the example of Figure 2D. For a sub-pixel in the i-th row of the pixel array (an example of a first-row sub-pixel), during the on-time of the gate signal G(i) provided to the first-row sub-pixel (i.e., when the gate signal G(i) is high), each data line sequentially provides a positive polarity data signal to the first sub-pixel and a negative polarity data signal to the second sub-pixel in the adjacent column of the first row, respectively. For example, multiple data lines first provide positive polarity data signals to the sub-pixels in odd-numbered rows, and then provide negative polarity data signals to the sub-pixels in even-numbered rows.

[0103] The turn-on period of the first gate signal includes a first sub-turn-on period Tkq1 and a second sub-turn-on period Tkq2. The duration of the first sub-turn-on period Tkq1 is longer than the duration of the second sub-turn-on period Tkq2. During the first sub-turn-on period Tkq1, multiple data lines provide positive polarity data signals to the sub-pixels in odd-numbered rows, and during the second sub-turn-on period Tkq2, multiple data lines provide negative polarity data signals to the sub-pixels in even-numbered rows. In the example of Figure 3C, for example, the second sub-turn-on period Tkq2 is later than the first sub-turn-on period Tkq1. In other embodiments, the second sub-turn-on period Tkq2 may also be earlier than the first sub-turn-on period Tkq1.

[0104] Similarly, after the first row of sub-pixels is turned off, the second row of sub-pixels is turned on. The second row of sub-pixels can be, for example, sub-pixels in a row adjacent to or not adjacent to the first row of sub-pixels. For example, when the second gate signal G(i+1) of the second row of sub-pixels is turned on, the second row of sub-pixels is turned on, thereby providing negative and positive data signals to the second row of sub-pixels respectively from multiple data lines.

[0105] This pixel-driven architecture provides data signals to two sub-pixels in an adjacent column (i.e., 1:2 control) through a single data line, which can reduce the number of COFs used, thereby indirectly improving the bonding yield and reducing costs. Furthermore, this driving architecture makes it easier to control the first and second write times.

[0106] Figure 4 shows a partial schematic diagram of another pixel driving architecture for a liquid crystal display panel according to an application driving method provided in at least one embodiment of the present disclosure.

[0107] As shown in Figure 4, each sub-pixel in the liquid crystal display panel includes a pixel electrode and a pixel switching element. For a description of the pixel electrode and pixel switching element, please refer to Figures 1A and 1B, but it is not limited to the situation shown in Figures 1A and 1B.

[0108] In this example, each data line provides a data signal to two adjacent columns of sub-pixels. For example, data line S1 provides a data signal to the first column of sub-pixels and the second column of sub-pixels. The first column of sub-pixels refers to any row of sub-pixels in the pixel array, and the second column of sub-pixels are those adjacent to the first column of sub-pixels. For example, the first column of sub-pixels is the column containing sub-pixel Q11, and the second column of sub-pixels is the column containing sub-pixel Q12.

[0109] It should be noted that although Figure 4 only shows the connection relationship between data line S1 and two columns of sub-pixels, it does not mean that the pixel driving architecture only includes data line S1 and these two columns of sub-pixels. In fact, the pixel driving architecture usually includes multiple data lines and multiple columns of sub-pixels. The arrangement of other data lines and other columns of sub-pixels is similar to that shown in Figure 4, and will not be described again.

[0110] As shown in Figure 4, each sub-pixel may include a multiplexed switching element in addition to the pixel switching element. For example, sub-pixel Q11 includes pixel switching element T11-1 and multiplexed switching element T11-2, and sub-pixel Q12 includes pixel switching element T12-1 and multiplexed switching element T12-2.

[0111] Each data line provides a positive data signal to the pixel electrode of the first sub-pixel through a first multiplexing switching element, and provides a negative data signal to the pixel electrode of the second sub-pixel through a second multiplexing switching element.

[0112] For example, if the liquid crystal molecules of sub-pixel Q11 are positive, then data line S1 provides a positive data signal to the source of pixel switching element T11-1 of sub-pixel Q11 through multiplexed switching element T11-2, thereby providing a positive data signal to the pixel electrode of sub-pixel Q11. If the liquid crystal molecules of sub-pixel Q12 are negative, then data line S1 provides a negative data signal to the source of pixel switching element T12-1 of sub-pixel Q12 through multiplexed switching element T12-2, thereby providing a negative data signal to the pixel electrode of sub-pixel Q12. Multiplexed switching elements T11-2 and T12-2 are examples of the first and second multiplexed switching elements, respectively. In some embodiments of this disclosure, another switching element in the sub-pixel may be, for example, a thin-film transistor or other types of switching elements. For example, the first multiplexed switching element, the second multiplexed switching element, and the pixel switching element are all thin-film transistors.

[0113] As shown in Figure 4, the multiplexed switching element T11-2 is connected to the control line VDDODD to receive the first control signal provided by the control line VDDODD. The multiplexed switching element T11-2 is configured to turn on and off in response to the control of the first control signal. The multiplexed switching element T12-2 is connected to the control line VDDEVEN to receive the second control signal provided by the control line VDDEVEN. The multiplexed switching element T12-2 is configured to turn on and off in response to the control of the second control signal.

[0114] For example, when the data line S1 provides a positive data signal, the first control signal provided by the control line VDDODD causes the multiplexing switching element T11-2 to turn on, thereby allowing the positive data signal to be provided to the pixel electrode of the pixel switching element T11-1. The second control signal provided by the control line VDDEVEN causes the multiplexing switching element T12-2 to turn off, thereby preventing the positive data signal from being provided to the pixel electrode of the multiplexing switching element T12-1.

[0115] For example, when the data line S1 provides a negative polarity data signal, the first control signal provided by the control line VDDODD causes the multiplexing switching element T11-2 to turn off, thereby preventing the negative polarity data signal from being provided to the pixel electrode of the pixel switching element T11-1. The second control signal provided by the control line VDDEVEN causes the multiplexing switching element T12-2 to turn on, thereby allowing the negative polarity data signal to be provided to the pixel electrode of the multiplexing switching element T12-1.

[0116] It should be noted that the above embodiments of this disclosure are only used as examples of data line S1, sub-pixel P11 and sub-pixel P12 to illustrate the embodiments provided by this disclosure, and are not intended to limit the scope of this disclosure. Other data lines and other sub-pixels in the pixel array are driven by a similar method to data line S1, sub-pixel P11 and sub-pixel P12, which will not be described in detail here.

[0117] For example, when the liquid crystal molecules in sub-pixel Q11 are negative and the liquid crystal molecules in sub-pixel Q12 are positive in a certain image frame, the multiplexed switching element T11-2 is turned on when the data line S1 provides a negative polarity signal, and the multiplexed switching element T12-2 is turned off when the data line S1 provides a positive polarity signal.

[0118] This embodiment uses a first multiplexing switching element and a second multiplexing switching element to determine whether to write data signals to sub-pixels during the first and second on-time periods, thereby achieving AC driving of liquid crystal molecules. Furthermore, by adjusting the time ratio of the second on-time period Tkq2 to the first on-time period Tkq1, the second on-time period Tkq2 (negative polarity charging time length) can be reduced, while the first on-time period Tkq1 (positive polarity charging time length) can be increased. This adjusts the positive and negative polarity charging time, enabling the pixel voltage to achieve a balance between positive and negative polarities, thereby improving the uniformity of the display panel and enhancing image quality.

[0119] The first sub-opening period and the second sub-opening period are the same as the opening time periods of the first multiplexing switching element and the second multiplexing switching element, respectively. For example, during sub-opening period Tkq1, multiplexing switching element T11-2 is opened; during sub-opening period Tkq2, multiplexing switching element T12-2 is opened.

[0120] Figure 5A shows a timing signal diagram of the Nth image frame provided in at least one embodiment of the present disclosure; Figure 5B shows a timing signal diagram of the N+1th image frame provided in at least one embodiment of the present disclosure.

[0121] As shown in Figure 5A, for the Nth image frame, the gate signals of the sub-pixels in multiple rows are sequentially turned on. For example, when the first gate signal G(i) of the first row of sub-pixels is turned on, the liquid crystal molecules of the odd-numbered columns of sub-pixels are negative polarity, and the liquid crystal molecules of the even-numbered columns of sub-pixels are positive polarity. The data lines connecting adjacent columns sequentially provide negative polarity data signals to the odd-numbered columns of sub-pixels and positive polarity data signals to the even-numbered columns of sub-pixels. That is, the polarity distribution of the data signals in the Nth image frame is shown in Figure 2C.

[0122] As shown in Figure 5A, during the sub-on period, Tkq1 is the same as the on-time period of the even-numbered multiplexed switching element (i.e., the time period when the VDDEVEN signal is high), and during the sub-on period, Tkq2 is the same as the on-time period of the odd-numbered multiplexed switching element (i.e., the time period when the VDDODD signal is high).

[0123] As shown in Figure 5B, for the (N+1)th image frame, the gate signals of the sub-pixels in multiple rows are sequentially turned on. For example, when the first gate signal G(i) of the first row of sub-pixels is turned on, the liquid crystal molecules of the odd-numbered columns of sub-pixels are positive polarity, and the liquid crystal molecules of the even-numbered columns of sub-pixels are negative polarity. The data lines connecting adjacent columns sequentially provide positive polarity data signals to the odd-numbered columns of sub-pixels and negative polarity data signals to the even-numbered columns of sub-pixels. That is, the polarity distribution of the data signals in the (N+1)th image frame is shown in Figure 2D.

[0124] As shown in Figure 5B, the sub-turn-on period Tkq1 is the same as the turn-on time period of the multiplexed switching element in the odd-numbered sequence (i.e., the time period when the VDDODD signal is high), and the sub-turn-on period Tkq2 is the same as the turn-on time period of the multiplexed switching element in the even-numbered sequence (i.e., the time period when the VDDEVEN signal is high).

[0125] Figure 6 shows another pixel driving architecture schematic diagram of a liquid crystal display panel for an application driving method provided in at least one embodiment of the present disclosure.

[0126] As shown in Figure 6, a first multiplexed switching element and a second multiplexed switching element are disposed around the periphery of the liquid crystal display panel. The periphery of the liquid crystal display panel is, for example, the control area of ​​the liquid crystal display panel. Multiple sub-pixels are disposed in the display area of ​​the liquid crystal display panel. For example, multiplexed switching elements TFT1 and TFT2 are disposed in the control area around the liquid crystal display panel. Multiplexed switching elements TFT1 and TFT2 are examples of the first and second multiplexed switching elements, respectively. For example, at a first moment, data line SD1 provides positive and negative data signals to sub-pixels W11 and W12 respectively through multiplexed switching elements TFT1 and TFT2; or, at a second moment, data line SD1 provides positive and negative data signals to sub-pixels W11 and W12 respectively through multiplexed switching elements TFT1 and TFT2. Sub-pixels W11 and W12 are examples of the first and second sub-pixels, respectively.

[0127] As shown in Figure 6, sub-pixels W11 share a column of multiplexing switching element TFT1, and sub-pixels W12 share a column of multiplexing switching element TFT2.

[0128] The connection method between other data lines in the liquid crystal display panel and two adjacent sub-pixels is the same as the connection method between data line S1 and sub-pixels P11 and P12, and will not be described again. The structure of each sub-pixel is similar to the structure of the sub-pixels in the aforementioned embodiments, and will not be described again.

[0129] This embodiment adds a first multiplexed switching element and a second multiplexed switching element controlled by voltages provided by the VDDODD signal line and the VDDEVEN signal line, and sets the first multiplexed switching element and the second multiplexed switching element in the control area, thereby reducing the number of the first multiplexed switching element and the second multiplexed switching element used, and setting the multiplexed switching element in the control area rather than the display area, which can further eliminate the impact of increasing the switching element on the pixel aperture ratio.

[0130] Figure 7 shows another pixel driving architecture schematic diagram of a liquid crystal display panel for an application driving method provided in at least one embodiment of the present disclosure.

[0131] For example, this pixel-driven architecture includes multiple sub-pixels P'11, P'12, ..., P' (nm), where each data line provides positive and negative data signals to the first and second sub-pixels located in adjacent columns of the same row. For instance, in a certain image frame, data line S'1 provides positive and negative data signals to sub-pixels P'11 and P'12, respectively. Sub-pixels P'11 and P'12 are examples of the first and second sub-pixels, respectively.

[0132] As shown in Figure 7, each sub-pixel may include a multiplexed switching element. For example, sub-pixel P'11 includes a multiplexed switching element T'11-1, and sub-pixel P'12 includes a multiplexed switching element T'12-1.

[0133] In the example of Figure 7, except for the addition of a multiplexed switching element in each sub-pixel, the structure of each sub-pixel is the same as in the aforementioned embodiments (e.g., Figures 1A and 1B), and will not be described again. For example, the switching element is placed between the pixel switching element and the pixel electrode.

[0134] Each data line provides a positive data signal to the pixel electrode of a first sub-pixel via a first multiplexing switching element, and a negative data signal to the pixel electrode of a second sub-pixel via a second multiplexing switching element. Multiplexing switching elements T'11-1 and T'12-1 are, for example, examples of the first and second multiplexing switching elements, respectively. For instance, in one image frame, data line S1 provides a positive data signal to the pixel electrode of sub-pixel P'11 via multiplexing switching element T'11-1, and a negative data signal to the pixel electrode of sub-pixel P'12 via multiplexing switching element T'12-1. In another image frame, data line S'1 provides a negative data signal to the pixel electrode of sub-pixel P'11 via multiplexing switching element T'11-1, and a positive data signal to the pixel electrode of sub-pixel P'12 via multiplexing switching element T'12-1.

[0135] As shown in Figure 7, the first multiplexing switching element is disposed within the first sub-pixel, and the second multiplexing switching element is disposed within the second sub-pixel. For example, the multiplexing switching element T'11-1 is disposed within sub-pixel P'11, and the multiplexing switching element T'12-1 is disposed within sub-pixel P'12.

[0136] In some embodiments of this disclosure, as shown in FIG7, each sub-pixel further includes a pixel switching element connected to a corresponding gate line to receive a gate signal provided by the corresponding gate line. For example, sub-pixel P'11 includes pixel switching element T'11-2, which is connected to gate line G1 to receive a gate signal provided by gate line G1. Sub-pixel P'12 includes pixel switching element T'12-2, which is also connected to gate line G1 to receive a gate signal provided by gate line G1.

[0137] As shown in Figure 7, the pixel switching element and the first multiplexing switching element in the first sub-pixel are connected in series between the data line and the pixel electrode, and the pixel switching element and the second multiplexing switching element in the second sub-pixel are connected in series between the data line and the pixel electrode. For example, the pixel switching element T'11-2 and the multiplexing switching element T'11-1 of sub-pixel P'11 are connected in series between the data line S1 and the pixel electrode. The pixel switching element T'12-2 and the multiplexing switching element T'12-1 of sub-pixel P'12 are connected in series between the data line and the pixel electrode.

[0138] The pixel driving structure sets up a multiplexing switching element in each sub-pixel to realize data line multiplexing, which facilitates individual control of each sub-pixel.

[0139] Another aspect of this disclosure provides a liquid crystal display panel. The liquid crystal display panel includes a pixel array. The pixel array includes multiple gate lines, multiple data lines, and multiple sub-pixels. The multiple sub-pixels are arranged in multiple rows and columns. Each gate line provides a gate signal to one row of sub-pixels, and each data line provides a data signal to two adjacent columns of sub-pixels. Each sub-pixel is connected to a corresponding gate line and a corresponding data line. A first gate line corresponding to a first row of sub-pixels is configured to provide a first gate signal to the first row of sub-pixels. The first gate signal includes an on period and an off period, used to control the first row of sub-pixels to be turned on and off respectively. Each data line is configured to provide a positive polarity data signal to a first sub-pixel in two adjacent columns and a positive polarity data signal to a second sub-pixel in two adjacent columns respectively during the first gate signal being on. During the period when the first gate signal is on, the first write time of each data line configured as a negative polarity data signal is shorter than the second write time of the positive polarity data signal. The on-time of the first gate signal includes a first sub-on period and a second sub-on period. During the on-time of the first gate signal, the first write time of each data line configured as a negative polarity data signal is shorter than the second write time of the positive polarity data signal, including: the positive polarity data signal is applied to the first sub-pixel during the first sub-on period, and the negative polarity data signal is applied to the second sub-pixel during the second sub-on period, with the duration of the first sub-on period being longer than the duration of the second sub-on period. This liquid crystal display panel can improve the image quality and yield of the display panel and alleviate problems such as uneven display, image retention, and even negative polarity data misalignment that are prone to occur in liquid crystal display panels.

[0140] In some embodiments of this disclosure, each sub-pixel further includes a pixel electrode, and each data line is electrically connected to the pixel electrode of the first sub-pixel through a first multiplexing switching element and electrically connected to the pixel electrode of the second sub-pixel through a second multiplexing switching element.

[0141] In some embodiments of this disclosure, a first multiplexing switching element is connected to a first control line to receive a first control signal provided by the first control line, and the first multiplexing switching element is configured to turn on and off in response to the control of the first control signal. A second multiplexing switching element is connected to a second control line to receive a second control signal provided by the second control line, and the second multiplexing switching element is configured to turn on and off in response to the control of the second control signal.

[0142] In some embodiments of this disclosure, the first multiplexing switching element and the second multiplexing switching element are disposed around the periphery of the liquid crystal display panel, and a column of sub-pixels containing the first sub-pixel shares the first multiplexing switching element, and a column of sub-pixels containing the second sub-pixel shares the second multiplexing switching element.

[0143] In some embodiments of this disclosure, a first multiplexing switching element is disposed within a first sub-pixel, and a second multiplexing switching element is disposed within a second sub-pixel.

[0144] In some embodiments of this disclosure, each sub-pixel further includes a pixel switching element connected to a corresponding gate line to receive a gate signal provided by the corresponding gate line.

[0145] The pixel switching element in the first sub-pixel is connected in series with the first multiplexing switching element between the data line and the pixel electrode.

[0146] The pixel switching element in the second sub-pixel is connected in series with the second multiplexing switching element between the data line and the pixel electrode.

[0147] The liquid crystal display panel provided in the above embodiments of this disclosure can be the pixel driving architecture of the liquid crystal display panel shown by any of the driving methods described above, such as the pixel driving architecture shown in FIG2B, FIG3A, FIG6 and FIG7. For specific functions and components of the liquid crystal display panel, please refer to the relevant descriptions of the driving methods, which will not be repeated here. For example, the components and structures of the liquid crystal display panels shown in FIG2B, FIG3A, FIG6 and FIG7 are merely exemplary and not limiting; as needed, the liquid crystal display panel may also include other components and structures.

[0148] Figures 8A to 8D illustrate some other exemplary pixel driving architectures for a liquid crystal display panel applied to a driving method, provided in at least one embodiment of the present disclosure.

[0149] For example, in the pixel driving architecture of Figure 8A, each gate line (e.g., gate line 1 to gate line 4) is electrically connected to a row of sub-pixels, and sub-pixels in adjacent rows of the same column are connected to two different data lines respectively. For example, the red sub-pixel in the first row is connected to data line 1, and the red sub-pixel in the second row is connected to data line 2. The pixel driving architecture shown in Figure 8A is called a single gate line + Z architecture.

[0150] For example, the pixel-driven architecture in Figure 8B includes multiple gate lines and multiple data lines. The multiple gate lines may include, for example, gate lines Gate1 to Gate8, and the multiple data lines may include, for example, Data1 to Data8. Each row of subpixels is connected to two gate lines; for example, the subpixels in the first row are connected to gate lines Gate1 and Gate2. Subpixels in adjacent columns of the same row are connected to different gate lines. For example, the red subpixels in the first column are connected to Gate1, and the green subpixels in the second column are connected to Gate2.

[0151] In the pixel-driven architecture of Figure 8B, two adjacent sub-pixels are connected to the same data line, and sub-pixels in adjacent rows of the same column are connected to two different data lines. For example, the red sub-pixel in the first row is connected to data line Data1, and the red sub-pixel in the second row is connected to data line Data2. Taking the first row as an example, the red sub-pixel in the first column is connected to data line Data1, and the green sub-pixel in the second column is also connected to data line Data1.

[0152] For example, the arrangement of sub-pixels in each row is red sub-pixels, green sub-pixels, blue sub-pixels, red sub-pixels, green sub-pixels, and blue sub-pixels, and this pattern repeats. As shown in Figure 8B, the first red sub-pixel is connected to gate line Gate1, the first green sub-pixel is connected to gate line Gate2, the first blue sub-pixel is connected to gate line Gate1, the second red sub-pixel is connected to gate line Gate2, the second green sub-pixel is connected to gate line Gate1, and the second blue sub-pixel is connected to gate line Gate2. That is, in the pixel driving architecture of Figure 8B, multiple sub-pixels emitting the same color of light in the same row are connected to different gate lines. The pixel driving architecture shown in Figure 8A is called the dual-gate + Z-2 architecture.

[0153] For example, in the pixel-driven architecture of Figure 8C, each row of subpixels is connected to two gate lines; for instance, the subpixels in the first row are connected to gate lines Gate1 and Gate2. In the pixel-driven architecture of Figure 8C, adjacent subpixels are connected to the same data line, and subpixels in adjacent rows of the same column are connected to two different data lines. For example, the red subpixel in the first row is connected to data line Data1, and the red subpixel in the second row is connected to data line Data2. Taking the first row as an example, the red subpixel in the first column is connected to data line Data1, and the green subpixel in the second column is also connected to data line Data1.

[0154] In the pixel-driven architecture of Figure 8C, sub-pixels emitting the same color of light in the same row are connected to the same gate line. For example, all red sub-pixels are connected to gate line Gate1, and all green sub-pixels are connected to gate line Gate2. The pixel-driven architecture shown in Figure 8C is called the dual-gate + Z-1 architecture.

[0155] For example, the pixel-driven architecture in Figure 8D includes multiple gate lines and multiple data lines. The multiple gate lines may include, for example, gate lines 1 to 4, and the multiple data lines may include, for example, Data1 to Data6. Each row is connected to one gate line, and sub-pixels in the same column are connected to the same data line.

[0156] In Figures 8A to 8D, "+" indicates a positive data signal and "-" indicates a negative data signal. It should be noted that the architecture shown in Figures 8A to 8D is merely an example and is not intended to limit this disclosure. For example, the pixel array in a liquid crystal display panel may include more gate lines, data lines, and sub-pixel units, and the positive and negative data signals may differ from the examples in Figures 8A to 8D.

[0157] The driving method in the above embodiments provided in this disclosure can be widely applied to various liquid crystal display panels, as shown in the architecture of Figures 8A to 8D.

[0158] The embodiments of this disclosure improve the poor performance (such as uneven display, image retention, etc.) caused by the difference in charging time due to the different output characteristics of thin-film transistors under positive and negative polarities by adjusting the writing time length of positive and negative polarities, thereby further improving the picture quality and performance of the display device.

[0159] At least one embodiment of the present invention also provides a display device, including a liquid crystal display panel provided in any embodiment of the present disclosure. For example, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0160] The following points should be noted regarding this disclosure:

[0161] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0162] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0163] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A driving method for a liquid crystal display panel, wherein, The liquid crystal display panel includes a pixel array, which includes multiple gate lines, multiple data lines, and multiple sub-pixels. The multiple sub-pixels are arranged in multiple rows and multiple columns. Each gate line provides a gate signal to at least one row of sub-pixels, and each data line provides a data signal to at least one column of sub-pixels. Each sub-pixel is connected to a corresponding gate line and a corresponding data line. The driving method includes: providing a first gate signal to a first gate line corresponding to a first row of sub-pixels in the multiple rows of sub-pixels, wherein the first gate signal includes an on period and an off period, used to control the first row of sub-pixels to be turned on and off respectively; during the on period of the first gate signal, writing multiple first data signals to the multiple sub-pixels of the first row of sub-pixels respectively through the multiple data lines, wherein the multiple... The first data signal includes a positive data signal and a negative data signal. During the on period of the first gate signal, the first write time length of the negative data signal is less than the second write time length of the positive data signal. The first time length is the delay time of the negative data signal relative to the start time point of the on period corresponding to the first gate signal, and the second time length is the delay time of the positive data signal relative to the start time point of the on period corresponding to the first gate signal. The first time length is greater than the second time length, such that during the on period of the first gate signal, the first write time length of the negative data signal is less than the second write time length of the positive data signal.

2. The driving method according to claim 1, wherein, The start time point of the negative polarity data signal relative to the first gate signal during the turn-on period may be the same as or different from the start time point of the positive polarity data signal relative to the first gate signal during the turn-on period.

3. The driving method according to claim 1 or 2, wherein, The first gate signal further includes a transition period between adjacent on and off periods, the first time length being longer than the second time length by a preset time length, the preset time length being the difference between the write time length of the negative polarity data signal and the write time length of the positive polarity data signal during the transition period of the first gate signal.

4. The driving method according to claim 1, wherein, Each data line provides a data signal to two adjacent columns of sub-pixels. During the on period of the first gate signal, each data line provides a positive data signal and a negative data signal to the first sub-pixel and the second sub-pixel located in two adjacent columns of the same row, respectively. The on period of the first gate signal includes a first sub-on period and a second sub-on period. The positive data signal is applied to the first sub-pixel during the first sub-on period, and the negative data signal is applied to the second sub-pixel during the second sub-on period. The duration of the first sub-on period is greater than the duration of the second sub-on period.

5. The driving method according to claim 4, wherein, Each sub-pixel also includes a pixel electrode. Each data line provides the positive polarity data signal to the pixel electrode of the first sub-pixel through a first multiplexing switching element, and provides the negative polarity data signal to the pixel electrode of the second sub-pixel through a second multiplexing switching element.

6. The driving method according to claim 5, wherein, The first multiplexing switching element is connected to a first control line to receive a first control signal provided by the first control line. The first multiplexing switching element is configured to turn on and off in response to the control of the first control signal. The second multiplexing switching element is connected to a second control line to receive a second control signal provided by the second control line. The second multiplexing switching element is configured to turn on and off in response to the control of the second control signal.

7. The driving method according to claim 6, wherein, The first sub-opening period and the second sub-opening period are the same as the opening time period of the first multiplexing switching element and the opening time period of the second multiplexing switching element, respectively.

8. The driving method according to any one of claims 5-7, wherein, The first multiplexing switching element and the second multiplexing switching element are disposed around the periphery of the liquid crystal display panel. A column of sub-pixels containing the first sub-pixel shares the first multiplexing switching element, and a column of sub-pixels containing the second sub-pixel shares the second multiplexing switching element.

9. The driving method according to any one of claims 5-7, wherein, The first multiplexing switching element is disposed within the first sub-pixel, and the second multiplexing switching element is disposed within the second sub-pixel.

10. The driving method according to claim 9, wherein, Each sub-pixel further includes a pixel switching element connected to a corresponding gate line to receive a gate signal provided by the corresponding gate line. The pixel switching element in the first sub-pixel is connected in series with the first multiplexing switching element between the data line and the pixel electrode. The pixel switching element in the second sub-pixel is connected in series with the second multiplexing switching element between the data line and the pixel electrode.

11. A liquid crystal display panel, comprising a pixel array, wherein, The pixel array includes multiple gate lines, multiple data lines, and multiple sub-pixels. The sub-pixels are arranged in multiple rows and columns. Each gate line provides a gate signal to one row of sub-pixels, and each data line provides a data signal to two adjacent columns of sub-pixels. Each sub-pixel is connected to a corresponding gate line and a corresponding data line. The first gate line corresponding to the first row of sub-pixels is configured to provide a first gate signal to the first row of sub-pixels. This first gate signal includes an on period and an off period, used to control the first row of sub-pixels to turn on and off respectively. Each data line is configured to provide a positive polarity data signal to the first sub-pixel in two adjacent columns and a negative polarity data signal to the second sub-pixel in two adjacent columns respectively during the on period of the first gate signal. During the on period of the first gate signal, the first write time length of the negative polarity data signal is less than the second write time length of the positive polarity data signal. The negative polarity data signal is relative to the first gate line. The delay time of the start time point of the turn-on period corresponding to the signal is a first time length, and the delay time of the positive polarity data signal relative to the start time point of the turn-on period corresponding to the first gate signal is a second time length. The first time length is greater than the second time length, such that when the first gate signal is in the turn-on period, the first write time length of the negative polarity data signal is less than the second write time length of the positive polarity data signal. The turn-on period of the first gate signal includes a first sub-turn-on period and a second sub-turn-on period. When the first gate signal is in the turn-on period, the configuration of each data line such that the first write time length of the negative polarity data signal is less than the second write time length of the positive polarity data signal includes: the positive polarity data signal is applied to the first sub-pixel during the first sub-turn-on period, and the negative polarity data signal is applied to the second sub-pixel during the second sub-turn-on period, wherein the time length of the first sub-turn-on period is greater than the time length of the second sub-turn-on period.

12. The liquid crystal display panel according to claim 11, wherein, Each sub-pixel also includes a pixel electrode. Each data line is electrically connected to the pixel electrode of the first sub-pixel through a first multiplexing switching element and electrically connected to the pixel electrode of the second sub-pixel through a second multiplexing switching element.

13. The liquid crystal display panel according to claim 12, wherein, The first multiplexing switching element is connected to a first control line to receive a first control signal provided by the first control line. The first multiplexing switching element is configured to turn on and off in response to the control of the first control signal. The second multiplexing switching element is connected to a second control line to receive a second control signal provided by the second control line. The second multiplexing switching element is configured to turn on and off in response to the control of the second control signal.

14. The liquid crystal display panel according to claim 12 or 13, wherein, The first multiplexing switching element and the second multiplexing switching element are disposed around the periphery of the liquid crystal display panel. A column of sub-pixels containing the first sub-pixel shares the first multiplexing switching element, and a column of sub-pixels containing the second sub-pixel shares the second multiplexing switching element.

15. The liquid crystal display panel according to claim 12 or 13, wherein, The first multiplexing switching element is disposed within the first sub-pixel, and the second multiplexing switching element is disposed within the second sub-pixel.

16. The liquid crystal display panel according to claim 14, wherein each sub-pixel further comprises a pixel switching element, the pixel switching element being connected to a corresponding gate line to receive a gate signal provided by the corresponding gate line, the pixel switching element in the first sub-pixel being connected in series with the first multiplexing switching element between the data line and the pixel electrode, and the pixel switching element in the second sub-pixel being connected in series with the second multiplexing switching element between the data line and the pixel electrode.

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