Pixel circuit, pixel driving method and display device

Abstract

The present disclosure provides a pixel circuit, a pixel driving method and a display device. The pixel circuit comprises a driving circuit, a light emitting element and a light emitting gate control circuit; the driving circuit is electrically connected with a first electrode of the light emitting element, and is used for driving the light emitting element; the light emitting gate control circuit forms a current path between a second electrode of the light emitting element and a first voltage terminal or forms a current path between the driving circuit and the light emitting element under the control of a first control signal provided by a first control terminal, according to a first light emitting control voltage provided by a first light emitting control voltage terminal and a light emitting data voltage provided by a light emitting data voltage terminal, so as to control the driving circuit to control the light emitting element to emit light. The present disclosure provides an external compensation pixel circuit with a pulse width modulation function and low gray scale, which is beneficial to realize high PPI (Pixels Per Inch).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel circuit, a pixel driving method, and a display device. Background Technology

[0002] Micro-LEDs (micro-light-emitting diodes) possess characteristics such as high resolution, low power consumption, high brightness, high contrast, high color saturation, fast response speed, thinness, and long lifespan, making them the future iterative technology for displays. Currently, TV-grade Micro-LED products are being showcased on the market, and the market for small-to-medium-sized products for close-range displays is gradually expanding. This means that the demand for higher PPI (Pixels Per Inch) is constantly increasing. High PPI designs require simple pixel circuit structures, while current internal compensation circuit structures are relatively complex.

[0003] Furthermore, when Micro-LED displays are used for low grayscale displays, the brightness uniformity of the LED (light-emitting diode) chips driven by low current density is relatively poor. Therefore, the completed pixel driving circuit needs to include two modules: a compensation module with threshold compensation function for driving transistors, and a dimming module with pulse width modulation function. However, the internal compensation circuit with the above two modules has a complex structure, which is not conducive to achieving a narrow bezel. Summary of the Invention

[0004] In one aspect, embodiments of this disclosure provide a pixel circuit, including a driving circuit, a light-emitting element, and a light-emitting gating control circuit;

[0005] The driving circuit is electrically connected to the first electrode of the light-emitting element and is used to drive the light-emitting element; the light-emitting gating control circuit is electrically connected to the second electrode, the first control terminal, the first light-emitting control voltage terminal, and the light-emitting data voltage terminal of the light-emitting element, respectively, and is used to form a current path between the second electrode and the first voltage terminal of the light-emitting element according to the first light-emitting control voltage provided by the first control terminal and the light-emitting data voltage provided by the light-emitting data voltage terminal, under the control of the first control signal provided by the first control terminal, so as to control the driving circuit to control the light-emitting element to emit light; or...

[0006] The driving circuit is electrically connected to the light-emitting element through the light-emitting control circuit; the light-emitting gating control circuit is electrically connected to the driving circuit, the first control terminal, the first control voltage terminal and the light-emitting data voltage terminal respectively, and is used to form a current path between the driving circuit and the light-emitting element according to the first light-emitting control voltage and the light-emitting data voltage under the control of the first control signal, so as to control the driving circuit to control the light-emitting element to emit light.

[0007] Optionally, the light emission gating control circuit is also electrically connected to the second light emission control voltage terminal; the light emission gating control circuit is also used to form the current path under the control of the second light emission control voltage provided by the second light emission control voltage terminal;

[0008] The light emission gating control circuit includes a first light emission control circuit, a second light emission control circuit, a first gating control circuit, and a second gating control circuit;

[0009] The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the second electrode of the light-emitting element, and the first voltage terminal, respectively, and is used to control the connection between the second electrode of the light-emitting element and the first voltage terminal under the control of the potential of the first light-emitting control terminal;

[0010] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the second electrode of the light-emitting element, and the first voltage terminal, respectively, and is used to control the connection between the second electrode of the light-emitting element and the first voltage terminal under the control of the potential of the second light-emitting control terminal;

[0011] The first gating control circuit is electrically connected to the first control terminal, the first light emission control voltage terminal and the first light emission control terminal respectively, and is used to write the first light emission control voltage provided by the first light emission control voltage terminal into the first light emission control terminal under the control of the first control signal provided by the first control terminal.

[0012] The second gating control circuit is electrically connected to the first control terminal, the second light emission control voltage terminal, the second control terminal, the light emission data voltage terminal, and the second light emission control terminal, respectively. It is used to write the second light emission control voltage provided by the second light emission control voltage terminal to the second control terminal under the control of the first control signal provided by the first control terminal, and to write the light emission data voltage provided by the light emission data voltage terminal to the second light emission control terminal under the control of the potential of the second control terminal.

[0013] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a first energy storage circuit and a second energy storage circuit;

[0014] The first terminal of the first energy storage circuit is electrically connected to the first light-emitting control terminal, and the second terminal of the first energy storage circuit is electrically connected to the first initial voltage terminal. The first energy storage circuit is used to store electrical energy.

[0015] The first terminal of the second energy storage circuit is electrically connected to the second control terminal, and the second terminal of the second energy storage circuit is electrically connected to the second initial voltage terminal. The second energy storage circuit is used to store electrical energy.

[0016] Optionally, the light emission gating control circuit is also electrically connected to the light emission control signal terminal, and is also used to form the current path according to the light emission control signal provided by the light emission control signal terminal;

[0017] The light emission gating control circuit includes a third light emission control circuit, a write control circuit, a first control circuit, and a third energy storage circuit.

[0018] The write control circuit is electrically connected to the first control terminal, the first light emission control voltage terminal, and the write node, respectively, and is used to control the connection between the first light emission control voltage terminal and the write node under the control of the first control signal provided by the first control terminal.

[0019] The first control circuit is electrically connected to the control terminal of the third light-emitting control circuit, the writing node, the light-emitting data voltage terminal, and the light-emitting control signal terminal, respectively, and is used to control the writing of the light-emitting data voltage or the light-emitting control signal provided by the light-emitting control signal terminal to the control terminal of the third light-emitting control circuit under the control of the potential of the writing node.

[0020] The third light-emitting control circuit is electrically connected to the second electrode and the first voltage terminal of the light-emitting element, respectively. The third light-emitting control circuit is used to form the current path under the control of the potential of its control terminal.

[0021] The first terminal of the third energy storage circuit is electrically connected to the write node, and the second terminal of the third energy storage circuit is electrically connected to the initial voltage terminal. The third energy storage circuit is used to store electrical energy.

[0022] Optionally, the light emission gating control circuit includes a fourth light emission control circuit, a fifth light emission control circuit, a third gating control circuit, and a fourth energy storage circuit;

[0023] The third gating control circuit is electrically connected to the first control terminal, the first light emission control voltage terminal and the control terminal of the fourth light emission control circuit, respectively, and is used to control the first light emission control voltage terminal to write the first light emission control voltage to the control terminal of the fourth light emission control circuit under the control of the first control signal provided by the first control terminal.

[0024] The fourth light-emitting control circuit is also electrically connected to the second electrode and the first voltage terminal of the light-emitting element, respectively, to form the current path under the control of the potential of the control terminal of the fourth light-emitting control circuit;

[0025] The control terminal of the fifth light-emitting control circuit is electrically connected to the light-emitting data voltage terminal. The fifth light-emitting control circuit is also electrically connected to the second electrode and the first voltage terminal of the light-emitting element, respectively, to form the current path under the control of the potential of the control terminal of the fifth light-emitting control circuit.

[0026] The first terminal of the fourth energy storage circuit is electrically connected to the control terminal of the fourth light-emitting control circuit, and the second terminal of the fourth energy storage circuit is electrically connected to the initial voltage terminal. The fourth energy storage circuit is used to store electrical energy.

[0027] Optionally, the light emission gating control circuit includes a sixth light emission control circuit, a seventh light emission control circuit, a fourth gating control circuit, a fifth gating control circuit, and a fifth energy storage circuit;

[0028] The fourth gating control circuit is electrically connected to the first control terminal, the first light emission control voltage terminal, and the control terminal of the sixth light emission control circuit, respectively, and is used to control the connection between the first light emission control voltage terminal and the control terminal of the sixth light emission control circuit under the control of the first control signal.

[0029] The fifth gating control circuit is electrically connected to the control terminal of the sixth light-emitting control circuit, the light-emitting data voltage terminal, and the control terminal of the seventh light-emitting control circuit, respectively, and is used to control the light-emitting data voltage terminal to be electrically connected to the control terminal of the seventh light-emitting control circuit under the control of the potential of the control terminal of the sixth light-emitting control circuit.

[0030] The sixth light-emitting control circuit is electrically connected to the second electrode of the light-emitting element and the first voltage terminal, respectively, and is used to form the current path under the control of the potential of the control terminal of the sixth light-emitting control circuit;

[0031] The seventh light-emitting control circuit is electrically connected to the second electrode of the light-emitting element and the first voltage terminal, respectively, and is used to form the current path under the control of the potential of the control terminal of the seventh light-emitting control circuit.

[0032] The first terminal of the fifth energy storage circuit is electrically connected to the control terminal of the sixth light-emitting control circuit, and the second terminal of the fifth energy storage circuit is electrically connected to the initial voltage terminal. The fifth energy storage circuit is used to store electrical energy.

[0033] Optionally, the first light-emitting control circuit includes a first transistor, and the second light-emitting control circuit includes a second transistor;

[0034] The control electrode of the first transistor is electrically connected to the first light-emitting control terminal, the first electrode of the first transistor is electrically connected to the second electrode of the light-emitting element, and the second electrode of the first transistor is electrically connected to the first voltage terminal.

[0035] The control electrode of the second transistor is electrically connected to the second light-emitting control terminal, the first electrode of the second transistor is electrically connected to the second electrode of the light-emitting element, and the second electrode of the second transistor is electrically connected to the first voltage terminal.

[0036] Optionally, the driving circuit includes a driving transistor; the width-to-length ratio of the first transistor is greater than that of the driving transistor, and the width-to-length ratio of the second transistor is greater than that of the driving transistor.

[0037] Optionally, the first gating control circuit includes a third transistor;

[0038] The control electrode of the third transistor is electrically connected to the first control terminal, the first electrode of the third transistor is electrically connected to the first light-emitting control voltage terminal, and the second electrode of the third transistor is electrically connected to the first light-emitting control terminal.

[0039] The second gating control circuit includes a fourth transistor and a fifth transistor;

[0040] The control electrode of the fourth transistor is electrically connected to the first control terminal, the first electrode of the fourth transistor is electrically connected to the second light-emitting control voltage terminal, and the second electrode of the fourth transistor is electrically connected to the second control terminal.

[0041] The control electrode of the fifth transistor is electrically connected to the second control terminal, the first electrode of the fifth transistor is electrically connected to the light-emitting data voltage terminal, and the second electrode of the fifth transistor is electrically connected to the second light-emitting control terminal.

[0042] Optionally, both the third transistor and the fourth transistor are n-type transistors, or both the third transistor and the fourth transistor are p-type transistors.

[0043] Optionally, the first light-emitting control voltage terminal and the second light-emitting control voltage terminal are the same voltage terminal;

[0044] The first transistor is an n-type transistor, and the fifth transistor is a p-type transistor; or, the first transistor is a p-type transistor, and the fifth transistor is an n-type transistor.

[0045] Optionally, the write control circuit includes a sixth transistor, the first control circuit includes a seventh transistor and an eighth transistor, and the third light-emitting control circuit includes a ninth transistor;

[0046] The control electrode of the sixth transistor is electrically connected to the first control terminal, the first electrode of the sixth transistor is electrically connected to the first light-emitting control voltage terminal, and the second electrode of the sixth transistor is electrically connected to the write node.

[0047] The control electrode of the seventh transistor is electrically connected to the write node, the first electrode of the seventh transistor is electrically connected to the light-emitting data voltage terminal, and the second electrode of the seventh transistor is electrically connected to the control electrode of the ninth transistor.

[0048] The control electrode of the eighth transistor is electrically connected to the write node, the first electrode of the eighth transistor is electrically connected to the light emission control signal terminal, and the second electrode of the eighth transistor is electrically connected to the control electrode of the ninth transistor.

[0049] The first terminal of the ninth transistor is electrically connected to the second terminal of the light-emitting element, and the second terminal of the ninth transistor is electrically connected to the first voltage terminal.

[0050] Optionally, the sixth transistor is an n-type transistor or an oxide transistor.

[0051] Optionally, the seventh transistor is a p-type transistor and the eighth transistor is an n-type transistor; or, the seventh transistor is an n-type transistor and the eighth transistor is a p-type transistor.

[0052] Optionally, the sixth transistor is a p-type transistor, the seventh transistor is a p-type transistor, and the eighth transistor is an n-type transistor; or,

[0053] The sixth transistor is an n-type transistor, the seventh transistor is a p-type transistor, and the eighth transistor is an n-type transistor.

[0054] Optionally, the third gating control circuit includes a tenth transistor, the fourth light-emitting control circuit includes an eleventh transistor, and the fifth light-emitting control circuit includes a twelfth transistor;

[0055] The control electrode of the tenth transistor is electrically connected to the first control terminal, the first electrode of the tenth transistor is electrically connected to the first light-emitting control voltage terminal, and the second electrode of the tenth transistor is electrically connected to the control electrode of the eleventh transistor.

[0056] The first terminal of the eleventh transistor is electrically connected to the second terminal of the light-emitting element, and the second terminal of the eleventh transistor is electrically connected to the first voltage terminal;

[0057] The control electrode of the twelfth transistor is electrically connected to the light-emitting data voltage terminal, the first electrode of the twelfth transistor is electrically connected to the second electrode of the light-emitting element, and the second electrode of the twelfth transistor is electrically connected to the first voltage terminal.

[0058] Optionally, the tenth transistor is an n-type transistor or an oxide transistor.

[0059] Optionally, the tenth transistor, the eleventh transistor, and the twelfth transistor are all n-type transistors; or,

[0060] The tenth transistor is an n-type transistor, the eleventh transistor is an n-type transistor, and the twelfth transistor is a p-type transistor; or...

[0061] The tenth and twelfth transistors are p-type transistors, and the eleventh transistor is an n-type transistor; or...

[0062] The tenth, eleventh, and twelfth transistors are all p-type transistors; or,

[0063] The tenth transistor is an n-type transistor, and the eleventh and twelfth transistors are both p-type transistors.

[0064] Optionally, the sixth light-emitting control circuit includes a thirteenth transistor; the seventh light-emitting control circuit includes a fourteenth transistor; the fourth gating control circuit includes a fifteenth transistor; and the fifth gating control circuit includes a sixteenth transistor.

[0065] The control electrode of the fifteenth transistor is electrically connected to the first control terminal, the first electrode of the fifteenth transistor is electrically connected to the first light-emitting control voltage terminal, and the second electrode of the fifteenth transistor is electrically connected to the control electrode of the thirteenth transistor.

[0066] The control electrode of the sixteenth transistor is electrically connected to the control electrode of the thirteenth transistor, the first electrode of the sixteenth transistor is electrically connected to the light-emitting data voltage terminal, and the second electrode of the sixteenth transistor is electrically connected to the control electrode of the fourteenth transistor.

[0067] The first terminal of the thirteenth transistor is electrically connected to the second terminal of the light-emitting element, and the second terminal of the thirteenth transistor is electrically connected to the first voltage terminal;

[0068] The first terminal of the fourteenth transistor is electrically connected to the second terminal of the light-emitting element, and the second terminal of the fourteenth transistor is electrically connected to the first voltage terminal.

[0069] Optionally, the thirteenth, fourteenth, and fifteenth transistors are all n-type transistors, and the sixteenth transistor is a p-type transistor; or,

[0070] The thirteenth and fourteenth transistors are n-type transistors, and the fifteenth and sixteenth transistors are p-type transistors; or,

[0071] The thirteenth transistor is an n-type transistor, and the fourteenth, fifteenth, and sixteenth transistors are all p-type transistors; or,

[0072] The thirteenth, fourteenth, and fifteenth transistors are all n-type transistors, and the sixteenth transistor is a p-type transistor.

[0073] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a data writing circuit and a compensation switching circuit; the first terminal of the driving circuit is electrically connected to the second voltage terminal; the driving circuit is used to generate a driving current under the control of the potential of its control terminal;

[0074] The data writing circuit is electrically connected to the first scan line, the data line and the control terminal of the driving circuit, respectively, and is used to write the data voltage provided by the data line into the control terminal of the driving circuit under the control of the first scan signal provided by the first scan line.

[0075] The compensation switching circuit is electrically connected to the second scan line, the external compensation line, and the second terminal of the driving circuit, respectively, and is used to control the connection between the external compensation line and the second terminal of the driving circuit under the control of the second scan signal provided by the second scan line.

[0076] Optionally, the pixel circuit further includes a sixth energy storage circuit;

[0077] The first terminal of the sixth energy storage circuit is electrically connected to the control terminal of the drive circuit, and the second terminal of the sixth energy storage circuit is electrically connected to the second terminal of the drive circuit. The sixth energy storage circuit is used to store electrical energy; or...

[0078] The first terminal of the sixth energy storage circuit is electrically connected to the control terminal of the drive circuit, and the second terminal of the sixth energy storage circuit is electrically connected to the first terminal of the drive circuit. The sixth energy storage circuit is used to store electrical energy.

[0079] Optionally, the data writing circuit includes a seventeenth transistor, the compensation switching circuit includes an eighteenth transistor, and the driving circuit includes a driving transistor;

[0080] The control electrode of the seventeenth transistor is electrically connected to the first scan line, the first electrode of the seventeenth transistor is electrically connected to the data line, and the second electrode of the seventeenth transistor is electrically connected to the gate of the driving transistor.

[0081] The control electrode of the eighteenth transistor is electrically connected to the second scan line, the first electrode of the eighteenth transistor is electrically connected to the external compensation line, and the second electrode of the eighteenth transistor is electrically connected to the second electrode of the driving transistor.

[0082] The first terminal of the driving transistor is electrically connected to the second voltage terminal; the second terminal of the driving transistor is electrically connected to the first terminal of the light-emitting element. 24. The pixel circuit as claimed in claim 23, wherein the seventeenth transistor, the eighteenth transistor, and the driving transistor are all n-type transistors; or, the seventeenth transistor and the driving transistor are p-type transistors, and the eighteenth transistor is an n-type transistor or a p-type transistor.

[0083] Optionally, the sixth energy storage circuit includes a storage capacitor; the driving circuit includes a driving transistor;

[0084] The first terminal of the storage capacitor is electrically connected to the control electrode of the driving transistor, and the second terminal of the storage capacitor is electrically connected to the second electrode of the driving transistor; or...

[0085] The first end of the storage capacitor is electrically connected to the control electrode of the driving transistor, and the second end of the storage capacitor is electrically connected to the first electrode of the driving transistor.

[0086] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a data writing circuit, a compensation switching circuit, and a sixth energy storage circuit; the first terminal of the driving circuit is electrically connected to the second voltage terminal; the driving circuit is used to generate a driving current under the control of the potential at its control terminal.

[0087] The data writing circuit is electrically connected to the first scan line, the data line and the control terminal of the driving circuit, respectively, and is used to write the data voltage provided by the data line into the control terminal of the driving circuit under the control of the first scan signal provided by the first scan line.

[0088] The compensation switching circuit is electrically connected to the second scan line, the external compensation line, and the control terminal of the driving circuit, respectively, and is used to control the connection between the external compensation line and the control terminal of the driving circuit under the control of the second scan signal provided by the second scan line;

[0089] The first terminal of the sixth energy storage circuit is electrically connected to the control terminal of the drive circuit, and the second terminal of the sixth energy storage circuit is electrically connected to the first terminal of the drive circuit. The sixth energy storage circuit is used to store electrical energy.

[0090] Optionally, the data writing circuit includes a seventeenth transistor, the compensation switching circuit includes an eighteenth transistor, and the driving circuit includes a driving transistor;

[0091] The control electrode of the seventeenth transistor is electrically connected to the first scan line, the first electrode of the seventeenth transistor is electrically connected to the data line, and the second electrode of the seventeenth transistor is electrically connected to the gate of the driving transistor.

[0092] The control electrode of the eighteenth transistor is electrically connected to the second scan line, the first electrode of the eighteenth transistor is electrically connected to the external compensation line, and the second electrode of the eighteenth transistor is electrically connected to the control electrode of the driving transistor.

[0093] The first terminal of the driving transistor is electrically connected to the second voltage terminal; the second terminal of the driving transistor is electrically connected to the first terminal of the light-emitting element.

[0094] Optionally, the seventeenth transistor, the eighteenth transistor, and the driving transistor are all p-type transistors.

[0095] In a second aspect, embodiments of this disclosure also provide a pixel driving method applied to the aforementioned pixel circuit, the pixel driving method comprising:

[0096] Under the control of the first control signal, the light-emitting gating control circuit forms a current path between the second electrode of the light-emitting element and the first voltage terminal according to the first light-emitting control voltage and the light-emitting data voltage, so as to control the driving circuit to control the light-emitting element to emit light; or...

[0097] Under the control of the first control signal, the light emission gating control circuit forms a current path between the driving circuit and the light emission element according to the first light emission control voltage and the light emission data voltage, so as to control the driving circuit to control the light emission element to emit light.

[0098] Optionally, the light emission gating control circuit is also electrically connected to the second light emission control voltage terminal; the light emission gating control circuit includes a first light emission control circuit, a second light emission control circuit, a first gating control circuit, and a second gating control circuit;

[0099] The pixel driving method includes:

[0100] The first gating control circuit, under the control of the first control signal, writes the first light-emitting control voltage into the first light-emitting control terminal;

[0101] Under the control of the first control signal, the second gating control circuit writes the second light emission control voltage into the second control terminal, and under the control of the potential of the second control terminal, writes the light emission data voltage into the second light emission control terminal.

[0102] The first light-emitting control circuit controls the connection between the second electrode of the light-emitting element and the first voltage terminal under the control of the potential of the first light-emitting control terminal;

[0103] The second light-emitting control circuit controls the connection between the second electrode of the light-emitting element and the first voltage terminal under the control of the potential of the second light-emitting control terminal.

[0104] Optionally, the light emission gating control circuit is also electrically connected to the light emission control signal terminal; the light emission gating control circuit includes a third light emission control circuit, a write control circuit, and a first control circuit;

[0105] The pixel driving method includes:

[0106] Under the control of the first control signal, the write control circuit controls the connection between the first light emission control voltage terminal and the write node;

[0107] The first control circuit, under the control of the potential of the writing node, controls the writing of the light-emitting data voltage or light-emitting control signal to the control terminal of the third light-emitting control circuit.

[0108] The third light-emitting control circuit forms the current path under the control of the potential at its control terminal.

[0109] Optionally, the light emission gating control circuit includes a fourth light emission control circuit, a fifth light emission control circuit, and a third gating control circuit; the pixel driving method includes:

[0110] Under the control of the first control signal, the third gating control circuit controls the first light emission control voltage terminal to write the first light emission control voltage to the control terminal of the fourth light emission control circuit.

[0111] The fourth light-emitting control circuit forms the current path under the control of the potential at its control terminal;

[0112] The fifth light-emitting control circuit forms the current path under the control of the potential at its control terminal.

[0113] Optionally, the light emission gating control circuit includes a sixth light emission control circuit, a seventh light emission control circuit, a fourth gating control circuit, and a fifth gating control circuit; the pixel driving method includes:

[0114] Under the control of the first control signal, the fourth gating control circuit controls the connection between the first light emission control voltage terminal and the control terminal of the sixth light emission control circuit.

[0115] The fifth gating control circuit, under the control of the potential of the control terminal of the sixth light-emitting control circuit, controls the light-emitting data voltage terminal to be electrically connected to the control terminal of the seventh light-emitting control circuit.

[0116] The sixth light-emitting control circuit forms the current path under the control of the potential at its control terminal;

[0117] The seventh light-emitting control circuit forms the current path under the control of the potential at its control terminal.

[0118] In a third aspect, embodiments of this disclosure provide a display device including the pixel circuit described above. Attached Figure Description

[0119] Figure 1 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0120] Figure 2 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0121] Figure 3 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0122] Figure 4 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0123] Figure 5 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0124] Figure 6 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0125] Figure 7 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0126] Figure 8 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0127] Figure 9 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0128] Figure 10 This is a public announcement. Figure 9 The timing diagram of at least one embodiment of the pixel circuit shown;

[0129] Figure 11 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0130] Figure 12 This is a public announcement. Figure 11 The timing diagram of at least one embodiment of the pixel circuit shown;

[0131] Figure 13 yes Figure 9 Simulation timing diagram of at least one embodiment of the pixel circuit shown;

[0132] Figure 14 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0133] Figure 15This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0134] Figure 16 This is a public announcement. Figure 15 The timing diagram of at least one embodiment of the pixel circuit shown;

[0135] Figure 17 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0136] Figure 18 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0137] Figure 19 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0138] Figure 20 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0139] Figure 21 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0140] Figure 22 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0141] Figure 23 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0142] Figure 24 This is a public announcement. Figure 23 The timing diagram of at least one embodiment of the pixel circuit shown;

[0143] Figure 25 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0144] Figure 26 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0145] Figure 27 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0146] Figure 28 This is a public announcement. Figure 27 The timing diagram of at least one embodiment of the pixel circuit shown;

[0147] Figure 29 This is a public announcement. Figure 27 Simulation timing diagram of at least one embodiment of the pixel circuit shown;

[0148] Figure 30This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0149] Figure 31 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0150] Figure 32 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0151] Figure 33 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0152] Figure 34 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0153] Figure 35 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0154] Figure 36 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0155] Figure 37 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0156] Figure 38 This is a public announcement. Figure 37 The timing diagram of at least one embodiment of the pixel circuit shown;

[0157] Figure 39 This is a public announcement. Figure 37 Simulation timing diagram of at least one embodiment of the pixel circuit shown;

[0158] Figure 40 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0159] Figure 41 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0160] Figure 42 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0161] Figure 43 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0162] Figure 44 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. Detailed Implementation

[0163] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0164] In all embodiments of this disclosure, the transistors used can be bipolar junction transistors (BJTs), thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the control terminal, one terminal is referred to as the first terminal and the other as the second terminal.

[0165] In actual operation, when the transistor is a bipolar junction transistor (BJT), the control electrode can be the base, the first electrode can be the collector, and the second electrode can be the emitter; or, the control electrode can be the base, the first electrode can be the emitter, and the second electrode can be the collector.

[0166] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the control electrode can be the gate, the first electrode can be the drain, and the second electrode can be the source; or, the control electrode can be the gate, the first electrode can be the source, and the second electrode can be the drain.

[0167] like Figure 1 As shown, the pixel circuit described in at least one embodiment of this disclosure includes a driving circuit 10, a light-emitting element F1, and a light-emitting gating control circuit X1;

[0168] The driving circuit 10 is electrically connected to the first electrode of the light-emitting element F1 and is used to drive the light-emitting element F1.

[0169] The light emission selection control circuit X1 is electrically connected to the second electrode, the first control terminal GC, the first light emission control voltage terminal VDT, and the light emission data voltage terminal VF of the light emission element F1, respectively. Under the control of the first control signal provided by the first control terminal GC, it forms a current path between the second electrode of the light emission element F1 and the first voltage terminal V1 according to the first light emission control voltage provided by the first light emission control voltage terminal VDT and the light emission data voltage HF provided by the light emission data terminal VF, so as to control the driving circuit 10 to control the light emission element to emit light.

[0170] The pixel circuit described in at least one embodiment of this disclosure can realize the dimming function through a simple structure. The embodiments of this disclosure can propose an external compensation pixel circuit with pulse width modulation function to realize low grayscale, which is beneficial to achieve high PPI (Pixels Per Inch).

[0171] In at least one embodiment of this disclosure, HF can be a high-frequency PWM (Pulse Width Modulation) signal.

[0172] Optionally, the first voltage terminal can be a low voltage terminal, but is not limited thereto.

[0173] like Figure 2 As shown, the pixel circuit described in at least one embodiment of this disclosure includes a driving circuit 10, a light-emitting element F1, and a light-emitting gating control circuit X1;

[0174] The driving circuit 10 is electrically connected to the light-emitting element F1 through the light-emitting gating control circuit X1;

[0175] The light emission selection control circuit X1 is electrically connected to the driving circuit 10, the first control terminal GC, the first control voltage terminal VDT, and the light emission data voltage terminal VF, respectively. Under the control of the first control signal, it forms a current path between the driving circuit 10 and the light emission element F1 according to the first light emission control voltage and the light emission data voltage HF, so as to control the driving circuit 10 to control the light emission element F1 to emit light.

[0176] The pixel circuit described in at least one embodiment of this disclosure can realize the dimming function through a simple structure. The embodiments of this disclosure can propose an external compensation pixel circuit with pulse width modulation function to realize low grayscale, which is beneficial to achieve high PPI (Pixels Per Inch).

[0177] Optionally, the light emission gating control circuit can also be electrically connected to the second light emission control voltage terminal; the light emission gating control circuit is also used to form the current path under the control of the second light emission control voltage provided by the second light emission control voltage terminal;

[0178] The light emission gating control circuit includes a first light emission control circuit, a second light emission control circuit, a first gating control circuit, and a second gating control circuit;

[0179] The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the second electrode of the light-emitting element, and the first voltage terminal, respectively, and is used to control the connection between the second electrode of the light-emitting element and the first voltage terminal under the control of the potential of the first light-emitting control terminal;

[0180] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the second electrode of the light-emitting element, and the first voltage terminal, respectively, and is used to control the connection between the second electrode of the light-emitting element and the first voltage terminal under the control of the potential of the second light-emitting control terminal;

[0181] The first gating control circuit is electrically connected to the first control terminal, the first light emission control voltage terminal and the first light emission control terminal respectively, and is used to write the first light emission control voltage provided by the first light emission control voltage terminal into the first light emission control terminal under the control of the first control signal provided by the first control terminal.

[0182] The second gating control circuit is electrically connected to the first control terminal, the second light emission control voltage terminal, the second control terminal, the light emission data voltage terminal, and the second light emission control terminal, respectively. It is used to write the second light emission control voltage provided by the second light emission control voltage terminal to the second control terminal under the control of the first control signal provided by the first control terminal, and to write the light emission data voltage provided by the light emission data voltage terminal to the second light emission control terminal under the control of the potential of the second control terminal.

[0183] like Figure 3 As shown, the pixel circuit described in this embodiment includes a driving circuit 10, a light-emitting element F1, a first light-emitting control circuit 11, a second light-emitting control circuit 12, a first gating control circuit 13, and a second gating control circuit 14.

[0184] The driving circuit 10 is electrically connected to the first electrode of the light-emitting element F1 and is used to drive the light-emitting element F1.

[0185] The first light-emitting control circuit 11 is electrically connected to the first light-emitting control terminal E1, the second electrode of the light-emitting element F1 and the first voltage terminal V1 respectively, and is used to control the connection between the second electrode of the light-emitting element F1 and the first voltage terminal V1 under the control of the potential of the first light-emitting control terminal E1.

[0186] The second light-emitting control circuit 12 is electrically connected to the second light-emitting control terminal E2, the second electrode of the light-emitting element F1, and the first voltage terminal V1, respectively, and is used to control the connection between the second electrode of the light-emitting element F1 and the first voltage terminal V1 under the control of the potential of the second light-emitting control terminal E2.

[0187] The first gating control circuit 13 is electrically connected to the first control terminal GC, the first light emission control voltage terminal VDT and the first light emission control terminal E1 respectively, and is used to write the first light emission control voltage provided by the first light emission control voltage terminal VDT into the first light emission control terminal E1 under the control of the first control signal provided by the first control terminal GC.

[0188] The second gating control circuit 14 is electrically connected to the first control terminal GC, the second light emission control voltage terminal DT, the second control terminal GD, the light emission data voltage terminal VF, and the second light emission control terminal E2, respectively. It is used to write the second light emission control voltage provided by the second light emission control voltage terminal DT to the second control terminal GD under the control of the first control signal provided by the first control terminal GC, and to write the light emission data voltage HF provided by the light emission data voltage terminal VF to the second light emission control terminal E2 under the control of the potential of the second control terminal GD.

[0189] In at least one embodiment of this disclosure, the first voltage terminal may be a low voltage terminal, but is not limited thereto.

[0190] In at least one embodiment of this disclosure, the light-emitting element may be a Micro LED (micro light-emitting diode) or a mini LED (mini light-emitting diode), but is not limited thereto.

[0191] This disclosure is as follows Figure 3 When the pixel circuit shown is working, the display cycle includes a first time period and a second time period that are set sequentially.

[0192] During the first time period, the first gating control circuit 13, under the control of the first control signal, writes the first light-emitting control voltage provided by VDT into the first light-emitting control terminal E1; the second gating control circuit 14, under the control of the first control signal, writes the second light-emitting control voltage provided by DT into the second control terminal GD; and the second gating control circuit 14, under the control of the potential of the second control terminal GD, writes the light-emitting data voltage HF into the second light-emitting control terminal E2.

[0193] During the second time period, when the first light-emitting control circuit 11 controls the second electrode of the light-emitting element F1 to be connected with the first voltage terminal V1 under the control of the potential of the first light-emitting control terminal E1, the driving circuit 10 drives the light-emitting element F1 to emit light and performs PAM (Pulse Amplitude Modulation) dimming operation.

[0194] During the second time period, when the first light-emitting control circuit 11 controls the second electrode of the light-emitting element F1 to disconnect from the first voltage terminal V1 under the control of the potential of the first light-emitting control terminal E1, the second light-emitting control circuit 12 controls the second electrode of the light-emitting element F1 to connect or disconnect from the first voltage terminal V1 under the control of the potential of the light-emitting data voltage HF, so as to perform PWM (pulse width modulation) dimming operation, wherein HF is a PWM signal.

[0195] The pixel circuit described in this disclosure can achieve dimming function through a simple structure. This disclosure provides an external compensation pixel circuit with pulse width modulation function to achieve low grayscale, which is beneficial to achieving high PPI (Pixels Per Inch).

[0196] In at least one embodiment of this disclosure, HF can be a high-frequency PWM signal, as described in this disclosure. Figure 1 When the pixel circuit shown is working, during the second time period, when the first light-emitting control circuit 11 controls the second electrode of the light-emitting element F1 to disconnect from the first voltage terminal V1 under the control of the potential of the first light-emitting control terminal E1, the second light-emitting control circuit 12 controls the second electrode of the light-emitting element F1 to connect or disconnect from the first voltage terminal V1 under the control of the potential of the light-emitting data voltage HF, so as to perform PWM (pulse width modulation) dimming operation, so as to control the light-emitting element F1 to emit light at a high frequency for a short time, so as to achieve low grayscale.

[0197] In at least one embodiment of this disclosure, the pixel circuit may further include a first energy storage circuit and a second energy storage circuit;

[0198] The first terminal of the first energy storage circuit is electrically connected to the first light-emitting control terminal, and the second terminal of the first energy storage circuit is electrically connected to the first initial voltage terminal. The first energy storage circuit is used to store electrical energy.

[0199] The first terminal of the second energy storage circuit is electrically connected to the second control terminal, and the second terminal of the second energy storage circuit is electrically connected to the second initial voltage terminal. The second energy storage circuit is used to store electrical energy.

[0200] like Figure 4 As shown, in Figure 3 Based on the pixel circuit embodiments shown, the pixel circuit of at least one embodiment of this disclosure further includes a first energy storage circuit 15 and a second energy storage circuit 16;

[0201] The first terminal of the first energy storage circuit 15 is electrically connected to the first light-emitting control terminal E1, and the second terminal of the first energy storage circuit 15 is electrically connected to the first initial voltage terminal I1. The first energy storage circuit 15 is used to store electrical energy; the first initial voltage terminal I1 is used to provide a first initial voltage.

[0202] The first terminal of the second energy storage circuit 16 is electrically connected to the second control terminal GD, and the second terminal of the second energy storage circuit 16 is electrically connected to the second initial voltage terminal I2. The second energy storage circuit 16 is used to store electrical energy; the second initial voltage terminal I2 is used to provide the second initial voltage.

[0203] In at least one embodiment of this disclosure, the first initial voltage terminal and the second initial voltage terminal may be the same initial voltage terminal, but this is not a limitation.

[0204] This disclosure is as follows Figure 4 In at least one embodiment of the pixel circuit shown, during operation, in a second time period, the first energy storage circuit 15 maintains the potential of the first light-emitting control terminal E1, and the second energy storage circuit 16 maintains the potential of the second control terminal GD.

[0205] In at least one embodiment of this disclosure, the light emission gating control circuit is also electrically connected to the light emission control signal terminal and is further used to form the current path according to the light emission control signal provided by the light emission control signal terminal;

[0206] The light emission gating control circuit includes a third light emission control circuit, a write control circuit, a first control circuit, and a third energy storage circuit.

[0207] The write control circuit is electrically connected to the first control terminal, the first light emission control voltage terminal, and the write node, respectively, and is used to control the connection between the first light emission control voltage terminal and the write node under the control of the first control signal provided by the first control terminal.

[0208] The first control circuit is electrically connected to the control terminal of the third light-emitting control circuit, the writing node, the light-emitting data voltage terminal, and the light-emitting control signal terminal, respectively, and is used to control the writing of the light-emitting data voltage or the light-emitting control signal provided by the light-emitting control signal terminal to the control terminal of the third light-emitting control circuit under the control of the potential of the writing node.

[0209] The third light-emitting control circuit is electrically connected to the second electrode and the first voltage terminal of the light-emitting element, respectively. The third light-emitting control circuit is used to form the current path under the control of the potential of its control terminal.

[0210] The first terminal of the third energy storage circuit is electrically connected to the write node, and the second terminal of the third energy storage circuit is electrically connected to the initial voltage terminal. The third energy storage circuit is used to store electrical energy.

[0211] In a specific implementation, the light emission gating control circuit may include a third light emission control circuit, a write control circuit, and a first control circuit. Under the control of the first control signal, the write control circuit writes the first light emission control voltage provided by the first light emission control voltage terminal into the write node. Under the control of the potential of the write node, the first control circuit writes the light emission data voltage or light emission control signal into the control terminal of the third light emission control circuit. Under the control of the potential of its control terminal, the third light emission control circuit forms the current path. The third energy storage circuit is used to maintain the potential of the write node.

[0212] like Figure 5 As shown, in Figure 1 Based on the pixel circuit embodiments shown, in the pixel circuit described in at least one embodiment of this disclosure, the light emission gating control circuit includes a third light emission control circuit 31, a write control circuit 32, a first control circuit 33, and a third energy storage circuit 34.

[0213] The write control circuit 32 is electrically connected to the first control terminal GC, the first light emission control voltage terminal VDT, and the write node NW, respectively, and is used to control the connection between the first light emission control voltage terminal VDT and the write node NW under the control of the first control signal provided by the first control terminal GC.

[0214] The first control circuit 33 is electrically connected to the control terminal of the third light-emitting control circuit 31, the write node NW, the light-emitting data voltage terminal VF, and the light-emitting control signal terminal EM, respectively. It is used to control the writing of the light-emitting data voltage HF provided by the light-emitting data voltage terminal VF or the light-emitting control signal provided by the light-emitting control signal terminal EM to the control terminal of the third light-emitting control circuit 31 under the control of the potential of the write node NW.

[0215] The third light-emitting control circuit 31 is electrically connected to the second electrode and the first voltage terminal V1 of the light-emitting element F1, respectively. The third light-emitting control circuit 31 is used to form the current path under the control of the potential of its control terminal.

[0216] The first terminal of the third energy storage circuit 34 is electrically connected to the write node NW, and the second terminal of the third energy storage circuit 34 is electrically connected to the initial voltage terminal I0. The third energy storage circuit is used to store electrical energy.

[0217] This disclosure is as follows Figure 5 When at least one embodiment of the pixel circuit shown is in operation, the first display cycle may include a first write phase and a first light emission phase set sequentially, and the second display cycle may include a second write phase and a second light emission phase set sequentially.

[0218] In the first writing stage, under the control of the first control signal, the writing control circuit 32 controls the first light emission control voltage terminal VDT to connect with the writing node NW, and the first control circuit 33, under the control of the writing node NW, writes the light emission control signal provided by the light emission control signal terminal EM into the control terminal of the third light emission control circuit 31.

[0219] During the first light emission stage, the third energy storage circuit 34 maintains the potential of the write node NW; under the control of the write node NW, the first control circuit 33 writes the light emission control signal provided by the light emission control signal terminal EM into the control terminal of the third light emission control circuit 31; under the control of the light emission control signal provided by EM, the third light emission control circuit 31 forms the current path, and during the entire time of the first light emission stage, the driving circuit 10 drives the light emission element F1 to emit light in order to perform PAM dimming.

[0220] In the second writing stage, under the control of the first control signal, the writing control circuit 32 controls the first light emission control voltage terminal VDT to connect with the writing node NW, and the first control circuit 33, under the control of the writing node NW, writes the light emission data voltage HF to the control terminal of the third light emission control circuit 31.

[0221] During the second light emission stage, the third energy storage circuit 34 maintains the potential of the write node NW; under the control of the write node NW, the first control circuit 33 writes the light emission data voltage HF into the control terminal of the third light emission control circuit 31; under the control of the light emission data voltage HF, the third light emission control circuit 31 forms the current path, and the light emission data voltage HF can be a high-frequency PWM signal for PWM dimming.

[0222] Optionally, the light emission gating control circuit includes a fourth light emission control circuit, a fifth light emission control circuit, a third gating control circuit, and a fourth energy storage circuit;

[0223] The third gating control circuit is electrically connected to the first control terminal, the first light emission control voltage terminal and the control terminal of the fourth light emission control circuit, respectively, and is used to control the first light emission control voltage terminal to write the first light emission control voltage to the control terminal of the fourth light emission control circuit under the control of the first control signal provided by the first control terminal.

[0224] The fourth light-emitting control circuit is also electrically connected to the second electrode and the first voltage terminal of the light-emitting element, respectively, to form the current path under the control of the potential of the control terminal of the fourth light-emitting control circuit;

[0225] The control terminal of the fifth light-emitting control circuit is electrically connected to the light-emitting data voltage terminal. The fifth light-emitting control circuit is also electrically connected to the second electrode and the first voltage terminal of the light-emitting element, respectively, to form the current path under the control of the potential of the control terminal of the fifth light-emitting control circuit.

[0226] The first terminal of the fourth energy storage circuit is electrically connected to the control terminal of the fourth light-emitting control circuit, and the second terminal of the fourth energy storage circuit is electrically connected to the initial voltage terminal. The fourth energy storage circuit is used to store electrical energy.

[0227] In a specific implementation, the light emission gating control circuit may include a fourth light emission control circuit, a fifth light emission control circuit, and a third gating control circuit. Under the control of the first control signal, the third gating control circuit writes the first light emission control voltage into the control terminal of the fourth light emission control circuit. Under the control of the potential of its control terminal, the fourth light emission control terminal circuit forms the current path. Under the control of the light emission data voltage, the fifth light emission control circuit forms the current path. The fourth energy storage circuit maintains the potential of the control terminal of the fourth light emission control circuit.

[0228] like Figure 6 As shown, in Figure 1 Based on the pixel circuit embodiments shown, in at least one embodiment of the pixel circuit described in this disclosure, the light emission gating control circuit includes a fourth light emission control circuit 41, a fifth light emission control circuit 42, a third gating control circuit 43, and a fourth energy storage circuit 44.

[0229] The third gating control circuit 43 is electrically connected to the first control terminal GC, the first light emission control voltage terminal VDT and the control terminal of the fourth light emission control circuit 41 respectively, and is used to control the first light emission control voltage terminal VDT to write the first light emission control voltage to the control terminal of the fourth light emission control circuit 41 under the control of the first control signal provided by the first control terminal GC.

[0230] The fourth light-emitting control circuit 41 is also electrically connected to the second electrode and the first voltage terminal V1 of the light-emitting element F1, respectively, to form the current path under the control of the potential of the control terminal of the fourth light-emitting control circuit 41.

[0231] The control terminal of the fifth light-emitting control circuit 42 is electrically connected to the light-emitting data voltage terminal VF. The fifth light-emitting control circuit 42 is also electrically connected to the second electrode and the first voltage terminal V1 of the light-emitting element F1, respectively, to form the current path under the control of the potential of the control terminal of the fifth light-emitting control circuit 42; the light-emitting data voltage terminal VF is used to provide the light-emitting data voltage HF.

[0232] The first terminal of the fourth energy storage circuit 44 is electrically connected to the control terminal of the fourth light-emitting control circuit 41, and the second terminal of the fourth energy storage circuit 44 is electrically connected to the initial voltage terminal I0. The fourth energy storage circuit 44 is used to store electrical energy.

[0233] This disclosure is as follows Figure 6 When at least one embodiment of the pixel circuit shown is in operation, the first display cycle includes a first write phase and a first light emission phase that are set sequentially, and the second display cycle includes a second write phase and a second light emission phase that are set sequentially.

[0234] During the first writing stage, the third gating control circuit 43, under the control of the first control signal, controls the first light-emitting control voltage terminal VDT to write the first light-emitting control voltage to the control terminal of the fourth light-emitting control circuit 41.

[0235] During the first light-emitting stage, the fourth energy storage circuit 44 maintains the potential of the control terminal of the fourth light-emitting control circuit 41; under the control of the potential of its control terminal, the fourth light-emitting control circuit 41 forms the current path, and during all the time of the first light-emitting stage, the driving circuit 10 drives the light-emitting element F1 for a period of time to perform PAM dimming.

[0236] In the second writing stage, the third gating control circuit 43, under the control of the first control signal, controls the first light-emitting control voltage terminal VDT to write the second first light-emitting control voltage to the control terminal of the fourth light-emitting control circuit 41.

[0237] During the second light-emitting stage, the fourth energy storage circuit 44 maintains the potential of the control terminal of the fourth light-emitting control circuit 41; the fifth light-emitting control circuit 42 forms the current path under the control of the light-emitting data voltage HF to perform PWM dimming; the light-emitting data voltage HF is a high-frequency PWM signal.

[0238] Optionally, the light emission gating control circuit includes a sixth light emission control circuit, a seventh light emission control circuit, a fourth gating control circuit, a fifth gating control circuit, and a fifth energy storage circuit;

[0239] The fourth gating control circuit is electrically connected to the first control terminal, the first light emission control voltage terminal, and the control terminal of the sixth light emission control circuit, respectively, and is used to control the connection between the first light emission control voltage terminal and the control terminal of the sixth light emission control circuit under the control of the first control signal.

[0240] The fifth gating control circuit is electrically connected to the control terminal of the sixth light-emitting control circuit, the light-emitting data voltage terminal, and the control terminal of the seventh light-emitting control circuit, respectively, and is used to control the light-emitting data voltage terminal to be electrically connected to the control terminal of the seventh light-emitting control circuit under the control of the potential of the control terminal of the sixth light-emitting control circuit.

[0241] The sixth light-emitting control circuit is electrically connected to the second electrode of the light-emitting element and the first voltage terminal, respectively, and is used to form the current path under the control of the potential of the control terminal of the sixth light-emitting control circuit;

[0242] The seventh light-emitting control circuit is electrically connected to the second electrode of the light-emitting element and the first voltage terminal, respectively, and is used to form the current path under the control of the potential of the control terminal of the seventh light-emitting control circuit;

[0243] The first terminal of the fifth energy storage circuit is electrically connected to the control terminal of the sixth light-emitting control circuit, and the second terminal of the fifth energy storage circuit is electrically connected to the initial voltage terminal. The fifth energy storage circuit is used to store electrical energy.

[0244] In a specific implementation, the light emission gating control circuit may include a sixth light emission control circuit, a seventh light emission control circuit, a fourth gating control circuit, a fifth gating control circuit, and a fifth energy storage circuit. Under the control of the first control signal, the fourth gating control circuit controls the connection between the first light emission control voltage terminal and the control terminal of the sixth light emission control circuit. Under the control of the potential of the control terminal of the sixth light emission control circuit, the fifth gating control circuit controls the connection between the light emission data voltage terminal and the control terminal of the seventh light emission control circuit. Under the control of the potential of its control terminal, the sixth light emission control circuit forms the current path. Under the control of the potential of its control terminal, the seventh light emission control circuit forms the current path. The fifth energy storage circuit maintains the potential of the sixth light emission control circuit.

[0245] like Figure 7 As shown, in Figure 1 Based on the illustrated pixel circuit embodiment, in at least one embodiment of the pixel circuit described in this disclosure, the light emission gating control circuit includes a sixth light emission control circuit 51, a seventh light emission control circuit 52, a fourth gating control circuit 53, a fifth gating control circuit 54, and a fifth energy storage circuit 55.

[0246] The fourth gating control circuit 53 is electrically connected to the first control terminal GC, the first light emission control voltage terminal VDT, and the control terminal of the sixth light emission control circuit 51, respectively, and is used to control the connection between the first light emission control voltage terminal VDT and the control terminal of the sixth light emission control circuit 51 under the control of the first control signal provided by the first control terminal GC.

[0247] The fifth gating control circuit 54 is electrically connected to the control terminal of the sixth light-emitting control circuit 51, the light-emitting data voltage terminal VF, and the control terminal of the seventh light-emitting control circuit 52, respectively, and is used to control the light-emitting data voltage terminal VF to be electrically connected to the control terminal of the seventh light-emitting control circuit 52 under the control of the potential of the control terminal of the sixth light-emitting control circuit 51.

[0248] The sixth light-emitting control circuit 51 is electrically connected to the second electrode of the light-emitting element F1 and the first voltage terminal V1, respectively, and is used to form the current path under the control of the potential of the control terminal of the sixth light-emitting control circuit 51.

[0249] The seventh light-emitting control circuit 52 is electrically connected to the second electrode of the light-emitting element F1 and the first voltage terminal V1, respectively, and is used to form the current path under the control of the potential of the control terminal of the seventh light-emitting control circuit 52.

[0250] The first terminal of the fifth energy storage circuit 55 is electrically connected to the control terminal of the sixth light-emitting control circuit 51, and the second terminal of the fifth energy storage circuit 55 is electrically connected to the initial voltage terminal I0. The fifth energy storage circuit 55 is used to store electrical energy.

[0251] This disclosure Figure 7 In at least one embodiment of the pixel circuit shown, the display cycle may include a writing phase and a light-emitting phase that are set sequentially when in operation;

[0252] During the writing phase, the fourth gating control circuit 53, under the control of the first control signal, controls the connection between the first light emission control voltage terminal VDT and the control terminal of the sixth light emission control circuit 51, so as to transmit the first light emission control voltage provided by VDT to the sixth light emission control circuit 51.

[0253] During the light-emitting phase, the fifth energy storage circuit 55 maintains the potential of the control terminal of the sixth light-emitting control circuit 51;

[0254] During the writing phase, when the VDT provides the first first light emission control voltage, during the light emission phase, the sixth light emission control circuit 51 forms the current path under the control of the potential at its control terminal to perform PAM dimming.

[0255] During the writing phase, when the VDT provides the second first light-emitting control voltage, the fifth gating control circuit 54, under the control of the potential of the control terminal of the sixth light-emitting control circuit 51, controls the connection between the light-emitting data voltage terminal VF and the control terminal of the seventh light-emitting control circuit 52; during the light-emitting phase, the fifth energy storage circuit 55 maintains the potential of the control terminal of the sixth light-emitting control circuit 51, and the fifth gating control circuit 54, under the control of the potential of the control terminal of the sixth light-emitting control circuit 51, controls the connection between the light-emitting data voltage terminal VF and the control terminal of the seventh light-emitting control circuit 52. The seventh light-emitting control circuit 52, under the control of the light-emitting data voltage HF, forms the current path to perform PWM dimming, where HF can be a high-frequency PWM signal.

[0256] Optionally, the first light-emitting control circuit includes a first transistor, and the second light-emitting control circuit includes a second transistor;

[0257] The control electrode of the first transistor is electrically connected to the first light-emitting control terminal, the first electrode of the first transistor is electrically connected to the second electrode of the light-emitting element, and the second electrode of the first transistor is electrically connected to the first voltage terminal.

[0258] The control electrode of the second transistor is electrically connected to the second light-emitting control terminal, the first electrode of the second transistor is electrically connected to the second electrode of the light-emitting element, and the second electrode of the second transistor is electrically connected to the first voltage terminal.

[0259] In at least one embodiment of this disclosure, the driving circuit includes a driving transistor; the aspect ratio of the first transistor is greater than that of the driving transistor, and the aspect ratio of the second transistor is greater than that of the driving transistor.

[0260] In specific implementation, the aspect ratio of the driving transistor is determined according to the magnitude of the driving current it generates. The first transistor and the second transistor are switching transistors used for light emission control. The aspect ratio of the first transistor and the aspect ratio of the second transistor need to satisfy that the maximum current that can be provided under a small drain-source voltage Vds is greater than the driving current generated by the driving transistor. Therefore, the aspect ratio of the first transistor is set to be greater than the aspect ratio of the driving transistor, and the aspect ratio of the second transistor is set to be greater than the aspect ratio of the driving transistor.

[0261] Optionally, the first gating control circuit includes a third transistor;

[0262] The control electrode of the third transistor is electrically connected to the first control terminal, the first electrode of the third transistor is electrically connected to the first light-emitting control voltage terminal, and the second electrode of the third transistor is electrically connected to the first light-emitting control terminal.

[0263] Optionally, the second gating control circuit includes a fourth transistor and a fifth transistor;

[0264] The control electrode of the fourth transistor is electrically connected to the first control terminal, the first electrode of the fourth transistor is electrically connected to the second light-emitting control voltage terminal, and the second electrode of the fourth transistor is electrically connected to the second control terminal.

[0265] The control electrode of the fifth transistor is electrically connected to the second control terminal, the first electrode of the fifth transistor is electrically connected to the light-emitting data voltage terminal, and the second electrode of the fifth transistor is electrically connected to the second light-emitting control terminal.

[0266] In at least one embodiment of this disclosure, both the third transistor and the fourth transistor are n-type transistors, or both the third transistor and the fourth transistor are p-type transistors.

[0267] In at least one embodiment of this disclosure, the first light-emitting control voltage terminal and the second light-emitting control voltage terminal are the same voltage terminal;

[0268] The first transistor is an n-type transistor, and the fifth transistor is a p-type transistor; or, the first transistor is a p-type transistor, and the fifth transistor is an n-type transistor.

[0269] In practical implementation, the first transistor and the second transistor can be set to transistors of opposite types. In this case, the first light-emitting control voltage terminal and the second light-emitting control voltage terminal can be the same voltage terminal, which can reduce the number of voltage terminals used.

[0270] Optionally, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0271] The first terminal of the first capacitor is electrically connected to the first light-emitting control terminal, and the second terminal of the first capacitor is electrically connected to the first initial voltage terminal.

[0272] The first terminal of the second capacitor is electrically connected to the second control terminal, and the second terminal of the second capacitor is electrically connected to the second initial voltage terminal.

[0273] like Figure 8 As shown, in Figure 4 Based on at least one embodiment of the pixel circuit shown, the pixel circuit of at least one embodiment of this disclosure further includes a data writing circuit 61, a compensation switching circuit 62, and a sixth energy storage circuit 63; the first terminal of the driving circuit 10 is electrically connected to the second voltage terminal V2; the driving circuit 10 is used to generate a driving current under the control of the potential of its control terminal.

[0274] The data writing circuit 61 is electrically connected to the first scan line GA, the data line DA and the control terminal of the driving circuit 10, respectively, and is used to write the data voltage Vdata provided by the data line DA into the control terminal of the driving circuit 10 under the control of the first scan signal provided by the first scan line GA.

[0275] The compensation switching circuit 62 is electrically connected to the second scan line GB, the external compensation line R1 and the second end of the driving circuit 10 respectively, and is used to control the connection between the external compensation line R1 and the second end of the driving circuit 10 under the control of the second scan signal provided by the second scan line GB.

[0276] The first end of the sixth energy storage circuit 63 is electrically connected to the control end of the drive circuit 10, and the second end of the sixth energy storage circuit 63 is electrically connected to the second end of the drive circuit 10. The sixth energy storage circuit 63 is used to store electrical energy.

[0277] This disclosure is as follows Figure 8In at least one embodiment of the pixel circuit shown, during operation, in the first time period, the data writing circuit 61, under the control of the first scan signal, writes the data voltage Vdata provided by the data line DA into the control terminal of the driving circuit 10; the compensation switching circuit 62, under the control of the second scan signal, controls the external compensation line R1 to connect with the second terminal of the driving circuit 10, thereby realizing the reading of the threshold voltage Vth of the driving transistor in the driving circuit 10 and completing the compensation function (the actual compensation of the data voltage can be performed in the blank time period between adjacent frames, but is not limited to this).

[0278] The embodiments disclosed herein provide a pixel circuit with a simple structure and threshold voltage compensation and PWM dimming function, which is beneficial for achieving high PPI.

[0279] In at least one embodiment of this disclosure, the second voltage terminal may be a high voltage terminal, but is not limited thereto.

[0280] Optionally, the data writing circuit includes a seventeenth transistor, the compensation switching circuit includes an eighteenth transistor, the driving circuit includes a driving transistor, and the sixth energy storage circuit includes a storage capacitor;

[0281] The control electrode of the seventeenth transistor is electrically connected to the first scan line, the first electrode of the seventeenth transistor is electrically connected to the data line, and the second electrode of the seventeenth transistor is electrically connected to the gate of the driving transistor.

[0282] The control electrode of the eighteenth transistor is electrically connected to the second scan line, the first electrode of the eighteenth transistor is electrically connected to the external compensation line, and the second electrode of the eighteenth transistor is electrically connected to the second electrode of the driving transistor.

[0283] The first terminal of the driving transistor is electrically connected to the second voltage terminal; the second terminal of the driving transistor is electrically connected to the first terminal of the light-emitting element.

[0284] The first terminal of the storage capacitor is electrically connected to the control electrode of the driving transistor, and the second terminal of the storage capacitor is electrically connected to the second electrode of the driving transistor.

[0285] Optionally, the seventeenth transistor, the eighteenth transistor, and the driving transistor are all n-type transistors; or, the seventeenth transistor and the driving transistor are p-type transistors, and the eighteenth transistor is either an n-type transistor or a p-type transistor.

[0286] The pixel circuit described in at least one embodiment of this disclosure may further include a data writing circuit, a compensation switching circuit, and a sixth energy storage circuit; the first terminal of the driving circuit is electrically connected to the second voltage terminal; the driving circuit is used to generate a driving current under the control of the potential of its control terminal;

[0287] The data writing circuit is electrically connected to the first scan line, the data line and the control terminal of the driving circuit, respectively, and is used to write the data voltage provided by the data line into the control terminal of the driving circuit under the control of the first scan signal provided by the first scan line.

[0288] The compensation switching circuit is electrically connected to the second scan line, the external compensation line, and the control terminal of the driving circuit, respectively, and is used to control the connection between the external compensation line and the control terminal of the driving circuit under the control of the second scan signal provided by the second scan line;

[0289] The first terminal of the sixth energy storage circuit is electrically connected to the control terminal of the drive circuit, and the second terminal of the sixth energy storage circuit is electrically connected to the first terminal of the drive circuit. The sixth energy storage circuit is used to store electrical energy.

[0290] Optionally, the data writing circuit includes a seventeenth transistor, the compensation switching circuit includes an eighteenth transistor, and the driving circuit includes a driving transistor;

[0291] The control electrode of the seventeenth transistor is electrically connected to the first scan line, the first electrode of the seventeenth transistor is electrically connected to the data line, and the second electrode of the seventeenth transistor is electrically connected to the gate of the driving transistor.

[0292] The control electrode of the eighteenth transistor is electrically connected to the second scan line, the first electrode of the eighteenth transistor is electrically connected to the external compensation line, and the second electrode of the eighteenth transistor is electrically connected to the control electrode of the driving transistor.

[0293] The first terminal of the driving transistor is electrically connected to the second voltage terminal; the second terminal of the driving transistor is electrically connected to the first terminal of the light-emitting element.

[0294] Optionally, the seventeenth transistor, the eighteenth transistor, and the driving transistor are all p-type transistors.

[0295] like Figure 9 As shown, in Figure 8 Based on at least one embodiment of the pixel circuit shown, the first light-emitting control circuit 11 includes a first transistor T1, the second light-emitting control circuit 12 includes a second transistor T2; the driving circuit 10 includes a driving transistor T0; and the light-emitting element is a miniature light-emitting diode M1.

[0296] The gate of the first transistor T1 is electrically connected to the first light-emitting control terminal E1, the drain of the first transistor T1 is electrically connected to the cathode of the miniature light-emitting diode M1, and the source of the first transistor T1 is electrically connected to the low-voltage terminal VSS.

[0297] The gate of the second transistor T2 is electrically connected to the second light-emitting control terminal E2, the drain of the second transistor T2 is electrically connected to the cathode of the miniature light-emitting diode M1, and the source of the second transistor T2 is electrically connected to the low-voltage terminal VSS.

[0298] The first gating control circuit 13 includes a third transistor T3;

[0299] The gate of the third transistor T3 is electrically connected to the first control terminal GC, the drain of the third transistor T3 is electrically connected to the first light-emitting control voltage terminal VDT, and the source of the third transistor T3 is electrically connected to the first light-emitting control terminal E1.

[0300] The second gating control circuit 14 includes a fourth transistor T4 and a fifth transistor T5;

[0301] The gate of the fourth transistor T4 is electrically connected to the first control terminal GC, the drain of the fourth transistor T4 is electrically connected to the second light-emitting control voltage terminal DT, and the source of the fourth transistor T4 is electrically connected to the second control terminal GD.

[0302] The gate of the fifth transistor T5 is electrically connected to the second control terminal GD, the drain of the fifth transistor T5 is electrically connected to the light-emitting data voltage terminal VF, and the source of the fifth transistor T5 is electrically connected to the second light-emitting control terminal E2; the light-emitting data voltage terminal VF is used to provide the light-emitting data voltage HF.

[0303] The first energy storage circuit 15 includes a first capacitor C1, and the second energy storage circuit 16 includes a second capacitor C2;

[0304] The first terminal of the first capacitor C1 is electrically connected to the first light-emitting control terminal E1, and the second terminal of the first capacitor C1 is electrically connected to the initial voltage terminal I0; the initial voltage terminal I0 is used to provide the initial voltage Vinit.

[0305] The first terminal of the second capacitor C2 is electrically connected to the second control terminal GD, and the second terminal of the second capacitor C2 is electrically connected to the initial voltage terminal I0;

[0306] The data writing circuit 61 includes a seventeenth transistor T17, the compensation switching circuit 62 includes an eighteenth transistor T18, and the sixth energy storage circuit 63 includes a storage capacitor C0.

[0307] The gate of the seventeenth transistor T17 is electrically connected to the first scan line GA, the drain of the seventeenth transistor T17 is electrically connected to the data line DA, and the source of the seventeenth transistor T17 is electrically connected to the gate of the driving transistor T0.

[0308] The gate of the eighteenth transistor T18 is electrically connected to the second scan line GB, the drain of the eighteenth transistor T18 is electrically connected to the external compensation line R1, and the source of the eighteenth transistor T18 is electrically connected to the source of the driving transistor T0.

[0309] The drain of the driving transistor T0 is electrically connected to the high voltage terminal VDD; the source of the driving transistor T0 is electrically connected to the anode of M1.

[0310] The first terminal of the storage capacitor C0 is electrically connected to the gate of the driving transistor T0, and the second terminal of the storage capacitor C0 is electrically connected to the source of the driving transistor T0.

[0311] exist Figure 9 In at least one embodiment of the pixel circuit shown, all transistors are n-type thin-film transistors, but this is not a limitation.

[0312] exist Figure 9 In at least one embodiment shown, the first node N1 is electrically connected to the gate of the driving transistor T0, the second node N2 is electrically connected to the source of the driving transistor T0, and the third node N3 is electrically connected to the cathode of M1.

[0313] like Figure 10 As shown, this disclosure is as follows Figure 9 When at least one embodiment of the pixel circuit shown is in operation, the display period includes a first time period S1 and a second time period S2 that are set sequentially.

[0314] During the first time period S1, GA, GB, and GC all provide high voltage signals, VDT provides a low voltage signal, DT provides a high voltage signal, T6, T7, T3, and T4 are all turned on, data line DA writes the data voltage Vdata to the gate of T0, T7 is turned on, and the potential of N2 is read for external IC (integrated circuit) to compensate for the threshold voltage Vth of T0; the potential of E1 is low voltage, the potential of GD is high voltage, T5 is turned on, and HF is written to E2;

[0315] During the second time period S2, T1 is turned off, and T2 is turned on or off under the control of HF to achieve PWM dimming mode; when T2 is on, T0 drives M1 to emit light, and when T2 is off, T0 does not drive M1.

[0316] like Figure 10As shown, during the second time period S2, the light-emitting data voltage HF is a PWM signal. Different HF pulse widths result in different grayscale levels being displayed.

[0317] exist Figure 10 In the process, when the potential of the first scan signal provided by GA is a high voltage, the potential of the first scan signal can be greater than or equal to 7V and less than or equal to 10V; when the potential of the first scan signal is a low voltage, the potential of the first scan signal can be greater than or equal to -10V and less than or equal to -7V.

[0318] When the potential of the second scan signal provided by GB is high, the potential of the second scan signal can be greater than or equal to 7V and less than or equal to 10V; when the potential of the second scan signal is low, the potential of the second scan signal can be greater than or equal to -10V and less than or equal to -7V.

[0319] When the potential of the first control signal provided by the first control terminal GC is high, the potential of the first control signal can be greater than or equal to 7V and less than or equal to 10V; when the potential of the first control signal is low, the potential of the first control signal can be greater than or equal to -10V and less than or equal to -7V.

[0320] When the emitting data voltage HF is high, the voltage value of the emitting data voltage HF can be greater than or equal to 7V and less than or equal to 10V. When the emitting data voltage HF is low, the voltage value of the emitting data voltage HF can be greater than or equal to -10V and less than or equal to -7V.

[0321] When the first light-emitting control voltage provided by the first light-emitting control voltage terminal VDT is a high voltage, the voltage value of the first light-emitting control voltage can be greater than or equal to 7V and less than or equal to 10V. When the first light-emitting control voltage is a low voltage, the voltage value of the first light-emitting control voltage can be greater than or equal to -10V and less than or equal to -7V.

[0322] When the second light-emitting control voltage provided by the second light-emitting control voltage terminal DT is a high voltage, the voltage value of the second light-emitting control voltage can be greater than or equal to 7V and less than or equal to 10V. When the second light-emitting control voltage is a low voltage, the voltage value of the second light-emitting control voltage can be greater than or equal to -10V and less than or equal to -7V.

[0323] The voltage value of the data voltage Vdata provided by the data line DA can be greater than or equal to 0V and less than or equal to 6V;

[0324] However, this is not the only limit.

[0325] This disclosure is as follows Figure 9In at least one embodiment of the pixel circuit shown, when VDT ​​provides a high voltage signal during the first time period S1, T1 remains on during the second time period S2 so that T0 drives M1 to emit light.

[0326] exist Figure 9 In at least one embodiment of the pixel circuit shown, T0 is a current output transistor, and the aspect ratio of T0 is specifically determined according to the magnitude of the driving current it needs to generate. T1 and T2 are switching transistors used for light emission control. The aspect ratios of T1 and T2 need to satisfy that the maximum current that can be provided under a small drain-source voltage Vds is greater than the driving current generated by T0. The aspect ratio of T1 can be set to be greater than the aspect ratio of T0, and the aspect ratio of T2 can be set to be greater than the aspect ratio of T0.

[0327] Figure 11 At least one embodiment of the pixel circuit shown is Figure 8 The difference in at least one embodiment of the pixel circuit shown is that the fifth transistor T5 is a p-type transistor;

[0328] The drain of the third transistor T3 is electrically connected to the second light-emitting control voltage terminal DT.

[0329] exist Figure 11 In at least one embodiment shown, the first light emission control voltage terminal and the second light emission control voltage terminal DT are the same voltage terminal, so as to reduce the number of voltage terminals used and facilitate the removal of the frame.

[0330] like Figure 12 As shown, this disclosure is as follows Figure 11 When at least one embodiment of the pixel circuit shown is in operation, the display period includes a first time period S1 and a second time period S2 that are set sequentially.

[0331] In the first time period S1, GA, GB, and GC all provide high voltage signals, DT provides a low voltage signal, T6, T7, T3, and T4 are all turned on, data line DA writes the data voltage Vdata to the gate of T0, T7 is turned on, and the potential of N2 is read for external IC (integrated circuit) to compensate for the threshold voltage Vth of T0; the potential of E1 is low voltage, the potential of GD is high voltage, T5 is turned on, and HF is written to E2;

[0332] During the second time period S2, T1 is turned off, and T2 is turned on or off under the control of HF to achieve PWM dimming mode; when T2 is on, T0 drives M1 to emit light, and when T2 is off, T0 does not drive M1.

[0333] like Figure 12 As shown, during the second time period S2, the emitting data voltage HF is a PWM signal.

[0334] like Figure 11 In at least one embodiment of the pixel circuit shown, when DT provides a high voltage signal during a first time period S1, T1 is turned on during a second time period S2, and T0 drives M1 to emit light.

[0335] exist Figure 12 In the process, when the potential of the first scan signal provided by GA is a high voltage, the potential of the first scan signal can be greater than or equal to 7V and less than or equal to 10V; when the potential of the first scan signal is a low voltage, the potential of the first scan signal can be greater than or equal to -10V and less than or equal to -7V.

[0336] When the potential of the second scan signal provided by GB is high, the potential of the second scan signal can be greater than or equal to 7V and less than or equal to 10V; when the potential of the second scan signal is low, the potential of the second scan signal can be greater than or equal to -10V and less than or equal to -7V.

[0337] When the potential of the first control signal provided by the first control terminal GC is high, the potential of the first control signal can be greater than or equal to 7V and less than or equal to 10V; when the potential of the first control signal is low, the potential of the first control signal can be greater than or equal to -10V and less than or equal to -7V.

[0338] When the emitting data voltage HF is high, the voltage value of the emitting data voltage HF can be greater than or equal to 7V and less than or equal to 10V. When the emitting data voltage HF is low, the voltage value of the emitting data voltage HF can be greater than or equal to -10V and less than or equal to -7V.

[0339] When the first light-emitting control voltage provided by the first light-emitting control voltage terminal VDT is a high voltage, the voltage value of the first light-emitting control voltage can be greater than or equal to 7V and less than or equal to 10V. When the first light-emitting control voltage is a low voltage, the voltage value of the first light-emitting control voltage can be greater than or equal to -10V and less than or equal to -7V.

[0340] When the second light-emitting control voltage provided by the second light-emitting control voltage terminal DT is a high voltage, the voltage value of the second light-emitting control voltage can be greater than or equal to 7V and less than or equal to 10V. When the second light-emitting control voltage is a low voltage, the voltage value of the second light-emitting control voltage can be greater than or equal to -10V and less than or equal to -7V.

[0341] The voltage value of the data voltage Vdata provided by the data line DA can be greater than or equal to 0V and less than or equal to 6V;

[0342] However, this is not the only limit.

[0343] Figure 13 yes Figure 9Simulation timing diagram of at least one embodiment of the pixel circuit shown.

[0344] exist Figure 13 In this context, Vgs is the gate-source voltage of T0, and Id is the drive current.

[0345] like Figure 14 As shown, in Figure 5 Based on at least one embodiment of the pixel circuit shown, the pixel circuit of at least one embodiment of this disclosure further includes a data writing circuit 61, a compensation switching circuit 62, and a sixth energy storage circuit 63; the first terminal of the driving circuit 10 is electrically connected to the second voltage terminal V2; the driving circuit 10 is used to generate a driving current under the control of the potential of its control terminal.

[0346] The data writing circuit 61 is electrically connected to the first scan line GA, the data line DA and the control terminal of the driving circuit 10, respectively, and is used to write the data voltage Vdata provided by the data line DA into the control terminal of the driving circuit 10 under the control of the first scan signal provided by the first scan line GA.

[0347] The compensation switching circuit 62 is electrically connected to the second scan line GB, the external compensation line R1 and the second end of the driving circuit 10 respectively, and is used to control the connection between the external compensation line R1 and the second end of the driving circuit 10 under the control of the second scan signal provided by the second scan line GB.

[0348] The first end of the sixth energy storage circuit 63 is electrically connected to the control end of the drive circuit 10, and the second end of the sixth energy storage circuit 63 is electrically connected to the second end of the drive circuit 10. The sixth energy storage circuit 63 is used to store electrical energy.

[0349] like Figure 15 As shown, in Figure 14 Based on at least one embodiment of the pixel circuit shown, the light-emitting element is a miniature light-emitting diode M1; the driving circuit 10 includes a driving transistor T0;

[0350] The write control circuit 32 includes a sixth transistor T6, the first control circuit 33 includes a seventh transistor T7 and an eighth transistor T8, and the third light emission control circuit 31 includes a ninth transistor T9.

[0351] The gate of the sixth transistor T6 is electrically connected to the first control terminal GC, the drain of the sixth transistor T6 is electrically connected to the first light emission control voltage terminal VDT, and the source of the sixth transistor T6 is electrically connected to the write node NW.

[0352] The gate of the seventh transistor T7 is electrically connected to the write node NW, the drain of the seventh transistor T7 is electrically connected to the light-emitting data voltage terminal VF, and the source of the seventh transistor T7 is electrically connected to the gate of the ninth transistor T9; the light-emitting data voltage terminal VF is used to provide the light-emitting data voltage HF.

[0353] The gate of the eighth transistor T8 is electrically connected to the write node NW, the drain of the eighth transistor T8 is electrically connected to the light emission control signal terminal EM, and the source of the eighth transistor T8 is electrically connected to the gate of the ninth transistor T9.

[0354] The drain of the ninth transistor T9 is electrically connected to the cathode of M1, and the source of the ninth transistor M9 is electrically connected to the low voltage terminal VSS.

[0355] The third energy storage circuit 34 includes a third capacitor C3;

[0356] The first end of C3 is electrically connected to the write node NW, and the second end of C3 is electrically connected to the initial voltage terminal I0, which is used to provide the initial voltage Vinit.

[0357] The data writing circuit 61 includes a seventeenth transistor T17, the compensation switching circuit 62 includes an eighteenth transistor T18, and the sixth energy storage circuit 63 includes a storage capacitor C0.

[0358] The gate of the seventeenth transistor T17 is electrically connected to the first scan line GA, the drain of the seventeenth transistor T17 is electrically connected to the data line DA, and the source of the seventeenth transistor T17 is electrically connected to the gate of the driving transistor T0.

[0359] The gate of the eighteenth transistor T18 is electrically connected to the second scan line GB, the drain of the eighteenth transistor T18 is electrically connected to the external compensation line R1, and the source of the eighteenth transistor T18 is electrically connected to the source of the driving transistor T0.

[0360] The drain of the driving transistor T0 is electrically connected to the high voltage terminal VDD; the source of the driving transistor T0 is electrically connected to the anode of M1.

[0361] The first terminal of the storage capacitor C0 is electrically connected to the gate of the driving transistor T0, and the second terminal of the storage capacitor C0 is electrically connected to the high voltage terminal VDD.

[0362] exist Figure 15In at least one embodiment of the pixel circuit shown, T17, T0, T7 and T9 are all p-type transistors, T18, T6 and T8 are all n-type transistors, T17, T0, T7 and T9 are all low-temperature polycrystalline silicon thin-film transistors, and T18, T6 and T8 are all oxide thin-film transistors, but are not limited thereto.

[0363] exist Figure 15 In at least one embodiment shown, the first node N1 is electrically connected to the gate of the driving transistor T0, the second node N2 is electrically connected to the source of the driving transistor T0, and the third node N3 is electrically connected to the cathode of M1.

[0364] This disclosure Figure 15 At least one embodiment of the pixel circuit shown is a pixel circuit that can realize PAM and PWM combined drive based on external compensation. It uses LTPS (low temperature polysilicon) and Oxide (oxide) integration process to fabricate oxide thin film transistors and low temperature polysilicon thin film transistors on the same backplane, which can achieve higher PPI (pixel density).

[0365] This disclosure Figure 15 At least one embodiment of the pixel circuit shown in operation employs PAM dimming for high grayscale display and PWM dimming for low grayscale display, thereby achieving uniform display across all grayscale levels.

[0366] In this public disclosure Figure 15 In at least one embodiment of the pixel circuit shown, T6 is an n-type transistor and an oxide thin-film transistor. The leakage current of the oxide thin-film transistor is two orders of magnitude smaller than that of the low-temperature polysilicon thin-film transistor. As a result, the requirement for the capacitance value of C3 is reduced, which is beneficial to achieving a higher PPI.

[0367] In practice, T6 can also be a p-type transistor.

[0368] like Figure 16 As shown in this disclosure Figure 15 When at least one embodiment of the pixel circuit shown is in operation, the first display cycle includes a first write stage S11 and a first light emission stage S12 that are set sequentially, and the second display cycle includes a second write stage S21 and a second light emission stage S22 that are set sequentially.

[0369] In the first write phase S11, GA provides a low voltage signal, GB provides a high voltage signal, GC provides a high voltage signal, VDT provides a high voltage signal to NW, T7 is turned off, T8 is turned on, and EM writes to the gate of T9; EM provides a high voltage signal, and T9 is turned off; T17 is turned on, and the data line DA writes the data voltage Vdata to the gate of T0; T18 is turned on, and the potential of N2 is read for external IC (integrated circuit) to compensate for the threshold voltage Vth of T0;

[0370] In the first light-emitting stage S12, C3 maintains the potential of NW, T7 is turned off, T8 is turned on, EM is written to the gate of T9, EM provides a low voltage signal, T9 is turned on, forming a current path between the cathode of M1 and VSS, and T0 drives M1 to emit light for PAM dimming.

[0371] In the second write stage S21, GA provides a low voltage signal, GB provides a high voltage signal, GC provides a high voltage signal, VDT provides a low voltage signal to NW, T7 is turned on, T8 is turned off, and HF writes to the gate of T9; HF provides a high voltage signal, and T9 is turned off; T17 is turned on, and the data line DA writes the data voltage Vdata to the gate of T0; T18 is turned on, and the potential of N2 is read for external IC (integrated circuit) to compensate for the threshold voltage Vth of T0;

[0372] In the second light-emitting stage S13, C3 maintains the potential of NW, T7 is turned on, T8 is turned off, and HF is written into the gate of T9. HF is a high-frequency PWM signal. When the potential of HF is high, T9 is turned on, and T0 drives M1 to emit light. When the potential of HF is low, T9 is turned off to achieve PWM dimming. When the on-pulse width of HF is different, different gray levels are displayed.

[0373] exist Figure 16 In the diagram, the driving current is labeled Id.

[0374] This disclosure Figure 15 In at least one embodiment of the pixel circuit shown, the HF gating stage and the EM gating stage are independently separated during operation, which facilitates control.

[0375] In this public disclosure Figure 15 In at least one embodiment of the pixel circuit shown, the type of each transistor is not limited to the types listed above, and each transistor can be an n-type transistor or a p-type transistor.

[0376] This disclosure Figure 17 At least one embodiment of the pixel circuit shown is consistent with this disclosure. Figure 15 The difference in at least one embodiment of the pixel circuit shown is that T6 is a p-type transistor and T6 is a low-temperature polycrystalline silicon thin-film transistor.

[0377] This disclosure Figure 18 At least one embodiment of the pixel circuit shown is consistent with this disclosure. Figure 15 The difference in at least one embodiment of the pixel circuit shown is that:

[0378] T0 and T17 are n-type transistors;

[0379] The second terminal of C0 is electrically connected to the source of T0;

[0380] M1 is positioned between T9 and the low-voltage terminal VSS.

[0381] This disclosure Figure 19 At least one embodiment of the pixel circuit shown is consistent with this disclosure. Figure 18 The difference in at least one embodiment of the pixel circuit shown is that T6 is a p-type transistor.

[0382] This disclosure Figure 20 At least one embodiment of the pixel circuit shown is consistent with this disclosure. Figure 19 The difference in at least one embodiment of the pixel circuit shown is that T0, T17 and T18 are p-type transistors;

[0383] The second terminal of C0 is electrically connected to VDD;

[0384] The source of T18 is electrically connected to the gate of T0.

[0385] This disclosure Figure 21 At least one embodiment of the pixel circuit shown is consistent with this disclosure. Figure 20 The difference in at least one embodiment of the pixel circuit shown is that T6 is an n-type transistor.

[0386] like Figure 22 As shown, in Figure 6 Based on at least one embodiment of the pixel circuit shown, the pixel circuit of at least one embodiment of this disclosure further includes a data writing circuit 61, a compensation switching circuit 62, and a sixth energy storage circuit 63; the first terminal of the driving circuit 10 is electrically connected to the second voltage terminal V2; the driving circuit 10 is used to generate a driving current under the control of the potential of its control terminal.

[0387] The data writing circuit 61 is electrically connected to the first scan line GA, the data line DA and the control terminal of the driving circuit 10, respectively, and is used to write the data voltage Vdata provided by the data line DA into the control terminal of the driving circuit 10 under the control of the first scan signal provided by the first scan line GA.

[0388] The compensation switching circuit 62 is electrically connected to the second scan line GB, the external compensation line R1 and the second end of the driving circuit 10 respectively, and is used to control the connection between the external compensation line R1 and the second end of the driving circuit 10 under the control of the second scan signal provided by the second scan line GB.

[0389] The first end of the sixth energy storage circuit 63 is electrically connected to the control end of the drive circuit 10, and the second end of the sixth energy storage circuit 63 is electrically connected to the second end of the drive circuit 10. The sixth energy storage circuit 63 is used to store electrical energy.

[0390] like Figure 23 As shown, in Figure 22 Based on at least one embodiment of the pixel circuit shown, in the pixel circuit described in at least one embodiment of this disclosure, the third gating control circuit 43 includes a tenth transistor T10, the fourth light-emitting control circuit 41 includes an eleventh transistor T11, the fifth light-emitting control circuit 42 includes a twelfth transistor T12; the fourth energy storage circuit 44 includes a fourth capacitor C4; the light-emitting element is a miniature light-emitting diode M1; and the driving circuit 10 includes a driving transistor T0.

[0391] The gate of the tenth transistor T10 is electrically connected to the first control terminal GC, the drain of the tenth transistor T10 is electrically connected to the first light-emitting control voltage terminal VDT, and the source of the tenth transistor T10 is electrically connected to the gate of the eleventh transistor T11.

[0392] The drain of the eleventh transistor T11 is electrically connected to the cathode of M1, and the source of the eleventh transistor T11 is electrically connected to the low voltage terminal VSS.

[0393] The gate of the twelfth transistor T12 is electrically connected to the light-emitting data voltage terminal VF, the drain of the twelfth transistor T12 is electrically connected to the cathode of M1, and the source of the twelfth transistor T12 is electrically connected to the low voltage terminal VSS; the light-emitting data voltage terminal VF is used to provide the light-emitting data voltage HF.

[0394] The first terminal of the fourth capacitor C4 is electrically connected to the gate of T11, and the second terminal of the fourth capacitor C4 is electrically connected to the initial voltage terminal I0, which is used to provide the initial voltage Vinit.

[0395] The data writing circuit 61 includes a seventeenth transistor T17, the compensation switching circuit 62 includes an eighteenth transistor T18, and the sixth energy storage circuit 63 includes a storage capacitor C0.

[0396] The gate of the seventeenth transistor T17 is electrically connected to the first scan line GA, the drain of the seventeenth transistor T17 is electrically connected to the data line DA, and the source of the seventeenth transistor T17 is electrically connected to the gate of the driving transistor T0.

[0397] The gate of the eighteenth transistor T18 is electrically connected to the second scan line GB, the drain of the eighteenth transistor T18 is electrically connected to the external compensation line R1, and the source of the eighteenth transistor T18 is electrically connected to the source of the driving transistor T0.

[0398] The drain of the driving transistor T0 is electrically connected to the high voltage terminal VDD; the source of the driving transistor T0 is electrically connected to the anode of M1.

[0399] The first terminal of the storage capacitor C0 is electrically connected to the gate of the driving transistor T0, and the second terminal of the storage capacitor C0 is electrically connected to the high voltage terminal VDD.

[0400] exist Figure 23 In at least one embodiment shown, the first node N1 is electrically connected to the gate of the driving transistor T0, the second node N2 is electrically connected to the source of the driving transistor T0, and the third node N3 is electrically connected to the cathode of M1.

[0401] In this public disclosure Figure 23 In at least one embodiment of the pixel circuit shown, T10 is an n-type transistor, T11 is an n-type transistor, T12 is a p-type transistor, T0 is a p-type transistor, T17 is a p-type transistor, and T18 is an n-type transistor; T10 is an oxide thin-film transistor, T11 is an oxide thin-film transistor, T12 is a low-temperature polycrystalline silicon thin-film transistor, T0 is a low-temperature polycrystalline silicon thin-film transistor, T17 is a low-temperature polycrystalline silicon thin-film transistor, and T18 is an oxide thin-film transistor, but not limited thereto.

[0402] This disclosure Figure 23 At least one embodiment of the pixel circuit shown is a pixel circuit that can realize PAM and PWM combined drive based on external compensation. It uses LTPS (low temperature polysilicon) and Oxide (oxide) integration process to fabricate oxide thin film transistors and low temperature polysilicon thin film transistors on the same backplane, which can achieve higher PPI (pixel density).

[0403] This disclosure Figure 23 At least one embodiment of the pixel circuit shown in operation employs PAM dimming for high grayscale display and PWM dimming for low grayscale display, thereby achieving uniform display across all grayscale levels.

[0404] In this public disclosure Figure 23 In at least one embodiment of the pixel circuit shown, T10 is an n-type transistor, and T10 is an oxide thin-film transistor. The leakage current of the oxide thin-film transistor is two orders of magnitude smaller than that of the low-temperature polysilicon thin-film transistor. As a result, the requirement for the capacitance value of C4 is reduced, which is beneficial to achieving a higher PPI.

[0405] In practice, T10 can also be a p-type transistor.

[0406] In this public disclosure Figure 23In at least one embodiment of the pixel circuit shown, since the drain of T12 is electrically connected to the cathode of M1, the source of T12 is electrically connected to the low voltage terminal VSS, and HF is a signal shared by all pixel circuits, T12 can be multiplexed among multiple pixel circuits. At the same time, by using LTPS and Oxide integration, and forming NTFT (n-type thin film transistor) and PTFT (p-type thin film transistor) processes on the same backplane, high PPI can be achieved.

[0407] like Figure 24 As shown, in Figure 23 When at least one embodiment of the pixel circuit shown is in operation, the first display cycle may include a first write stage S11 and a first light emission stage S12 that are set sequentially, and the second display cycle may include a second write stage S21 and a second light emission stage S22 that are set sequentially.

[0408] In the first write phase S11, GA provides a low voltage signal, GB provides a high voltage signal, GC provides a high voltage signal, T10 is turned on, VDT provides a high voltage signal to the gate of T11, and T11 is turned on; T17 is turned on, the data line DA writes the data voltage Vdata to the gate of T0, T18 is turned on, and the potential of N2 is read for external IC (integrated circuit) to compensate for the threshold voltage Vth of T0;

[0409] In the first light-emitting stage S12, C4 maintains the potential of the gate of T11, T11 is turned on, and T0 drives M1 to emit light in order to perform PAM dimming.

[0410] In the second write stage S21, GA provides a low voltage signal, GB provides a high voltage signal, GC provides a high voltage signal, and VDT provides a low voltage signal to the gate of T11, and T11 is turned off; T17 is turned on, the data line DA writes the data voltage Vdata to the gate of T0, T18 is turned on, and the potential of N2 is read for external IC (integrated circuit) to compensate for the threshold voltage Vth of T0.

[0411] In the second light-emitting stage S22, C4 maintains the potential of the gate of T11, T11 is turned off, and HF is a high-frequency PWM signal; when the potential of HF is high voltage, T12 is turned off; when the potential of HF is low voltage, T12 is turned on; so as to perform PWM dimming; different HF turn-on pulse widths result in different display gray levels.

[0412] exist Figure 24 In this context, Id represents the driving current.

[0413] In this public disclosure Figure 23 In at least one embodiment of the pixel circuit shown, the type of each transistor is not limited to the types listed above, and each transistor can be an n-type transistor or a p-type transistor.

[0414] This disclosure Figure 25 At least one embodiment of the pixel circuit shown is consistent with this disclosure. Figure 23 The difference in at least one embodiment of the pixel circuit shown is that T10 is a p-type transistor and T10 is a low-temperature polycrystalline silicon thin-film transistor.

[0415] This disclosure Figure 25 At least one embodiment of the pixel circuit shown is consistent with this disclosure. Figure 25 The difference in at least one embodiment of the pixel circuit shown is that: T11 is a p-type transistor, and T18 is a p-type transistor.

[0416] This disclosure Figure 27 At least one embodiment of the pixel circuit shown is consistent with this disclosure. Figure 23 The difference in at least one embodiment of the pixel circuit shown is that all transistors are n-type transistors, all transistors are oxide thin-film transistors, and the second terminal of C0 is electrically connected to the source of T0.

[0417] This disclosure Figure 23 , Figure 25 , Figure 26 , Figure 27 The pixel circuit shown in at least one embodiment has a simple structure, uses fewer transistors, can reduce the layout area, and further improve PPI while ensuring low grayscale display.

[0418] This disclosure Figure 27 In at least one embodiment of the pixel circuit shown, during high grayscale display, a high voltage signal is written to the gate of T11 by VDT during the writing phase, and T11 is turned on during the light-emitting phase; during low grayscale display, a low voltage signal is written to the gate of T11 by VDT during the writing phase, and T11 is turned off during the light-emitting phase, while T12 is turned on or off under the control of HF to achieve low grayscale display; by reasonably selecting the values ​​of T11 and T12, the number of transistors used can be reduced while maintaining stable drive current.

[0419] like Figure 28 As shown in this disclosure Figure 27 When at least one embodiment of the pixel circuit shown is in operation, the first display cycle includes a first write stage S11 and a first light emission stage S12 that are set sequentially, and the second display cycle includes a second write stage S21 and a second light emission stage S22 that are set sequentially.

[0420] In the first write phase S11, GA provides a low voltage signal, GB provides a high voltage signal, GC provides a high voltage signal, T10 is turned on, VDT provides a high voltage signal to the gate of T11, and T11 is turned on; T17 is turned on, the data line DA writes the data voltage Vdata to the gate of T0, T18 is turned on, and the potential of N2 is read for external IC (integrated circuit) to compensate for the threshold voltage Vth of T0;

[0421] In the first light-emitting stage S12, C4 maintains the potential of the gate of T11, T11 is turned on, and T0 drives M1 to emit light in order to perform PAM dimming.

[0422] In the second write stage S21, GA provides a low voltage signal, GB provides a high voltage signal, GC provides a high voltage signal, and VDT provides a low voltage signal to the gate of T11, and T11 is turned off; T17 is turned on, the data line DA writes the data voltage Vdata to the gate of T0, T18 is turned on, and the potential of N2 is read for external IC (integrated circuit) to compensate for the threshold voltage Vth of T0.

[0423] In the second light-emitting stage S22, C4 maintains the potential of the gate of T11, T11 is turned off, and HF is a high-frequency PWM signal; when the potential of HF is low, T12 is turned off; when the potential of HF is high, T12 is turned on; so as to perform PWM dimming; different HF turn-on pulse widths result in different display gray levels.

[0424] Figure 29 This is a public announcement Figure 27 The simulation timing diagram shows at least one embodiment of the pixel circuit. Figure 29 In the diagram, the current labeled Id represents the drive current.

[0425] This disclosure Figure 30 At least one embodiment of the pixel circuit shown is consistent with this disclosure. Figure 27 The differences between at least one embodiment of the pixel circuit shown are as follows:

[0426] T10, T11, and T12 are p-type transistors;

[0427] The second terminal of C0 is electrically connected to the source terminal of T0.

[0428] This disclosure Figure 31 At least one embodiment of the pixel circuit shown is consistent with this disclosure. Figure 30 The difference in at least one embodiment of the pixel circuit shown is as follows: T10 is an n-type transistor.

[0429] This disclosure Figure 32 At least one embodiment of the pixel circuit shown is consistent with this disclosure. Figure 30The differences in at least one embodiment of the pixel circuit shown are as follows: T0, T17, and T18 are p-type transistors;

[0430] The second terminal of C0 is electrically connected to VDD;

[0431] The source of T18 is electrically connected to the gate of T0.

[0432] This disclosure Figure 33 At least one embodiment of the pixel circuit shown is consistent with this disclosure. Figure 30 The difference in at least one embodiment of the pixel circuit shown is as follows: M1 is disposed between T9 and the low voltage terminal VSS.

[0433] This disclosure Figure 34 At least one embodiment of the pixel circuit shown is consistent with this disclosure. Figure 31 The difference in at least one embodiment of the pixel circuit shown is as follows: M1 is disposed between T9 and the low voltage terminal VSS.

[0434] This disclosure Figure 35 At least one embodiment of the pixel circuit shown is consistent with this disclosure. Figure 32 The difference in at least one embodiment of the pixel circuit shown is as follows: M1 is disposed between T9 and the low voltage terminal VSS.

[0435] like Figure 36 As shown, in Figure 7 Based on at least one embodiment of the pixel circuit shown, the pixel circuit of at least one embodiment of this disclosure further includes a data writing circuit 61, a compensation switching circuit 62, and a sixth energy storage circuit 63; the first terminal of the driving circuit 10 is electrically connected to the second voltage terminal V2; the driving circuit 10 is used to generate a driving current under the control of the potential of its control terminal.

[0436] The data writing circuit 61 is electrically connected to the first scan line GA, the data line DA and the control terminal of the driving circuit 10, respectively, and is used to write the data voltage Vdata provided by the data line DA into the control terminal of the driving circuit 10 under the control of the first scan signal provided by the first scan line GA.

[0437] The compensation switching circuit 62 is electrically connected to the second scan line GB, the external compensation line R1 and the second end of the driving circuit 10 respectively, and is used to control the connection between the external compensation line R1 and the second end of the driving circuit 10 under the control of the second scan signal provided by the second scan line GB.

[0438] The first end of the sixth energy storage circuit 63 is electrically connected to the control end of the drive circuit 10, and the second end of the sixth energy storage circuit 63 is electrically connected to the second end of the drive circuit 10. The sixth energy storage circuit 63 is used to store electrical energy.

[0439] like Figure 37 As shown, in Figure 36 Based on at least one embodiment of the pixel circuit shown, the light-emitting element is a miniature light-emitting diode M1, and the fifth energy storage circuit 55 includes a fifth capacitor C5;

[0440] The sixth light-emitting control circuit 51 includes a thirteenth transistor T13; the seventh light-emitting control circuit 52 includes a fourteenth transistor T14; the fourth gating control circuit 53 includes a fifteenth transistor T15; and the fifth gating control circuit 54 includes a sixteenth transistor T16.

[0441] The gate of the fifteenth transistor T15 is electrically connected to the first control terminal GC, the drain of the fifteenth transistor T15 is electrically connected to the first light-emitting control voltage terminal VDT, and the source of the fifteenth transistor T15 is electrically connected to the gate of the thirteenth transistor T13.

[0442] The gate of the sixteenth transistor T16 is electrically connected to the gate of the thirteenth transistor T13, the drain of the sixteenth transistor T16 is electrically connected to the light-emitting data voltage terminal VF, and the source of the sixteenth transistor T16 is electrically connected to the gate of the fourteenth transistor T14.

[0443] The drain of the thirteenth transistor T13 is electrically connected to the cathode of the miniature light-emitting diode M1, and the source of the thirteenth transistor T13 is electrically connected to the low-voltage terminal VSS.

[0444] The drain of the fourteenth transistor T14 is electrically connected to the cathode of the miniature light-emitting diode M1, and the source of the fourteenth transistor T14 is electrically connected to the low-voltage terminal VSS.

[0445] The first terminal of C5 is electrically connected to the gate of T13, and the second terminal of C5 is electrically connected to the initial voltage terminal I0, which is used to provide the initial voltage Vinit.

[0446] The data writing circuit 61 includes a seventeenth transistor T17, the compensation switching circuit 62 includes an eighteenth transistor T18, and the sixth energy storage circuit 63 includes a storage capacitor C0.

[0447] The gate of the seventeenth transistor T17 is electrically connected to the first scan line GA, the drain of the seventeenth transistor T17 is electrically connected to the data line DA, and the source of the seventeenth transistor T17 is electrically connected to the gate of the driving transistor T0.

[0448] The gate of the eighteenth transistor T18 is electrically connected to the second scan line GB, the drain of the eighteenth transistor T18 is electrically connected to the external compensation line R1, and the source of the eighteenth transistor T18 is electrically connected to the source of the driving transistor T0.

[0449] The drain of the driving transistor T0 is electrically connected to the high voltage terminal VDD; the source of the driving transistor T0 is electrically connected to the anode of M1.

[0450] The first terminal of the storage capacitor C0 is electrically connected to the gate of the driving transistor T0, and the second terminal of the storage capacitor C0 is electrically connected to the source of T0.

[0451] exist Figure 37 In at least one embodiment shown, the first node N1 is electrically connected to the gate of the driving transistor T0, the second node N2 is electrically connected to the source of the driving transistor T0, and the third node N3 is electrically connected to the cathode of M1.

[0452] exist Figure 37 In at least one embodiment of the pixel circuit shown, T16 is a p-type transistor, T16 is a low-temperature polysilicon thin-film transistor, and all transistors other than T16 are n-type transistors, and all transistors other than T16 are oxide thin-film transistors, but are not limited thereto.

[0453] This disclosure Figure 37 At least one embodiment of the pixel circuit shown is an externally compensated pixel circuit based on LTPO technology, which can realize high and low grayscale display, while minimizing flicker and alleviating eye fatigue during low grayscale display.

[0454] This disclosure Figure 37 In at least one embodiment of the pixel circuit shown, during medium-to-high grayscale display, the first light-emitting control voltage provided by the VDT controls the conduction of T13 to achieve a duty cycle of greater than 98%, thereby realizing medium-to-high grayscale display. During low grayscale display, in the light-emitting phase, T16 is turned on, and HF is written into the gate of T14. HF is a high-frequency PWM signal to achieve low grayscale display. Since HF is an equal-periodic pulse signal (e.g., 50 pulse signals in one frame), the display frequency is increased by 50 times, achieving a 3000Hz display and reducing eye strain.

[0455] This disclosure Figure 37 The pixel circuit shown in at least one embodiment uses fewer transistors and fewer capacitors, which can effectively reduce the layout area and improve the PPI.

[0456] This disclosure Figure 37In at least one embodiment of the pixel circuit shown, T16 can be disposed on the bottom layer of the stacked TFT (thin-film transistor), and the n-type transistor is located on the top layer. The stacked TFT can further improve the PPI.

[0457] like Figure 38 As shown in this disclosure Figure 37 When at least one embodiment of the pixel circuit shown is in operation, the display cycle may include a writing phase S01 and a light-emitting phase S02 that are set sequentially.

[0458] During the write phase S01, GA, GB, and GC all provide high voltage signals, T15 is turned on, T17 is turned on, the data line DA writes the data voltage Vdata to the gate of T0, T18 is turned on, and the potential of N2 is read for external IC (integrated circuit) to compensate for the threshold voltage Vth of T0.

[0459] During the write phase S01, when VDT ​​provides a high voltage signal, the gate of T13 is connected to the high voltage signal, T13 is turned on, and T16 is turned off.

[0460] During the write phase S01, when VDT ​​provides a low voltage signal, the gate of T13 is connected to the low voltage signal, the gate of T16 is connected to the low voltage signal, T16 is turned on, and HF is connected to the gate of T14.

[0461] During the light-emitting phase S02, C5 maintains the potential of the gate of T13;

[0462] When a high voltage signal is applied to the gate of T13 during the writing stage S01, T13 is turned on during the light emission stage S02, and T0 drives M1 to emit light.

[0463] When a low voltage signal is applied to the gate of T13 during the writing stage S01, T16 is turned on during the light emission stage S02, and HF is written to the gate of T14. When the potential of HF is low, T14 is turned off; when the potential of HF is high, T14 is turned on, and T0 drives M1 to emit light, thereby realizing low grayscale PWM modulation.

[0464] exist Figure 38 In the diagram, VDT1 is the first first light-emitting control voltage, and VDT2 is the second first light-emitting control voltage.

[0465] Figure 39 This is a public announcement. Figure 37 Simulation timing diagram of at least one embodiment of the pixel circuit shown.

[0466] exist Figure 39 In the diagram, Vgs represents the gate-source voltage of T0, and Id represents the drive current.

[0467] This disclosure Figure 40At least one embodiment of the pixel circuit shown is consistent with this disclosure. Figure 37 The difference in at least one embodiment of the pixel circuit shown is that T15 is a p-type transistor.

[0468] This disclosure Figure 41 At least one embodiment of the pixel circuit shown is consistent with this disclosure. Figure 40 The difference in at least one embodiment of the pixel circuit shown is that T14 is a p-type transistor.

[0469] This disclosure Figure 42 At least one embodiment of the pixel circuit shown is consistent with this disclosure. Figure 37 The difference in at least one embodiment of the pixel circuit shown is that T0, T17 and T18 are p-type transistors;

[0470] The second terminal of C0 is electrically connected to VDD;

[0471] The source of T18 is electrically connected to the gate of T0.

[0472] This disclosure Figure 43 At least one embodiment of the pixel circuit shown is consistent with this disclosure. Figure 40 The difference in at least one embodiment of the pixel circuit shown is that T0, T17 and T18 are p-type transistors;

[0473] The second terminal of C0 is electrically connected to VDD;

[0474] The source of T18 is electrically connected to the gate of T0.

[0475] This disclosure Figure 44 At least one embodiment of the pixel circuit shown is consistent with this disclosure. Figure 41 The difference in at least one embodiment of the pixel circuit shown is that T0, T17 and T18 are p-type transistors;

[0476] The second terminal of C0 is electrically connected to VDD;

[0477] The source of T18 is electrically connected to the gate of T0.

[0478] In this public disclosure Figure 9 , Figure 11 , Figure 15 , Figure 17 , Figure 23 , Figure 25 , Figure 26 , Figure 27 , Figure 30 , Figure 31 , Figure 32 , Figure 37 , Figure 40 , Figure 41 , Figure 42 , Figure 43 and Figure 44 In at least one embodiment of the pixel circuit shown, M1 can also be replaced by being disposed on its cathode and directly electrically connected to the low voltage terminal VSS.

[0479] In at least one embodiment of this disclosure, when the type of transistor changes, that is, when the transistor changes from an n-type transistor to a p-type transistor, or when the transistor changes from a p-type transistor to an n-type transistor, the potential of the transistor's gate is reversed.

[0480] The pixel driving method described in this disclosure is applied to the pixel circuit described above, and the pixel driving method includes:

[0481] Under the control of the first control signal, the light emission gating control circuit forms a current path between the second electrode of the light emission element and the first voltage terminal according to the first light emission control voltage and the light emission data voltage, so as to control the driving circuit to control the light emission element to emit light.

[0482] In at least one embodiment of this disclosure, the light emission gating control circuit is also electrically connected to a second light emission control voltage terminal; the light emission gating control circuit includes a first light emission control circuit, a second light emission control circuit, a first gating control circuit, and a second gating control circuit;

[0483] The pixel driving method includes:

[0484] The first gating control circuit, under the control of the first control signal, writes the first light-emitting control voltage into the first light-emitting control terminal;

[0485] Under the control of the first control signal, the second gating control circuit writes the second light emission control voltage into the second control terminal, and under the control of the potential of the second control terminal, writes the light emission data voltage into the second light emission control terminal.

[0486] The first light-emitting control circuit controls the connection between the second electrode of the light-emitting element and the first voltage terminal under the control of the potential of the first light-emitting control terminal;

[0487] The second light-emitting control circuit controls the connection between the second electrode of the light-emitting element and the first voltage terminal under the control of the potential of the second light-emitting control terminal.

[0488] In at least one embodiment of this disclosure, the light emission gating control circuit is also electrically connected to the light emission control signal terminal; the light emission gating control circuit includes a third light emission control circuit, a write control circuit, and a first control circuit;

[0489] The pixel driving method includes:

[0490] Under the control of the first control signal, the write control circuit controls the connection between the first light emission control voltage terminal and the write node;

[0491] The first control circuit, under the control of the potential of the writing node, controls the writing of the light-emitting data voltage or light-emitting control signal to the control terminal of the third light-emitting control circuit.

[0492] The third light-emitting control circuit forms the current path under the control of the potential at its control terminal.

[0493] In at least one embodiment of this disclosure, the light emission gating control circuit includes a fourth light emission control circuit, a fifth light emission control circuit, and a third gating control circuit; the pixel driving method includes:

[0494] Under the control of the first control signal, the third gating control circuit controls the first light emission control voltage terminal to write the first light emission control voltage to the control terminal of the fourth light emission control circuit.

[0495] The fourth light-emitting control circuit forms the current path under the control of the potential at its control terminal;

[0496] The fifth light-emitting control circuit forms the current path under the control of the potential at its control terminal.

[0497] In at least one embodiment of this disclosure, the light emission gating control circuit includes a sixth light emission control circuit, a seventh light emission control circuit, a fourth gating control circuit, and a fifth gating control circuit; the pixel driving method includes:

[0498] Under the control of the first control signal, the fourth gating control circuit controls the connection between the first light emission control voltage terminal and the control terminal of the sixth light emission control circuit.

[0499] The fifth gating control circuit, under the control of the potential of the control terminal of the sixth light-emitting control circuit, controls the light-emitting data voltage terminal to be electrically connected to the control terminal of the seventh light-emitting control circuit.

[0500] The sixth light-emitting control circuit forms the current path under the control of the potential at its control terminal;

[0501] The seventh light-emitting control circuit forms the current path under the control of the potential at its control terminal.

[0502] The display device described in this disclosure includes the pixel circuit described above.

[0503] The display device provided in this disclosure can be any product or component with display function, such as wearable devices, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, and navigators.

[0504] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A pixel circuit, characterized in that, Includes driving circuit, light-emitting element, and light-emitting gating control circuit; The driving circuit is electrically connected to the first electrode of the light-emitting element and is used to drive the light-emitting element; the light-emitting gating control circuit is electrically connected to the second electrode, the first control terminal, the first light-emitting control voltage terminal, and the light-emitting data voltage terminal of the light-emitting element, respectively, and is used to form a current path between the second electrode and the first voltage terminal of the light-emitting element according to the first light-emitting control voltage provided by the first control terminal and the light-emitting data voltage provided by the light-emitting data voltage terminal, under the control of the first control signal provided by the first control terminal, so as to control the driving circuit to control the light-emitting element to emit light; or, The driving circuit is electrically connected to the light-emitting element through the light-emitting gating circuit; the light-emitting gating control circuit is electrically connected to the driving circuit, the first control terminal, the first control voltage terminal and the light-emitting data voltage terminal respectively, and is used to form a current path between the driving circuit and the light-emitting element according to the first light-emitting control voltage and the light-emitting data voltage under the control of the first control signal, so as to control the driving circuit to control the light-emitting element to emit light. The light emission gating control circuit is also electrically connected to the light emission control signal terminal and is also used to form the current path according to the light emission control signal provided by the light emission control signal terminal; The light emission gating control circuit includes a third light emission control circuit, a write control circuit, a first control circuit, and a third energy storage circuit. The write control circuit is electrically connected to the first control terminal, the first light emission control voltage terminal, and the write node, respectively, and is used to control the connection between the first light emission control voltage terminal and the write node under the control of the first control signal provided by the first control terminal. The first control circuit is electrically connected to the control terminal of the third light-emitting control circuit, the writing node, the light-emitting data voltage terminal, and the light-emitting control signal terminal, respectively, and is used to control the writing of the light-emitting data voltage or the light-emitting control signal provided by the light-emitting control signal terminal to the control terminal of the third light-emitting control circuit under the control of the potential of the writing node. The third light-emitting control circuit is electrically connected to the second electrode and the first voltage terminal of the light-emitting element, respectively. The third light-emitting control circuit is used to form the current path under the control of the potential of its control terminal. The first terminal of the third energy storage circuit is electrically connected to the write node, and the second terminal of the third energy storage circuit is electrically connected to the initial voltage terminal. The third energy storage circuit is used to store electrical energy.

2. The pixel circuit as described in claim 1, characterized in that, The write control circuit includes a sixth transistor, the first control circuit includes a seventh transistor and an eighth transistor, and the third light emission control circuit includes a ninth transistor. The control electrode of the sixth transistor is electrically connected to the first control terminal, the first electrode of the sixth transistor is electrically connected to the first light-emitting control voltage terminal, and the second electrode of the sixth transistor is electrically connected to the write node. The control electrode of the seventh transistor is electrically connected to the write node, the first electrode of the seventh transistor is electrically connected to the light-emitting data voltage terminal, and the second electrode of the seventh transistor is electrically connected to the control electrode of the ninth transistor. The control electrode of the eighth transistor is electrically connected to the write node, the first electrode of the eighth transistor is electrically connected to the light emission control signal terminal, and the second electrode of the eighth transistor is electrically connected to the control electrode of the ninth transistor. The first terminal of the ninth transistor is electrically connected to the second terminal of the light-emitting element, and the second terminal of the ninth transistor is electrically connected to the first voltage terminal.

3. The pixel circuit as described in claim 2, characterized in that, The sixth transistor is an n-type transistor and an oxide transistor.

4. The pixel circuit as described in claim 2, characterized in that, The seventh transistor is a p-type transistor and the eighth transistor is an n-type transistor; or, the seventh transistor is an n-type transistor and the eighth transistor is a p-type transistor.

5. The pixel circuit as described in claim 2, characterized in that, The sixth transistor is a p-type transistor, the seventh transistor is a p-type transistor, and the eighth transistor is an n-type transistor; or... The sixth transistor is an n-type transistor, the seventh transistor is a p-type transistor, and the eighth transistor is an n-type transistor.

6. The pixel circuit according to any one of claims 1 to 5, characterized in that, It also includes a data writing circuit and a compensation switching circuit; the first terminal of the driving circuit is electrically connected to the second voltage terminal; the driving circuit is used to generate a driving current under the control of the potential at its control terminal; The data writing circuit is electrically connected to the first scan line, the data line and the control terminal of the driving circuit, respectively, and is used to write the data voltage provided by the data line into the control terminal of the driving circuit under the control of the first scan signal provided by the first scan line. The compensation switching circuit is electrically connected to the second scan line, the external compensation line, and the second terminal of the driving circuit, respectively, and is used to control the connection between the external compensation line and the second terminal of the driving circuit under the control of the second scan signal provided by the second scan line.

7. The pixel circuit as described in claim 6, characterized in that, The pixel circuit also includes a sixth energy storage circuit; The first terminal of the sixth energy storage circuit is electrically connected to the control terminal of the drive circuit, and the second terminal of the sixth energy storage circuit is electrically connected to the second terminal of the drive circuit. The sixth energy storage circuit is used to store electrical energy; or... The first terminal of the sixth energy storage circuit is electrically connected to the control terminal of the drive circuit, and the second terminal of the sixth energy storage circuit is electrically connected to the first terminal of the drive circuit. The sixth energy storage circuit is used to store electrical energy.

8. The pixel circuit as described in claim 6, characterized in that, The data writing circuit includes a seventeenth transistor, the compensation switching circuit includes an eighteenth transistor, and the driving circuit includes a driving transistor; The control electrode of the seventeenth transistor is electrically connected to the first scan line, the first electrode of the seventeenth transistor is electrically connected to the data line, and the second electrode of the seventeenth transistor is electrically connected to the gate of the driving transistor. The control electrode of the eighteenth transistor is electrically connected to the second scan line, the first electrode of the eighteenth transistor is electrically connected to the external compensation line, and the second electrode of the eighteenth transistor is electrically connected to the second electrode of the driving transistor. The first terminal of the driving transistor is electrically connected to the second voltage terminal; the second terminal of the driving transistor is electrically connected to the first terminal of the light-emitting element.

9. The pixel circuit as described in claim 8, characterized in that, The seventeenth transistor, the eighteenth transistor, and the driving transistor are all n-type transistors; or, the seventeenth transistor and the driving transistor are p-type transistors, and the eighteenth transistor is either an n-type transistor or a p-type transistor.

10. The pixel circuit as described in claim 7, characterized in that, The sixth energy storage circuit includes a storage capacitor; the driving circuit includes a driving transistor. The first terminal of the storage capacitor is electrically connected to the control electrode of the driving transistor, and the second terminal of the storage capacitor is electrically connected to the second electrode of the driving transistor. or, The first end of the storage capacitor is electrically connected to the control electrode of the driving transistor, and the second end of the storage capacitor is electrically connected to the first electrode of the driving transistor.

11. The pixel circuit according to any one of claims 1 to 5, characterized in that, It also includes a data writing circuit, a compensation switching circuit, and a sixth energy storage circuit; the first terminal of the driving circuit is electrically connected to the second voltage terminal; the driving circuit is used to generate a driving current under the control of the potential at its control terminal; The data writing circuit is electrically connected to the first scan line, the data line and the control terminal of the driving circuit, respectively, and is used to write the data voltage provided by the data line into the control terminal of the driving circuit under the control of the first scan signal provided by the first scan line. The compensation switching circuit is electrically connected to the second scan line, the external compensation line, and the control terminal of the driving circuit, respectively, and is used to control the connection between the external compensation line and the control terminal of the driving circuit under the control of the second scan signal provided by the second scan line; The first terminal of the sixth energy storage circuit is electrically connected to the control terminal of the drive circuit, and the second terminal of the sixth energy storage circuit is electrically connected to the first terminal of the drive circuit. The sixth energy storage circuit is used to store electrical energy.

12. The pixel circuit as described in claim 11, characterized in that, The data writing circuit includes a seventeenth transistor, the compensation switching circuit includes an eighteenth transistor, and the driving circuit includes a driving transistor; The control electrode of the seventeenth transistor is electrically connected to the first scan line, the first electrode of the seventeenth transistor is electrically connected to the data line, and the second electrode of the seventeenth transistor is electrically connected to the gate of the driving transistor. The control electrode of the eighteenth transistor is electrically connected to the second scan line, the first electrode of the eighteenth transistor is electrically connected to the external compensation line, and the second electrode of the eighteenth transistor is electrically connected to the control electrode of the driving transistor. The first terminal of the driving transistor is electrically connected to the second voltage terminal; the second terminal of the driving transistor is electrically connected to the first terminal of the light-emitting element.

13. The pixel circuit as described in claim 12, characterized in that, The seventeenth transistor, the eighteenth transistor, and the driving transistor are all p-type transistors.

14. A pixel circuit, characterized in that, Includes driving circuit, light-emitting element, and light-emitting gating control circuit; The driving circuit is electrically connected to the first electrode of the light-emitting element and is used to drive the light-emitting element; the light-emitting gating control circuit is electrically connected to the second electrode, the first control terminal, the first light-emitting control voltage terminal, and the light-emitting data voltage terminal of the light-emitting element, respectively, and is used to form a current path between the second electrode and the first voltage terminal of the light-emitting element according to the first light-emitting control voltage provided by the first control terminal and the light-emitting data voltage provided by the light-emitting data voltage terminal, under the control of the first control signal provided by the first control terminal, so as to control the driving circuit to control the light-emitting element to emit light; or, The driving circuit is electrically connected to the light-emitting element through the light-emitting gating circuit; the light-emitting gating control circuit is electrically connected to the driving circuit, the first control terminal, the first control voltage terminal and the light-emitting data voltage terminal respectively, and is used to form a current path between the driving circuit and the light-emitting element according to the first light-emitting control voltage and the light-emitting data voltage under the control of the first control signal, so as to control the driving circuit to control the light-emitting element to emit light. The light emission gating control circuit includes a sixth light emission control circuit, a seventh light emission control circuit, a fourth gating control circuit, a fifth gating control circuit, and a fifth energy storage circuit. The fourth gating control circuit is electrically connected to the first control terminal, the first light emission control voltage terminal, and the control terminal of the sixth light emission control circuit, respectively, and is used to control the connection between the first light emission control voltage terminal and the control terminal of the sixth light emission control circuit under the control of the first control signal. The fifth gating control circuit is electrically connected to the control terminal of the sixth light-emitting control circuit, the light-emitting data voltage terminal, and the control terminal of the seventh light-emitting control circuit, respectively, and is used to control the light-emitting data voltage terminal to be electrically connected to the control terminal of the seventh light-emitting control circuit under the control of the potential of the control terminal of the sixth light-emitting control circuit. The sixth light-emitting control circuit is electrically connected to the second electrode of the light-emitting element and the first voltage terminal, respectively, and is used to form the current path under the control of the potential of the control terminal of the sixth light-emitting control circuit; The seventh light-emitting control circuit is electrically connected to the second electrode of the light-emitting element and the first voltage terminal, respectively, and is used to form the current path under the control of the potential of the control terminal of the seventh light-emitting control circuit; The first terminal of the fifth energy storage circuit is electrically connected to the control terminal of the sixth light-emitting control circuit, and the second terminal of the fifth energy storage circuit is electrically connected to the initial voltage terminal. The fifth energy storage circuit is used to store electrical energy.

15. The pixel circuit as described in claim 14, characterized in that, The sixth light-emitting control circuit includes a thirteenth transistor; the seventh light-emitting control circuit includes a fourteenth transistor; the fourth gating control circuit includes a fifteenth transistor; and the fifth gating control circuit includes a sixteenth transistor. The control electrode of the fifteenth transistor is electrically connected to the first control terminal, the first electrode of the fifteenth transistor is electrically connected to the first light-emitting control voltage terminal, and the second electrode of the fifteenth transistor is electrically connected to the control electrode of the thirteenth transistor. The control electrode of the sixteenth transistor is electrically connected to the control electrode of the thirteenth transistor, the first electrode of the sixteenth transistor is electrically connected to the light-emitting data voltage terminal, and the second electrode of the sixteenth transistor is electrically connected to the control electrode of the fourteenth transistor. The first terminal of the thirteenth transistor is electrically connected to the second terminal of the light-emitting element, and the second terminal of the thirteenth transistor is electrically connected to the first voltage terminal; The first terminal of the fourteenth transistor is electrically connected to the second terminal of the light-emitting element, and the second terminal of the fourteenth transistor is electrically connected to the first voltage terminal.

16. The pixel circuit as described in claim 15, characterized in that, The thirteenth, fourteenth, and fifteenth transistors are all n-type transistors, and the sixteenth transistor is a p-type transistor; or, The thirteenth and fourteenth transistors are n-type transistors, and the fifteenth and sixteenth transistors are p-type transistors; or, The thirteenth transistor is an n-type transistor, and the fourteenth, fifteenth, and sixteenth transistors are all p-type transistors; or, The thirteenth, fourteenth, and fifteenth transistors are all n-type transistors, and the sixteenth transistor is a p-type transistor.

17. The pixel circuit according to any one of claims 14 to 16, characterized in that, It also includes a data writing circuit and a compensation switching circuit; the first terminal of the driving circuit is electrically connected to the second voltage terminal; the driving circuit is used to generate a driving current under the control of the potential at its control terminal; The data writing circuit is electrically connected to the first scan line, the data line and the control terminal of the driving circuit, respectively, and is used to write the data voltage provided by the data line into the control terminal of the driving circuit under the control of the first scan signal provided by the first scan line. The compensation switching circuit is electrically connected to the second scan line, the external compensation line, and the second terminal of the driving circuit, respectively, and is used to control the connection between the external compensation line and the second terminal of the driving circuit under the control of the second scan signal provided by the second scan line.

18. The pixel circuit as described in claim 17, characterized in that, The pixel circuit also includes a sixth energy storage circuit; The first terminal of the sixth energy storage circuit is electrically connected to the control terminal of the drive circuit, and the second terminal of the sixth energy storage circuit is electrically connected to the second terminal of the drive circuit. The sixth energy storage circuit is used to store electrical energy; or... The first terminal of the sixth energy storage circuit is electrically connected to the control terminal of the drive circuit, and the second terminal of the sixth energy storage circuit is electrically connected to the first terminal of the drive circuit. The sixth energy storage circuit is used to store electrical energy.

19. The pixel circuit as described in claim 17, characterized in that, The data writing circuit includes a seventeenth transistor, the compensation switching circuit includes an eighteenth transistor, and the driving circuit includes a driving transistor; The control electrode of the seventeenth transistor is electrically connected to the first scan line, the first electrode of the seventeenth transistor is electrically connected to the data line, and the second electrode of the seventeenth transistor is electrically connected to the gate of the driving transistor. The control electrode of the eighteenth transistor is electrically connected to the second scan line, the first electrode of the eighteenth transistor is electrically connected to the external compensation line, and the second electrode of the eighteenth transistor is electrically connected to the second electrode of the driving transistor. The first terminal of the driving transistor is electrically connected to the second voltage terminal; the second terminal of the driving transistor is electrically connected to the first terminal of the light-emitting element.

20. The pixel circuit as described in claim 19, characterized in that, The seventeenth transistor, the eighteenth transistor, and the driving transistor are all n-type transistors; or, the seventeenth transistor and the driving transistor are p-type transistors, and the eighteenth transistor is either an n-type transistor or a p-type transistor.

21. The pixel circuit as described in claim 18, characterized in that, The sixth energy storage circuit includes a storage capacitor; the driving circuit includes a driving transistor. The first terminal of the storage capacitor is electrically connected to the control electrode of the driving transistor, and the second terminal of the storage capacitor is electrically connected to the second electrode of the driving transistor. or, The first end of the storage capacitor is electrically connected to the control electrode of the driving transistor, and the second end of the storage capacitor is electrically connected to the first electrode of the driving transistor.

22. The pixel circuit according to any one of claims 14 to 16, characterized in that, It also includes a data writing circuit, a compensation switching circuit, and a sixth energy storage circuit; the first terminal of the driving circuit is electrically connected to the second voltage terminal; the driving circuit is used to generate a driving current under the control of the potential at its control terminal; The data writing circuit is electrically connected to the first scan line, the data line and the control terminal of the driving circuit, respectively, and is used to write the data voltage provided by the data line into the control terminal of the driving circuit under the control of the first scan signal provided by the first scan line. The compensation switching circuit is electrically connected to the second scan line, the external compensation line, and the control terminal of the driving circuit, respectively, and is used to control the connection between the external compensation line and the control terminal of the driving circuit under the control of the second scan signal provided by the second scan line; The first terminal of the sixth energy storage circuit is electrically connected to the control terminal of the drive circuit, and the second terminal of the sixth energy storage circuit is electrically connected to the first terminal of the drive circuit. The sixth energy storage circuit is used to store electrical energy.

23. The pixel circuit as described in claim 22, characterized in that, The data writing circuit includes a seventeenth transistor, the compensation switching circuit includes an eighteenth transistor, and the driving circuit includes a driving transistor; The control electrode of the seventeenth transistor is electrically connected to the first scan line, the first electrode of the seventeenth transistor is electrically connected to the data line, and the second electrode of the seventeenth transistor is electrically connected to the gate of the driving transistor. The control electrode of the eighteenth transistor is electrically connected to the second scan line, the first electrode of the eighteenth transistor is electrically connected to the external compensation line, and the second electrode of the eighteenth transistor is electrically connected to the control electrode of the driving transistor. The first terminal of the driving transistor is electrically connected to the second voltage terminal; the second terminal of the driving transistor is electrically connected to the first terminal of the light-emitting element.

24. The pixel circuit as described in claim 23, characterized in that, The seventeenth transistor, the eighteenth transistor, and the driving transistor are all p-type transistors.

25. A pixel driving method, applied to a pixel circuit as described in any one of claims 1 to 13, characterized in that, The pixel driving method includes: Under the control of the first control signal, the light-emitting gating control circuit forms a current path between the second electrode of the light-emitting element and the first voltage terminal according to the first light-emitting control voltage and the light-emitting data voltage, so as to control the driving circuit to control the light-emitting element to emit light; or... Under the control of the first control signal, the light emission gating control circuit forms a current path between the driving circuit and the light emission element according to the first light emission control voltage and the light emission data voltage, so as to control the driving circuit to control the light emission element to emit light; the light emission gating control circuit is also electrically connected to the light emission control signal terminal; the light emission gating control circuit includes a third light emission control circuit, a write control circuit and a first control circuit; The pixel driving method includes: Under the control of the first control signal, the write control circuit controls the connection between the first light emission control voltage terminal and the write node; The first control circuit, under the control of the potential of the writing node, controls the writing of the light-emitting data voltage or light-emitting control signal to the control terminal of the third light-emitting control circuit. The third light-emitting control circuit forms the current path under the control of the potential at its control terminal.

26. A pixel driving method, applied to a pixel circuit as described in any one of claims 14 to 24, characterized in that, The pixel driving method includes: Under the control of the first control signal, the light-emitting gating control circuit forms a current path between the second electrode of the light-emitting element and the first voltage terminal according to the first light-emitting control voltage and the light-emitting data voltage, so as to control the driving circuit to control the light-emitting element to emit light; or... Under the control of the first control signal, the light emission gating control circuit forms a current path between the driving circuit and the light-emitting element based on the first light emission control voltage and the light emission data voltage, so as to control the driving circuit to control the light-emitting element to emit light; the light emission gating control circuit includes a sixth light emission control circuit, a seventh light emission control circuit, a fourth gating control circuit, and a fifth gating control circuit; the pixel driving method includes: Under the control of the first control signal, the fourth gating control circuit controls the connection between the first light emission control voltage terminal and the control terminal of the sixth light emission control circuit. The fifth gating control circuit, under the control of the potential of the control terminal of the sixth light-emitting control circuit, controls the light-emitting data voltage terminal to be electrically connected to the control terminal of the seventh light-emitting control circuit. The sixth light-emitting control circuit forms the current path under the control of the potential at its control terminal; The seventh light-emitting control circuit forms the current path under the control of the potential at its control terminal.

27. A display device, characterized in that, Includes the pixel circuit as described in any one of claims 1 to 24.

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