Signal quantization methods and image processing devices

Abstract

This application provides a signal quantization method and an image processing apparatus. The method is applied to an image processing apparatus including a comparator, a counter, a first latch, and a second latch. The method includes: the comparator performing pairwise comparisons (one ramp signal matches one signal) between two input ramp signals and two signals under a first conversion gain, obtaining two comparison results respectively; the counter counting these two comparison results to obtain a final count result for the first conversion gain; and the first latch storing the final count result for the first conversion gain; the comparator performing pairwise comparisons between the two input ramp signals and two signals under a second conversion gain, obtaining two comparison results respectively; the counter counting these two comparison results to obtain a final count result for the second conversion gain; and the second latch storing the final count result under the second conversion gain. This satisfies the requirements of low power consumption and small chip footprint.

Description

Technical Field

[0001] This application relates to the field of image sensor technology, and more specifically, to a signal quantization method and an image processing apparatus. Background Technology

[0002] Dynamic range (DR) is one of the key performance parameters of complementary metal-oxide-semiconductor image sensors (CIS), which determines the image quality in scenarios such as daytime outdoor backlighting and night scenes.

[0003] At the pixel level, existing methods for extending DR mainly include: dual conversion gain (DCG), lateral overflow integration capacitor (LOFIC), and multi-conversion gain (MCG). Among them, DCG and LOFIC can read two sets of reset and signal levels with different conversion gains, while MCG can read multiple sets of reset and signal levels with different conversion gains.

[0004] Among them, the aforementioned DCG / LOFIC / MCG technologies use multiple (at least two) analog-to-digital converter (ADC) modules to quantize the reset level and signal level under different conversion gains, which will increase the chip area and power consumption of the readout circuit. Summary of the Invention

[0005] This application provides a signal quantization method and an image processing device that can meet the requirements of small chip footprint and low power consumption.

[0006] A first aspect provides an image processing apparatus, comprising: a comparator, a counter, and at least two latches, the at least two latches including a first latch and a second latch; the comparator is used to compare a second ramp signal output by a ramp generator with a second signal output by a pixel unit to obtain a second comparison result; the counter is used to convert the second comparison result based on a first inverted counting result to obtain a second counting result, wherein the first inverted counting result is obtained by inverting the first counting result by the counter, the first counting result is obtained by converting the first comparison result by the counter, and the first comparison result is obtained by comparing the first ramp signal output by the ramp generator with the first signal output by the pixel unit by the comparator; the first latch... The system includes a register for storing the second counting result; a comparator for comparing the fourth ramp signal output by the ramp generator with the fourth signal output by the pixel unit to obtain a fourth comparison result; a counter for converting the fourth comparison result based on the second inverted counting result to obtain a fourth counting result, wherein the second inverted counting result is obtained by inverting the third counting result obtained by converting the third comparison result by the counter; and the third comparison result is obtained by comparing the third ramp signal output by the ramp generator with the third signal output by the pixel unit by the comparator; and a second latch for storing the fourth counting result; wherein the first and second signals belong to the first conversion gain, and the third and fourth signals belong to the second conversion gain.

[0007] Specifically, the first latch is used to store the second count result under the first conversion gain, and the second latch is used to store the fourth count result under the second conversion gain.

[0008] By employing an architecture consisting of a comparator, a counter, and at least two latches, this application enables an image processing device to perform double sampling processing of four signals at two conversion gains in a low-power and small-chip-area manner.

[0009] Specifically, this application supports an image processing device to complete double sampling processing of signals with different conversion gains simply by increasing the number of latches. This can reduce the power consumption and chip area occupied by the image processing device when performing signal double sampling processing.

[0010] In addition, by employing an architecture consisting of a comparator, a counter, and at least two latches, this application supports a simplified circuit structure for the readout circuit in an image processing device, thereby reducing power consumption and saving chip footprint.

[0011] In one possible implementation, the output order of the first signal is before the output order of the third signal, the output order of the third signal is after the output order of the fourth signal, and the output order of the fourth signal is before the output order of the second signal. The counter is also used to output the first inverted count result to the first latch; the latch is also used to store the first inverted count result; when the comparator is used to compare the second ramp signal with the second signal, the counter is also used to obtain the first inverted count result from the first latch.

[0012] Specifically, there is information exchange between the counter and the latch. When the output order of two signals under the same conversion gain among the multiple different conversion gains that the image processing device needs to process is not continuous, the counter can obtain the inverted count result from the latch corresponding to the conversion gain, thereby supporting the completion of double sampling processing of the signal under the conversion gain.

[0013] In one possible implementation, the output order of the third signal is before the output order of the first signal, the output order of the first signal is after the output order of the second signal, and the output order of the second signal is before the output order of the fourth signal. The counter is also used to output the second inverted count result to the second latch; the latch is also used to store the second inverted count result; when the comparator is used to compare the fourth ramp signal with the fourth signal, the counter is also used to obtain the second inverted count result from the second latch.

[0014] Specifically, there is information exchange between the counter and the latch. When the output order of two signals under the same conversion gain among the multiple different conversion gains that the image processing device needs to process is not continuous, the counter can obtain the inverted count result from the latch corresponding to the conversion gain, thereby supporting the completion of double sampling processing of the signal under the conversion gain.

[0015] One possible implementation is that the output order of the first signal is before the output order of the second signal, the output order of the second signal is after the output order of the third signal, and the output order of the third signal is before the output order of the fourth signal; or, the output order of the third signal is before the output order of the fourth signal, the output order of the fourth signal is after the output order of the first signal, and the output order of the first signal is before the output order of the second signal.

[0016] In one possible implementation, the image processing device also includes a ramp generator.

[0017] Specifically, the aforementioned ramp generator can be used to output ramp signals.

[0018] In one possible implementation, the image processing apparatus further includes a pixel array comprising at least one pixel unit.

[0019] In one possible implementation, the image processing apparatus further includes an image processing circuit for processing the second counting result and the fourth counting result.

[0020] One possible implementation is that the first signal includes a reset signal and the second signal includes a working signal; or, the first signal includes a working signal and the second signal includes a reset signal.

[0021] One possible implementation is that the third signal includes a reset signal and the fourth signal includes a working signal; or, the third signal includes a working signal and the fourth signal includes a reset signal.

[0022] Secondly, a signal quantization method is provided, applied to an image processing device. The image processing device includes a comparator, a counter, and at least two latches, the at least two latches including a first latch and a second latch. The method includes: the comparator comparing a second ramp signal output from a ramp generator with a second signal output from a pixel unit to obtain a second comparison result; the counter converting the second comparison result based on a first inverted counting result to obtain a second counting result, wherein the first inverted counting result is obtained by inverting the first counting result by the counter, the first counting result is obtained by converting the first comparison result by the counter, and the first comparison result is obtained by comparing the first ramp signal output from the ramp generator with the first signal output from the pixel unit by the comparator; the first latch... The counter stores the second counting result output by the counter; and the comparator compares the fourth ramp signal output by the ramp generator with the fourth signal output by the pixel unit to obtain a fourth comparison result; the counter converts the fourth comparison result based on the second inverted counting result to obtain a fourth counting result, the second inverted counting result is obtained by inverting the third counting result by the counter, the third counting result is obtained by converting the third comparison result by the counter, and the third comparison result is obtained by comparing the third ramp signal output by the ramp generator with the third signal output by the pixel unit by the comparator; the second latch stores the fourth counting result output by the counter; wherein, the first signal and the second signal belong to the first conversion gain, and the third signal and the fourth signal belong to the second conversion gain.

[0023] In one possible implementation, the output order of the first signal is before the output order of the third signal, the output order of the third signal is after the output order of the fourth signal, and the output order of the fourth signal is before the output order of the second signal. The counter outputs the first inverted count result to the first latch; the first latch stores the first inverted count result; when the comparator is used to compare the second ramp signal with the second signal, the counter obtains the first inverted count result from the first latch.

[0024] In one possible implementation, the output order of the third signal is before the output order of the first signal, the output order of the first signal is after the output order of the second signal, and the output order of the second signal is before the output order of the fourth signal. The counter outputs the second inverted count result to the second latch; the second latch stores the second inverted count result; when the comparator compares the fourth ramp signal with the fourth signal, the counter obtains the second inverted count result from the second latch.

[0025] One possible implementation is that the output order of the first signal is before the output order of the second signal, the output order of the second signal is after the output order of the third signal, and the output order of the third signal is before the output order of the fourth signal; or, the output order of the third signal is before the output order of the fourth signal, the output order of the fourth signal is after the output order of the first signal, and the output order of the first signal is before the output order of the second signal.

[0026] In one possible implementation, the image processing apparatus further includes a ramp generator, and the method further includes: the ramp generator outputting a first ramp signal; or, the ramp generator outputting a second ramp signal; or, the ramp generator outputting a third ramp signal; or, the ramp generator outputting a fourth ramp signal.

[0027] In one possible implementation, the image processing apparatus further includes a pixel array, the pixel array including at least one pixel unit, and the method further includes: the pixel unit outputting a first signal; or, the pixel unit outputting a second signal; or, the pixel unit outputting a third signal; or, the pixel unit outputting a fourth signal.

[0028] In one possible implementation, the image processing apparatus further includes an image processing circuit, the method further including: the image processing circuit processing the second counting result and the fourth counting result.

[0029] One possible implementation is that the first signal includes a reset signal and the second signal includes a working signal; or, the first signal includes a working signal and the second signal includes a reset signal.

[0030] One possible implementation is that the third signal includes a reset signal and the fourth signal includes a working signal; or, the third signal includes a working signal and the fourth signal includes a reset signal.

[0031] Thirdly, a chip system is provided, characterized in that it includes: logic circuitry for coupling with an input / output interface to transmit data through the input / output interface to perform the method described in any one of the second aspect and any possible implementation thereof.

[0032] Fourthly, a computer-readable storage medium is provided, comprising a computer program or instructions that, when executed on a computer, cause the computer to perform the method of the second aspect and any possible implementation thereof.

[0033] Fifthly, a computer program product is provided, comprising instructions that, when executed on a computer, cause the computer to perform the method of the second aspect and any possible implementation thereof.

[0034] The descriptions of the beneficial effects of aspects two through five can be found in the description of the beneficial effects of aspect one, and will not be repeated here. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the imaging system 100.

[0036] Figure 2 This is a schematic diagram of ADC unit 200.

[0037] Figure 3 This is a schematic diagram of the ADC unit 300 according to an embodiment of this application.

[0038] Figure 4 This is a schematic diagram of the interaction process of the signal quantization method 400 according to an embodiment of this application.

[0039] Figure 5 This is a schematic diagram of the structure of the counting unit 500 of the counter in an embodiment of this application.

[0040] Figure 6 This is a schematic diagram of the structure of the counting unit 600 of the counter in an embodiment of this application.

[0041] Figure 7 This is a schematic diagram of the structure of the pixel unit 700 in an embodiment of this application.

[0042] Figure 8 This is an interactive schematic diagram of the signal quantization method 800 according to an embodiment of this application.

[0043] Figure 9 This is a schematic diagram of the structure of the pixel unit 900 in an embodiment of this application.

[0044] Figure 10 This is an interactive schematic diagram of the signal quantization method 1000 according to an embodiment of this application. Detailed Implementation

[0045] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0046] Specifically, a CIS (CMOS Image Sensor) is an optical sensor widely used in the field of vision that converts light signals into electrical signals and then converts those electrical signals into digital signals through a readout circuit. The following description uses the application of CIS in a camera as an example.

[0047] For example, a camera lens focuses light onto a CIS (CMOS Image Sensor). The CIS, through its photosensitive unit array, converts the light signal carrying information such as the brightness and color of the subject into an electrical signal. This electrical signal is then converted into a digital signal by a readout circuit, and finally, the digital signal is pre-processed and output. As a photosensitive element performing photoelectric conversion, the CIS plays a crucial role in image quality. Specifically, the DR (Dynamic Dynamic Range) of the CIS has a more significant impact on image quality. Therefore, the pursuit of high dynamic range (HDR) CIS has become a core requirement in the industry.

[0048] At the pixel level, existing extended DR technologies mainly include DCG, LOFIC, and MCG. Among them, DCG and LOFIC can read two sets of reset level and signal level under different conversion gains, while MCG can read multiple sets of reset level and signal level under different conversion gains.

[0049] However, the aforementioned DCG / LOFIC / MCG technologies suffer from technical problems such as excessively large chip area occupied by the readout circuit and high power consumption. The following section combines... Figure 1 and Figure 2 This will be described in further detail.

[0050] Figure 1 This is a schematic diagram of the imaging system 100. The aforementioned CIS includes the imaging system 100. (As...) Figure 1 As shown, the imaging system 100 includes a pixel array 101, a readout circuit 102, an image processing circuit 103, and other circuits 104. The pixel array 101 is used to convert optical signals into electrical signals; the readout circuit 102 is used to quantize the pixel signals output from the pixel array 101; the image processing circuit 103 is used to perform image processing on the output signal of the readout circuit 102; and the other circuits 104 are used to further process the output signal of the image processing circuit 103, thereby completing the basic imaging process.

[0051] exist Figure 1In this array, pixel array 101 includes multiple rows of horizontally arranged pixel units or multiple columns of vertically arranged pixel units. For example, pixel array 101 includes horizontally arranged pixel units 11-14, 21-24, 31-34, and 41-44; or, pixel array 101 includes vertically arranged pixel units 11-41, 12-42, 13-43, and 14-44. The circuit structure of the pixel units in pixel array 101 will be described below and will not be repeated here.

[0052] exist Figure 1 In the image, the readout circuit 102 includes multiple ADC units, wherein the number of ADC units in the readout circuit 102 is consistent with the number of pixel unit columns in the pixel array 101. For example, if the pixel array 101 includes 4 columns of pixel units, the readout circuit 102 includes 4 ADC units, namely ADC unit 1, ADC unit 2, ADC unit 3, and ADC unit 4. ADC unit 1 corresponds to the first column of pixel units in the pixel array 101 (all pixel units in the first column share ADC1), ADC unit 2 corresponds to the second column of pixel units (all pixel units in the second column share ADC2), ADC unit 3 corresponds to the third column of pixel units (all pixel units in the third column share ADC unit 3), and ADC unit 4 corresponds to the fourth column of pixel units (all pixel units in the fourth column share ADC unit 4). The following section will further elaborate on this. Figure 2 The ADC unit will be described in more detail.

[0053] Figure 2 This is a schematic diagram of the ADC unit 200. (See attached diagram.) Figure 2 As shown, the ADC unit 200 includes a ramp generator, N comparators, N counters, and N latches (N≥2). The ramp generator generates a ramp signal. The comparators receive the pixel signals output from the pixel units and compare them with the ramp signal to obtain the comparison result. The counters convert the comparison result (or quantization result) of the comparators into a digital signal. The latches store the counting result of the counters.

[0054] It should be understood that any technical solution that converts photoelectric signals on a sensor array plane will face the problem of fixed pattern noise (FPN) caused by the uneven manufacturing of the sensor array plane. Due to the influence of FPN, the sensor array plane will output a fixed pattern signal even when there is no light signal illumination. When there is optical image illumination, this fixed pattern signal will be superimposed on the real image signal.

[0055] To reduce the impact of FPN, a correlated double sampling (CDS) circuit is currently used for signal double sampling processing. Specifically, the CDS circuit does not directly measure the output voltage of each pixel unit, but instead measures the output voltage twice after each pixel unit's exposure: first, the reset voltage; second, the working signal voltage. The CDS circuit ultimately outputs the voltage difference between these two sampling measurements. Therefore, the ADC unit 200 also performs the aforementioned double sampling processing. The details of the CDS processing performed by the ADC unit 200 are not elaborated in this application.

[0056] Figure 2 In this example, taking N=2, the multi-group dual-sampling signal processing is divided into two groups of dual-sampling signal processing. Each group of dual-sampling signals includes a reset voltage and a working signal voltage (hereinafter referred to as "signal voltage"). The ADC unit 200 includes a ramp generator, two comparators, two counters, and two latches.

[0057] During the pixel signal readout stage, the ADC unit 200 reads the reset level and signal level (or working signal level) under high conversion gain (HCG) and low conversion gain (LCG) respectively. Since the LCG reset level and signal level are not read out continuously, two ADC modules (each including a comparator, a counter, and a latch) are needed to quantize the HCG and LCG reset and signal levels respectively to achieve double sampling. Pixel signals under different conversion gains can be connected to comparator 1 and comparator 2 via switches S1 and S2 respectively, and the counter's count result is latched into latch 1 and latch 2 respectively, achieving double sampling of the reset level and signal level under the same conversion gain (the effective level value of the pixel signal is obtained by subtracting the two level values). Similarly, for multiple sets of double-sampled signals, multiple ADC modules are needed to quantize the reset level and signal level under different conversion gains.

[0058] As described above, the quantization processing of multiple sets of dual-sampled signals (N≥2) requires multiple ADC modules, which makes the circuit structure of the readout circuit more complex, occupies a larger chip area and consumes more power, thus failing to meet the requirements of low power consumption and small chip area.

[0059] In view of the above-mentioned technical problems, this application provides a signal quantization method and an image processing device that enable the readout circuit to meet the requirements of small chip footprint and low power consumption.

[0060] The signal quantization method of this application embodiment will be described below with reference to the accompanying drawings.

[0061] Figure 3 This is a schematic diagram of the ADC unit 300 according to an embodiment of this application. Figure 3 As shown, the ADC unit 300 includes a ramp generator, a comparator, a counter, and N latches (N≥2). Descriptions of the ramp generator, comparator, counter, and latches can be found above and will not be repeated here. Furthermore, the number of latches corresponds to the number of conversion gains. For example, for DCG (including HCG and LCG), the number of latches is 2; for MCG (including N conversion gains), the number of latches is N.

[0062] contrast Figure 2 and Figure 3 It can be seen that, compared with the circuit design scheme of multiple comparators and multiple counters used in ADC unit 200, ADC unit 300 can save chip area and reduce power consumption by using one counter and one comparator.

[0063] One possible implementation is that this application supports information exchange between the counter and the latch (described further below). Additionally, the counter in the ADC unit 300 has a bit-inverting function.

[0064] Figure 4 This is a schematic diagram of the interaction flow of the signal quantization method 400 according to an embodiment of this application. The method 400 is applied to an image processing apparatus, which includes a comparator, a counter, and at least two latches, including a first latch and a second latch. Alternatively, the image processing apparatus may include some or all of the components of an ADC unit.

[0065] like Figure 4 As shown, method 400 includes:

[0066] S401, The comparator compares the second ramp signal output by the ramp generator with the second signal output by the pixel unit to obtain a second comparison result.

[0067] Specifically, the second ramp signal generated by the ramp generator is input to the comparator, and the second signal generated by the pixel unit is also input to the comparator. The comparator then compares the two signals. The specific comparison process will be described below and will not be repeated here.

[0068] One possible implementation is that the second signal includes a reset signal, or it may include a working signal; this application does not specifically limit this.

[0069] S402. Based on the first inverted count result, the counter converts the second comparison result to obtain the second count result.

[0070] Specifically, the first inverted count result is obtained by inverting the first count result using the counter. The first count result is obtained by converting the first comparison result using the counter, and the first comparison result is obtained by comparing the first ramp signal output by the ramp generator with the first signal output by the pixel unit using the comparator.

[0071] One possible implementation is that the output order of the first signal precedes the output order of the second signal. A counter inverts the first count result obtained by converting the first comparison result (obtained by comparing the first signal with the first ramp signal) to obtain a first inverted result. When the counter needs to count the comparison result between the second signal and the second ramp signal, it counts based on the first inverted count result. In this way, double sampling processing of pixel signals under the same conversion gain can be completed, resulting in an effective pixel signal (pixel signal after deducting the FPN effect).

[0072] In one example, the first ramp signal and the second ramp signal may be the same or different, and this application does not limit this.

[0073] In one example, the output order of the first signal preceding the output order of the second signal may include: there are no other signals between the first and second signals, or there are other signals between the first and second signals, such as a third and / or a fourth signal.

[0074] One possible implementation is that the first signal and the second signal belong to a first conversion gain. For example, the first conversion gain is LCG, the first signal is a reset signal, and the second signal is an operating signal; or, the first conversion gain is LCG, the first signal is an operating signal, and the second signal is a reset signal. For example, the first conversion gain is HCG, the first signal is a reset signal, and the second signal is an operating signal; or, the first conversion gain is LCG, the first signal is an operating signal, and the second signal is a reset signal. This will be further described below.

[0075] S403, The first latch stores the second counting result output by the counter.

[0076] Specifically, after the counter completes the conversion of the second comparison result, it obtains the second count result. The counter outputs the second count result to the first latch. The first latch stores the second count result.

[0077] S404. The comparator compares the fourth ramp signal output by the ramp generator with the fourth signal output by the pixel unit to obtain the fourth comparison result.

[0078] Specifically, the fourth ramp signal generated by the ramp generator is input to the comparator, and the fourth signal generated by the pixel unit is also input to the comparator. The comparator then compares the two signals. The specific comparison process will be described below and will not be repeated here.

[0079] One possible implementation is that the fourth signal may include a reset signal or a working signal; this application does not specifically limit this.

[0080] S405. Based on the second inverted count result, the counter converts the fourth comparison result to obtain the fourth count result.

[0081] Specifically, the second inverted count result is obtained by inverting the third count result using the counter. The third count result is obtained by converting the third comparison result using the counter, and the third comparison result is obtained by comparing the third ramp signal output by the ramp generator with the third signal output by the pixel unit using the comparator.

[0082] One possible implementation is that the output order of the third signal precedes the output order of the fourth signal. The counter inverts the third comparison result obtained by the comparator comparing the third signal with the third ramp signal, resulting in a second inverted result. When the counter needs to count the comparison result between the fourth signal and the fourth ramp signal, it counts based on the second inverted count result. In this way, double sampling processing of pixel signals under the same conversion gain can be completed, thus obtaining the effective pixel signal.

[0083] In one example, the third ramp signal and the fourth ramp signal may be the same or different, and this application does not limit this.

[0084] In one example, the output order of the third signal precedes the output order of the fourth signal, which may include: there are no other signals between the third and fourth signals, or there are other signals between the third and fourth signals, such as the first signal and / or the second signal.

[0085] One possible implementation is that the third and fourth signals belong to the second conversion gain. For example, the second conversion gain is LCG, the third signal is a reset signal, and the fourth signal is an operating signal; or, the second conversion gain is LCG, the third signal is an operating signal, and the fourth signal is a reset signal. For example, the second conversion gain is HCG, the third signal is a reset signal, and the fourth signal is an operating signal; or, the second conversion gain is LCG, the third signal is an operating signal, and the fourth signal is a reset signal. This will be further described below.

[0086] S406, the second latch stores the fourth count result output by the counter.

[0087] Specifically, after the counter completes the conversion of the fourth comparison result, it obtains the fourth count result. The counter outputs the fourth count result to the second latch, which stores the fourth count result.

[0088] Specifically, the first latch is used to store the second count result under the first conversion gain, and the second latch is used to store the fourth count result under the second conversion gain.

[0089] By employing an architecture consisting of a comparator, a counter, and at least two latches, this application enables an image processing device to perform double sampling processing of four signals at two conversion gains in a low-power and small-chip-area manner.

[0090] Specifically, this application supports image processing devices to complete double sampling processing of signals under different conversion gains by simply increasing the number of latches, which can reduce the power consumption and chip area occupied by the image processing device when performing signal double sampling processing.

[0091] In addition, by employing an architecture consisting of a comparator, a counter, and at least two latches, this application supports a simplified circuit structure for the readout circuit in an image processing device, thereby reducing power consumption and saving chip footprint.

[0092] It should be understood that this application does not limit the order of S401 to S406. For example, S405 can come before S401, etc.

[0093] One possible implementation, method 400 also includes:

[0094] Between the first signal and the second signal, there is at least one of the third signal and the fourth signal. The counter outputs the first inverted count result to the first latch.

[0095] For example, when the first signal and the second signal include the third signal and the fourth signal, that is, the output order of the four signals is: the first signal before the third signal, the third signal before the fourth signal, the fourth signal before the second signal, the first signal and the second signal belong to the first conversion gain, and the third signal and the fourth signal belong to the second conversion gain.

[0096] Specifically, the counter first counts the first signal to obtain a first count result, then inverts this first count result to obtain a first inverted count result, which is output to the first latch. Next, the counter counts the third signal to obtain a third count result, which is then inverted to obtain a second inverted count result. Then, based on the second inverted count result, the counter counts the fourth signal to obtain a fourth count result, which is stored in the second latch. Finally, the counter retrieves the first inverted count result from the first latch, counts the second signal based on this result to obtain a second count result, which is also stored in the first latch.

[0097] Specifically, there is information exchange between the counter and the latch. When the output order of two signals under the same conversion gain among the multiple different conversion gains that the image processing device needs to process is not continuous, the counter can obtain the inverted count result from the latch corresponding to the conversion gain, thereby supporting the completion of double sampling processing of the signal under the conversion gain.

[0098] In summary, this application supports the dual sampling processing of the reset signal and the working signal under the first conversion gain and the dual sampling processing of the reset signal and the working signal under the second conversion gain. It uses a comparator, a counter and at least two latches, which simplifies the circuit structure of the readout circuit, thereby reducing the power consumption of the readout circuit and saving chip area.

[0099] One possible implementation, method 400 also includes:

[0100] The third signal and the fourth signal include at least one of the first signal and the second signal. The counter outputs the second inverted count result to the second latch.

[0101] For example, when the third signal and the fourth signal include the first signal and the second signal, that is, the output order of the four signals is: the third signal precedes the first signal, the first signal precedes the second signal, the second signal precedes the fourth signal, the first signal and the second signal belong to the first conversion gain, and the third signal and the fourth signal belong to the second conversion gain.

[0102] Specifically, the counter first counts the third signal to obtain a third count result, then inverts this third count result to obtain a third inverted count result, which is output to the second latch. Next, the counter counts the first signal to obtain a first count result, which is then inverted to obtain a first inverted count result. Then, based on the first inverted count result, the counter counts the second signal to obtain a second count result, which is stored in the first latch. Finally, the counter retrieves the second inverted count result from the second latch, and based on this second inverted count result, counts the fourth signal to obtain a fourth count result, which is then stored in the second latch.

[0103] Specifically, there is information exchange between the counter and the latch. When the output order of two signals under the same conversion gain among the multiple different conversion gains that the image processing device needs to process is not continuous, the counter can obtain the inverted count result from the latch corresponding to the conversion gain, thereby supporting the completion of double sampling processing of the signal under the conversion gain.

[0104] In summary, this application supports the dual sampling processing of the reset signal and the working signal under the first conversion gain and the dual sampling processing of the reset signal and the working signal under the second conversion gain. It uses a comparator, a counter and at least two latches, which simplifies the circuit structure of the readout circuit, thereby reducing the power consumption of the readout circuit and saving chip area.

[0105] In one possible implementation, the image processing apparatus includes a ramp generator; alternatively, method 400 may further include:

[0106] S401a, The ramp generator outputs at least one of the following ramp signals: a first ramp signal, a second ramp signal, a third ramp signal, and a fourth ramp signal.

[0107] It should be understood that the ramp signal output by the ramp generator is used to compare with the signal output by the pixel unit, thereby enabling the quantization processing of the pixel signal output by the pixel unit.

[0108] In one possible implementation, the image processing apparatus includes a pixel array, the pixel array comprising at least one pixel unit; alternatively, method 400 may further include:

[0109] S401b, the pixel unit outputs at least one of the first signal, the second signal, the third signal, and the fourth signal.

[0110] Specifically, each signal output by the pixel unit can be either a reset signal or a working signal. The comparator and counter mentioned above need to perform double sampling on the reset signal and the working signal in order to obtain the effective level of the pixel signal output by the pixel unit.

[0111] This application does not specify the order of S401a, S401b and S401.

[0112] In one possible implementation, the image processing apparatus includes image processing circuitry, and method 400 further includes:

[0113] S407, the image processing circuit processes the second and fourth counting results. This completes the main imaging process.

[0114] Specifically, the image processing device described above may further include an image processing circuit, which is used to perform further processing on the second and fourth counting results, thereby completing the basic imaging process.

[0115] In summary, the image processing device completes the double sampling processing of reset level and signal level under multiple different conversion gains through an architecture of a comparator, a counter, and multiple latches. This application can reduce the power consumption of the readout circuit and the chip area occupied in the image processing circuit.

[0116] The following will combine Figures 5-10 right Figure 4 The signal quantization method shown will be described in further detail.

[0117] Figure 5 This is a schematic diagram of the structure of the counting unit 500 of the counter according to an embodiment of this application. Figure 5 As shown, the counting unit 500 includes a first circuit. The input terminal of the first circuit is connected to the output terminal of the previous counting unit (for acquiring the count value output by the previous counting unit), and the output terminal of the first circuit is connected to the input terminal of the next counting unit (for outputting the count value of the counting unit 500). The first circuit can receive a first control signal, which controls the bit-by-bit inversion function of the first circuit.

[0118] Optionally, the counting unit 500 further includes a second circuit. The input terminal of the second circuit is connected to the output terminal of the first circuit, and the output terminal of the second circuit is connected to the input terminal of the next counting unit. The second circuit is used to retrieve the inverted counting result from the latch input. Additionally, the second circuit can receive a second control signal to control its function of retrieving the inverted counting result from the latch input.

[0119] Figure 6This is a schematic diagram of the structure of the counting unit 600 of the counter according to an embodiment of this application. Figure 6 As shown, the counting unit 600 includes a bit-wise inversion (BWI) circuit and a D flip-flop circuit (this is an optional structure). The input of the BWI circuit is connected to the output of the previous counting unit (to obtain the count value output by the previous counting unit). The output of the BWI circuit is connected to the clock input of the D flip-flop circuit. The inverted output of the D flip-flop circuit is connected to its input. The signal output after the inverted output of the D flip-flop circuit is connected to its input serves as the count value of this counting unit. The BWI circuit can also receive a BWI signal, which controls the BWI circuit to reset to zero, reset to one, or output the inverted value of the count value output by the previous counting unit. Additionally, the D flip-flop circuit can receive a set signal, which is used to obtain the inverted count result latched by the latch.

[0120] It should be understood that the BWI circuit described above can be the first circuit, and the D flip-flop circuit can be the second circuit. This application does not limit other possible implementations of the first and second circuits.

[0121] In one example, the number of counting units in the counter corresponds to the number of bits the counter can quantize. For instance, if the counter can quantize a 10-bit signal, it has 10 counting units. Each counting unit is sequentially connected to the others.

[0122] In one example, a counter can count under the drive of a counting clock to record comparison results, thereby enabling the conversion from the analog domain to the digital domain.

[0123] Figure 7 This is a schematic diagram of the structure of a pixel unit 700 according to an embodiment of this application. The pixel unit 700 employs DCG technology. Figure 7 As shown, pixel unit 700 includes: photodiode (PD) #711, transmission gate (TG) transistor #712, first floating diffusion (FD) #713, source follower (SF) #714, select (SEL) transistor #715, DCG transistor #716, reset (RST) transistor #717, and second FD #718.

[0124] Specifically, PD#711 is used to perform photoelectric conversion; TG transistor#712 controls the transfer of electrons from PD#711 to the first FD#713 and the second FD#718; the first FD#713 and the second FD#718 are used to store the electrons generated by photoelectric conversion; SF#714 is used to control the transfer of electrons from the FD to the signal line; SEL transistor#715 is used to control the signal output switch, which controls the output sequence of the signals (including the output sequence between the first and fourth signals); DCG transistor#716 is used to switch between the two conversion gains; and RST transistor#717 is used to reset the voltage signal in the circuit.

[0125] Pixel unit 700 comprises five working stages. Specifically:

[0126] 1) First working stage: PD#711 receives light and performs photoelectric conversion. During this stage, TG / RES / SEL are all in the off state.

[0127] 2) Second operating stage: SEL transistor #715 and RST transistor #717 are in the on state and the transistors are reset. The transistors are reset to allow the electrons remaining in PD #711 from the previous signal transmission to be conducted out, so as to avoid interference with the current signal transmission. At the same time, PD #711 is still receiving light and generating photoelectrons.

[0128] 3) Third working stage: RST transistor #717 is turned off, and the reset is complete.

[0129] 4) Fourth working stage: TG transistor #712 turns on, transferring electrons from PD #711 to the first FD #713.

[0130] 5) Fifth operating stage: TG transistor #712 is turned off to prevent subsequent photoelectric conversion of the first PD #711 from affecting the first FD #711. At the same time, the first FD #711 generates a voltage due to electrons, which controls the SF transistor #714, thereby enabling signal transmission.

[0131] It should be understood that DCG transistor #716 can be used to control the type of conversion gain. For example, when DCG transistor #716 is in the off state, pixel unit 700 is in HCG, and when DCG transistor #716 is in the on state, pixel unit 700 is in LCG. The following will combine... Figure 8 This will be described in further detail.

[0132] Figure 8This is a schematic diagram of a signal quantization method 800 according to an embodiment of this application. The application describes an example where the first conversion gain is LCG, the second conversion gain is HCG, and the output order of the first to fourth signals is: the first signal before the third signal, the third signal before the fourth signal, and the fourth signal before the second signal. Figure 8 As shown, method 800 includes:

[0133] #1: The first signal and the first ramp signal are connected to the input of the comparator. The level of the first ramp signal is higher than the level of the first signal (displayed as LRST) (reset signal), and the output of the comparator is high.

[0134] #2: During the quantization phase of the first signal, the level of the first ramp signal gradually decreases, and the counter starts counting from 0. When the level of the first ramp signal is lower than the level of the first signal, the comparator flips, and the comparator output changes from high to low. The counter stops counting, and the first count result is obtained.

[0135] #3: When the quantization phase of the first signal ends, the bitwise inverted signal (BWI signal) is set to high level. The counter inverts the first count result to obtain the first inverted count result (C1). The first latch is set to high level to store the first inverted count result. The counter is then reset (by setting the reset signal to high level).

[0136] #4: The third signal and the third ramp signal are connected to the input of the comparator. The level of the third ramp signal is higher than the level of the third signal (displayed as HRST) (reset signal), and the output of the comparator is high.

[0137] #5: In the quantization stage of the third signal, the counter starts counting from 0 and stops counting when the comparator flips, thus obtaining the third counting result.

[0138] #6: When the quantization stage of the third signal ends, the bit-inverted signal is set to high level, and the counter inverts the third counting result to obtain the second inverted counting result (C2).

[0139] #7: The fourth signal and the fourth ramp signal are connected to the input of the comparator. The level of the fourth ramp signal is higher than the level of the fourth signal (displayed as HISG) (working signal), and the output of the comparator is high.

[0140] #8: During the quantization stage of the fourth signal, the counter starts counting from the second inverted count result and stops counting when the comparator flips, thus obtaining the fourth count result (C3).

[0141] #9: When the quantization phase of the fourth signal ends, the second latch is set to a high level to store the fourth counting result. The fourth counting result is the code value obtained by double sampling of the reset signal and the working signal under HCG.

[0142] #10: Set the set signal to high level, and the first inverted count result (C1) in the first set of latches is input to the counter through the set signal.

[0143] #11: The second signal and the second ramp signal are connected to the input of the comparator. The level of the second ramp signal is higher than the level of the second signal (displayed in LISG) (operating signal), and the output of the comparator is high.

[0144] #12: During the quantization phase of the second signal, the counter starts counting from the first inverted count result and stops counting when the comparator flips, thus obtaining the second count result (C4).

[0145] #13: When the quantization phase of the second signal ends, the first latch is set to a high level to store the second counting result. The second counting result is the code value obtained by double sampling of the reset level and the working signal level under LCG.

[0146] During the quantization process described above, the voltage levels of SEL transistor #715, RST transistor #717, TG transistor #712, and DCG transistor #716 of pixel unit 700 are described below. Specifically:

[0147] Q1, SEL, RST, and DCG are set to high level, SEL transistor #715, RST transistor #717 and DCG transistor #716 are turned on, and the first FD #713 and the second FD #718 are reset.

[0148] Q2, RST transistor #717 is set to low level, read the reset voltage (LRST) under LCG;

[0149] Q3, DCG transistor #716 is set to low level, read the reset voltage (HRST) under HCG;

[0150] Q4, TG transistor #712 is set to high level, TG transistor #712 is turned on, and the charge accumulated in PD #711 is transferred to the first FD #713.

[0151] Q5, TG transistor #712 is set to low level to read the working signal voltage (HSIG) under HCG.

[0152] Q6, DCG transistor #716 and TG transistor #712 are set to high level, DCG transistor #716 and TG transistor #712 are turned on, and the charge accumulated in PD #711 is transferred to the first region #711 and the second FD #718.

[0153] Q7, TG transistor #712 is set to low level to read the operating signal voltage (LSIG) under LCG.

[0154] Q8, DCG transistor #716 and SEL transistor #715 are set to low level to complete the reading of a pixel signal.

[0155] In summary, the image processing device completes the double sampling processing of reset level and signal level under multiple different conversion gains through an architecture of a comparator, a counter, and multiple latches. This application can reduce the power consumption of the readout circuit and the chip area occupied in the image processing circuit.

[0156] Figure 9 This is a schematic diagram of the structure of a pixel unit 900 according to an embodiment of this application. The pixel unit 900 employs LOFIC technology. Figure 9 As shown, pixel unit 900 includes: PD#811, TG transistor#912, first FD#913, SF#914, SEL transistor#915, SG transistor#916, RST transistor#917, and LOFIC capacitor#918.

[0157] Specifically, PD#911 is used for photoelectric conversion, TG transistor#912 controls the transfer of electrons from PD#911 to the first FD#913 and LOFIC capacitor#918, both of which store the electrons generated by photoelectric conversion. SF#914 controls the transfer of electrons from the FD to the signal line. SEL transistor#715 controls the signal output switch, allowing control of the signal output sequence. SG transistor#916 switches between the two conversion gains. RST transistor#917 resets the voltage signal in the circuit. The following will combine... Figure 10 This will be described in further detail.

[0158] Figure 10 This is a schematic diagram of a signal quantization method 1000 according to an embodiment of this application. The application describes an example where the first conversion gain is HCG, the second conversion gain is LCG, and the output order of the first to fourth signals is: the first signal precedes the second signal, the second signal precedes the third signal, and the third signal precedes the fourth signal. Figure 10 As shown, method 1000 includes:

[0159] #1. The first signal and the first ramp signal are connected to the input of the comparator. The level of the first ramp signal is higher than the level of the first signal (displayed as HRST) (reset signal), and the output of the comparator is high.

[0160] #2. During the quantization phase of the first signal, the level of the first ramp signal gradually decreases, and the counter starts counting from 0. When the level of the first ramp signal is lower than the level of the first signal, the comparator flips, the output of the comparator becomes low, the counter stops counting, and the first counting result is obtained.

[0161] #3. When the quantization stage of the first signal ends, the bit-inverted signal is set to high level, and the counter inverts the first count result to obtain the first inverted count result (C1).

[0162] #4. The second signal and the second ramp signal are connected to the input of the comparator. The level of the second ramp signal is higher than the level of the second signal (displayed as HSIG) (working signal), and the output of the comparator is high.

[0163] #5. In the quantization stage of the second signal, the counter starts counting from the first inverted count result and stops counting when the comparator flips, thus obtaining the second count result (C2).

[0164] #6. When the quantization phase of the second signal ends, the first latch is set to a high level to store the second counting result. The second counting result is the code value obtained by double sampling of the reset signal and the working signal under HCG.

[0165] #7. The third signal and the third ramp signal are connected to the input of the comparator. The level of the third ramp signal is higher than the level of the third signal (displayed as LRST) (reset signal). The output of the comparator is high.

[0166] #8. During the quantization phase of the third signal, the level of the third ramp signal gradually decreases, and the counter starts counting from 0. When the level of the third ramp signal is lower than the level of the third signal, the comparator flips, the comparator output is low, the counter stops counting, and the third counting result is obtained.

[0167] #9. When the quantization stage of the third signal ends, the bit-inverted signal is set to high level, and the counter inverts the third counting result to obtain the second inverted counting result (C3).

[0168] #10. The fourth signal and the fourth ramp signal are connected to the input of the comparator. The level of the fourth ramp signal is higher than the level of the fourth signal (displayed in LISG) (operating signal), and the output of the comparator is high.

[0169] #11. In the quantization stage of the fourth signal, the counter starts counting from the second inverted count result and stops counting when the comparator flips, thus obtaining the fourth count result (C4).

[0170] #12. When the quantization phase of the fourth signal ends, the second latch is set to a high level to store the fourth counting result. The fourth counting result is the code value obtained by double sampling of the reset signal and the working signal under the LCG.

[0171] During the quantization process described above, the voltage levels of SEL transistor #915, RST transistor #917, TG transistor #912, and SG transistor #916 in pixel unit 900 are described below. Specifically:

[0172] When S1 and SEL transistor #915 are set to high level, SEL transistor #915 is turned on, and the voltage (HRST) of the first signal under HCG is read.

[0173] When S2 and TG transistor #912 are set to high level, TG transistor #912 is turned on, and the charge accumulated in PD #911 is transferred to the first FD #913.

[0174] S3, TG transistor #912 is set to low level to read the voltage of the second signal (HSIG) under HCG.

[0175] S4, SG transistor #916 and TG transistor #912 are set to high level, SG transistor #916 and TG transistor #912 are turned on, and the charge accumulated in PD #911 is transferred to the first FD #912 and LOFIC capacitor #918.

[0176] S5, TG transistor #912 is set to low level, and the voltage of the third signal (LSIG) under LCG is read.

[0177] S6 and RST transistor #917 are set to high level, RST transistor #917 is turned on, and the first FD #913 and LOFIC capacitor #918 are reset.

[0178] S7 and RST transistor #917 are set to low level to read the voltage of the fourth signal (LRST) under LCG.

[0179] When S8, SG transistor #916, and SEL transistor #915 are set to low level, the readout of one pixel signal is completed.

[0180] In summary, the image processing device described above can perform double sampling processing of reset levels and signal levels under multiple different conversion gains through an architecture consisting of a comparator, a counter, and multiple latches. This application can reduce the power consumption of the readout circuit and the chip area occupied in the image processing device.

[0181] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0182] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0183] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0184] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0185] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0186] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0187] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An image processing apparatus, characterized in that, include: A comparator, a counter, and at least two latches, the at least two latches including a first latch and a second latch; The comparator is used to compare the second ramp signal output by the ramp generator with the second signal output by the pixel unit to obtain a second comparison result. The counter is used to convert the second comparison result based on the first inverted count result to obtain the second count result. The first inverted count result is obtained by the counter inverting the first count result. The first count result is obtained by the counter converting the first comparison result. The first comparison result is obtained by the comparator comparing the first ramp signal output by the ramp generator with the first signal output by the pixel unit. The first latch is used to store the second counting result; as well as, The comparator is also used to compare the fourth ramp signal output by the ramp generator with the fourth signal output by the pixel unit to obtain a fourth comparison result; The counter is also used to convert the fourth comparison result based on the second inverted count result to obtain a fourth count result. The second inverted count result is obtained by inverting the third count result by the counter. The third count result is obtained by converting the third comparison result by the counter. The third comparison result is obtained by comparing the third ramp signal output by the ramp generator with the third signal output by the pixel unit by the comparator. The second latch is used to store the fourth counting result; Wherein, the first signal and the second signal belong to the first conversion gain, and the third signal and the fourth signal belong to the second conversion gain.

2. The apparatus according to claim 1, characterized in that, The first signal is output before the third signal, the third signal is output after the fourth signal, and the fourth signal is output before the second signal. The counter is also used to output the first inverted count result to the first latch; The first latch is also used to store the first inverted count result; When the comparator is used to compare the second ramp signal with the second signal... The counter is also used to obtain the first inverted count result from the first latch.

3. The apparatus according to claim 1, characterized in that, The third signal is output before the first signal, the first signal is output after the second signal, and the second signal is output before the fourth signal. The counter is also used to output the second inverted count result to the second latch; The second latch is also used to store the second inverted count result; When the comparator is used to compare the fourth ramp signal with the fourth signal... The counter is also used to obtain the second inverted count result from the second latch.

4. The apparatus according to claim 1, characterized in that, The first signal is output before the second signal, the second signal is output after the third signal, and the third signal is output before the fourth signal; or, The output order of the third signal is before the output order of the fourth signal, the output order of the fourth signal is after the output order of the first signal, and the output order of the first signal is before the output order of the second signal.

5. The apparatus according to any one of claims 1 to 4, characterized in that, The image processing device also includes the ramp generator.

6. The apparatus according to any one of claims 1 to 5, characterized in that, The image processing apparatus further includes a pixel array, which includes at least one of the pixel units.

7. The apparatus according to any one of claims 1 to 6, characterized in that, The image processing device also includes an image processing circuit. The image processing circuit is used to process the second counting result and the fourth counting result.

8. The apparatus according to any one of claims 1 to 7, characterized in that, The first signal includes a reset signal, and the second signal includes a working signal; or, The first signal includes a working signal, and the second signal includes a reset signal.

9. The apparatus according to any one of claims 1 to 8, characterized in that, The third signal includes a reset signal, and the fourth signal includes a working signal; or... The third signal includes a working signal, and the fourth signal includes a reset signal.

10. A signal quantization method, characterized in that, The method is applied to an image processing apparatus, the image processing apparatus including a comparator, a counter, and at least two latches, the at least two latches including a first latch and a second latch, the method comprising: The comparator compares the second ramp signal output by the ramp generator with the second signal output by the pixel unit to obtain a second comparison result. The counter converts the second comparison result based on the first inverted count result to obtain the second count result. The first inverted count result is obtained by the counter inverting the first count result. The first count result is obtained by the counter converting the first comparison result. The first comparison result is obtained by the comparator comparing the first ramp signal output by the ramp generator with the first signal output by the pixel unit. The first latch stores the second counting result output by the counter; as well as, The comparator compares the fourth ramp signal output by the ramp generator with the fourth signal output by the pixel unit to obtain a fourth comparison result; The counter converts the fourth comparison result based on the second inverted count result to obtain the fourth count result. The second inverted count result is obtained by the counter inverting the third count result. The third count result is obtained by the counter converting the third comparison result. The third comparison result is obtained by the comparator comparing the third ramp signal output by the ramp generator with the third signal output by the pixel unit. The second latch stores the fourth counting result output by the counter; Wherein, the first signal and the second signal belong to the first conversion gain, and the third signal and the fourth signal belong to the second conversion gain.

11. The method according to claim 10, characterized in that, The first signal is output before the third signal, the third signal is output after the fourth signal, and the fourth signal is output before the second signal. The counter outputs the first inverted count result to the first latch; The first latch stores the first inverted count result; When the comparator is used to compare the second ramp signal with the second signal... The counter obtains the first inverted count result from the first latch.

12. The method according to claim 10, characterized in that, The third signal is output before the first signal, the first signal is output after the second signal, and the second signal is output before the fourth signal. The counter outputs the second inverted count result to the second latch; The second latch stores the second inverted count result; When the comparator compares the fourth ramp signal with the fourth signal... The counter obtains the second inverted count result from the second latch.

13. The method according to claim 10, characterized in that, The first signal is output before the second signal, the second signal is output after the third signal, and the third signal is output before the fourth signal; or, The output order of the third signal is before the output order of the fourth signal, the output order of the fourth signal is after the output order of the first signal, and the output order of the first signal is before the output order of the second signal.

14. The method according to any one of claims 10 to 13, characterized in that, The image processing apparatus further includes the ramp generator, and the method further includes: The ramp generator outputs the first ramp signal; or... The ramp generator outputs the second ramp signal; or... The ramp generator outputs the third ramp signal; or... The ramp generator outputs the fourth ramp signal.

15. The method according to any one of claims 10 to 14, characterized in that, The image processing apparatus further includes a pixel array, the pixel array comprising at least one of the pixel units, and the method further includes: The pixel unit outputs the first signal; or... The pixel unit outputs the second signal; or... The pixel unit outputs the third signal; or... The pixel unit outputs the fourth signal.

16. The method according to any one of claims 10 to 15, characterized in that, The image processing apparatus further includes an image processing circuit, and the method further includes: The image processing circuit processes the second counting result and the fourth counting result.

17. The method according to any one of claims 10 to 16, characterized in that, The first signal includes a reset signal, and the second signal includes a working signal; or, The first signal includes a working signal, and the second signal includes a reset signal.

18. The method according to any one of claims 10 to 17, characterized in that, The third signal includes a reset signal, and the fourth signal includes a working signal; or... The third signal includes a working signal, and the fourth signal includes a reset signal.

19. A chip system, characterized in that, include: A logic circuit for coupling with an input / output interface, through which data is transmitted to perform the signal quantization method of any one of claims 10 to 18.

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