Automotive processors supporting PQK encryption

Abstract

The invention relates to a secure microcontroller (1) for controlling devices in a car, comprising a semiconductor substrate, a storage element, at least one internal bus (2), at least one 8 / 16 / 32 / 64-bit microcontroller core, one or more data interfaces and at least one quantum process-based generator (15) for true random numbers. The storage element, the data interface, the quantum process-based generator (15) and the microcontroller core (16) are connected to the internal bus (2). The quantum process-based generator (15) generates random numbers at the request of the microcontroller core (16) and provides random numbers. The microcontroller core (16) uses a program from one or more of its storage elements and uses the random numbers to generate a key. The microcontroller core (16) uses the program and the key from one or more of its storage elements to encrypt and decrypt data exchanged with an external device of the secure microcontroller (1). The semiconductor substrate integrally comprises part of the devices of the secure microcontroller (1) listed herein.

Description

[0001] Application Reference

[0002] This PCT application claims the priority of German national patent applications 10 2021 128005.2 of October 27, 2021, DE 10 2021 130 107.6 of November 18, 2021, DE 10 2022 110 713.2 of May 2, 2022, DE 10 2022 125 574.3 of October 4, 2022, DE 10 2022 125 617.0 of October 5, 2022 and DE 10 2022125 768.1 of October 6, 2022, the contents of which are hereby incorporated by reference into the subject matter of the present application. Technical Field

[0003] The invention relates to a microcontroller which comprises, in particular, at least one generator for true random numbers based on quantum processes (quantum random number generator: QRNG) as a random number generator, in particular for cryptography. Background Art

[0004] The automotive industry and other branches of industry are increasingly subject to various forms of piracy. Counterfeiters copy parts and products of manufacturers of the relevant industry and often use their brand names. Another danger point is hacker attacks, for example affecting data transmission within or to and from the product, such as in vehicle-to-vehicle or vehicle-to-x communication or data communication within components of the vehicle, which is particularly important in autonomous systems as well as in data communication from outside to such autonomous systems and from these autonomous systems to the outside in terms of preventing hacker attacks.

[0005] The entropy properties of random number generators currently used in such systems for data encryption are mostly insufficient. Generators based on quantum processes for true random numbers (quantum random number generators: QRNG) are known in the prior art, but they are difficult to integrate or have poor quantum yields.

[0006] For example, the details of a data and signal processing unit utilizing a microcontroller and a generator based on a quantum process for generating random numbers are described in the following document:

[0007] -US-B-10 802 800

[0008] -Session key. See: Wikipedia, the free encyclopedia. Edited: October 1, 2020. URL: https: / / en.wikipedia.org / w / index.php?title=Session_key&oldid= 981281879 [Accessed on May 31, 2022];

[0009] -Integrated circuit. See: Wikipedia, the free encyclopedia. Edited: 12 October 2021. URL: https: / / en.wikipedia.org / w / index.php?title=Integrated_circuit&oldid= 1049603915 [Accessed on May 31, 2022];

[0010] -BIOS. See: Wikipedia, the free encyclopedia. Edited: 24 October 2021. URL: https: / / en.wikipedia.org / w / index.php?title=BIOS&oldid=1051566527 [Accessed 31 May 2022];

[0011] -BURRI, S. [et al.]: SPADs for Quantum Random Number Generators and beyond. See: 19 th Asia and South Pacific Design Automation Conference(ASP-DAC),20-23January 2014,Singapore,IEEE,p.788-794.DOI:10.1109 / ASPDAC.2014.6742986;

[0012] -Fabio Acerbi,Nicola Massari,Leonardo Gasparini,Alessandro Tomasi,Nicola Zorzi,Giorgio Fontana,Lorenzo Pavesi,Alberto Gola in"Structures andMethods for fully-integrated Quantum Random Number Generators",IEEE Journal of selected topics in quantum electronics,Vol.26,No.3,May / June 2020. Summary of the invention

[0013] The object of the present invention is to provide a device and method for generating true random numbers based on a photon process.

[0014] Technical Solution

[0015] This object is achieved by a microcontroller for controlling a device in a vehicle according to the present invention, wherein the microcontroller is provided with:

[0016] - semiconductor substrates,

[0017] - storage element,

[0018] - at least one internal bus,

[0019] - at least one microcontroller core,

[0020] - one or more data interfaces, and

[0021] - at least one generator based on quantum processes for true random numbers,

[0022] - wherein said storage element is connected to said internal bus,

[0023] - wherein said data interface is connected to said internal bus,

[0024] - wherein said quantum process based generator is connected to said internal bus, and

[0025] - wherein said microcontroller core is connected to said internal bus,

[0026] - wherein the generator based on a quantum process generates random numbers, in particular at the request of the microcontroller core,

[0027] - wherein said generator based on a quantum process provides said random numbers,

[0028] - wherein the microcontroller core uses a program from one or more memory elements thereof and uses the random number to generate a key,

[0029] - wherein the microcontroller core uses a program from one or more of its storage elements and the key to encrypt and decrypt data exchanged with external devices or internally via the data interface,

[0030] - wherein the semiconductor substrate integrally comprises a sub-device of the secure microcontroller listed herein,

[0031] - wherein the generator based on quantum processes comprises at least one first SPAD diode as a light source of optical quantum signals,

[0032] - wherein the generator based on quantum processes comprises at least one second SPAD diode as a photodetector for receiving the optical quantum signal,

[0033] - wherein the generator based on quantum processes comprises at least one processing circuit,

[0034] - wherein the generator based on quantum processes comprises at least one optical fiber for optically coupling the at least one first SPAD diode with the at least one second SPAD diode,

[0035] - wherein the quantum based generator comprises an operating circuit for supplying electrical energy for emitting light to the at least one first SPAD diode, and

[0036] - wherein said quantum based generator comprises a processing circuit for detecting the signal of said at least one second SPAD diode and for forming a random number from said signal of said at least one second SPAD diode and for providing said random number to said microcontroller core.

[0037] A feature of the microcontroller that is essential to the present invention is a quantum process-based generator (quantum process-based entropy source) for generating true random numbers. The generator is based on an optical quantum process, i.e., a combination of excitation and spontaneous photon emission of at least one second or receiver SPAD diode, respectively. The receiver SPAD diode is coupled to at least one first or transmitter SPAD diode via an optical waveguide. Both SPAD diodes operate in Geiger mode.

[0038] The invention is characterized in that the optical fiber is formed as at least a part or a portion of one or more dielectric layers, which are part of the metallization stack as an insulating layer, which is formed on the semiconductor material in which the first and second SPAD diodes are integrated. Alternatively, the optical fiber can also couple two semiconductor substrates together, forming at least one first and at least one second SPAD diode in each semiconductor substrate. However, it is preferred to design a microcontroller with a semiconductor substrate, into which all SPAD diodes are integrated, and the optical fiber is arranged on the surface of the semiconductor substrate.

[0039] Due to the occurrence of spontaneous and stimulated photon emission from the second SPAD diode, its emission signal has extremely narrow pulses of different heights (hereinafter referred to as spikes). Therefore, the emission signal includes a first spike that appears due to single photon emission. When the spontaneous photon emission coincides with the stimulated photon emission, a second spike appears in the emission signal of the second SPAD diode that is higher than the first spike. The occurrence of such a combined photon emission is highly random, i.e., based on quantum processes, which is why the evaluation of the time sequence of the occurrence of the second spike is now suitable for generating true random numbers therefrom.

[0040] In this respect, in an advantageous further development of the invention, it is provided that the emission signal of the at least one second SPAD diode has a first peak and a second peak larger than the first peak, wherein the first peak and the second peak are respectively larger than a definable reference value, wherein the first peak is caused by the spontaneous photon emission of the at least one second SPAD diode without simultaneously causing the stimulated photon emission of the at least one second SPAD diode, and the second peak is caused by the spontaneous photon emission of the at least one second SPAD diode stimulated by the simultaneous occurrence of photon reception by the at least one first SPAD diode, and the processing circuit of the quantum process-based generator generates a first logic value or a second logic value as a bit for generating the random number based on a comparison of the time interval of the second peak with a threshold or based on a comparison of the time intervals of the second peaks with each other.

[0041] According to a variant of the present invention, the true random number is generated so that the processing circuit generates the first logic value or the second logic value based on a comparison of a time interval between two spikes with a threshold, and if the time interval is less than the threshold, the processing circuit outputs the first logic value as a bit of the random number, and if the time interval is greater than the threshold, the processing circuit outputs the second logic value as a bit of the random number.

[0042] According to a second variant, the true random number is generated so that the processing circuit generates the first logic value or the second logic value based on a comparison of the time intervals of second spikes in different pairs of second spikes, and if the time interval of the last occurring second spike is smaller than, for example, the time interval between the second-to-last second spike and the third-to-last second spike or other previous pairs of second spikes, the processing circuit outputs the first logic value as a bit for generating the random number, and if the time interval of the last occurring second spike is larger than, for example, the time interval between the second-to-last second spike and the third-to-last second spike or other previous pairs of second spikes, the processing circuit outputs the second logic value as a bit for generating the random number.

[0043] For the two above-mentioned variants of generating true random numbers, it applies that if equality is detected when comparing the time intervals with a threshold value (variant 1) or with each other (variant 2), this result is discarded for the random number. Alternatively, an equal comparison result can also be used, but this will have to be evaluated purely by chance as a first logical value or a second logical value.

[0044] For the sake of completeness, it should also be mentioned that a third spike may also appear in the transmit signal of the second or receiver SPAD diode, which is essentially three times the height of the first spike. Such an event occurs when the photon emission stimulated by receiving photons of the first SPAD diode coincides with the spontaneous photon emission from the second SPAD diode (which in turn is stimulated). Advantageously, these "tripple spikes" are not used. In this regard, when checking the transmit signal of each second SPAD diode, its signal is compared with a predetermined reference value range within which the signal must lie in order to be evaluated for the generation of true random numbers.

[0045] If multiple pairs of first SPAD diodes and second SPAD diodes are provided, it is advantageous to generate individual bits of a true random number in parallel, wherein the emission signals of the second SPAD diodes can be fed to the processing circuit and the processing circuit outputs different bits of the bits used to generate the random number based on the emission signals of the second SPAD diodes.

[0046] A pair of a first SPAD diode and a second SPAD diode is generally sufficient to sequentially generate individual bits of a true random number, wherein the processing circuit sequentially outputs logic values ​​for the bits used to generate the random number.

[0047] Another variation of the optical coupling of the first and second SPAD diodes can be seen, in which a single first SPAD diode and a plurality of second SPAD diodes optically coupled to the single SPAD diode are provided, wherein the emission signals of the second SPAD diodes can be fed to the processing circuit, and the processing circuit outputs different bits of the bits used to generate the random number based on the emission signals of the second SPAD diodes.

[0048] In order to be able to detect function errors and to generate random numbers even in the presence of errors, an error detection unit and a pseudo-random number generator can be advantageously provided, wherein when the error detection unit detects an error in the function of the component of the quantum-based generator responsible for the photon-based process or an error in its processing circuit, the processing circuit of the quantum-based generator switches from outputting bits for generating the random number based on the emission signal of the at least one second SPAD diode to outputting bits generated by the pseudo-random number generator for generating pseudo-random numbers. Here, it is desirable that, when an error is detected, the error detection unit outputs an error signal that in particular indicates the type and / or cause of the error. The error detection unit advantageously identifies not only the presence of an error, but also what type of error has occurred. The reaction of the quantum-based generator to such events depends on the application and, for example, may mean performing a self-test. However, preferably, in the event of a malfunction of the quantum-based generator, it is switched to a pseudo-random number generator that generates pseudo-random numbers, for example, based on the last bit generated by the quantum-based generator before the error was detected.

[0049] Possible sources of error could be:

[0050] - Failure of the supply voltage of various components of the microcontroller,

[0051] - erroneous signal generation of the first and / or second SPAD diode,

[0052] - a fault in the optical fiber and / or when coupling the first SPAD diode and / or the second SPAD diode to the optical fiber,

[0053] - Circuit failures in the analog and / or digital parts of the microcontroller and the quantum random number generator,

[0054] - The error entropy of the provided random numbers, which can be done by testing as described in David Johnston, Random Number Generators–Principles and Practices, 2018, Chapters 8 and 9, Walter De Gruyter GmbH, Berlin / Bonston, ISBN 978-1-5015-1530-2.

[0055] The above-described variant of a microcontroller with an error detection unit and a pseudo-random number generator can also be implemented with a microcontroller with a quantum-based generator other than the above-described generators. In this respect, an independent protection claim is filed for the subject matter of this further development.

[0056] In an advantageous configuration of the invention, it can be provided that the storage element comprises one or more read / write memories RAM and / or one or more writable non-volatile memories, in particular EEPROM memories and / or flash memories and / or one-time programmable (OTP) memories, and / or one or more read-only memories and / or one or more non-volatile manufacturer memories, in particular one or more manufacturer ROMs, and / or one or more manufacturer EEPROMs and / or one or more manufacturer flash memories.

[0057] In a preferred configuration of the invention, it may be provided that the manufacturer ROM includes boot software.

[0058] In another preferred configuration of the present invention, it may be provided that a manufacturer firewall is provided between the manufacturer memory and the internal bus.

[0059] In an advantageous further development of the invention, the microcontroller can be provided with:

[0060] - Basic clock generator,

[0061] - a clock generator circuit, and / or

[0062] - Reset circuit, and / or

[0063] - a power supply or Vcc circuit with a voltage regulator to provide the operating voltage, and / or

[0064] - grounding circuit, and / or

[0065] - input / output circuits, and / or

[0066] - one or more processing modules,

[0067] - wherein said processing module is in communication with said internal bus, and

[0068] -Wherein the processing module comprises one or more of the following modules:

[0069] -CRC module (cyclic redundancy check),

[0070] - Clock generator module,

[0071] - has a DES accelerator and / or an AES accelerator,

[0072] - one or more timer modules,

[0073] - Safety monitoring and control circuits,

[0074] - Data interfaces, in particular universal asynchronous receiver / transmitters.

[0075] In another advantageous configuration of the invention, it can be provided that

[0076] - the semiconductor substrate comprises a surface,

[0077] - the semiconductor substrate comprises a semiconductor material beneath its surface,

[0078] - said surface of said semiconductor substrate comprises a metallization stack,

[0079] - the metallization stack comprises an optically transparent and electrically insulating layer of typical structure located on the surface of the semiconductor substrate,

[0080] - at least a portion of the transparent and electrically insulating layer forms said at least one optical fiber,

[0081] - the first SPAD diode emits photons from the semiconductor material of the semiconductor substrate into the optical fiber,

[0082] - said at least one optical fiber transmits such photons to said second SPAD diode.

[0083] In a preferred configuration of the invention, it can be provided that the optical fiber illuminates the second SPAD diode so that light from inside the optical fiber re-enters the semiconducting material of the semiconductor substrate and strikes device components of the second SPAD diode there.

[0084] In another preferred configuration of the present invention, it may be provided that

[0085] - at least one operating circuit at least temporarily supplies electrical energy to said at least one first SPAD diode,

[0086] - said at least one first SPAD diode feeds photons into said at least one optical fiber when supplied with sufficient electrical energy,

[0087] - said at least one optical fiber transmits such photons to said second SPAD diode, and

[0088] - said at least one optical fiber transmits such photons to said second SPAD diode.

[0089] In an advantageous embodiment of the invention, it can be provided that one data bus interface is a wired vehicle data bus interface or one or more of the plurality of data bus interfaces are wired vehicle data bus interfaces.

[0090] In a further advantageous embodiment of the invention, it can be provided that one or more wired vehicle data bus interfaces are designed as:

[0091] -CAN data bus interface, and / or

[0092] -CAN FD data bus interface, and / or

[0093] -Flexray data bus interface, and / or

[0094] -PSI5 data bus interface, and / or

[0095] -DSI3 data bus interface, and / or

[0096] -LIN data bus interface, and / or

[0097] - Ethernet data bus interface, and / or

[0098] -MELIBUS data bus interface.

[0099] In an advantageous further development of the invention, it can be provided that one data bus interface is a wireless data bus interface or one or more of the data interfaces are wireless data bus interfaces.

[0100] In a further advantageous embodiment of the invention, it can be provided that one or more wireless data bus interfaces are designed as:

[0101] - WLAN interface, and / or

[0102] - a mobile radio interface, and / or

[0103] -Bluetooth interface.

[0104] In a preferred configuration of the invention, it can be provided that one data bus interface is a wired data bus interface or that one or more of the plurality of data interfaces are wired data bus interfaces.

[0105] In another advantageous configuration of the invention, it can be provided that one or more wired data bus interfaces are configured as:

[0106] - KNX data bus interface, and / or

[0107] -EIB data bus interface, and / or

[0108] -DALI data bus interface, and / or

[0109] -PROFIBUS data bus interface.

[0110] A significant advantage of the present invention is that the semiconductor material in which the optically coupled SPAD diode is integrated is not used to transmit the photons, but rather one or more dielectric layers close to the surface of the semiconductor material, i.e., the insulating layers of the metallization stack, are used for transmission. This greatly increases the "yield" of photons reaching the receiver SPAD diode, which means that more events can be observed in the receiver SPAD in a shorter time, which in turn can be used to generate longer quantum process-based random numbers in a very short time and multiple quantum process-based random numbers in a very short time, respectively. This increases the effectiveness of generating quantum process-based random numbers that are also secure for so-called post-quantum cryptography (PQK) or quantum computer-resistant cryptography. BRIEF DESCRIPTION OF THE DRAWINGS

[0111] The invention is explained in more detail below by means of various exemplary embodiments and with reference to the accompanying drawings.

[0112] Figure 1 is a block diagram showing an example of the secure microcontroller 1 .

[0113] Figure 2 A diagram showing an exemplary process of protecting a product by a first secure microcontroller (IC1) and by a second secure microcontroller (IC2) according to the invention. Here, the first secure microcontroller (IC1) and the second secure microcontroller (IC2) exchange data with each other which are preferably encrypted using one or more generators 15 based on quantum processes for true random numbers.

[0114] Figure 3 Shown is the integration of a SPAD diode in a semiconductor material.

[0115] Figure 4 and Figure 5 Shown is a combination of a first SPAD diode and a second SPAD diode, both diodes being integrated in a semiconductor material and optically coupled via an optical waveguide applied to the semiconductor material as part of a metallization stack, ie as part of an insulating layer of the metallization stack.

[0116] Figure 6 A combination of a quantum-based entropy source of at least one transmitter SPAD diode and at least one receiver SPAD diode with an optical fiber which optically couples the at least one transmitter SPAD diode and at least one receiver SPAD diode and comprises evaluation and operating circuitry is shown.

[0117] Figure 7 Shows something like Figure 6 arrangement, but with the addition of monitoring circuitry.

[0118] Figure 8is a flow chart illustrating an entropy extraction method according to an exemplary embodiment of the present invention.

[0119] Fig. 9 is a diagram showing a typical output signal of a receiver SPAD diode.

[0120] Fig.10 The individual method steps for generating quantum random numbers using a photon-based process according to the invention are schematically illustrated. DETAILED DESCRIPTION

[0121] The accompanying drawings show the main parts of the proposed device and method in an exemplary and simplified manner.For illustrative purposes, certain examples designed according to the teachings of the present invention will now be described with reference to the accompanying drawings.

[0122] The exemplary embodiments of the present invention in the following description and the accompanying drawings are considered illustrative and are not considered to limit the specific examples or elements described. Multiple examples can be derived from the following description and / or the accompanying drawings by deforming, combining or changing certain elements. In addition, those skilled in the art can derive examples or elements that are not literally described from the description and the accompanying drawings.

[0123] The integrated circuit according to the invention preferably comprises a secure microcontroller 1 , ie a microcontroller supporting secure data encryption. Figure 1An example of a secure microcontroller 1 at the block diagram level is shown. For example, the secure microcontroller 1 includes a storage element connected to an internal bus 2. For example, the storage element may include one or more read / write memories RAM 3 and / or one or more writable non-volatile memories such as EEPROM memory 4 and / or flash memory 4 and / or OTP memory 4. In addition, the secure microcontroller 1 preferably includes one or more non-volatile read-only memories 5 such as ROM. In addition, the secure microcontroller 1 preferably includes one or more non-volatile, writable and / or non-writable manufacturer memories 6, which typically include reference data that may be important for potential subsequent research on the microcontroller or other electronic devices. In the case of a non-writable manufacturer memory 6, the manufacturer memory 6 may be a manufacturer ROM. Preferably, the manufacturer ROM 6 includes boot software. For example, the secure microcontroller 1 includes one or more cryptographic accelerators 7, such as a DES accelerator and / or an AES accelerator 7, which accelerate cryptographic calculations and are connected to the internal bus 2. For example, preferably, at least one manufacturer firewall 8 is provided between the manufacturer memory 6 and the internal bus 2. The microcontroller core 16 accesses the memory via the data bus 2. For example, the secure microcontroller 1 includes a processing module that communicates with a microcontroller core 16 via an internal bus 2. The processing module of the microcontroller 1 preferably includes at least one of the following modules: a CRC module (cyclic redundancy check) 11, a clock generator module 12, one or more timer modules 13, a security monitoring and control circuit 14, one or more generators based on quantum processes for true random numbers 15 (quantum random number generator: QRNG), an 8 / 16 / 32 / 64-bit microcontroller core 16 and one or more data interfaces 17, in particular one or more universal asynchronous receiver transmitters (UART) to support high-speed serial data. Other circuit parts of the secure microcontroller 1 include, for example, one or more basic clock generator circuits 21 (CLK) and / or one or more clock generator modules 12, a reset circuit 22, a power supply or Vcc circuit 23 with a voltage regulator providing an operating voltage, a ground circuit 24 and an input / output circuit 25.

[0124] Preferably, the secure microcontroller 1 is designed such that it can carry out a secure authentication. Thus, in addition to the authentication code, the secure microcontroller 1 also stores further data, such as one or more lifetime and usage duration data and / or for example logistics data and / or for example business data and / or website and email addresses and / or image data, for the instruction set of the control unit of the motor vehicle with which the microcontroller core 16 communicates via the data interface. In addition, the secure microcontroller 1 can store other application data.

[0125] Preferably, the first integrated circuit comprises a secure microcontroller 1 , for example configured to facilitate secure authentication of a product.

[0126] Figure 2 An example of a method for manufacturing a circuit of a product including a secure microcontroller 1 according to the present invention is shown. For example, the method includes writing a product ID into a second integrated circuit of the product (block 250). The second integrated circuit preferably includes a second secure microcontroller 1 according to the present application. For example, the method includes writing an authentication code corresponding to the product ID into a memory of a first integrated circuit of a first secure microcontroller 1 (block 211). The first integrated circuit of the product preferably also includes a secure microcontroller 1 according to the present application. For example, the method includes writing various product IDs and various corresponding authentication codes into the memories of various integrated circuits of various secure microcontrollers 1. Various product IDs and various corresponding authentication codes may also be written into the memories of the corresponding integrated circuits of the corresponding secure microcontroller 1 of each product (block 221), so that each product has a unique product ID and a unique authentication code. For example, the latter step provides a secure and unique authentication code for each product.

[0127] For example, some of the features described in this specification enable secure authentication of a circuit or product while enabling integration and cost-effective manufacture of the circuit or product. For example, the second integrated circuit is preferably constructed so that it can perform secure authentication. In various examples, different host devices are able to authenticate the circuit or product, for example, a car, a smartphone, a network server, any data processing device, etc. In one example, the interface between the host device and the circuit is established via a control computer of the car. In another example, the first integrated circuit of the circuit is constructed to store additional data such as product-related codes, product setting information, etc. For example, only after the security authentication is performed via the first integrated circuit can the host device access, modify or process such additional data. For example, the first integrated circuit is constructed to provide or enable access to the above-mentioned additional data only after authentication. In one example, the product requires little or no adjustment for use in different motor vehicle series.

[0128] Internal data bus 2 (refer to Figure 1 ) may include multiple data buses 2 for multiple microcontroller cores 16, so that these microcontroller cores can access different sub-devices of the secure microcontroller 1 independently of each other with time delays and / or overlaps or simultaneously. However, the secure microcontroller 1 usually includes only one internal data bus 2 and only one microcontroller core 16. Preferably, the microcontroller core 16 is an Advanced Risc Maschine (AMR) processor or the like. Preferably, it is an 8-bit or 16-bit or 32-bit or 64-bit microcontroller computer core.

[0129] Preferably, the secure microcontroller 1 comprises one or more read / write memories RAM 3. This can be SRAM and / or MRAM and / or FRAMS etc. They can also be dynamic read / write memories such as DRAM which must be read and rewritten at regular intervals in an update cycle. The secure microcontroller 1 according to the invention can have access logic that regularly performs an update process in order to access its memory. However, DRAM usually opens opportunities for attacks and is usually a potential vulnerability. The microcontroller core 16 can preferably access this read / write memory RAM 3 via the internal data bus 2.

[0130] Preferably, the secure microcontroller 1 comprises one or more writable and non-volatile memories 4. The microcontroller core 16 can preferably access these writable and non-volatile memories 4 via an internal data bus 2. For example, the non-volatile memory may comprise an EEPROM memory 4 or a Flash memory 4 or an OTP memory 4. OTP stands for "One Time Programmable".

[0131] One attack option may be to erase the non-volatile memory 4 by radiation, such as X-rays and / or ionizing radiation and / or heating of the memory cells. To this end, the secure microcontroller 1 preferably comprises one or more security monitoring and control circuits 14, which monitor the data integrity of the memory cells of the erasable memory 4. Preferably, the memory cells have redundancy, so that at least two check bits are provided for a data word, which is preferably a data word with a length of 8 bits, i.e. a byte, and at least one check bit must always have a content 1, while the other check bit must always have a content 0. For example, the first check bit can be the parity bit of the byte, and the second check bit can be the inversion bit of the parity bit. If an attack such as ionizing radiation now occurs, the attack will reset the two check bits to the same value. The one or more security monitoring and control circuits 14 detect this deviation and block further access by the secure microcontroller 1.

[0132] Preferably, each bit of the memory of the secure microcontroller 1 is designed twice so that each logical data bit is implemented as a pair of a first physical data bit with a first internal logical value and a second physical data bit with a second internal logical value. The second internal logical value is usually the logical inverse of the first internal logical value. The one or more security monitoring and control circuits 14 preferably monitor that this is always the case. The one or more security monitoring and control circuits 14 detect deviations and, for example, preferably block further execution of a program or certain program parts by the microcontroller core 16 and / or block access to data in the event of a deviation.

[0133] Preferably, the secure microcontroller 1 comprises one or more reset circuits 22 (see Figure 1). If a predetermined or determinable reset condition and / or a combination and / or a time sequence of such reset conditions exist, the reset circuit 22 resets the safety microcontroller 1 and / or a sub-device of the safety microcontroller 1 to a predetermined state. For example, the condition may be a signaling of one or more safety monitoring and control circuits 14. The condition may also be a change in the potential and / or value of the operating voltage of the safety microcontroller. In addition, such a condition may affect the integrity of the housing of the safety microcontroller 1.

[0134] Preferably, the secure microcontroller 1 comprises a detector for opening the housing of the secure microcontroller 1. For example, this can be a single line, such as a textile network or fabric, surrounding or covering the secure microcontroller 1, or at least covering parts of the secure microcontroller 1. It can also be a network of lines covering the secure microcontroller 1 specifically for detecting attacks. For example, the secure microcontroller 1 can have a first input / output through which the secure microcontroller 1 can feed current into such a line and draw the current again at a second input / output. For example, if the current is interrupted, this is a sign of an attack, which is detected by one or more security monitoring and control circuits 14, which then send the attack signal to the microcontroller core 16 of the secure microcontroller 1 according to the invention. For example, in such a suspected violation of the integrity of the housing, one or more of the one or more security monitoring and control circuits 14 can prohibit write and / or read access to the memory contents of the memory of the secure microcontroller 1, or erase the contents or set the contents to a predetermined value, or overwrite them with meaningless data, or manipulate them in other ways. The memory of the secure microcontroller 1 preferably comprises one or more non-volatile read-only memories 5, such as ROMs. The ROM 6 of the secure microcontroller preferably contains data and / or program instructions as defined by the design.

[0135] Preferably, the secure microcontroller 1 (eg, see Figure 1) comprises one or more non-volatile, writable and / or non-writable manufacturer memories 6, in which the semiconductor manufacturer or other supplier can store production and security data such as serial numbers. Preferably, the semiconductor manufacturer blocks access to the writable and / or non-writable non-volatile manufacturer memory 6 after the final production test has been performed. Preferably, the writable and / or non-writable manufacturer memory 6 is accessible via a manufacturer password. In some cases, a dual key procedure makes sense. In this case, the customer (downstream of the semiconductor manufacturer) stores the customer password in a customer blocking register, which can also be blocked from access using a password. Preferably, the semiconductor manufacturer uses the customer password and the manufacturer password to access all storage areas of the secure microcontroller 1. Preferably, the semiconductor manufacturer provides an analysis password, by which the manufacturer can cause one or more of the one or more security monitoring and control circuits 14, usually with the help of a reset circuit 22, to erase the customer content and then make all storage areas of the secure microcontroller 1 accessible for error analysis. In the case of a non-writable manufacturer memory, the manufacturer memory 6 can be, for example, a manufacturer ROM, the content of which is determined, for example, during the manufacture of the semiconductor circuit of the secure microcontroller.

[0136] The secure microcontroller is generally adapted to receive and / or send encrypted data and / or program code portions and / or instructions by means of encryption methods stored in its memory and executed by the microcontroller core 16. Some of these methods require considerable computing power. Therefore, it has proven useful for the microcontroller core 16 not to execute certain program portions in these encryption methods in the form of sub-steps of these encryption methods, but to use specially synthesized hardware logic instead of the microcontroller core 16 to execute these program portions at an accelerated rate for one or more special hardware accelerators, preferably in the form of one or more cryptographic accelerators 7. To this end, for example, the secure microcontroller 1 preferably has a DES accelerator for the Data Encryption Standard (DES) algorithm and / or an AES accelerator 7 for executing the Advanced Encryption Standard (AES) algorithm. The microcontroller core 16 typically addresses these hardware accelerators 7 via an internal data bus 2. Preferably, the microcontroller core 16 has a redundant clock system so that access to the clock system can be identified. One or more of the one or more security monitoring and control circuits 14 monitor the consistency of the logic content of the preferred multiple redundant clock systems, so that attacks and errors can be detected. Preferably, one or more manufacturer memory firewalls 8 prevent the microcontroller core 16 and the test logic of the secure microcontroller 1 from accessing the manufacturer memory. They can preferably be unlocked using a manufacturer password as described. Preferably, the number of false entries is very limited in order to minimize the probability of a successful attack.

[0137] Preferably, the secure microcontroller comprises one or more CRC modules (Cyclic Redundancy Check) 11 in order to generate CRC data for serial data communication in the case of a transmission process, which are used in most data protocols to detect faulty data transmission, and to be able to verify the correct reception of data messages when receiving. Preferably, the secure microcontroller 1 comprises one or more clock generator modules 12 (clock driver, CLK), which generate one or more clocks for operating the circuits of the secure microcontroller. Preferably, one or more clock generator modules (clock driver, CLK) generate 12 redundant clocks representing an attack on the clock system. Typically, the secure microcontroller 1 comprises one or more timer modules 13 such as are required to detect timeouts. Preferably, the secure microcontroller 1 comprises one or more watchdog timers that monitor the execution of various program parts. The watchdog timer can be part of one or more security monitoring and control circuits 14.

[0138] According to the present invention (for example, referring to Figure 1), the secure microcontroller 1 includes at least one generator 15 based on quantum processes. Quantum-based processes have the advantage of being based on true coincidences. In the 1970s, physicist Bell proved that the "hidden parameter" theory was wrong. This means that the randomness of quantum mechanical events has no hidden causes such as photon emission. For example, the microcontroller core 16 can be an 8-bit microcontroller core or a 16-bit microcontroller core or a 32-bit microcontroller core or a 64-bit microcontroller core or a 128-bit microcontroller core, etc. The secure microcontroller 1 may include one or more 8 / 16 / 32 / 64 / 128-bit microcontroller cores 16, which can preferably access other sub-devices via one or more internal data buses 2. Preferably, the secure microcontroller 1 includes one or more data interfaces 17. For example, such a data interface can be one or more universal asynchronous receivers and transmitters (UARTs) to support high-speed serial data. Preferably, the secure microcontroller 1 includes one or more basic clock generators 21 (CLK), each of which preferably provides a basic clock 12 to one or more clock generator modules (clock drivers, CLK). Preferably, the basic clock generator 21 (CLK) is an oscillator. Preferably, the secure microcontroller 1 also comprises one or more power supply or Vcc circuits 23 with a voltage regulator, which provides the secure microcontroller 1 with an operating voltage. Preferably, the secure microcontroller 1 also comprises one or more grounding circuits 24 (i.e. a circuit inserted into the ground line or a "grounding" circuit, in the simplest case a line), which for example comprise reverse polarity protection and a protection circuit to prevent the potential of the semiconductor substrate from being manipulated. It is useful, for example, if one or more grounding circuits 24 have reverse polarity protection. It is useful, for example, if one or more grounding circuits 24 and / or one or more power supply or Vcc circuits 23 interact in such a way that the modulation of the power consumption and / or the internal resistance and / or the voltage drop between the supply voltage terminals of the secure microcontroller, at least temporarily, does not allow any conclusions to be drawn about the operating process and / or the state of the secure microcontroller.

[0139] In order to control other devices and / or communicate with other devices and / or monitor other devices, it is usually useful that the safety microcontroller has one or more input / output circuits 25, which are usually designed as digital inputs and / or digital outputs, which preferably can also present a three-state condition. The safety microcontroller 1 can include an analog-to-digital converter, which allows the safety microcontroller 1 to monitor internal analog values ​​such as operating voltages and external analog values. Possibly, the safety microcontroller 1 can be provided with a driver stage for driving an actuator, for example. The actuator can be a motor and / or other resistive and / or inductive and / or capacitive loads, etc. For example, such a driver stage can be a half-bridge and / or H-bridge, etc. It is also conceivable that it can be a power current source, for example for a lamp such as an LED, etc.

[0140] Therefore, the present invention (for example, referring to Figure 1 ) proposes a secure microcontroller 1 for controlling devices in a car, which comprises a semiconductor substrate. Preferably, the secure microcontroller 1 is manufactured using CMOS circuit technology or bipolar circuit technology or BiCMOS circuit technology. The secure microcontroller preferably comprises storage elements, one or more internal data buses 2, one or more 8 / 16 / 32 / 64-bit microcontroller cores 16, one or more data interfaces and one or more generators based on quantum processes 15. The one or more generators based on quantum processes 15 distinguish the secure microcontroller 1 proposed herein from the prior art, which is based on so-called true random number generators, which show a poor von Neumann entropy of the generated random numbers, which are accordingly "not very random".

[0141] The internal data bus 2 may include multiple data buses. The storage elements of the secure microcontroller 1 are typically connected to the internal data bus 2. The data interface is typically also connected to the internal data bus 2. One or more quantum process-based generators 15 are preferably also connected to the internal data bus 2. One or more microcontroller cores 16 are preferably also connected to the internal data bus 2. One or more quantum process-based generators 15 preferably and typically generate one or more random numbers at the request of the microcontroller core 16. These generators are characterized by particularly favorable entropy compared to the random numbers of the true random number generators of the prior art. Preferably, one or more microcontroller cores 16 use corresponding programs from one or more storage elements thereof and use one or more random numbers in the generated random numbers to generate one or more keys. Typically, one or more microcontroller cores 16 encrypt and / or decrypt data, and the microcontroller cores 16 typically use corresponding programs of the corresponding microcontroller cores 16, respectively derived from one or more storage elements thereof, and use corresponding keys in possible multiple keys to exchange the data with a device external to the secure microcontroller via one or more data interfaces. Typically, the semiconductor substrate substantially integrally includes all sub-devices of the secure microcontroller 1.

[0142] In a first further development of the secure microcontroller 1 (cf. Figure 1 ), the storage elements of the secure microcontroller 1 include one or more read / write memories RAM 3 and / or one or more writable non-volatile memories 4, in particular EEPROM memories 4, and / or flash memories 4 and / or OTP memories 4 and / or one or more read-only memories and / or one or more non-volatile manufacturer memories. For example, the one or more manufacturer memories may include one or more manufacturer ROMs 6 and / or one or more manufacturer EEPROMs and / or one or more manufacturer flash memories.

[0143] In a second further development, the manufacturer memory, in particular the manufacturer ROM 6 , comprises boot software to securely start the secure microcontroller.

[0144] In the third further development (ref. Figure 1 ), the secure microcontroller 1 includes a manufacturer memory firewall 8 between the manufacturer memory 6 and the internal bus 2, the firewall preventing access to the manufacturer memory without authentication.

[0145] In the fourth further development (ref. Figure 1 ), the secure microcontroller 1 comprises one or more of the following components: a basic clock generator 21 (CLK), a clock generator circuit 12, a reset circuit 22, a power supply or Vcc circuit 23 with a voltage regulator providing an operating voltage, a ground circuit 24, an input / output circuit 25 and one or more processing modules. The processing module communicates with the internal data bus 2 and therefore typically communicates with the microcontroller core 16. The processing module preferably comprises one or more of the following components: a CRC module (cyclic redundancy check) 11, a clock generator module 12, an encryption accelerator, in particular a DES accelerator and / or an AES accelerator 7, one or more timer modules 13, one or more security monitoring and control circuits 14, one or more data interfaces, in particular one or more universal asynchronous receiver transmitters (UARTs) 17 (cf. Figure 1 ).

[0146] In a fourth further development of the secure microcontroller 1 (cf. Figure 4 and Figure 5 ), the secure microcontroller 1 includes at least one first SPAD diode 44 and at least one second SPAD diode 45, at least one optical fiber 50, at least one processing circuit and at least one operating circuit. The circuit integration of the SPAD diode (e.g., SPAD diode 44 or 45) is again as shown in Figure 3 As shown. Figure 4 In a fourth further development, a generator based on a quantum process 15 (cf. Figure 1) comprises at least a first SPAD diode 44 as a source of a photon signal and a second SPAD diode 45 as a photodetector of the photon signal. In addition, in the fourth further development, the generator 15 based on the quantum process comprises at least a processing circuit and an optical fiber 50. In the fourth further development, at least one optical fiber 50 typically optically couples at least one first SPAD diode 44 with at least one second SPAD diode 45. The operating voltage supplies electrical energy to the first SPAD diode 44 so that the first SPAD diode 44 emits photons. This is the case when the first SPAD diode 44 has a sufficient electrical bias voltage. In the fourth further development, the processing circuit detects the (output) signal of the second SPAD diode 45 and forms a random number therefrom.

[0147] However, in Figure 4 In the exemplary embodiment of FIG. 5 , it is assumed that the optical fiber 50 is formed by an electrically insulating layer applied to the surface 46 of the semiconductor substrate. Figure 5 An exemplary embodiment is shown in which, for example, two optically transparent and electrically insulating insulating layers 34 ′, 34 ″ form an optical fiber 50 .

[0148] The processing circuitry then provides the random number thus formed to one or more of the one or more microcontroller cores 16 ( Figure 1 ). The following will combine Figures 6 to 9 The construction of the processing circuit is discussed.

[0149] In a sixth further development of the invention (cf. Figure 4 and Figure 5 ), the semiconductor substrate includes a surface 46. Typically, the semiconductor substrate includes semiconductor material below its surface 46. In particular, when conventional manufacturing processes for semiconductor circuits are used, such as CMOS processes, bipolar processes and BiCMOS processes, there is typically a metallization stack of structured metal layers on the surface 46 of the semiconductor substrate, and the metal layers have electrically insulating insulating layers thereon, wherein at least one of the insulating layers 34 at least partially or partially forms an optical fiber 50. The structured metal layers typically form conductive paths that are electrically separated from each other by the insulating layers. Thus, the metallization stack includes, for example, an optically transparent and electrically insulating layer 34 of a typical structure of silicon oxide located on the surface 46 of the semiconductor substrate. Preferably, at least a portion of the insulating layer 34 on the surface 46 of the semiconductor substrate (i.e., a portion of the insulating layer extending laterally and / or vertically) forms the optical fiber 50. At Figure 4 and Figure 5A portion of the metallization stack located above the insulating layer 34 is schematically shown in FIG. The first SPAD diode 44 typically emits light 47 from the semiconductor material of the semiconductor substrate into the optical fiber 50. This means that, compared to the prior art, the first SPAD diode 44 typically irradiates upward perpendicularly to the surface 46, rather than laterally to the semiconductor substrate with high attenuation. This allows the device to couple more photons of the first SPAD diode 44 directly to the second SPAD diode 45. The optical fiber 50 transmits the photons 48 of the first SPAD diode 44 in the optical fiber 50 to the second SPAD diode 45 with almost no losses compared to the prior art. The lowest layer of the metallization stack 43 is used to reflect light (photons). The optical fiber 50 illuminates the second SPAD diode 45 with the photons 48 of the first SPAD diode 44, so that the light 49 from the inside of the optical fiber 50 re-enters the semiconductor material of the semiconductor substrate from the surface 46 and hits the device components of the second SPAD diode 44 there. The second SPAD diode 45 then generates an output signal in response to the illumination by the photon 48 (of light 49 ), thereby generating a random number based on a quantum process, as will be further described below.

[0150] Typically, at least one operating circuit at least temporarily supplies electrical energy to at least one first SPAD diode 44. When sufficient electrical energy is supplied, at least one first SPAD diode 44 then feeds photons 47 into at least one optical fiber 50. The optical fiber 50 then further transmits the photons 48. The at least one optical fiber 50 then irradiates the photons 48 as photons 49 essentially “from above” into the second SPAD diode 45. Since this transmission of photons from the first SPAD diode 44 to the second SPAD diode 45 loses significantly fewer photons due to the low attenuation in the optical fiber 50 than the prior art structures using a strongly absorbing semiconductor substrate, the quantum efficiency is much higher. Therefore, in the structure proposed herein, a pair of a single first SPAD diode 44 and a single second SPAD diode 45 are sufficient (although multiple pairs of SPAD diodes can also be used according to the invention). The prior art always uses several SPAD diodes on both the transmitter and receiver sides.

[0151] Figure 5Two or more dielectric layers (i.e. optically transparent insulating layers 34', 34" which are directly adjacent to each other at least in certain areas (i.e. not separated by metallization layers in these areas) are shown forming an optical fiber 50'. In this exemplary embodiment, the contacts 51 and 52 of the SPAD diodes 44 and 45 are positioned so that they are arranged in pairs on both sides of a central area of ​​the optical fiber 50', so that the optical fiber transmits the photons 47 of the SPAD diode in the portion of the insulating layers 34', 34" adjacent to each other at the plane 53, as shown at 48, not necessarily only in the upper part of the two insulating layers 34', 34", but also through both, until they meet the SPAD diode 45 at 49. The contacts 51, 52 are also advantageously used to reflect the photons and thus "introduce" the photons into the SPAD diode 45. In this regard, the contacts 51, 52 of the SPAD diode 44 also serve to reflect and "redirect" the photons 47 emerging from the SPAD diode 44 in the direction of the SPAD diode 45.

[0152] In another further development of the safety microcontroller 1 according to the invention, at least one of the one or more data interfaces is a wired vehicle data bus interface. In this case, the wired vehicle data bus interface can be, for example, a CAN data bus interface or a CAN FD data bus interface or a Flexray data bus interface or a PSI5 data bus interface or a DSI3 data bus interface or a LIN data bus interface or an Ethernet data bus interface or a MELIBUS data bus interface.

[0153] In another further development of the secure microcontroller 1 according to the invention, at least one data interface is a wireless data bus interface. For example, the wireless data bus interface can be a WLAN interface or a Bluetooth interface.

[0154] In another further development of the safety microcontroller 1 according to the invention, at least one data interface is a wired data bus interface. For example, the wireless data bus interface can be a KNX data bus interface or an EIB data bus interface or a DALI data bus interface or a PROFUBUS data bus interface.

[0155] Figure 6 A simplified block diagram of a quantum-based random number generator QRNG400 according to an exemplary embodiment of the present invention is schematically shown. Preferably, Figure 6 The digital circuits of the exemplary device shown are clocked with a preferably universal clock. The structure includes an entropy source 401 based on a quantum process, a preferably wideband radio frequency amplifier 402, an analog-to-digital converter 403 with, for example, a 14-bit resolution and, for example, a 125MS / s sampling rate, and a field programmable gate array (FPGA) 404.

[0156] The entropy source 401 comprises a 2D array of single photon avalanche diodes (SPADs) 401.1 and 401.3. The SPAD diodes operate in Geiger mode with a supply voltage higher than the breakdown voltage. In addition, a quenching resistor 401.4 is connected in series with each SPAD diode. In the event of a charge carrier avalanche being triggered, the quenching resistor 401.4 prevents thermal destruction of the diode. The current signal of the SPAD diode is measured via a shunt resistor, which can be a quenching resistor or a resistor provided in addition thereto. Figure 6 In the example of FIG. 5 , the SPAD diode array consists of, for example, four (active or transmitter) SPAD diodes 401.1 and 12 (passive or receiver) SPAD diodes 401.3, which are coupled to the SPAD diodes 401.1 via optical waveguides 401.2, as described above with reference to the optical fiber 50. Figure 4 and Figure 5 The active SPAD diodes 401.1 emit light. They correspond to Figure 4 and Figure 5 The first SPAD diode 44 of the active SPAD diode 401.1 is preferably located inside the SPAD diode array. The proposed arrangement supplies an increased supply voltage to the active SPAD diode 401.1, thus effectively operating the active SPAD diode 401.1 above the breakdown voltage. This increases the dark count rate, resulting in a higher number of spontaneously emitted photons 47. The optical waveguide 401.2 forwards some of these photons as photons 48 to the passive SPAD diode 401.3. For example, the optical waveguide 401.2 is connected to the Figure 4 and Figure 5 For example, each passive SPAD diode 401.3 corresponds to the optical fiber 50. Figure 4 and Figure 5 The proposed device supplies an increased supply voltage to the passive SPAD diode 401.3 and operates the passive SPAD diode 401.3 slightly above the breakdown voltage. Preferably, the passive SPAD diode 401.3 is arranged as a ring around the active SPAD diode 401.2. The passive SPAD diode 401.3 detects photons arriving via the waveguide 401.2. Depending on the arriving photons, the passive SPAD diode 401.3 generates a current, for example, flowing through a shunt resistor, thereby generating a voltage signal.

[0157] The voltage signal 405 of the entropy source 401 is preferably fed to a broadband, for example, 40 dB high frequency amplifier 402. The high frequency amplifier 402 preferably has a bandwidth of 30 to 4000 MHz and preferably has a 1 dB compression point of 20 dBm. The voltage swing of the voltage signal 405 of the entropy source 401 is typically in the sub-millivolt range. The high frequency amplifier 402 amplifies the voltage swing of the voltage signal 405 of the entropy source 401 to, for example, 50 mV to 150 mV.

[0158] For example, the amplifier output signal 406 of the high frequency amplifier 402 is transferred to the FPGA 404 after analog-to-digital conversion in the ADC 403. Of course, other discrete or ASIC-based solutions are also possible. In this respect, the FPGA is only one of many different implementations of the technical teachings presented in this exemplary embodiment. The FPGA 404 preferably includes a microcontroller. For example, the FPGA 404 can be a Zynq7010 with a dual-core ARM Cortex-A9 MPCore from Xilinx. This is part of the SPAD evaluation circuit of this exemplary embodiment. In addition, in Figure 4 and Figure 5 In the example of the circuit, the circuit has, for example, a 14-bit ADC 403, an exemplary sampling rate of 125 megasamples / second and an exemplary bandwidth of 50 MHz. The amplified voltage signal is available as an amplifier output signal 406 at the input of the high-frequency amplifier 402. The ADC 403 samples the amplifier output signal 406 of the high-frequency amplifier 402. For example, the ADC 403 digitally transmits the determined samples of the amplifier output signal 406 of the high-frequency amplifier 402 to the built-in FPGA 404 of the measuring board with a bit width of, for example, 14 bits.

[0159] exist Figure 6 The device shown in a simplified manner as a block diagram in FIG. 4 comprises a comparator 404.2, a time-to-digital converter (TDC) 404.3, an entropy extraction device 404.4 and a finite state machine 404.8.

[0160] For example, the comparator 404.2 compares the 14-bit digital value 407 of the ADC 403 with a reference value 404.1 representing a threshold value and generates a 1-bit output pulse of two clock lengths as an output signal 409 of the comparator 404.2 if the value at the output of the ADC 403 is greater than the reference value 404.1. The output signal 409 of the comparator 404.2 is fed to the time digital converter 404.3. The time digital converter 404.3 preferably has a 32-bit counter, which counts in time using a SPAD evaluation circuit, for example. The bit width of the counter can vary depending on the application. For example, the frequency of the clock can be 125 MHz. The 1-bit output signal of the comparator 404.2 preferably resets the counter reading of the counter. The time digital converter 404.3 transmits the counter reading present at this time (i.e. the counter reading present immediately before the reset) to its output 410. For an exemplary 125 MHz clock, the resolution of the counting result is 1 / 125 MHz=8 ns. The output 410 of the time digital converter (TDC) 404.3 delivers an exemplary 32-bit count result (also referred to as raw data RD) of the time digital converter 404.3 to an entropy extraction device 404.4. The entropy extraction device 404.4 converts the raw data RD of the TDC 404.3 of the signal of the output 410 of the time digital converter (TDC) 404.3 into a 1-bit random number RN 411 at the output of the entropy extraction device 404, the raw data RD being random with respect to its composition and sequence. The output 411 of the entropy extraction device 404.4 is connected to the input of a finite state machine (FSM) 404.8.

[0161] FSM 404.8 has the task of receiving data from entropy extraction device 404.4 and generating QRNG random numbers therefrom, which FSM 404.8 stores in memory RAM 404.9 of FPGA 404. After a successful write operation, FSM 404.8 sets completion flag 404.10. Completion flag 404.10 is not set at system startup. Microcontroller 404.11, for example a dual-core Arm Cortex-A9 MPCore, accesses RAM 404.9 block and reads random numbers from RAM 404.9. Microcontroller 404.11 is therefore, for example, a microcontroller core according to the present invention.

[0162] Figure 7 An extended exemplary FPGA design is shown which monitors a signal for a random number RN at the output 411 of the entropy extraction device 404.4 and includes an additional backup system in case potential errors occur during the generation of QRNG-based random numbers.

[0163] according to Figure 7Expansion of the arrangement involves the addition of a watchdog 404.5, a linear feedback shift register 404.6 as an example of a PRN generator, a signal multiplexer 404.7 and a voltage monitor 413. A microcontroller 404.11 can also be configured externally together with these components.

[0164] The output 411 of the entropy extraction device 404.4 is now connected to the watchdog 404.5 and the signal multiplexer 404.7. The watchdog 404.5 monitors the validity of the 1-bit random number RN at the output 411 of the entropy extraction device 404.4. The watchdog 404.5 detects at least three defined error conditions. For example, the watchdog 404.5 sends the last valid random number as a seed S output signal 412 to the linear feedback shift register 404.6. If an error occurs, the watchdog sets the error bit in the undrawn error register ER of the microcontroller 404.11. Which error bit the watchdog 404.5 sets in the error register of the microcontroller 404.11 preferably depends on the type of error. In addition, the watchdog 404.5 is connected to the voltage monitor 413 via one or more preferably digital input-output signal lines 414.

[0165] For example, the voltage monitor 413 monitors the operating voltage of the entropy source 401. If the operating voltage of one of the circuits of the SPAD diodes 401.1 and 401.3 is too low, i.e., the amount is below the lower SPAD operating voltage threshold, or too high, i.e., the amount is above the higher SPAD operating voltage threshold, the voltage monitor 413 detects this voltage deviation. In the case of such a voltage deviation, the voltage monitor 413 sends this signal to the watchdog 404.5 or directly to the microcontroller 404.11. For example, in the case of sending a signal to the watchdog 404.5, the watchdog 404.5 can generate an interrupt signal for the microcontroller 404.11. For example, if the power supply voltage of another device part of the entropy source 401 or the radio frequency amplifier 402 or the quantum random number generator QRNG 400 fails, the watchdog 404.5 can trigger such an interrupt of the microcontroller 404.11 or other sub-devices of the application system.

[0166] If the watchdog 404.5 detects an error, the quantum random number generator 400 switches to an emergency state. To this end, the watchdog 404.5 sets the selection signal 416 of the signal multiplexer 404.7 so that the signal multiplexer 404.7 applies the pseudo-random number PRN generated by the linear feedback shift register 404.6 to the input of the FSM 404.8 in the form of a pseudo-random bit stream via the pseudo-random number signal line 417 instead of the output 411 of the entropy extraction device 404.4 as a substitute for the potentially erroneous 1-bit random number RN appearing at the output 411 of the entropy extraction device 404.4.

[0167] The linear feedback shift register 404.6 is connected to the output 412 of the watchdog 404.5 and receives its seed S output signal 412 therefrom. In the event of an error, the watchdog 404.5 activates the linear feedback shift register 404.6 (cf. connection 418). The linear feedback shift register 404.6 then generates a pseudo-random number PRN. The seed S of the watchdog output signal 412 preferably comprises the last, for example, still valid 16 random numbers (for example, 1 bit each). The watchdog 404.5 preferably applies said last valid random number to the input of the linear feedback shift register 404.6. The seed S is thus used as a random PQC-safe initial value for the generator polynomial of the feedback of the linear feedback shift register 404.6 for generating the pseudo-random number PRN for the pseudo-random signal line 417. The generator polynomial and the degree of the generator polynomial are preferably freely selectable.

[0168] The signal of the output 411 of the entropy extraction device 404.4 with the 1-bit random number RN and the signal of the pseudo-random signal line 417 of the linear feedback shift register 404.6 with the pseudo-random number PRN are connected to the input of the signal multiplexer 404.7, respectively. The signal multiplexer 404.7 forwards one of its two input signals to the FSM 404.8 according to the value SEL of the selection signal 416. If the application requires, it is conceivable to use a multiplexer with more than two inputs and more complex control signals. Therefore, the number of inputs of the signal multiplexer 404.7 is usually greater than or equal to two.

[0169] The FSM 404.8 in turn has the task of receiving the random number RN or pseudo-random number PRN from the output of the signal multiplexer 404.7 and writing them to the memory RAM 404.9 of the FPGA 404. If the writing process is successful, the FSM 404.8 sets the completion flag 404.10 again. The microcontroller 404.11 can then access the memory 404.9 RAM and read the random number and use it for example for encryption, authentication, signature, etc.

[0170] Figure 8 For example, it is shown that Figure 6 and Figure 7Flowchart 500 of an entropy extraction method performed by an entropy extraction device 404.4 of a QRNG 400. The method provides in a first step 501 that two values ​​of the output 410 of the time-to-digital converter 404.3 are first determined and stored in a shift register of the entropy extraction device 404.4. If two values ​​are stored in the shift register of the entropy extraction device 404.4, the entropy extraction device 404.4 compares the two values ​​in a second step 502. The two values ​​in the shift register of the entropy extraction device 404.4 thus comprise a first value and a second value, both of which are determined by the time-to-digital converter 404 by two different measurements of the corresponding period between two signal pulses above the reference value 404.1. In a third step 503, the entropy extraction device 404.4 evaluates the two values. If the first value is less than the second value and the difference between value 1 and value 2 is greater than a minimum difference ∈, the entropy extraction device 404.4 sets the value of its output 411 to a first logic value. If the first value is greater than the second value, and the difference between the first value and the second value is greater than the minimum difference ∈, the entropy extraction device 404.4 sets its output to a second logic value different from the first logic value.

[0171] If the difference between the first value and the second value is less than the minimum difference ∈, the entropy extraction discards the first value and the second value. In this case, the entropy extraction method preferably enables the watchdog (in Figure 7 ) increases the error counter by a first error counter increment. The first error counter increment may be negative. Conversely, if the difference between the first value and the second value is greater than the minimum difference ∈, the entropy extraction device 404.4 may reduce the error counter of the watchdog by a second error counter increment. The second error counter increment may be the same as the first error counter increment. Typically, the signs of the first error counter increment and the second error counter increment are the same. Preferably, the microcontroller 404.11 may set the error counter increment as well as the initial value of the error counter and the error counter threshold. If the count reading of the error counter exceeds the error counter threshold, the watchdog 404.5 preferably signals the occurrence of a critical error state by interrupting or sending another signal to the microcontroller. The microcontroller 404.11 then typically initiates a self-test routine to test the error counter according to Figure 7 The various parts of the quantum random number generator 400 of the embodiment of the present invention. Preferably, the microcontroller can, for example, set the analog-to-digital converter 403 to a state in which the microcontroller 404.11 can write a test value to the output register of the analog-to-digital converter, and the subsequent signal chain then processes the test value like a real sampled value. Since the test value is known in advance, the correct reaction of the rest of the system, such as the increase of the error counter in the watchdog 404.5, can be monitored and evaluated by the microcontroller 404.11. Preferably, the microcontroller 404.11 can therefore monitor all storage nodes of the FPGA 404 and read their logical states.

[0172] If the value is less than the minimum value, it is a value within the dead time of the SPAD diode. Such a value is preferably discarded and the error counter is increased by the first error increment. In this case, the entropy extraction device 404.4 waits for the time digital converter 404.3 to determine the next value.

[0173] Once the random bits have been extracted in this way, the method starts over again from the beginning.

[0174] For example, if the error counter exceeds or reaches the error counter threshold, there may be an error in the time-to-digital converter providing a constant number.

[0175] Thus, the device is able to detect a malfunction of the power supply of the entropy source or other parts of the device. The microcontroller 404.11 can also record the voltage and current in the ADC 403 and the quantum random number generator 400 for test purposes, and compare the values ​​determined in this way with the expected value range in which these values ​​must be located. The microcontroller 404.11 can also record digital values ​​within the quantum random number generator 400. For example, for test purposes, the microcontroller 404.11 can set the reference value 404.1 so low that the time digital converter 404.3 is essentially controlled by the signal noise at its input. Then, the value of the time digital converter 404.3 should meet the expected statistics within the tolerance range. If this is not the case, there is an error.

[0176] The watchdog 404.5 can monitor the entropy of the random numbers provided. If the average entropy of the bits during the entropy measurement period deviates by more than a permissible entropy deviation value of, for example, 50%, the watchdog concludes that an error has occurred and increments an error counter. Preferably, the watchdog then stops using these random bits at the output 411 of the entropy extraction device 404.4 to prevent the sending of plain text. "Plain text" refers to information that can be understood by a third party using statistical methods or directly due to poor encryption of the information. It is conceivable that even with a properly functioning sub-device, logical "permanent ones" or logical "permanent zeros" can be generated randomly. Therefore, it makes sense if the maximum length of the bit sequence at the output of the entropy extraction device is limited to a value that can be programmed by the microcontroller 404.11.

[0177] Basically, the quantum random number generator 400 as described above can therefore identify the following errors and catch them at a lower security level via emergency mode using the linear feedback shift register 404.6 or another PRN generator:

[0178] - Supply voltage failure,

[0179] - generation of erroneous signals by SPAD diodes 401.1 and 401.3,

[0180] - a coupling failure of the optical fiber 401.2 and / or the SPAD diodes 401.1 and 401.3 to the optical fiber 401.2,

[0181] - a circuit failure in the FPGA 404 (i.e., the digital portion of the quantum random number generator 400),

[0182] - the error entropy of the provided random numbers, which can be done by testing the 1-bit random number RN, as described in David Johnston, Random Number Generators – Principles and Practices, 2018, Chapters 8 and 9, Walter De Gruyter GmbH, Berlin / Bonston, ISBN 978-1-5015-1530-2.

[0183] It is conceivable to use a second fully quantum random number generator 400 instead of the linear feedback shift register 404 . 6 , the signal at the output of its entropy extraction device 404 . 4 then being used for the emergency mode instead of the signal of the pseudo-random signal line 417 .

[0184] Fig. 9 An exemplary oscillogram of the voltage signal 405 at the output of the entropy source 401 is shown. It can be seen that a first peak occurs at a first height level 601 and a second peak occurs at a second height level 602. The scattering of the first height level 601 of the first peak and the scattering of the second height level of the second peak are in each case so small that the two height levels 601, 602 can be clearly separated by a cut level 603. The cut level 603 corresponds to the value set by the microcontroller 404.11 to the reference value 404.1. For the first and second peaks (second peaks) formed due to the simultaneous occurrence of spontaneous and stimulated photon emission of the second SPAD diode or one of the second SPAD diodes, as well as the first and second peaks (first peaks) formed only due to spontaneous photon emission of the second SPAD diode or one of the second SPAD diodes, please refer to the above description in the test.

[0185] Fig.10The proposed method 3700 for generating quantum random numbers is schematically shown. The method 3700 starts at 3710: generating a random single photon current (47, 48, 49, 401.2) by one or more first SPAD diodes (401.1, 44). The method 3700 continues at 3720: transmitting the random single photon current (47, 48, 49, 401.2) to one or more second SPAD diodes (401.3, 45) through an optical fiber (44, 401.2) different from the semiconductor substrate (49, 48). Next is 3730: converting the random single photon current (47, 48, 49, 401.2) into a detection signal in the form of a voltage signal 405 of an entropy source 401, which preferably includes a first SPAD diode 401.1 and an optical fiber 401.2 and a second SPAD diode 401.3. Next is 3740: conditioning the detection signal, in particular amplifying and / or filtering and / or converting the detection signal into a conditioned detection signal, in particular a 14-bit digital value 407 of the analog-to-digital converter 403. Then 3750: comparing the conditioned detection signal with a threshold, in particular in a comparator (cf. Figure 6 and Figure 7 404.2 in the embodiment of the present invention, separate the pulses of the conditioned detection signal generated by coupling the emission of the first SPAD diode 401.1 and the second SPAD diode 401.3 from the pulses of the conditioned detection signal generated only by spontaneous emission, and generate a corresponding output signal 409 of the comparator 404.2 in particular. Next is 3760: determine a first time interval between a first pulse and a second pulse of a first pair of two consecutive photons generated by coupling of the spontaneous photon emission of the first SPAD diode 401.1 and the photon emission of the second SPAD diode 401.3 excited by the photon emission, and determine a second time interval between a third pulse and a fourth pulse of a second pair of two consecutive pulses of the conditioned detection signal generated by the same type of coupling of the emission of the first SPAD diode 401.1 and the second SPAD diode 401.3, in particular for determining a first value of the output 410 of the time digital converter 404.3 and a second value of the output 410 of the time digital converter 404.3. Then 3670: determine the bit value of the random bit on this basis by comparing the value of the first time interval with the value of the second time interval. The last step 3680 is to check whether the number of random bits n determined is still less than the number of random bits m of the desired quantum random number. If not, the above steps are repeated. Otherwise, the process of generating a quantum random number is completed.

[0186] Advantages

[0187] The secure microcontroller proposed herein has improved entropy of at least one of its random number generators. Thus, the encryption that can be achieved using the microcontroller is more efficient and also post-quantum secure compared to the prior art. However, the advantages of the present invention are not limited thereto.

[0188] The above description is not claimed to be exhaustive and is not limited to the examples shown. Other variations of the examples described herein may be understood and practiced by those of ordinary skill in the art with reference to the drawings, the specification and the claims. The indefinite singular article "a" does not exclude pluralities, and the mention of a certain number of elements does not exclude the possibility of more or fewer elements. A single unit may perform the functions of several elements mentioned in the description, and vice versa, several elements may perform the functions of one unit. Many alternatives, equivalents, variations and combinations are possible without departing from the scope of the present application.

[0189] Unless otherwise stated, all features of the invention can be freely combined with one another. This applies to the entire application presented herein. Unless otherwise stated, the features described in the figure description can also be freely combined with other features that are characteristic of the invention. There is no explicit provision to restrict individual features of the exemplary embodiment to a combination with other features of the exemplary embodiment. In addition, device features of the device can also be restated as method features, and method features can be restated as device characteristics of the device. Such restatements are therefore also automatically disclosed.

[0190] In the foregoing detailed description, reference is made to the accompanying drawings. The examples in the description and drawings are to be regarded as illustrative and are not to be regarded as limiting the specific examples or elements described. Some examples may be derived from the foregoing description and / or drawings and / or claims by deforming, combining or changing certain elements. In addition, a person skilled in the art may derive from the description and / or drawings examples or elements not literally described.

[0191] The invention has been described above with reference to a microcontroller for automotive applications. However, it is clear to a person skilled in the art that the intended use in this regard is not limited based on the disclosure in the patent application giving rise to priority and in the present PCT application. On the contrary, the microcontroller according to the invention can be used in all devices involving PQK secure encryption and / or PQR signing of data and the editing and processing of security-related data. PQR encryption can preferably be performed using one of the following methods:

[0192] BIKE1-L1-CPA, BIKE1-L3-CPA, BIKE1-L1-FO, BIKE1-L3-FO, Kyber512, Kyber768, Kyber1024, Kyber512-90s, Ky ber768-90s, Kyber1024-90s, LEDAcryptKEM-LT12, LEDAcrypt-KEM-LT32, LEDAcryptKEM-LT52, NewHope-512-C CA, NewHope-1024-CCA, NTRU-HPS-2048-509, NTRU-HPS-2048-677, NTRU-HPS-4096-821, NTRU-HRSS-701, Light Saber-KEM, Saber-KEM, FireSaber-KEM, BabyBear, BabyBearEphem, Mama-Bear, MamaBearEphem, PapaBear, Pap aBearEphem, FrodoKEM-640-AES, FrodoKEM-640-SHAKE, FrodoKEM-976-AES, FrodoKEM-976-SHAKE, FrodoKEM-1 344-AES, FrodoKEM-1344-SHAKE, SIDH-p434, SIDH-p503, SIDH-p610, SIDH-p751, SIDH-P434-compressed, SIDH -P503-compressed, SIDH-P610-compressed, SIDH-P751-compressed, SIKE-P434', SIKE-P503, SIKE-P610', 'SIKE-P751, SIKE-P434-compressed, SIKE-P503-compressed, SIKE-P610-compressed, SIKE-P751-compressed.

[0193] Preferably one of the following methods may be used to create a PQR signature:

[0194] DILITHIUM_2、DILITHIUM_3、DILITHIUM_4、MQDSS-31-48、MQDSS-31-64、SPHINCS+-Haraka-128f-robust、SPHINCS+-Haraka-128f-simple、SPHINCS+-Haraka-128s-robust、SPHINCS+-Haraka-128s-simple、SPHINCS+-Haraka-192f-robust、SPHINCS+-Haraka-192f-simple、SPHINCS+-Haraka-192s-robust、SPHINCS+-Haraka-192s-simple、SPHINCS+-Haraka-256f-robust、SPHINCS+-Haraka-256f-simple、SPHINCS+-Haraka-256s-robust、'SPHINCS+-Haraka-256s-simple、SPHINCS+-SHA256-128f-robust、SPHINCS+-SHA256-128f-simple、SPHINCS+-SHA256-128s-robust、SPHINCS+-SHA256-128s-simple、SPHINCS+-SHA256-192f-robust、SPHINCS+-SHA256-192f-simple、SPHINCS+-SHA256-192s-robust、SPHINCS+-SHA256-192s-simple、SPHINCS+-SHA256-256f-robust、SPHINCS+-SHA256-256f-simple、SPHINCS+-SHA256-256s-robust、SPHINCS+-SHA256-256s-simple、SPHINCS+-SHAKE256-128f-robust、SPHINCS+-SHAKE256-128f-simple、SPHINCS+-SHAKE256-128s-robust、SPHINCS+-SHAKE256-128s-simple、SPHINCS+-SHAKE256-192f-robust、SPHINCS+-SHAKE256-192fsimple、SPHINCS+-SHAKE256-192s-robust、SPHINCS+-SHAKE256-192s-simple、SPHINCS+-SHAKE256-256f-robust、SPHINCS+-SHAKE256-256fsimple、SPHINCS+-SHAKE256-256s-robust、SPHINCS+-SHAKE256-256s-simple、picnic_L1_FS、 picnic_L1_UR, picnic_L3_FS, picnic_L3_UR, picnic_L5_FS, picnic_L5_UR, 'picnic2_L1_FS', picnic2_L3_FS, picnic2_L5_FS, qTesla-pI, qTesla-p-III'. ,

[0195] For example, the concept according to the invention can be used to generate addresses in communication bus systems with automatic addressing of users by the bus master in the bus master or in the user to be addressed. Thus, the invention can be used not only for cryptographic techniques for generating PQK security codes. PQK stands for "post-quantum cryptography" and refers to a subfield of cryptography, i.e. quantum computer-resistant cryptography, which, unlike most asymmetric cryptographic systems currently in use, deals with cryptographic primitives that are virtually impossible to decrypt even with a quantum computer (see definition in Wikipedia). Different codes can also be used to better distinguish signals emitted by systems of essentially any design in order to separate these signals and to separate these signals from neighboring systems that may interfere with each other in terms of signal technology. For example, if you think of ultrasonic measuring devices in the automotive industry, it may be advantageous to make the individual received signals distinguishable with respect to their source, i.e. the transmitting transmitter from which the signal originates.

[0196] Features of the Invention

[0197] The following list of the present invention summarizes the features of the present invention and its further development again. The application of technical teaching can combine features with each other, provided that these combinations do not cause factual contradictions. In this regard, the dependencies and references given herein represent only particularly preferred exemplary embodiments.

[0198] 1) A secure microcontroller for controlling a device in a car 1

[0199] - comprises a semiconductor substrate, and

[0200] - comprises a storage element, and

[0201] - comprises at least one internal bus 2, and

[0202] - includes at least one 8 / 16 / 32 / 64-bit microcontroller core 16, and

[0203] - includes one or more data interfaces, and

[0204] - comprises at least one generator 15 based on a quantum process, and

[0205] - wherein the storage element is connected to the internal bus 2, and

[0206] - wherein the data interface is connected to the internal bus 2, and

[0207] - wherein the generator 15 based on quantum processes is connected to the internal bus 2, and

[0208] - wherein the microcontroller core 16 is connected to the internal bus 2, and

[0209] - wherein the generator 15 based on a quantum process generates random numbers at the request of the microcontroller core 16, and

[0210] - wherein the microcontroller core 16 generates a key using a program from one or more of its memory elements and using the random number, and

[0211] - wherein the microcontroller core 16 uses a program from one or more of its storage elements and the key to encrypt and decrypt data it exchanges with devices external to the secure microcontroller, and

[0212] - wherein the semiconductor substrate integrally comprises a sub-device of the secure microcontroller 1,

[0213] The sub-devices of the secure microcontroller 1 include storage elements, an internal bus 2 , at least one 8 / 16 / 32 / 64-bit microcontroller core 16 , a data interface and a generator 15 based on quantum processes.

[0214] 2) The secure microcontroller 1 according to item 1),

[0215] - wherein the storage elements comprise one or more read / write memories RAM 3 and / or one or more writable non-volatile memories, in particular EEPROM memories 4 and / or Flash memories 4 and / or OTP memories 4, and / or one or more read-only memories and / or one or more non-volatile manufacturer memories, in particular one or more manufacturer ROMs 6, and / or one or more manufacturer EEPROMs and / or one or more manufacturer Flash memories.

[0216] 3) The secure microcontroller 1 according to item 2),

[0217] - wherein said manufacturer ROM 6 comprises boot software.

[0218] 4) The secure microcontroller 1 according to item 2) or item 3),

[0219] A manufacturer firewall 8 is provided between the manufacturer memory 6 and the internal bus 2 .

[0220] 5) A secure microcontroller 1 according to one or more of items 1) to 4),

[0221] - Includes one or more of the following components:

[0222] - basic clock generator 21 (CLK),

[0223] - a clock generator circuit 12, and / or

[0224] - a reset circuit 22, and / or

[0225] - a power supply or Vcc circuit 23 having a voltage regulator providing an operating voltage, and / or

[0226] - a ground circuit 24, and / or

[0227] - input / output circuit 25, and / or

[0228] - one or more processing modules,

[0229] - wherein the processing module is in communication with the internal bus 2, and

[0230] -Wherein the processing module comprises one or more of the following modules:

[0231] -CRC module (cyclic redundancy check) 11,

[0232] - a clock generator module 12,

[0233] - comprising a DES accelerator and / or an AES accelerator 7,

[0234] - one or more timer modules 13,

[0235] - Safety monitoring and control circuit 14,

[0236] - a data interface, in particular a Universal Asynchronous Receiver / Transmitter (UART) 17 .

[0237] 6) A secure microcontroller 1 according to one or more of items 1) to 5),

[0238] - comprises at least one first SPAD diode 44, and

[0239] - comprises at least one second SPAD diode 45, and

[0240] - comprises at least one optical fiber 50, and

[0241] - comprises at least one processing circuit, and

[0242] - comprises at least one operating circuit,

[0243] - wherein the generator 15 based on quantum processes comprises at least the first SPAD diode 44 as a light source of optical quantum signals, and

[0244] - wherein the generator 15 based on quantum processes comprises at least the second SPAD diode 45 as a photodetector of light quantum signals, and

[0245] - wherein said quantum process based generator 15 comprises at least said processing circuit, and

[0246] - wherein the generator 15 based on quantum processes comprises at least an optical fiber, and

[0247] wherein the at least one optical fiber 50 optically couples the at least one first SPAD diode 44 with the at least one second SPAD diode 45, and

[0248] - wherein the operating circuit supplies electrical energy to the first SPAD diode 44 so that the first SPAD diode emits light 44, and

[0249] wherein the processing circuit detects the signal of the second SPAD diode 45 and forms a random number therefrom and supplies the latter to the microcontroller core 16 .

[0250] 7) The secure microcontroller 1 according to item 6),

[0251] - wherein the semiconductor substrate comprises a surface 46, and

[0252] - wherein the semiconductor substrate comprises semiconductor material below its surface 46, and

[0253] - wherein said surface 46 of said semiconductor substrate comprises a metallization stack, and

[0254] - wherein the metallization stack comprises an optically transparent and electrically insulating layer 34 of typical structure, and

[0255] - wherein at least a portion of the transparent and electrically insulating layer of said typical structure of said surface 46 forms said optical fiber 50, and

[0256] - wherein the first SPAD diode 44 shines from the semiconductor material of the semiconductor substrate into the optical fiber 50, and

[0257] wherein the optical fiber illuminates the second SPAD diode 44 , so that light from inside the optical fiber 50 re-enters the semiconductor material of the semiconductor substrate from the surface and strikes device components of the second SPAD diode 44 there.

[0258] 8) The secure microcontroller 1 according to item 6) and / or item 7),

[0259] - wherein at least one operating circuit at least temporarily supplies electrical energy to the at least one first SPAD diode 44, and

[0260] - wherein the at least one first SPAD diode 44 feeds photons into the at least one optical fiber 50 when supplied with sufficient electrical energy, and

[0261] wherein the at least one optical fiber 50 emits such photons to the second SPAD diode 45 .

[0262] 9) A secure microcontroller 1 according to one or more of the preceding items,

[0263] - wherein the data interface of the one or more data interfaces is a wired vehicle data bus interface, and

[0264] - wherein the wired vehicle data bus interface comprises in particular:

[0265] -CAN data bus interface, and / or

[0266] -CAN FD data bus interface, and / or

[0267] -Flexray data bus interface, and / or

[0268] -PSI5 data bus interface, and / or

[0269] -DSI3 data bus interface, and / or

[0270] -LIN data bus interface, and / or

[0271] - Ethernet data bus interface, and / or

[0272] -MELIBUS data bus interface.

[0273] 10) A secure microcontroller 1 according to one or more of the preceding items,

[0274] - wherein the data interface of the one or more data interfaces is a wireless data bus interface, and

[0275] - wherein the wireless data bus interface comprises in particular:

[0276] - WLAN interface, and / or

[0277] -Bluetooth interface.

[0278] 11) A secure microcontroller 1 according to one or more of the preceding items,

[0279] - wherein a data interface of the one or more data interfaces is a wired data bus interface, and

[0280] - wherein the wireless data bus interface comprises in particular

[0281] - KNX data bus interface, and / or

[0282] -EIB data bus interface, and / or

[0283] -DALI data bus interface, and / or

[0284] -PROFIBUS data bus interface.

[0285] 12) A device

[0286] - wherein the device comprises an integrated circuit 4 having a first processor 10-1 and a non-volatile memory 16, and

[0287] - wherein the device comprises a first memory,

[0288] - wherein the non-volatile memory stores at least one security code,

[0289] - said first memory stores data thereon, and

[0290] - wherein the data in the first memory is encrypted and protected in a first format, and

[0291] - wherein the integrated circuit is configured to verify data read from the first memory during the transfer of data from the first memory, and

[0292] - wherein the device comprises a quantum random number generator 28, and

[0293] - wherein the integrated circuit and the quantum random number generator 28 are manufactured in a semiconductor crystal, and

[0294] - wherein the semiconductor crystal has a surface 46, and

[0295] - wherein the semiconductor crystal comprises semiconductor material below its surface 46, and

[0296] - wherein the surface 46 of the semiconductor crystal comprises a metallization stack, and

[0297] - wherein the metallization stack comprises an optically transparent and electrically insulating layer 34 of typical structure, and

[0298] - wherein at least a portion of the transparent and electrically insulating layer 34 of said typical structure of the surface 46 forms an optical fiber 50, and

[0299] - wherein the first SPAD diode 44 radiates photons 47 from the semiconductor material of the semiconductor substrate into the optical fiber 50, and

[0300] wherein the at least one optical fiber 50 transmits such photons 48 to the second SPAD diode 45, and

[0301] wherein the optical fiber 50 illuminates the second SPAD diode 45 so that light 49 from inside the optical fiber 50 re-enters the semiconductor material of the semiconductor substrate from the surface 46 and hits the device portion of the second SPAD diode 45, and

[0302] wherein the first SPAD diode 44 and the second SPAD diode 45 and the optical fiber 50 are part of the quantum random number generator 28 .

[0303] 13) The device according to item 12),

[0304] - wherein the device comprises at least one operating circuit, and

[0305] - wherein the at least one operating circuit at least temporarily supplies electrical energy to the at least one first SPAD diode 44, and

[0306] - wherein the at least one first SPAD diode 44 feeds photons 47 into the at least one optical fiber 50 when supplied with sufficient electrical energy, and

[0307] wherein the at least one optical fiber 50 transmits such photons 48 to the second SPAD diode 45, and

[0308] wherein the at least one optical fiber 50 emits such photons 49 to the second SPAD diode 45 .

[0309] 14) The device according to item 13),

[0310] - wherein the quantum random number generator 28 comprises at least the first SPAD diode 44 as a light source of the optical quantum signal, and

[0311] - wherein the quantum random number generator 28 comprises at least the second SPAD diode 45 as a photodetector of the optical quantum signal, and

[0312] - wherein the quantum random number generator 28 comprises at least one processing circuit, and

[0313] - wherein the quantum random number generator 28 comprises at least an optical fiber 50, and

[0314] wherein the at least one optical fiber 50 optically couples the at least one first SPAD diode 44 with the at least one second SPAD diode 45, and

[0315] - wherein the operating circuit supplies electrical energy to the first SPAD diode 44 so that the first SPAD diode emits light 44, and

[0316] - wherein the processing circuit detects the signal of the second SPAD diode 45 and forms the random number therefrom and supplies the latter to the data processor 10 or other device components.

[0317] 15) A device according to any one of items 12) to 14),

[0318] - wherein the first memory is external to the integrated circuit, and

[0319] - wherein the device comprises a second memory for storing data, and

[0320] - wherein the first memory is external to the integrated circuit;

[0321] - wherein the device is constructed as

[0322] - transferring data from the first memory to the second memory via the integrated circuit for access by the data processor from the second memory, and

[0323] - wherein the integrated circuit is constructed as

[0324] - verifying data read from said first memory during the transfer of data from said first memory to said second memory using a security code stored in a non-volatile memory, and

[0325] - if the data is verified, applying cryptographic protection to the verified data in a second format using a security code stored in the non-volatile memory, and

[0326] - storing data protected in said second format in said second memory.

[0327] 16) An apparatus according to any one of items 12) to 15), wherein the first memory comprises a read-only memory.

[0328] 17) An apparatus according to any one of items 15) to 16), wherein the second memory comprises a random access memory.

[0329] 18) An apparatus according to any one of items 15) to 17), wherein the password protection applied to the data in the first memory is different from the password protection applied to the data in the second memory.

[0330] 19) A device according to any one of items 12) to 18),

[0331] - wherein the integrated circuit comprises a memory for storing data to be processed by the data processor, and

[0332] - wherein the apparatus is configured to store some data of the verified dataset in the memory and to store the remaining data in the second memory.

[0333] 20) An apparatus according to any one of items 15) to 19), wherein the first memory stores data in a first data format and the second memory is arranged to store data in a different second data format.

[0334] 21) The device according to item 20),

[0335] - wherein the data stored in the first memory is protected by a first authentication technique, and

[0336] - wherein the device is configured to protect data in the second memory by a second, different authentication technique.

[0337] 22) A device according to any one of items 15) to 21),

[0338] - wherein the data in the first memory is stored in at least one data set, and the or each data set as a set is encrypted and protected, and

[0339] - wherein the device is designed to store words or word groups of the verified data set in the second memory, wherein each word or word group is individually cryptographically protected.

[0340] 23) The device according to item 22) is constructed as follows

[0341] - reading said word or words from said second memory, and

[0342] - verifying the read word or words by using a security code stored in said non-volatile memory, and

[0343] - Processing the read and verified word or word groups in said data processor.

[0344] 24) The device according to item 23),

[0345] - wherein the integrated circuit comprises a hash calculator, and

[0346] - wherein the data processor and the hash calculator are arranged such that they

[0347] -a) calculating a hash function of each word or each word group according to the security code stored in the non-volatile memory, and storing the hash in the second memory in association with the word or the word group,

[0348] -b) retrieving a stored word or group of words from said second memory, recalculating the hash function of the retrieved word or group of words by using the security code and comparing the newly calculated hash with the stored hash, and

[0349] -c) allowing the retrieved word or word groups to be processed by the data processing system only if the newly calculated and stored hashes have a specific relationship to each other.

[0350] 25) An apparatus according to item 24), wherein the hash calculator is a circuit in the integrated circuit.

[0351] 26) An apparatus according to any one of items 12) to 25), wherein the non-volatile memory of the integrated circuit is a one-time programmable memory.

[0352] 27) An apparatus according to any one of items 12) to 26), wherein the data set or each data set stored in the first memory is encrypted and protected by a corresponding digital signature.

[0353] 28) An apparatus according to any one of items 12) to 28), wherein the data set or each data set stored in the first memory is encrypted and protected by a corresponding digital signature with the aid of at least one random number in the quantum random number generator.

[0354] 29) A device according to item 27) or item 28), wherein a security code is stored in the non-volatile memory of the integrated circuit, and the security code has been generated by the device at least in part by at least one random number of the quantum random number generator (28).

[0355] 30) A device according to any one of items 27) to 29), wherein the device is constructed to verify the digital signature of the data set by referring to a security code stored in the non-volatile memory of the integrated circuit or the security code.

[0356] 31) A data processing device,

[0357] - wherein the data processing means comprises an integrated circuit, and

[0358] - wherein the integrated circuit comprises a data processor, and

[0359] - wherein the integrated circuit comprises a non-volatile memory, and

[0360] - wherein the non-volatile memory stores at least one security code, and

[0361] - wherein the integrated circuit comprises a hash calculator, and

[0362] - wherein the integrated circuit has an interface at a boundary of the integrated circuit, and

[0363] - wherein the integrated circuit comprises a quantum random number generator, and

[0364] - wherein the integrated circuit and the quantum random number generator are fabricated in a semiconductor crystal, and

[0365] - wherein the semiconductor crystal has a surface 46, and

[0366] - wherein the semiconductor crystal comprises semiconductor material below its surface 46, and

[0367] - wherein said surface 46 of said semiconductor crystal comprises a metallization stack, and

[0368] - wherein the metallization stack comprises an optically transparent and electrically insulating layer 34 of typical structure, and

[0369] - wherein at least a portion of the transparent and electrically insulating layer 34 of said typical structure of the surface 36 forms an optical fiber 50, and

[0370] - wherein the first SPAD diode 44 radiates photons 47 from the semiconductor material of the semiconductor substrate into the optical fiber 50, and

[0371] wherein the at least one optical fiber 50 transmits such photons 48 to the second SPAD diode 45, and

[0372] wherein the optical fiber 50 illuminates the second SPAD diode 45 so that light 49 from inside the optical fiber 50 re-enters the semiconductor material of the semiconductor substrate from the surface 46 and hits device components of the second SPAD diode 45, and

[0373] wherein the first SPAD diode 44 and the second SPAD diode 45 and the optical fiber 50 are part of a quantum random number generator 28 .

[0374] 32) A data processing device according to item 31), wherein the data processor and / or other device parts of the data processing device encrypt or decrypt data with the help of at least one random number of the quantum random number generator.

[0375] 33) The data processing device according to item 31) or item 32),

[0376] - wherein the data processing means comprises a memory, and

[0377] - wherein the memory is adapted to store data when used by the processor; and

[0378] - wherein the memory is coupled to the data processor to receive words from the data processor and to deliver words to the data processor.

[0379] 34) A data processing device according to any one of items 31) to 33),

[0380] - wherein the memory is external to the integrated circuit, and

[0381] - wherein the memory is coupled to the data processor via the interface at the boundary of the integrated circuit to receive words from the data processor and to deliver words to the data processor.

[0382] 35) A data processing device according to any one of items 31) to 34),

[0383] - wherein the data processor and the hash calculator are arranged such that they

[0384] a) calculating a hash function for each word according to a security code stored in said non-volatile memory and storing said hash in association with said word,

[0385] b) retrieving the stored words from the memory, recalculating the hash function for each retrieved word using the security code, and comparing the recalculated hash value with the stored hash value, and

[0386] c) Processing of the retrieved word by the data processing system is allowed only if the newly calculated and stored hashes have a previously defined relationship.

[0387] 36. An apparatus comprising:

[0388] - an integrated circuit comprising data processing means and non-volatile memory means storing at least one security code;

[0389] - a first device storing data, wherein said data is encrypted and protected by at least one authentication code in a first format; and

[0390] - a quantum random number generator 28 as part of said integrated circuit,

[0391] - wherein the quantum random number generator comprises a first SPAD diode 44 and a second SPAD diode 45 which are connected or connectable to each other on the surface of the integrated circuit via an optical fiber 50 manufactured outside the semiconductor substrate of the integrated circuit, and

[0392] - wherein the device at least temporarily uses at least one random number of the quantum random number generator 28 to encrypt or decrypt a date or the authentication code.

[0393] 37) The device according to item 36),

[0394] - wherein the device comprises second means, in particular external to the integrated circuit, for storing data, and

[0395] - wherein the device comprises transfer means for transferring data from the first memory to the second memory via the integrated circuit for access by the data processor from the second memory, and

[0396] - wherein said device comprises verification means for verifying data read from said first memory during transmission by using a security code stored in said non-volatile memory, and

[0397] - wherein the device comprises cryptographic protection applying means for applying cryptographic protection including at least one verification code to the verified data in a second format using the security code stored in the non-volatile memory when verifying the data, and

[0398] - wherein said device comprises storing means for storing protected data in said second memory in said second format.

[0399] 38) A device, in particular according to any one of items 12) to 37),

[0400] - wherein the device comprises a quantum random number generator 400, and

[0401] -Wherein the quantum random number generator comprises the following device components:

[0402] - a first SPAD diode 404.1,

[0403] - a second SPAD diode 404.3,

[0404] an optical fiber 404.2 which optically couples the first SPAD diode 404.1 and the second SPAD diode 404.3 to each other,

[0405] - an amplifier 403 and / or a filter,

[0406] - an analog-to-digital converter 403,

[0407] - Comparator 404.2,

[0408] -Time to Digital Converter 404.3,

[0409] - Entropy extraction means 404.4, which converts the output value of the time-to-digital converter 403 into a first value and a second value and generates random bits therefrom.

[0410] 39) An apparatus according to item 27), wherein the apparatus comprises a watchdog 404.5, which monitors the apparatus components of the quantum random number generator 400.

[0411] 40) An apparatus according to any one of items 38) and 39), wherein the apparatus comprises a voltage monitor 413, which detects and monitors an analog value of an analog signal.

[0412] 41) An apparatus according to any one of items 38) to 40), wherein the apparatus comprises a pseudo-random number generator 404.6, in particular in the form of a linear feedback shift register 404.6.

[0413] 42) An apparatus according to any one of items 38) to 41), wherein the apparatus comprises a signal multiplexer which, in the event of an error, switches the signal from the output 411 of the entropy extraction device to the signal of an equivalent random number generator or an equivalent pseudo-random number generator 404.6.

[0414] 43) An apparatus according to any one of items 38) to 42), wherein in the event of an error, the initial value of the pseudo-random number generator 404.6 depends on the random bits previously correctly generated by the quantum random number generator 400.

[0415] 44) A method for generating random bits, comprising the following steps:

[0416] - generating a pulse train with random intervals by means of at least two SPAD diodes,

[0417] - wherein the pulse sequence comprises pulses of a first height level 601 and a second height level 602;

[0418] - separation of the pulses of the first height level 601 from the pulses of the second height level 602 by cutting levels 603, 404.1;

[0419] - detecting 501 a first value of a time interval between a first pulse of said second height level 602 and a second pulse of said second height level 602 different from said first pulse;

[0420] - detecting 501 a second value of the time interval between a third pulse of the second height level 602 different from the first pulse and a fourth pulse of the second height level 602 different from the first pulse, the second pulse and the third pulse,

[0421] - comparing 502 said first value with said second value, and

[0422] - if the first value is greater than the second value, outputting a first logic value as a random bit 503, and

[0423] If the first value is smaller than the second value, a second logic value different from the first logic value is output as the random bit 503 .

[0424] 45) A method 3700 for generating a quantum random number QZ having m random bits comprises the following steps:

[0425] - 3710: Generate random single photon currents 47, 48, 49, 401.2 from single photons via one or more first SPAD diodes 401.1, 44;

[0426] - 3720: transmitting the random single photon current 47, 48, 49, 401.2 to one or more second SPAD diodes 401.3, 45 via an optical fiber 50, 401.2 different from the semiconductor substrate 39, 38;

[0427] - 3730: converting the random single photon current 47, 48, 49, 401.2 into a detection signal via the one or more second SPAD diodes 401.3, 45;

[0428] -3740: Adjust the detection signal to an adjusted detection signal;

[0429] -3750: separating pulses of the conditioned detection signal generated by emission coupling of a first SPAD diode 401.1 of the one or more first SPAD diodes 401.1, 44 and a second SPAD diode 401.3, 45 of the one or more second SPAD diodes 401.3, 45 from pulses of the conditioned detection signal generated by spontaneous emission of the second SPAD diode 401.3, 45 by comparing the conditioned detection signal with a threshold value 404.1;

[0430] -3760: determining a first time interval between a first pulse and a second pulse of a first pair of two consecutive pulses of the conditioned detection signal generated by coupling the emission of the first SPAD diode 401.1, 44 and the second SPAD diode 401.3, 45, and determining a second time interval between a third pulse and a fourth pulse of a second pair of two consecutive pulses of the conditioned detection signal generated by coupling the emission of the first SPAD diode 401.1, 44 and the second SPAD diode 401.3, 45;

[0431] -3670: Determine the bit value of the random bit by comparing the value of the first time interval with the value of the second time interval;

[0432] -3680: If the determined number of random bits 3680n is less than the expected number m of random bits of the quantum random number QZ to be generated, repeat the above steps 3710 to 3770, and if the determined number of random bits n is greater than or equal to the expected number m of random bits of the quantum random number QZ to be generated, terminate the process of generating quantum random numbers.

[0433] 46) A device comprising:

[0434] - an integrated circuit comprising data processing means and non-volatile memory means storing at least one security code;

[0435] - a first device storing data, wherein said data is encrypted and protected by at least one authentication code in a first format; and

[0436] - a quantum random number generator 28 as part of said integrated circuit,

[0437] - wherein the quantum random number generator comprises a first SPAD diode 44 and a second SPAD diode 45 which are connected or connectable to each other on the surface of the integrated circuit via an optical fiber 50 manufactured outside the semiconductor substrate of the integrated circuit, and

[0438] - wherein the device at least temporarily uses at least one random number of the quantum random number generator 28 to encrypt or decrypt a date or the authentication code.

[0439] 47) The device according to claim 46,

[0440] - wherein the device comprises second means, in particular external to the integrated circuit, for storing data, and

[0441] - wherein the device comprises transfer means for transferring data from the first memory to the second memory via the integrated circuit for access by the data processor from the second memory, and

[0442] - wherein said device comprises verification means for verifying data read from said first memory during transmission by using a security code stored in said non-volatile memory, and

[0443] - wherein the device comprises cryptographic protection applying means for applying cryptographic protection including at least one verification code to the verified data in a second format using the security code stored in the non-volatile memory when verifying the data, and

[0444] - wherein said device comprises storing means for storing protected data in said second memory in said second format.

[0445] 48) The device according to item 46) or item 47),

[0446] - wherein the device comprises a quantum random number generator 400, and

[0447] -Wherein the quantum random number generator comprises the following device components:

[0448] - a first SPAD diode 404.1,

[0449] - a second SPAD diode 404.3,

[0450] an optical fiber 404.2 which optically couples the first SPAD diode 404.1 and the second SPAD diode 404.3 to each other,

[0451] - an amplifier 403 and / or a filter,

[0452] - an analog-to-digital converter 403,

[0453] - Comparator 404.2,

[0454] -Time to Digital Converter 404.3,

[0455] - Entropy extraction means 404.4, which converts the output value of the time-to-digital converter 403 into a first value and a second value and generates therefrom random bits for a random number.

[0456] 49) An apparatus according to item 48), wherein the apparatus comprises a watchdog 404.5, which monitors the apparatus components of the quantum random number generator 400.

[0457] 50) An apparatus according to any one of items 48) and 49), wherein the apparatus comprises a voltage monitor 413, which detects and monitors an analog value of an analog signal.

[0458] 51) An apparatus according to any one of items 48) to 50), wherein the apparatus comprises a random number generator or a pseudo-random number generator 404.6, in particular in the form of a linear feedback shift register 404.6.

[0459] 52) An apparatus according to any one of items 48) to 51), wherein the apparatus comprises a signal multiplexer which, in the event of an error, switches the signal from the output 411 of the entropy extraction device to the signal of an equivalent random number generator or an equivalent pseudo-random number generator 404.6.

[0460] 53) An apparatus according to any one of items 48) to 52), wherein in the event of an error, the initial value of the pseudo-random number generator 404.6 depends on the random bits previously correctly generated by the quantum random number generator 400.

[0461] 54) A method for generating random bits, comprising the following steps:

[0462] - generating a pulse train with random intervals by means of at least two SPAD diodes,

[0463] - wherein the pulse sequence comprises pulses of a first height level 601 and a second height level 602;

[0464] - separation of the pulses of the first height level 601 from the pulses of the second height level 602 by cutting levels 603, 404.1;

[0465] - detecting 501 a first value of a time interval between a first pulse of said second height level 602 and a second pulse of said second height level 602 different from said first pulse;

[0466] - detecting 501 a second value of the time interval between a third pulse of the second height level 602 different from the first pulse and a fourth pulse of the second height level 602 different from the first pulse, the second pulse and the third pulse,

[0467] - comparing 502 said first value with said second value, and

[0468] - if the first value is greater than the second value, outputting a first logic value as a random bit 503, and

[0469] If the first value is smaller than the second value, a second logic value different from the first logic value is output as the random bit 503 .

[0470] 55) A method 3700 for generating a quantum random number QZ having m random bits comprises the following steps:

[0471] - 3710: Generate random single photon currents 47, 48, 49, 401.2 from single photons via one or more first SPAD diodes 401.1, 54;

[0472] - 3720: transmitting the random single photon current 47, 48, 49, 401.2 to one or more second SPAD diodes 401.3, 45 via an optical fiber 50, 401.2 different from the semiconductor substrate 39, 38;

[0473] - 3730: converting the random single photon current 47, 48, 49, 401.2 into a detection signal via the one or more second SPAD diodes 401.3, 45;

[0474] -3740: Adjust the detection signal to an adjusted detection signal;

[0475] -3750: separating pulses of the conditioned detection signal generated by emission coupling of a first SPAD diode 401.1 of the one or more first SPAD diodes 401.1, 44 and a second SPAD diode 401.3, 45 of the one or more second SPAD diodes 401.3, 45 from pulses of the conditioned detection signal generated by spontaneous emission of the second SPAD diode 401.3, 45 by comparing the conditioned detection signal with a threshold value 404.1;

[0476] -3760: determining a first time interval between a first pulse and a second pulse of a first pair of two consecutive pulses of the conditioned detection signal generated by coupling the emission of the first SPAD diode 401.1, 44 and the second SPAD diode 401.3, 45, and determining a second time interval between a third pulse and a fourth pulse of a second pair of two consecutive pulses of the conditioned detection signal generated by coupling the emission of the first SPAD diode 401.1, 44 and the second SPAD diode 401.3, 45;

[0477] -3670: Determine the bit value of the random bit by comparing the value of the first time interval with the value of the second time interval;

[0478] -3680: If the determined number of random bits 3680n is less than the expected number m of random bits of the quantum random number QZ to be generated, repeat the above steps 3710 to 3770, and if the determined number of random bits n is greater than or equal to the expected number m of random bits of the quantum random number QZ to be generated, terminate the process of generating quantum random numbers.

[0479] 56) A device for generating a quantum random number QZ,

[0480] - comprises one or more first SPAD diodes 401.1, 44, which generate a random single photon current 47, 48, 49, 401.2 3710 based on a photon quantum process from a single photon, and

[0481] - comprises one or more second SPAD diodes 401.3, 45, and

[0482] - comprises an optical fiber 50, 401.2 different from the semiconductor substrate 39, 38, which transmits the random single photon current 47, 48, 49, 401.2 to one or more second SPAD diodes 401.3, 45 3720, and

[0483] - wherein the one or more second SPAD diodes 401.3, 45 convert the random single photon current 47, 48, 49, 401.2 into a detection signal 3730, and

[0484] wherein the signal processing means, in particular the amplifier 402, conditions the detection signal into a conditioned detection signal 3740, and

[0485] - wherein the comparator 404.02 or a functionally equivalent device separates 3750 the pulses of the conditioned detection signal generated by the emission coupling of the first SPAD diode 401.1 of the one or more first SPAD diodes 401.1, 44 and the second SPAD diode 401.3, 45 of the one or more second SPAD diodes 401.3, 45 from the pulses of the conditioned detection signal generated by the spontaneous emission of the second SPAD diode 401.3, 45 by comparing the conditioned detection signal with a threshold value 404.1, and

[0486] - wherein the time-to-digital converter 404.3 determines a first time interval between a first pulse and a second pulse of a first pair of two consecutive pulses of the conditioned detection signal generated by emission coupling of the first SPAD diode 401.1, 44 and the second SPAD diode 401.3, 45, and determines a second time interval 3760 between a third pulse and a fourth pulse of a second pair of two consecutive pulses of the conditioned detection signal generated by emission coupling of the first SPAD diode 401.4, 44 and the second SPAD diode 401.3, 45; and

[0487] - wherein the entropy extraction means 404.4 determines the bit value 3670 of the random bit by comparing the value of the first time interval with the value of the second time interval, and

[0488] - wherein the finite state machine 404.8 generates a quantum random number QZ 417 from the bit data stream of random bits 411.

[0489] Reference numerals list

[0490] 1Secure Microcontroller

[0491] 2One or more internal data buses

[0492] 3 One or more read / write memory RAM

[0493] 4 One or more writable non-volatile memories; for example, the non-volatile memory may include EEPROM memory or flash memory or OTP memory

[0494] 5 One or more non-volatile read-only memories, such as ROM, etc.

[0495] 6 One or more non-volatile, writable and / or non-writable manufacturer memories; for example, in the case of a non-writable manufacturer memory, the manufacturer memory may be a manufacturer ROM

[0496] 7 One or more cryptographic accelerators, such as a DES accelerator and / or an AES accelerator

[0497] 8One or more manufacturer storage firewalls

[0498] 11 One or more CRC modules (cyclic redundancy check)

[0499] 12 One or more clock generator modules (CLK)

[0500] 13 Timer module

[0501] 14 One or more safety monitoring and control circuits

[0502] 15 Generators based on quantum processes

[0503] 16 Microcontroller core

[0504] 17 Data interface, typically one or more Universal Asynchronous Receiver Transmitters (UARTs) to support high-speed serial data

[0505] 21 One or more basic clock generators (CLK)

[0506] 22One or more reset circuits

[0507] 23 One or more power supply or Vcc circuits having a voltage regulator to provide operating voltage for the secure microcontroller

[0508] 24 One or more ground circuits

[0509] 25 One or more input / output circuits

[0510] 30 Example SPAD diode used as sensor element of single photon detector

[0511] 31 Example of shallow trench isolation STI of SPAD diode

[0512] 32 Anode contact of an exemplary SPAD diode

[0513] 33 Cathode contact of an exemplary SPAD diode; The cathode contact of the exemplary SPAD diode is preferably made of indium tin oxide (ITO) or other transparent conductive material

[0514] 34 Insulation layer

[0515] 34' Insulation Layer

[0516] 34” insulation layer

[0517] 35 A highly doped first connection region of a first line type; for example, in CMOS technology with p-doped wafer material, it can be an n-doped first connection region in the semiconductor substrate material of the SPAD diode. + Doping area

[0518] 36 a first doped tray of the second line type; for example, in CMOS technology with p-doped wafer material, it can be a weakly doped region in the semiconductor substrate material of the SPAD diode 1820, i.e., p -- Doping area

[0519] 37 A second doping tray of a second line type; for example, in CMOS technology with p-doped wafer material, it can be a weakly doped region in the semiconductor substrate material of the SPAD diode, i.e., a p - Doping area

[0520] 38 second linear epitaxial layer; for example, in CMOS technology with p-doped wafer material, it can be a p-doped epitaxial layer in the semiconductor substrate material of the SPAD diode

[0521] 39 A substrate having a semiconductor single crystal wafer of the second conductivity type; for example, in CMOS technology having a p-doped wafer material, it is a p-doped single crystal semiconductor wafer

[0522] 40 A second doping tray of a second line type below the anode contact; for example, in CMOS technology with p-doped wafer material, it can be a p-doped region in the semiconductor substrate material of the SPAD diode

[0523] 41 A highly doped second connection region of a second line type; for example, in CMOS technology with p-doped wafer material, it can be a p-doped second connection region in the semiconductor substrate material of the SPAD 1820 diode. + Doping area

[0524] 42 Insulation, such as oxide or the like

[0525] 43 Metal cover for optical fiber

[0526] 44 a first SPAD diode; the first SPAD diode is at least temporarily used as a light source for illuminating the second SPAD diode with photons from the first SPAD diode

[0527] 45 second SPAD diode; the second SPAD diode is used, for example, at least temporarily as a photodetector for light from the first SPAD diode

[0528] 46 According to the wafer surface of the present application

[0529] 47 The light emitted vertically upward by the first SPAD diode in a direction perpendicular to the surface

[0530] 48 Light transmitted horizontally in the optical fiber, which is part of the light emitted vertically into the optical fiber by the first SPAD diode

[0531] 49 light of the first SPAD diode emitted vertically downward from the optical fiber into the second SPAD diode in a direction perpendicular to the surface, the light being emitted by the first SPAD diode into the optical fiber as vertical light and then being transmitted horizontally from the optical fiber to the second SPAD diode;

[0532] 50 is an optical fiber for transmitting photons from a first SPAD diode to a second SPAD diode; the optical fiber is formed by a capping oxide or other optically transparent insulating layer on the circuit of the exemplary SPAD diode.

[0533] 50' is an optical fiber for transmitting photons from a first SPAD diode to a second SPAD diode; the optical fiber is formed by a capping oxide or other optically transparent insulating layer on the circuit of the exemplary SPAD diode, or by two optically transparent insulating layers (eg, a metallization stack) arranged one above the other.

[0534] 51 Contacts

[0535] 52 Contacts

[0536] 53 The plane between the two electrically insulating layers of the waveguide

[0537] 400 Quantum Random Number Generator QRNG

[0538] 401 Entropy Source

[0539] 401.1 One or more first SPAD diodes

[0540] 401.2 Fiber

[0541] 401.3 One or more second SPAD diodes

[0542] 402 High Frequency Amplifier

[0543] 403 Analog-to-digital converter (ADC)

[0544] 404 Measurement Board with FPGA

[0545] 404.1 Constant

[0546] 404.2 Comparator

[0547] 404.3 Time to Digital Converter

[0548] 404.4 Entropy Extraction Device

[0549] 404.5 Watchdog

[0550] 404.6 Linear feedback shift register; the feedback is preferably a simple native polynomial to generate a pseudo-random bit sequence;

[0551] 404.7 Signal Multiplexer

[0552] 404.8 Finite State Machine

[0553] 404.9RAM

[0554] 404.10 Completion Flag

[0555] 404.11 Microcontroller

[0556] 405 Voltage signal of entropy source 401

[0557] 406 Amplified output signal 406 of high frequency amplifier 402

[0558] 407 14-bit digital value 407 of analog-to-digital converter 403; other bit widths are also conceivable 408 signal of constant 404.1

[0559] 409 Output signal 409 of comparator 404.2

[0560] 410 Output 410 of the time-to-digital converter 404.3

[0561] 411 Entropy Extraction Output of 404.4

[0562] 412 Seeds S

[0563] 413 Voltage Monitor

[0564] 414 Signal Line

[0565] 416 Select Signal

[0566] 417 Pseudo-random signal line

[0567] 418 Random Data Words

[0568] 419 internal data bus of the quantum random number generator 400; preferably, this is the internal data bus of the control device 4

[0569] 420 are interrupt signals of the watchdog 404.5 of the quantum random number generator 400 and the control device 4 of the fuse 1.

[0570] 500 Flowchart of entropy extraction method 500

[0571] 501 A first step 501 of determining a first value of the output 410 of the time digital converter 404.3 and a second value of the output 410 of the time digital converter 404.3 and storing in a shift register of the entropy extraction 404.4 502 A second step of comparing the first value with the second value 503 A third step of evaluating the first value and the second value and generating random bits

[0572] 601 First Peak

[0573] 602 Second Peak

[0574] 603 Cutting Level

[0575] 3700 Method for generating a quantum random number QZ having m random bits

[0576] 3710 Generate random single photon current (57, 58, 59, 401.2) through one or more first SPAD diodes (401.1, 54)

[0577] 3720 transmitting the random single photon current (57, 58, 59, 401.2) to one or more second SPAD diodes (401.3, 55) through an optical fiber (44, 401.2) different from the semiconductor substrate (49, 48)

[0578] 3730 converts the random single photon current (57, 58, 59, 401.2) into a detection signal in the form of a voltage signal 405 of an entropy source 401, the entropy source 401 preferably comprising a first SPAD diode 401.1 and an optical fiber 401.2 and a second SPAD diode 401.3

[0579] 3740 Conditioning the detection signal, in particular amplifying and / or filtering and / or converting the analog-to-digital signal into a conditioned detection signal, in particular the 14-bit digital value 407 of the analog-to-digital converter 403

[0580] 3750 The pulses of the conditioned detection signal generated by the emission coupling of the first SPAD diode 401.1 and the second SPAD diode 401.3 are separated from the pulses of the conditioned detection signal generated by the spontaneous emission by comparing the conditioned detection signal with a threshold value, in particular in the comparator 404.2, and a corresponding output signal 409, in particular the output signal of the comparator 404.2, is generated.

[0581] 3760 for determining a first time interval between a first pulse and a second pulse of a first pair of two consecutive pulses of a conditioned detection signal generated by coupling the emission of the first SPAD diode 401.1 and the second SPAD diode 401.3, and for determining a second time interval between a third pulse and a fourth pulse of a second pair of two consecutive pulses of the conditioned detection signal generated by coupling the emission of the first SPAD diode 401.1 and the second SPAD diode 401.3, and, in particular, for determining a first value of the output 410 of the time digital converter 404.3 and a second value of the output 410 of the time digital converter 404.3

[0582] 3670 Determine the bit value of the random bit by comparing the value of the first time interval with the value of the second time interval

[0583] 3680 If the number n of random bits determined up to this step is less than the number m of random bits required for the required quantum random number, repeat the above steps. Otherwise, terminate the process to generate a quantum random number with m random bits.

Claims

1. A microcontroller for controlling a device in a car, comprising: - semiconductor substrates, - storage element, - at least one internal bus (2), - at least one microcontroller core (16), - one or more data interfaces, and - at least one generator (15) for true random numbers based on quantum processes, - wherein the storage element is connected to the internal bus (2), - wherein the data interface is connected to the internal bus (2), - wherein the generator (15) based on quantum processes is connected to the internal bus (2), and - wherein the microcontroller core (16) is connected to the internal bus (2), - wherein the generator (15) based on a quantum process generates random numbers, - wherein said generator (15) based on a quantum process provides said random number, - wherein the microcontroller core (16) uses a program from one or more of its storage elements and uses the random number to generate a key, - wherein the microcontroller core (16) uses a program from one or more of its storage elements and the key to encrypt and decrypt data exchanged with external devices or internally via the data interface, - wherein the semiconductor substrate integrally comprises the sub-devices of the microcontroller listed herein, - wherein the generator (15) based on quantum processes comprises at least one first SPAD diode (44) as a light source for the optical quantum signal, - wherein the generator (15) based on quantum processes comprises at least one second SPAD diode (45) as a photodetector for receiving the optical quantum signal, - wherein the generator (15) based on quantum processes comprises at least one processing circuit, - wherein the generator (15) based on quantum processes comprises at least one optical fiber (50) for optically coupling the at least one first SPAD diode (44) with the at least one second SPAD diode (45), - wherein the generator (15) based on quantum processes comprises an operating circuit for supplying electrical energy for emitting light to the at least one first SPAD diode (44), - wherein the generator (15) based on a quantum process comprises a processing circuit for detecting a signal of the at least one second SPAD diode (45) and for forming a random number from the signal of the at least one second SPAD diode and for providing the random number to the microcontroller core (16), wherein - the semiconductor substrate comprises a surface (46), - the semiconductor substrate comprises semiconductor material below its surface (46), - said surface (46) of said semiconductor substrate comprises a metallization stack, - the metallization stack comprises an optically transparent and electrically insulating layer (34) of typical structure located on the surface (46) of the semiconductor substrate, - at least a portion of the transparent and electrically insulating layer (34) forms said at least one optical fiber (50), - the first SPAD diode (44) emits photons (47) from the semiconductor material of the semiconductor substrate into the optical fiber (50), and - said at least one optical fiber (50) transmits such photons (48) to said second SPAD diode (45).

2. The microcontroller according to claim 1, characterized in that The quantum process based generator (15) generates the random number at the request of the microcontroller core (16).

3. The microcontroller according to claim 1, characterized in that The emission signal of the at least one second SPAD diode (45) has a first peak (601) and a second peak (602) larger than the first peak (601), wherein the first peak and the second peak (601, 602) are respectively larger than a definable reference value (404.1, 603), wherein the first peak (601) is generated by the spontaneous photon emission of the at least one second SPAD diode (45) without simultaneously causing the excitation photon emission of the at least one second SPAD diode (45), and the second peak (602) is generated by the spontaneous photon emission of the at least one second SPAD diode (45) excited by the photon reception of the at least one first SPAD diode (44), and the processing circuit of the generator (15) based on the quantum process generates a first logic value or a second logic value as a bit for generating the random number based on a comparison of the time interval of the second peak (602) with a threshold value or based on a comparison of the time intervals of the second peaks (602) with each other.

4. The microcontroller according to claim 3, characterized in that: The processing circuit generates the first logic value or the second logic value based on a comparison of a time interval between two second spikes (602) and a threshold value, and outputs the first logic value as a bit of the random number if the time interval is less than the threshold value, and outputs the second logic value as a bit of the random number if the time interval is greater than the threshold value.

5. The microcontroller according to claim 3, characterized in that: The processing circuit generates the first logic value or the second logic value based on a comparison of the time intervals of the second spikes (602) in different pairs of second spikes (602), and outputs the first logic value as a bit for generating the random number if the time interval of the last second spike (602) is less than the time interval between the second-to-last second spike (602) and the third-to-last second spike (602) or between other previous pairs of second spikes (602), and outputs the second logic value as a bit for generating the random number if the time interval of the last second spike (602) is greater than the time interval between the second-to-last second spike (602) and the third-to-last second spike (602) or between other previous pairs of second spikes (602).

6. The microcontroller according to any one of claims 1 to 5, characterized in that A plurality of pairs of first SPAD diodes (44) and second SPAD diodes (45), wherein emission signals of the second SPAD diodes (45) can be fed to the processing circuit, and the processing circuit outputs different bits of the bits used to generate the random number based on the emission signals of the second SPAD diodes (45).

7. The microcontroller according to any one of claims 1 to 5, characterized in that A pair of a first SPAD diode (44) and a second SPAD diode (45), wherein the processing circuit sequentially outputs the logic values ​​of the bits used to generate the random number.

8. The microcontroller according to any one of claims 1 to 5, characterized in that A single first SPAD diode (44) and a plurality of second SPAD diodes (45) optically coupled to the single first SPAD diode (44), wherein emission signals of the second SPAD diodes (45) can be fed to the processing circuit, and the processing circuit outputs different bits of the bits used to generate the random number based on the emission signals of the second SPAD diodes (45).

9. The microcontroller according to any one of claims 1 to 5, characterized in that An error detection unit and a pseudo-random number generator, wherein when the error detection unit detects an error in the function of a component of the quantum process-based generator (15) responsible for a photon-based process or an error in its processing circuit, the processing circuit of the quantum process-based generator (15) switches from outputting bits for generating the random number based on an emission signal of the at least one second SPAD diode (45) to outputting bits generated by the pseudo-random number generator for generating a pseudo-random number.

10. The microcontroller according to claim 9, characterized in that: When an error is detected, the error detection unit outputs an error signal.

11. The microcontroller according to claim 10, characterized in that: When an error is detected, the error detection unit outputs an error signal indicating the type and / or cause of the error.

12. The microcontroller according to any one of claims 1 to 5, characterized in that: The storage element comprises one or more read / write memories RAM (3) and / or one or more writable non-volatile memories and / or one or more read-only memories and / or one or more non-volatile manufacturer memories.

13. The microcontroller according to claim 12, characterized in that: The one or more writable non-volatile memories include EEPROM memory and / or flash memory and / or one-time programmable memory.

14. The microcontroller according to claim 12, characterized in that: The one or more non-volatile manufacturer memories include one or more manufacturer ROMs (6), and / or one or more manufacturer EEPROMs and / or one or more manufacturer flash memories.

15. The microcontroller according to claim 14, characterized in that: The manufacturer ROM (6) includes boot software.

16. The microcontroller according to claim 12, characterized in that A manufacturer firewall (8) is arranged between the manufacturer memory and the internal bus (2).

17. The microcontroller according to any one of claims 1 to 5, characterized in that Includes one or more of the following components: - a basic clock generator (21), - a clock generator circuit (12), and / or - a reset circuit (22), and / or - a power supply or Vcc circuit (23) having a voltage regulator for providing an operating voltage, and / or - a grounding circuit (24), and / or - input / output circuits (25), and / or - one or more processing modules, - wherein the processing module is in communication with the internal bus (2), and -Wherein the processing module comprises one or more of the following modules: - CRC module (11), - a clock generator module (12), - a DES accelerator and / or an AES accelerator (7), - one or more timer modules (13), - safety monitoring and control circuit (14), - said data interface.

18. The microcontroller according to claim 17, characterized in that: The data interface is a Universal Asynchronous Receiver / Transmitter (UART) (17).

19. The microcontroller according to claim 17, characterized in that: The optical fiber (50) illuminates the second SPAD diode (45) so that light (49) from inside the optical fiber (50) re-enters the semiconductor material of the semiconductor substrate and strikes device components of the second SPAD diode (45) there.

20. The microcontroller according to any one of claims 1 to 5, characterized in that: - at least one operating circuit at least temporarily supplies electrical energy to the at least one first SPAD diode (44), - the at least one first SPAD diode (44) feeds photons (47) into the at least one optical fiber (50) when supplied with sufficient electrical energy, - said at least one optical fiber (50) transmits such photons (48) to said second SPAD diode (45).

21. The microcontroller according to any one of claims 1 to 5, characterized in that: The data interface is a wired vehicle data bus interface, or one or more of the multiple data interfaces are wired vehicle data bus interfaces.

22. The microcontroller according to claim 21, characterized in that One or more wired vehicle data bus interfaces are configured as: -CAN data bus interface, and / or -CAN FD data bus interface, and / or -Flexray data bus interface, and / or -PSI5 data bus interface, and / or -DSI3 data bus interface, and / or -LIN data bus interface, and / or - Ethernet data bus interface, and / or -MELIBUS data bus interface.

23. The microcontroller according to any one of claims 1 to 5, characterized in that: The data interface is a wireless data bus interface, or one or more of the plurality of data interfaces is a wireless data bus interface.

24. The microcontroller according to claim 23, characterized in that The one or more wireless data bus interfaces are configured as: - WLAN interface, and / or - a mobile radio interface, and / or -Bluetooth interface.

25. The microcontroller according to any one of claims 1 to 5, characterized in that: The data interface is a wired data bus interface, or one or more data interfaces among the multiple data interfaces are wired data bus interfaces.

26. The microcontroller according to claim 25, characterized in that One or more wired data bus interfaces are configured as: - KNX data bus interface, and / or -EIB data bus interface, and / or -DALI data bus interface, and / or -PROFIBUS data bus interface.

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