A large-plate external capacitor LDO with overcurrent loop structure and high PSR performance

Abstract

The application belongs to the technical field of power management, and particularly relates to a large-plate external capacitor LDO with an overcurrent loop structure and high PSR performance. ds The application utilizes the large-plate external capacitor to benefit voltage stabilization and the high-voltage power tube has the characteristics of large r The application converts the common low-voltage drop and small-load-current LDO into a high-voltage drop and large-load-current LDO, and improves the PSR performance of the LDO in the full frequency band. Compared with the traditional structure, the power supply noise at low frequency can be suppressed through large loop gain, and the power supply noise at medium and high frequencies can be filtered out through the large-plate external capacitor.

Description

Technical Field

[0001] This invention belongs to the field of power management technology, and in particular relates to a large-area external capacitor LDO with high PSR performance and an overcurrent loop structure. Background Technology

[0002] Low dropout regulators (LDOs) have become another important type of power management chip compared to switching regulators due to their low cost, low noise, simple structure, and low power consumption. Capless LDOs, which have seen rapid development in recent years, are well-suited for on-chip integration because they do not require an external load capacitor at the output. However, the stability of capless LDOs is not as good as traditional large-capacitor LDOs. When the load current undergoes a large change, the output voltage of a capless LDO becomes unstable because it lacks an external capacitor to buffer and filter the charge changes. Furthermore, the different structures of the two lead to different dominant pole locations. The dominant pole of a capless LDO is located at the output of the error amplifier, and the location of its secondary pole at the output changes with the load, making the compensation design of capless LDO circuits more difficult. In addition, for capless LDOs, the smaller load capacitor makes it difficult to filter out noise from the power supply, resulting in a decrease in the high-frequency power supply rejection ratio (PSR) of the LDO, which affects the normal operation of subsequent precision analog circuits.

[0003] Figure 1 This demonstrates a typical structure of a conventional capacitor LDO, with the load capacitor being a large off-chip capacitor. The circuit typically employs Miller compensation for pole separation to ensure loop stability under different loads. Summary of the Invention

[0004] The purpose of this invention is to provide an LDO circuit suitable for large current loads, utilizing a large external capacitor for voltage regulation and a high-voltage power transistor with a large r ds The characteristics of this technology have been transformed from the common low voltage drop and small load current LDO to high voltage drop and large load current LDO, which improves the PSR performance of the LDO across the entire frequency band.

[0005] The technical solution of this invention is as follows:

[0006] A large-area external capacitor LDO with high PSR performance and an overcurrent loop structure is disclosed. The structure includes the LDO main circuit and an overcurrent loop, specifically including a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, a first bias current source, a second bias current source, and a third bias current source.

[0007] The source of the first PMOS transistor is connected to one end of the second bias current source, and the gate of the first PMOS transistor is connected to the reference voltage; the source of the second PMOS transistor is connected to one end of the second bias current source, and the gate of the second PMOS transistor is connected to the feedback voltage; the other end of the second bias current source is connected to the 5V power rail VPRE.

[0008] The drain and gate of the fifth NMOS transistor are connected to one end of the first bias current source, and the other end of the first bias current source is connected to the power supply VDD; the gate and drain of the sixth NMOS transistor are connected to the source of the fifth NMOS transistor, and the source of the sixth NMOS transistor is grounded.

[0009] The source of the third PMOS transistor is connected to the power supply VDD, and its gate and drain are interconnected; the source of the fifth PMOS transistor is connected to the drain of the third PMOS transistor, and the gate and drain of the fifth PMOS transistor are interconnected; the drain of the first NMOS transistor is connected to the drain of the fifth PMOS transistor, the gate of the first NMOS transistor is connected to the drain of the fifth NMOS transistor, and the source of the first NMOS transistor is connected to the drain of the second PMOS transistor and one end of the third bias current source.

[0010] The source of the fourth PMOS transistor is connected to the power supply VDD, and its gate is connected to the drain of the third PMOS transistor; the source of the sixth PMOS transistor is connected to the drain of the fourth PMOS transistor, and the gate of the sixth PMOS transistor is connected to the drain of the fifth PMOS transistor; the drain of the second NMOS transistor is connected to the drain of the sixth PMOS transistor, and the gate of the second NMOS transistor is connected to the drain of the fifth NMOS transistor; the source of the second NMOS transistor is connected to one end of the first capacitor, the drain of the first PMOS transistor, and one end of the third bias current source; the other end of the third bias current source is grounded.

[0011] The source of the seventh PMOS transistor is connected to the power supply VDD through the first resistor, and its gate is connected to the drain of the sixth PMOS transistor. The drain of the seventh PMOS transistor is grounded through the second resistor.

[0012] The source of the eighth PMOS transistor is connected to the power supply VDD, and its gate is connected to the source of the seventh PMOS transistor. The drain of the eighth PMOS transistor is grounded after passing through the third resistor and the fourth resistor in sequence. The connection point of the third resistor and the fourth resistor outputs the feedback voltage.

[0013] The other end of the first capacitor is connected to the drain of the eighth PMOS transistor and one end of the second capacitor. This connection point is the LDO output terminal; the other end of the second capacitor is grounded.

[0014] The source of the ninth PMOS transistor is connected to the power supply VDD, its gate is connected to the source of the seventh PMOS transistor, and the drain of the ninth PMOS transistor is grounded through the fifth resistor.

[0015] The drain and gate of the third NMOS transistor are connected to the drain of the ninth PMOS transistor; the drain and gate of the fourth NMOS transistor are connected to the source of the third NMOS transistor, and the source of the fourth NMOS transistor is grounded.

[0016] The drain of the fifth NMOS transistor is connected to the drain of the second PMOS transistor, the gate of the fifth NMOS transistor is connected to the drain of the ninth PMOS transistor, and the source of the fifth NMOS transistor is grounded through the sixth resistor.

[0017] The beneficial effects of this invention are: compared with the traditional structure, the power supply noise at low frequencies can be suppressed by a larger loop gain, while the power supply noise at medium and high frequencies can be filtered out by a large external capacitor. Attached Figure Description

[0018] Figure 1 It is a traditional off-chip large capacitor LDO structure.

[0019] Figure 2 The circuit diagram for the high PSR large-area external capacitor LDO with an overcurrent loop proposed in this invention is shown.

[0020] Figure 3 This is a schematic diagram illustrating the equivalent principle of low-frequency and mid-to-high-frequency PSR analysis in this invention.

[0021] Figure 4 The simulation waveform diagram of the PSR performance of the LDO proposed in this invention is shown.

[0022] Figure 5 The present invention provides a simulation waveform diagram of the load regulation rate of the LDO. Detailed Implementation

[0023] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings.

[0024] Figure 2 This invention presents a transistor schematic diagram of a large external capacitor LDO with an attached overcurrent loop structure. DD External power supply voltage: 9~34V; VPRE For V DD The 5V fast-response power rail is generated via the pre-step-down module; V SS Ground voltage; V G V is the gate voltage of the power transistor. REF As the reference voltage, I B1 This is the pre-amplifier bias current, the purpose of which is to generate the bias voltage V. B1 ;I B2 I is the bias current for the differential pair input to the amplifier. B3 The bias current for the amplifier's cascode branch is determined by the reference voltage and bias current, both of which can be generated by a bandgap reference circuit; V OUT V is the output voltage of the LDO. FB For the output voltage V OUT The voltage divider is used with V REF In comparison; V COPY The control voltage generated for the overcurrent loop is designed to adjust the control strength of the overcurrent loop. The circuit structure includes the LDO main circuit and an overcurrent limiting loop that limits the maximum load current.

[0025] The main circuit of the LDO is as follows: The fifth low-voltage PMOS transistor MP5 and the sixth low-voltage PMOS transistor MP6 constitute the pre-amplifier circuit for generating the bias voltage; the first low-voltage PMOS transistor MP1 and the second low-voltage PMOS transistor MP2 are the input differential pair transistors of the error amplifier; the first low-voltage NMOS transistor MN1 and the second low-voltage NMOS transistor MN2 are folded cascode transistors; the third low-voltage PMOS transistor MP3, the fourth low-voltage PMOS transistor MP4, the fifth high-voltage PMOS transistor MP5, and the sixth high-voltage PMOS transistor MP6 together form a cascode active load. The seventh high-voltage PMOS transistor MP6 is the buffer transistor for the second-stage gain structure, forming the second-stage buffer structure together with the first resistor R1 and the second resistor R2. The eighth high-voltage PMOS transistor MP8 is the power transistor, and the third resistor R3 and the fourth resistor R4 form a feedback resistor voltage divider structure to generate the feedback voltage V. FB The error amplifier will V FB With V REF By comparing and adjusting the gate voltage of the power transistor, the output voltage V is maintained. OUT The stability of the system loop is ensured by the following capacitors: The first capacitor, C1, is a Miller compensation capacitor with a typical value of 1-10pF, used to achieve pole separation and ensure system loop stability. The fourth capacitor, C4, is an external load capacitor with a typical value of 1uF. It is worth noting that because the external capacitor C4 is very large, generally much larger than the parasitic gate-drain capacitance and drain-substrate capacitance of the power transistor, the aforementioned parasitic capacitances can be ignored.

[0026] The overcurrent limiting loop is as follows: the ninth high-voltage PMOS transistor MP9 is a mirror image of the power transistor MP8, and can proportionally replicate the LDO's load current to the branch where MP9 is located; this current flows through the fifth resistor R5 and the two parallel branches of the third low-voltage NMOS transistor MN3 and the fourth low-voltage NMOS transistor MN4, generating V COPY Voltage; V COPY The voltage control of the gate voltage of the fifth low-voltage NMOS transistor MN5 controls the current in the branch containing MN5 to turn it on or off. This can break the current balance between the two branches of the input pair transistors, causing the gain of the first stage of the error amplifier to change from maximum gain to zero gain, thus causing the LDO to stop working completely.

[0027] The principle used to improve PSR performance is that a power transistor operating under high voltage drop conditions... It is much larger than a regular power transistor, which can effectively improve PSR performance across the entire frequency band. Its working principle is as follows: Figure 3 As shown, at low frequencies, it can be simplified to an impedance voltage divider between VDD to the output and the output to ground. It is the saturation region impedance of the power transistor. It is the closed-loop output impedance of the LDO. It can be represented as

[0028]

[0029] Therefore, low frequency

[0030] That is, at low frequencies, the PSR capability mainly depends on the loop gain of the LDO. This is because the power transistor... The gain is relatively large, so the power transistor stage can provide greater gain. The LDO in this paper has a greater gain than the conventional low dropout LDO, and therefore has better PSR performance at low frequencies.

[0031] At intermediate frequencies, the LDO's feedback loop can be approximated as open, and the system is considered open-loop. Voltage divider resistors. The impedance is still greater than the capacitance. The impedance, at which point PSR mainly depends on and The results of the voltage division between

[0032] Therefore, mid-frequency

[0033] This is when the PSR characteristics of the LDO are at their worst.

[0034] At high frequencies, due to capacitance The impedance is much smaller than that of the voltage divider resistor. The impedance, at which point PSR mainly depends on and The results of the voltage division between

[0035] Therefore, high frequency

[0036] Since the PSR across the entire frequency range depends on the power transistor... And the LDO power transistor Significantly higher than conventional low-dropout power transistors Therefore, the LDO in this paper can achieve better PSR performance across the entire frequency range.

[0037] Figure 4 The simulation of the PSR performance of the LDO is presented, and it can be seen that under different load conditions, the LDO in this paper has a significant improvement in PSR performance across the entire frequency band compared to a conventional low-dropout LDO.

[0038] Figure 5 The load regulation waveform of the LDO is shown. It can be seen that after using the overcurrent loop, the maximum load current of the LDO is limited. After the external load current exceeds the maximum load current, the output voltage of the LDO drops rapidly, thus completing the current limiting function.

Claims

1. A large-slab external capacitor LDO with over-current loop structure and high PSR performance, characterized in that, It includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, a first bias current source, a second bias current source, and a third bias current source; The source of the first PMOS transistor is connected to one end of the second bias current source, and the gate of the first PMOS transistor is connected to the reference voltage; the source of the second PMOS transistor is connected to one end of the second bias current source, and the gate of the second PMOS transistor is connected to the feedback voltage; the other end of the second bias current source is connected to the 5V power rail VPRE. The drain and gate of the fifth NMOS transistor are connected to one end of the first bias current source, and the other end of the first bias current source is connected to the power supply VDD; the gate and drain of the sixth NMOS transistor are connected to the source of the fifth NMOS transistor, and the source of the sixth NMOS transistor is grounded. The source of the third PMOS transistor is connected to the power supply VDD, and its gate and drain are interconnected; the source of the fifth PMOS transistor is connected to the drain of the third PMOS transistor, and the gate and drain of the fifth PMOS transistor are interconnected; the drain of the first NMOS transistor is connected to the drain of the fifth PMOS transistor, the gate of the first NMOS transistor is connected to the drain of the fifth NMOS transistor, and the source of the first NMOS transistor is connected to the drain of the second PMOS transistor and one end of the third bias current source. The source of the fourth PMOS transistor is connected to the power supply VDD, and its gate is connected to the drain of the third PMOS transistor; the source of the sixth PMOS transistor is connected to the drain of the fourth PMOS transistor, and the gate of the sixth PMOS transistor is connected to the drain of the fifth PMOS transistor; the drain of the second NMOS transistor is connected to the drain of the sixth PMOS transistor, and the gate of the second NMOS transistor is connected to the drain of the fifth NMOS transistor; the source of the second NMOS transistor is connected to one end of the first capacitor, the drain of the first PMOS transistor, and one end of the third bias current source; the other end of the third bias current source is grounded. The source of the seventh PMOS transistor is connected to the power supply VDD through the first resistor, and its gate is connected to the drain of the sixth PMOS transistor. The drain of the seventh PMOS transistor is grounded through the second resistor. The source of the eighth PMOS transistor is connected to the power supply VDD, and its gate is connected to the source of the seventh PMOS transistor. The drain of the eighth PMOS transistor is grounded after passing through the third resistor and the fourth resistor in sequence. The connection point of the third resistor and the fourth resistor outputs the feedback voltage. The other end of the first capacitor is connected to the drain of the eighth PMOS transistor and one end of the second capacitor. This connection point is the LDO output terminal; the other end of the second capacitor is grounded. The source of the ninth PMOS transistor is connected to the power supply VDD, its gate is connected to the source of the seventh PMOS transistor, and the drain of the ninth PMOS transistor is grounded through the fifth resistor. The drain and gate of the third NMOS transistor are connected to the drain of the ninth PMOS transistor; the drain and gate of the fourth NMOS transistor are connected to the source of the third NMOS transistor, and the source of the fourth NMOS transistor is grounded. The drain of the fifth NMOS transistor is connected to the drain of the second PMOS transistor, the gate of the fifth NMOS transistor is connected to the drain of the ninth PMOS transistor, and the source of the fifth NMOS transistor is grounded through the sixth resistor.

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