Semiconductor device and method of manufacturing the same
By setting a capacitor structure with a high drop on the substrate of a semiconductor device, the complexity problem of dynamic random access memory in high-aggregation and high-density designs is solved, and better operational performance and reliability are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2024-04-24
- Publication Date
- 2026-06-23
AI Technical Summary
Existing recessed gate structure dynamic random access memory (DRAM) suffers from increased manufacturing process and design complexity in high-integration and high-density designs, making it difficult to effectively improve the performance and reliability of memory devices.
A capacitor structure with a significant height difference is disposed on the substrate of a semiconductor device. The capacitor structure is divided into a first region and a second region by an insulating layer and an additional metal layer, and electrically connected to different components to perform different operations.
By setting capacitor structures with varying heights in different areas, the operational performance of semiconductor devices is optimized, the manufacturing process is simplified, and the reliability of the devices is improved.
Smart Images
Figure CN118215288B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and provides a semiconductor device and a method for manufacturing the same, particularly a semiconductor device with a capacitor structure and a method for manufacturing the same. Background Technology
[0002] With the trend towards miniaturization in various electronic products, the design of semiconductor devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, it can achieve a longer carrier channel length within the same semiconductor substrate, reducing leakage current caused by capacitor structures. Therefore, under the current mainstream development trend, it has gradually replaced DRAM with only planar gate structures. Generally, DRAM with a recessed gate structure consists of a large number of memory cells clustered into an array area to store information. Each memory cell can be composed of transistor components and capacitor components connected in series to receive voltage information from the word line (WL) and bit line (BL). Due to product demands, the density of memory cells in the array area must continue to increase, resulting in increasing difficulty and complexity in related manufacturing processes and designs. Therefore, existing technologies or structures still need further improvement to effectively enhance the performance and reliability of related memory devices. Summary of the Invention
[0003] One objective of this application is to provide a semiconductor device and a method for manufacturing the same, wherein capacitor structures with a height difference are respectively disposed in two regions of a substrate to be electrically connected to different components and perform different operations, thereby achieving more optimized operating performance.
[0004] To achieve the above objectives, one embodiment of this application provides a semiconductor device including a first region and a second region. The semiconductor device includes a substrate, a first metal layer, an insulating layer, a first capacitor structure, a second metal layer, and a second capacitor structure. The first metal layer is disposed on the substrate and located within the second region. The insulating layer is disposed within the first region and the second region, and covers the first metal layer. The first capacitor structure is disposed on the insulating layer within the first region and partially penetrates the insulating layer. The second metal layer is disposed on the insulating layer and electrically connected to the first metal layer. The second capacitor structure is disposed on the insulating layer and the second metal layer within the second region, and is located within the second region.
[0005] To achieve the above objectives, one embodiment of this application provides a method for fabricating a semiconductor device. The semiconductor device includes a first region and a second region. The fabrication method includes the following steps: Providing a substrate; Forming a first metal layer on the substrate, the first metal layer being located within the second region; Forming an insulating layer within the first region and the second region, the insulating layer covering the first metal layer; Forming a first capacitor structure on the insulating layer within the first region, the first capacitor structure partially penetrating the insulating layer; Forming a second metal layer on the insulating layer within the second region, the second metal layer being electrically connected to the first metal layer; Forming a second capacitor structure on the second metal layer. Attached Figure Description
[0006] The accompanying drawings provide a more in-depth understanding of embodiments of this application and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams and are for illustrative and drawing convenience, and relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.
[0007] Figure 1 The diagram shown is a cross-sectional schematic of a semiconductor device according to the first embodiment of this application.
[0008] Figure 2 The diagram shown is a cross-sectional schematic of a semiconductor device according to a second embodiment of this application.
[0009] Figures 3 to 9 The illustration is a schematic diagram of a method for fabricating a semiconductor device according to a preferred embodiment of this application, wherein:
[0010] Figure 3 This is a schematic cross-sectional view of a semiconductor device after the formation of a barrier material layer.
[0011] Figure 4 This is a schematic cross-sectional view of a semiconductor device after the metal material layer has been formed.
[0012] Figure 5 This is a schematic cross-sectional view of a semiconductor device after the formation of an insulating layer.
[0013] Figure 6 This is a schematic cross-sectional view of a semiconductor device after another insulating layer has been formed.
[0014] Figure 7 This is a schematic cross-sectional view of a semiconductor device after the support layer structure has been formed.
[0015] Figure 8 This is a schematic cross-sectional view of a semiconductor device after through-hole formation; and
[0016] Figure 9This is a schematic cross-sectional view of a semiconductor device after the capacitor structure has been formed.
[0017] The reference numerals in the attached figures are explained as follows:
[0018] 10, 30 Semiconductor devices
[0019] 100 substrate
[0020] 101 First District
[0021] 103 Second District
[0022] 104 Shallow Ditch Isolation
[0023] 110 First gate
[0024] 112 Dielectric Layer
[0025] 114 Gate dielectric layer
[0026] 116 Gate Layer
[0027] 118 cap layer
[0028] 120 Dielectric Layer
[0029] 122 Silicon oxide layer
[0030] 124 Silicon nitride layer
[0031] 126 Silicon oxide layer
[0032] 132 First plug
[0033] 134 Metal silicide layer
[0034] 136 Insulation Spacing
[0035] 138a, 238a Insulation Material Layer
[0036] 140 pads
[0037] Barrier layers 142 and 242
[0038] 144, 244 metal layers
[0039] 144a and 244a metallic material layers
[0040] 150 insulation layers
[0041] 160 First capacitor structure
[0042] 160b bottom surface
[0043] 162, 262 Bottom Electrode Layer
[0044] 164, 264 capacitor dielectric layer
[0045] 166, 266 top electrode layers
[0046] 170, 270 Intermetallic Dielectric Layer
[0047] Connection structures 176 and 276
[0048] 180 and 280 support layer structures
[0049] 180a, 280a perforations
[0050] 182, 282 First Support Material Layer
[0051] 184, 284 Second Support Material Layer
[0052] 186, 286 Third Support Material Layer
[0053] 188, 288 Fourth Support Material Layer
[0054] 210 Second Gate
[0055] 212 Semiconductor Layer
[0056] 214 Barrier Layer
[0057] 216 metal layer
[0058] 218 cap layer
[0059] 220 doped region
[0060] 222 Gate Dielectric Layer
[0061] 230 Spacer Wall Structure
[0062] 232, 234, 236 Spacer walls
[0063] 238 Interlayer Dielectric Layer
[0064] 238b Insulation Material
[0065] 240 First Metal Layer
[0066] 240t top surface
[0067] 242a Barrier Material Layer
[0068] 250 Second metal layer
[0069] 250e sidewall
[0070] 250t top surface
[0071] 252 Insulation Layer
[0072] 260 Second capacitor structure
[0073] 260b bottom surface
[0074] 272, 372 Second plug
[0075] 274 Metal interconnect structure
[0076] 302 Intermetallic Dielectric Layer
[0077] 310, 320 metal interconnect layers
[0078] 374 Third plug
[0079] D1 Horizontal direction
[0080] D2 Vertical direction
[0081] O1, O2 openings Detailed Implementation
[0082] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.
[0083] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.
[0084] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0085] Please refer to Figure 1 As shown, Figure 1 This is a schematic cross-sectional view of the semiconductor device 10 in the first embodiment of this application. Figure 1As shown, the semiconductor device 10 includes a substrate 100, a first metal layer 240, an insulating layer 150, a first capacitor structure 160, a second metal layer 250, and a second capacitor structure 260. The substrate 100 includes, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or a substrate made of other suitable materials, but is not limited thereto. The semiconductor device 10 further includes a first region 101 with relatively high component density, for example, serving as a cell region of the semiconductor device 10, and a second region 102 with relatively low component density, for example, serving as a peripheral region of the semiconductor device 10. In one embodiment, the first region 101 and the second region 102 are, for example, arranged adjacent to each other. Figure 1 As shown, but not limited thereto. Furthermore, multiple shallow trench isolation (STI) 104s are provided in the substrate 100 within the first region 101 and the second region 102, and multiple active regions are defined in the substrate 100.
[0086] like Figure 1 As shown, a first metal layer 240 is disposed on a substrate 100, located within a second region 102. An insulating layer 150 is disposed simultaneously within both the first region 101 and the second region 102, and the insulating layer 150 disposed within the second region 102 covers the first metal layer 240. A second metal layer 250 is further disposed above the insulating layer 150 located within the second region 102, and is electrically connected to the first metal layer 240 disposed below the insulating layer 150. It should be noted that a first capacitor structure 160 is disposed on the insulating layer 150 within the first region 101, and partially penetrates the insulating layer 150 to electrically connect to the underlying component, while a second capacitor structure 260 is disposed on the second metal layer 250 located within the second region 102, such that the bottom surface 160b of the first capacitor structure 160 and the bottom surface 260b of the second capacitor structure 260 are not coplanar. In other words, by setting the insulating layer 150 and additionally setting the second metal layer 250 in the second region 102, a height difference is created between the first capacitor structure 160 and the second capacitor structure 260 in the first region 101 and the second region 102. This facilitates the subsequent manufacturing process by electrically connecting the first capacitor structure 160 and the second capacitor structure 260, which are located in different regions, to different components through individual connection structures 176 and 276, forming different devices to perform different operations, thereby enabling the semiconductor device 10 to achieve more optimized operating performance.
[0087] In one embodiment, such as Figure 1 As shown, the first capacitor structure 160 includes a plurality of bottom electrode layers 162, a capacitor dielectric layer 164, and a top electrode layer 166 arranged in sequence, while the second capacitor structure 260 includes a plurality of bottom electrode layers 262, a capacitor dielectric layer 264, and a top electrode layer 266 arranged in sequence. Each bottom electrode layer 162 and each bottom electrode layer 262 has a U-shaped cross-section structure. Each bottom electrode layer 162 penetrates the insulating layer 150 located in the first region 101, and each bottom electrode layer 262 penetrates the insulating layer 252 located in the second region 102, so as to physically contact and electrically connect the plurality of pads 140 located in the first region 101 and the second metal layer 250 located in the second region 102, respectively. An insulating spacer 136 is also provided between adjacent pads 140 to isolate them from each other. The pads 140 and the first metal layer 240 located in the second region 102 preferably comprise the same conductive material. The pads 140 and the first metal layer 240 include, for example, barrier layers 142 and 242 and metal layers 144 and 244 stacked sequentially. The barrier layers 142 and 242 include, for example, titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN) and other conductive barrier materials. The metal layers 144 and 244 include, for example, copper (Cu), aluminum (Al), tungsten (W), or other suitable low-resistivity conductive materials, but are not limited thereto. It should be noted that the second capacitor structure 260 is disposed on the insulating layer 150 and the second metal layer 250 within the second region 102, such that the bottom surface of the bottom electrode layer 262 of the second capacitor structure 260 (i.e., the bottommost surface 260b of the second capacitor structure 260) is higher than the bottom surface of the bottom electrode layer 162 of the first capacitor structure 160 (i.e., the bottommost surface 160b of the first capacitor structure 160). Figure 1 As shown.
[0088] Specifically, such as Figure 1As shown, the semiconductor device 10 also includes a plurality of first plugs 132 and a plurality of first gates 110 disposed within the first region 101. The first plugs 132 are disposed on the substrate 100, below each pad 140, and physically contact the active region of the substrate 100. A metal silicide layer 134 may be further disposed between the first plugs 132 and the pads 140, and adjacent first plugs 132 are similarly isolated from each other by an insulating spacer 136. In one embodiment, the metal silicide layer 134 may include, for example, cobalt disilicide (CoSi2), titanium silicide (TiSi2), or nickel silicide (Ni2Si), and the first plugs 132 may include, for example, epitaxial materials such as silicon (Si), silicon-phosphorus (SiP), silicon-germanium (SiGe), or germanium (Ge), but are not limited thereto. Thus, the first plug 132 and the pad 140 can serve as the storage node contact (SN contact) and storage node pad (SN pad) of the semiconductor device 10, respectively, and are electrically connected to the first capacitor structure 160.
[0089] like Figure 1As shown, the first gate 110 is disposed within the substrate 100, and includes, in detail, a dielectric layer 112, a gate dielectric layer 114, a gate layer 116, and a capping layer 118 disposed sequentially. The top surface of the capping layer 118 is flush with the top surface of the substrate 100, such that the first gate 110 is covered by the dielectric layer 120 disposed on the substrate 100 in the first region 101, thus forming a buried gate. In one embodiment, the dielectric layer 120 includes, for example, a silicon oxide layer 122, a silicon nitride layer 124, and a silicon oxide layer 126 stacked sequentially, having an oxide-nitride-oxide (ONO) structure, but is not limited thereto. Therefore, the first gate 110 can serve as a buried word line (BWL) of the semiconductor device 10, and can also form a transistor assembly (not shown) together with a doped region (not shown) in the substrate 100 also disposed within the first region 101. In this configuration, the semiconductor device 10 of this embodiment can receive voltage information from bit lines (not shown) and buried word lines by means of the first capacitor structure 160 located in the first region 101 and the transistor assembly forming the smallest memory cell of the memory device. Furthermore, the smallest memory cell can be electrically connected to specific desired components through the connection structure 176 disposed in the intermetallic dielectric layer 170 that is integrally covered on the first capacitor structure 160. This allows the semiconductor device 10 of this embodiment to function as a dynamic random access memory (DRAM), thereby achieving more optimized operational performance.
[0090] On the other hand, for example Figure 1As shown, the semiconductor device 10 also includes a plurality of second gates 210, second plugs 272, and metal interconnect structures 274 disposed within the second region 102. The second gates 210 are disposed on a gate dielectric layer 222 on the substrate 100, and specifically include a semiconductor layer 212, a barrier layer 214, a metal layer 216, and a capping layer 218 stacked sequentially from bottom to top. In one embodiment, the gate dielectric layer 222 may include, for example, an insulating material such as silicon oxide; the semiconductor layer 212 may include, for example, semiconductor materials such as doped polycrystalline silicon or doped amorphous silicon; the barrier layer 214 may include, for example, conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide; the metal layer 216 may include, for example, copper, aluminum, tungsten, or other suitable low-resistivity conductive materials; and the capping layer 218 may include, for example, an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, but is not limited thereto. Each second gate 210 has a spacer wall structure 230 disposed on its sidewalls, including spacer walls 232, 234, and 236 stacked sequentially on the sidewalls. In one embodiment, spacer walls 232 and 236 may contain the same insulating material, such as silicon nitride or silicon carbonitride, while spacer wall 234 may contain an insulating material different from that of spacer walls 232 and 236, such as silicon oxide or silicon oxynitride, but is not limited thereto. Furthermore, doped regions 220 are disposed within the substrate 100 on both sides of the second gate 210, such that the second gate 210 and the doped regions 220 together form a transistor assembly (not shown) within the second region 102.
[0091] It should be noted that the aforementioned first metal layer 240 is disposed within the interlayer dielectric layer 238 on the second gate 210, and specifically includes a conductive portion located in the horizontal direction D1 and a plug portion located in the vertical direction D2. The plug portions of each first metal layer 240 physically contact the metal layer 216 of the second gate 210 or the doped region 220 on one side of the second gate 210, while the aforementioned insulating layer 150 covers the conductive portions of each first metal layer 240.
[0092] like Figure 1As shown, the second plug 272 and the metal interconnect structure 274 are respectively disposed within the intermetallic dielectric layer 270 on the insulating layer 150 and the second capacitor structure 260, such that each second plug 272 penetrates the insulating layer 150 and physically contacts the conductive portion of the first metal layer 240, while the metal interconnect structure 274 simultaneously physically contacts at least one conductive portion of the first metal layer 240 and the second metal layer 250. That is, the metal interconnect structure 274 simultaneously contacts the top surface 240t of the first metal layer 240, the top surface 250t of the second metal layer 250, and the sidewall 250e, to electrically connect the transistor assembly and the second capacitor structure 260 within the second region 102. With this configuration, the second capacitor structure 260 and the transistor assembly located within the second region 102 together form a minimum storage cell, and can be electrically connected to specific desired components via the connection structure 276 also disposed within the intermetallic dielectric layer 270, achieving more optimized operational performance. In one embodiment, each of the second plugs 272 and the metal interconnect structure 274 may include, for example, a barrier layer (not shown, such as titanium and / or titanium nitride, tantalum and / or tantalum oxide and other conductive barrier materials) and a metal layer (not shown, such as copper, aluminum, tungsten or other low resistivity conductive materials) stacked sequentially, but are not limited thereto.
[0093] According to the semiconductor device 10 of this embodiment, such as Figure 1 As shown, an insulating layer 150 is simultaneously disposed in both the first region 101 and the second region 102, and a second metal layer 250 is additionally disposed in the second region 102. This allows the first capacitor structure 160 located in the first region 101 and the second capacitor structure 260 located in the second region 102 to be disposed on the insulating layer 150 and the second metal layer 250 respectively, without being coplanar. Furthermore, an additional insulating layer 252 is disposed on the second metal layer 250, located only in the second region 102. Thus, the first capacitor structure 160 disposed in the first region 101 partially penetrates the insulating layer 150 and is electrically connected to the transistor assembly in the first region 101 via the storage node pads and the storage node plugs. The second capacitor structure 260 disposed in the second region 102 partially penetrates the insulating layer 252 and is electrically connected to the transistor assembly in the second region 102 via the second metal layer 250 and the first metal layer 240. In this configuration, by additionally providing a second metal layer 250 in the second region 102, a height difference is created between the first capacitor structure 160 and the second capacitor structure 260 in different regions. This facilitates the subsequent fabrication process by using individual connection structures 176 and 276 to electrically connect to different components and form different devices to perform different operations, thereby enabling the semiconductor device 10 to achieve more optimized operational performance.
[0094] Those skilled in the art to which this application pertains will readily understand that, to meet actual product requirements, the semiconductor device of this application may have other forms and is not limited to those described above. Further embodiments or variations of the semiconductor device of this application will be described below. For the sake of simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, identical components in the embodiments of this application are designated with the same reference numerals to facilitate comparison between embodiments.
[0095] Please refer to Figure 2 The diagram shown is a cross-sectional view of the semiconductor device 30 in the second embodiment of this application. The structure of the semiconductor device 30 in this embodiment is largely the same as that of the semiconductor device 10 in the previous embodiment. For example, the semiconductor device 30 also includes a first region 101 and a second region 102; the similarities will not be repeated here. The main difference between the semiconductor device 30 in this embodiment and the previous embodiment is that the semiconductor device 30 includes a metal interconnect layer 320 disposed in the second region 102 and a plurality of third plugs 374, wherein the third plugs 374 physically contact a first metal layer 240 and a second metal layer 250, respectively.
[0096] Specifically, such as Figure 2 As shown, in this embodiment, the semiconductor device 30 has a second plug 372 and a third plug 374 simultaneously disposed within the intermetallic dielectric layer 270, which physically contact the conductive portions of each of the first metal layers 240 and the second metal layer 250, respectively. Furthermore, an intermetallic dielectric layer 302 and metal interconnect layers 310 and 320 located within the intermetallic dielectric layer 302 are disposed on the intermetallic dielectric layers 170 and 270, such that the metal interconnect layer 310 disposed within the first region 101 physically contacts the connection structure 176 and is electrically connected to the smallest storage cell located within the first region 101, while the metal interconnect layer 320 disposed within the second region 102 physically contacts the connection structure 276, the second plug 372, and the third plug 374, respectively. It should be noted that at least one metal interconnect layer 320 simultaneously physically contacts at least two third plugs 374, wherein the bottom of at least one third plug 374 is physically in contact with the second metal layer 250, the bottom of the other third plug 374 is in contact with the wire portion of the first metal layer 240, and its sidewall may selectively not contact the sidewall of the second metal layer 250 (e.g., Figure 2 (as shown) or physical contact (not shown). Thus, in this embodiment, the second metal layer 250 is also electrically connected to the first metal layer 240, so that the metal interconnect layer 320 disposed in the second region 102 can be electrically connected to the smallest storage cell located in the second region 102 through the connection structure 276.
[0097] Under this configuration, the semiconductor device 30 of this embodiment can also create a height difference between the first capacitor structure 160 and the second capacitor structure 260 in the first region 101 and the second region 102 by means of the insulating layer 150 and the second metal layer 250. This is beneficial for the first capacitor structure 160 and the second capacitor structure 260 disposed in different regions to be electrically connected to different components and formed into different devices to perform different operations in subsequent manufacturing processes through the connection structures 176, 276 and the metal interconnect layers 310, 320, thereby achieving a more optimized operating performance.
[0098] To enable those skilled in the art to easily understand the semiconductor device of this application, the manufacturing method of the semiconductor device of this application will be further described below.
[0099] Please see Figures 3 to 9 The diagram shown illustrates a method for fabricating a semiconductor device 10 / 30 according to a preferred embodiment of this application. The semiconductor device 10 / 30 includes a first region 101 and a second region 102. Firstly, as... Figure 3 As shown, a substrate 100 is provided, and shallow trench isolation 104s are formed in the substrate 100 within a first region 101 and a second region 102, while active regions are defined simultaneously in the first region 101 and the second region 102. In one embodiment, the shallow trench isolation 104 is formed, for example, by first forming a plurality of trenches (not shown) in the substrate 100 using an etching process, and then filling the trenches with at least one insulating material (such as silicon oxide, silicon nitride, etc.) to form a shallow trench isolation 104 with a surface flush with the top surface of the substrate 100, but this is not a limitation.
[0100] Next, as Figure 3As shown, a plurality of first gates 110 are formed in the substrate 100 within the first region 101. In one embodiment, the fabrication of the first gates 110 includes, but is not limited to, the following steps: for example, first forming a plurality of trenches (not shown) that can simultaneously pass through the plurality of active regions and the shallow trench isolation 104; then forming a dielectric layer 112 covering the entire surface of the trench, a gate dielectric layer 114 covering the lower half of the surface of the trench, a gate layer 116 filling the lower half of the trench, and a capping layer 118 filling the upper half of the trench, but not limited thereto. Furthermore, a dielectric layer 120 and a gate dielectric layer 222 are formed on the substrates 100 within the first region 101 and the second region 102, respectively. In one embodiment, the fabrication of the dielectric layer 120 and the gate dielectric layer 222 includes, but is not limited to, the following steps: for example, firstly, a dielectric material layer is formed on the substrate 100 within the first region 101 and the second region 102, including a first silicon oxide material layer (not shown), a silicon nitride material layer (not shown), and a second silicon oxide material layer (not shown) stacked sequentially; then, at least the second silicon oxide material layer and the silicon nitride material layer formed on the substrate 100 within the second region 102 are removed, such that the first silicon oxide material layer located in the second region 102 of the substrate 100 forms the gate dielectric layer 222, while the dielectric material layer located on the substrate 100 within the first region 101 forms the dielectric layer 120. Alternatively, in another embodiment, the dielectric material layer located on the substrate 100 within the second region 102 may be completely removed, and then the gate dielectric layer 222 may be formed separately. In other words, the fabrication process of the gate dielectric layer 222 located in the second region 102 can be selectively integrated with the fabrication process of the dielectric layer 120 located in the first region, so that the gate dielectric layer 222 preferably includes the same material as the silicon oxide layer 122, but is not limited thereto.
[0101] Then, as Figure 3As shown, a second gate 210 and a spacer structure 230 are formed on a substrate 100 within the second region 102. Furthermore, a doped region 220 is formed within the substrate 100 on one side of the second gate 210 and the spacer structure 230. In one embodiment, the fabrication process of the second gate 210 includes, but is not limited to, the following steps: First, a semiconductor material layer (not shown, such as polycrystalline silicon, doped amorphous silicon, etc.), a barrier material layer (not shown, such as titanium and / or titanium nitride, tantalum and / or tantalum oxide, etc.), a metal material layer (not shown, such as tungsten, aluminum, or copper, etc., with low resistivity), and a capping material layer (not shown, such as silicon oxide, silicon nitride, or silicon oxynitride, etc., with insulating materials) are sequentially formed within the second region 102. Finally, the second gate 210 is formed through a patterning fabrication process. Furthermore, a spacer structure 230 is formed on the sidewall of the second gate 210. In one embodiment, the fabrication process of the spacer wall structure 230 includes, for example, sequentially forming a first spacer wall material layer (not shown, such as silicon nitride or silicon carbonitride), a second spacer wall material layer (not shown, such as silicon oxide or silicon oxynitride), and a third spacer wall material layer (not shown, such as silicon nitride or silicon carbonitride) to integrally cover the second gate 210, and then performing an etch-back process to form spacer walls 232, 234, and 236 sequentially disposed on the sidewalls of each of the second gates 210, thus forming the spacer wall structure 230. It should be noted that, in a preferred embodiment, the fabrication process of the second gate 210 located in the second region 102 may also be selectively integrated with the fabrication process of the bit line structure (not shown) located in the first region 101, such that the bit line and the second gate 210 include the same stacked structure and materials, but this is not a limitation.
[0102] Then, as Figure 3As shown, a deposition process is performed to simultaneously form insulating material layers 138a and 238a on the substrate 100 in the first region 101 and the second region 102. The insulating material layer 138a in the first region 101 and the insulating material layer 238a in the second region 102 are then partially removed through a mask layer (not shown), forming multiple openings O1 and O2 in the first region 101 and the second region 102, respectively. Each opening O1 exposes a portion of the substrate 100 in the first region 101, while each opening O2 exposes the metal layer 216 and the doped region 220 of the second gate 210, respectively. After completely removing the mask layer, an epitaxial process is performed through another mask layer (not shown) to sequentially form a first plug 132 within the opening O1 in the first region 101. Then, a metal silicide process is performed to form a metal silicide layer 134 on the first plug 132. Thus, the formed first plug 132 can serve as a memory node plug for the semiconductor device 10 / 30. After completely removing the other mask layer, a deposition process is performed again to form a barrier material layer (not shown, but including, for example, conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide) covering the substrate 100 in both the first region 101 and the second region 102. The barrier material layer is partially located within the openings O1 and O2, and partially located outside the openings O1 and O2, such as... Figure 3 As shown. Subsequently, a barrier layer 142 is formed in the first region 101 by performing a back etching process on the barrier material layer in the first region 101, and a barrier material layer 242a is formed in the second region 102.
[0103] like Figure 4 As shown, another deposition process is performed to simultaneously form metal material layers 144a and 244a (e.g., copper, aluminum, tungsten or other suitable low resistivity metal materials) on the substrate 100 in the first region 101 and the second region 102, filling the remaining space of the openings O1 and O2 and further covering the top surface of the insulating material layers 138a and 238a.
[0104] like Figure 5As shown, a patterning process is performed on the metal material layers 144a, 244a and the barrier material layer 242a to form pads 140 and a first metal layer 240 on the substrate 100 in the first region 101 and the second region 102, respectively. Next, the insulating material layer 138a in the first region 101 is completely removed, and a deposition and etch-back process is performed in the first region 101. A suitable insulating material, such as silicon nitride, silicon oxynitride, or silicon carbonitride, is filled between adjacent pads 140 and adjacent first plugs 132 to form an insulating gap 136 with the top surface aligned with the pads 140. Thus, the formed pads 140 can serve as memory node pads for the semiconductor device 10 / 30, and the formed first metal layer 240 simultaneously includes the plug portion that physically contacts the metal layer 216 or the doped region 220, and the conductive portion located in the horizontal direction D1. In addition, another deposition and etch-back process is performed in the second region 102 to fill the space between adjacent first metal layers 240 with insulating material 238b, so that the insulating material 238b and the aforementioned insulating material layer 238a together form an interlayer dielectric layer 238 with its top surface flush with the first metal layer 240. Then, a deposition process is performed to form an insulating layer 150 on the substrate 100 in the first region 101 and the second region 102. This insulating layer 150 may be made of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, and integrally covers the pads 140 and insulating spacers 136 in the first region 101, and the first metal layer 240 and interlayer dielectric layer 238 in the second region 102.
[0105] like Figure 6 As shown, at least one deposition and patterning process is performed to form a second metal layer 250 and an insulating layer 252 on the substrate 100 within the second region 102. The second metal layer 250 and the insulating layer 252 cover a portion of the first metal layer 240 and have mutually flush sidewalls. In one embodiment, the second metal layer 250 may include, for example, copper, aluminum, tungsten, or other low-resistivity conductive materials, but is not limited thereto.
[0106] like Figure 7As shown, support layer structures 180 and 280 are simultaneously formed on the substrate 100 within the first region 101 and the second region 102. These structures include, in detail, a first support material layer 182, 282 (e.g., silicon oxide), a second support material layer 184, 284 (e.g., silicon nitride or silicon carbonitride), a third support material layer 186, 286 (e.g., silicon oxide), and a fourth support material layer 188, 288 (e.g., silicon nitride or silicon carbonitride), but are not limited thereto, stacked sequentially from bottom to top. In one embodiment, the first support material layer 182, 282 and the third support material layer 186, 286 preferably have a relatively large thickness, for example, approximately 5 to 10 times or more the thickness of the second support material layer 184, 284 and the fourth support material layer 188, 288. Furthermore, the thickness of the fourth support material layer 188, 288 is preferably greater than the thickness of the second support material layer 184, 284, but is not limited thereto. Thus, the overall thickness of the support layer structures 180 and 280 can reach approximately 1600 to 2000 angstroms, but is not limited to this.
[0107] like Figure 8 As shown, multiple through-holes 180a and 280a are formed within the support layer structures 180 and 280, sequentially penetrating the fourth support material layers 188 and 288, the third support material layers 186 and 286, the second support material layers 184 and 284, and the first support material layers 182 and 282. The through-hole 180a further penetrates the insulating layer 150 formed within the first region 101 to align with and physically contact the underlying pads 140, while the through-hole 280a further penetrates the insulating layer 252 formed only within the second region 102 to physically contact the underlying second metal layer 250.
[0108] like Figure 9 As shown, bottom electrode layers 162 and 262 with U-shaped cross-sections are formed in the through-holes 180a and 280a of the first region 101 and the second region 102, respectively. Then, at least one etching process is performed through a mask layer (not shown) to completely remove the third support material layers 186 and 286 and the first support material layers 182 and 282, and to partially remove the fourth support material layers 188 and 288 and the second support material layers 184 and 284. After completely removing the mask layer, at least one deposition process is performed to simultaneously form capacitor dielectric layers 164 and 264 and top electrode layers 166 and 266 on the substrate 100 in the first region 101 and the second region 102. The capacitor dielectric layers 164 and 264 cover the bottom electrode layers 162 and 262, while the top electrode layers 166 and 266 fill the remaining space between adjacent bottom electrode layers 162 and 262.
[0109] Thus, as Figure 9As shown, the bottom electrode layer 162, capacitor dielectric layer 164, and top electrode layer 166 located in the first region 101 together form the first capacitor structure 160, while the remaining fourth support material layer 188 and second support material layer 184 together form the support structure of the first capacitor structure 160. On the other hand, the bottom electrode layer 262, capacitor dielectric layer 264, and top electrode layer 266 located in the second region 102 together form the second capacitor structure 260, while the remaining fourth support material layer 288 and second support material layer 284 together form the support structure of the second capacitor structure 260. The bottom electrode layer 162 of the first capacitor structure 160 passes through the insulating layer 150 located in the first region 101, and the bottom electrode layer 262 of the second capacitor structure 260 passes through the insulating layer 252 located in the second region 102, and is respectively disposed on the pad 140 and the first metal layer 240, such that the first capacitor structure 160 and the second capacitor structure 260 are not coplanar. Under this operation, the height difference between the first capacitor structure 160 and the second capacitor structure 260 in different areas facilitates the formation of a connection structure that electrically connects the first capacitor structure 160 and the second capacitor structure 260 respectively in subsequent manufacturing processes. This allows the first capacitor structure 160 and the second capacitor structure 260 to be synchronously connected to different components and form different devices to perform different operations.
[0110] For example, in subsequent manufacturing processes, intermetallic dielectric layers 170 and 270 that integrally cover the first capacitor structure 160 and the second capacitor structure 260 can be formed on the first region 101 and the second region 102. Then, similar processes are performed to simultaneously or separately form, as shown in the example, within the intermetallic dielectric layers 170 and 270. Figure 1 The second plug 272, metal interconnect structure 274, and connection structures 176 and 276 are shown. Alternatively, they can be formed simultaneously or separately within the intermetallic dielectric layer 270. Figure 2 After the second plug 372 and the third plug 374 are shown, a metal interconnect layer 320 is formed. The metal interconnect layer 320 simultaneously makes physical contact with at least two of the third plugs 374. The bottom of at least one third plug 374 is in physical contact with the second metal layer 250, and the bottom of the other third plug 374 is in contact with the first metal layer 240. Its sidewall may selectively not contact or make physical contact with the sidewall of the second metal layer 250, but is not limited thereto.
[0111] According to the fabrication method of this embodiment, an insulating layer 150 covering the entire structure is formed on the first region 101 and the second region 102, and a second metal layer 250 is formed on the second region 102. Then, by integrating the fabrication process of components on the substrate 100 within the first region 101 and the second region 102, a first capacitor structure 160 and a second capacitor structure 260 are formed in the first region 101 and the second region 102 respectively using a similar process, creating a height difference between the first capacitor structure 160 and the second capacitor structure 260 within the first region 101 and the second region 102. This facilitates the subsequent fabrication process by electrically connecting the first capacitor structure 160 and the second capacitor structure 260 formed in different regions to different components through connection structures 176, 276 and metal interconnect layers 310, 320, forming different devices to perform different operations. Under this operation, the fabrication method of the semiconductor device 10 / 30 in this embodiment can form a semiconductor device 10 / 30 with reliable structure and performance while simplifying the fabrication process.
[0112] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A semiconductor device, characterized in that, The semiconductor device includes a first region and a second region, comprising: Substrate; A first metal layer is disposed on the substrate and located within the second region; An insulating layer is disposed within the first region and the second region, and covers the first metal layer; The solder pads are disposed within the first area and located below the insulating layer; A first capacitor structure is disposed on the insulating layer in the first region and partially penetrates the insulating layer. The first capacitor structure is disposed on the pad and physically contacts the pad. A second metal layer is disposed on the insulating layer within the second region and electrically connected to the first metal layer; and The second capacitor structure is disposed on the second metal layer; The insulating layer is sandwiched between the first metal layer and the second metal layer in a direction perpendicular to the substrate; A metal interconnect structure physically contacts the top surface of the first metal layer, the top surface of the second metal layer, and the sidewall of the second metal layer; The first connection structure is connected to the first capacitor structure; The second connection structure is connected to the second capacitor structure.
2. The semiconductor device according to claim 1, characterized in that, The bottom surface of the second capacitor structure and the bottom surface of the first capacitor structure are not coplanar.
3. The semiconductor device according to claim 1, characterized in that, The second capacitor structure and the first capacitor structure each include a bottom electrode layer, a capacitor dielectric layer and a top electrode layer arranged in sequence, and the bottom electrode layer of the second capacitor structure is in physical contact with the second metal layer.
4. The semiconductor device according to claim 3, characterized in that, The bottom surface of the bottom electrode layer of the second capacitor structure is higher than the bottom surface of the bottom electrode layer of the first capacitor structure.
5. The semiconductor device according to claim 1, characterized in that, The pads and the first metal layer comprise the same conductive material.
6. The semiconductor device according to claim 5, characterized in that, Also includes: The first gate is disposed in the substrate within the first region and together with the first capacitor structure forms a memory cell.
7. The semiconductor device according to claim 1, characterized in that, Also includes: A first gate is disposed in the substrate within the first region; A first plug is disposed in the substrate within the first region and is in physical contact with the substrate; as well as A second gate is disposed on the substrate and located within the second region, wherein the first metal layer includes a plug portion of the doped region that physically contacts one side of the second gate.
8. The semiconductor device according to claim 7, characterized in that, Also includes: Multiple second plugs are disposed within the second area and physically contact the first metal layer and the second metal layer, respectively; as well as A metal interconnect layer is disposed on the second plug and physically contacts the second plug.
9. A semiconductor device, characterized in that, The semiconductor device includes a first region and a second region, comprising: Substrate; A first metal layer is disposed on the substrate and located within the second region; An insulating layer is disposed within the first region and the second region, and covers the first metal layer; A first capacitor structure is disposed on the insulating layer within the first region and partially penetrates the insulating layer; A second metal layer is disposed on the insulating layer within the second region and electrically connected to the first metal layer; and The second capacitor structure is disposed on the second metal layer; The insulating layer is sandwiched between the first metal layer and the second metal layer in a direction perpendicular to the substrate; The metal interconnect structure physically contacts the top surface of the first metal layer, the top surface of the second metal layer, and the sidewall of the second metal layer.
10. A method for fabricating a semiconductor device, characterized in that, The semiconductor device includes a first region and a second region, and the fabrication method includes: Provide substrate; A first metal layer is formed on the substrate, the first metal layer being located within the second region; An insulating layer is formed in the first region and the second region, the insulating layer covering the first metal layer; A pad is formed in the first region beneath the insulating layer; A first capacitor structure is formed on the insulating layer in the first region, the first capacitor structure partially penetrates the insulating layer, and the first capacitor structure is formed on the pad and physically contacts the pad; A second metal layer is formed on the insulating layer within the second region, the second metal layer being electrically connected to the first metal layer; and A second capacitor structure is formed on the second metal layer; The insulating layer is sandwiched between the first metal layer and the second metal layer in a direction perpendicular to the substrate; A metal interconnect structure is formed on the first metal layer and the second metal layer, the metal interconnect structure physically contacting the top surface of the first metal layer, the top surface of the second metal layer and the sidewall of the second metal layer; A first connection structure is formed on the first capacitor structure; A second connection structure is formed on the second capacitor structure.
11. The method for fabricating a semiconductor device according to claim 10, characterized in that, Also includes: A first gate is formed in the substrate, and the first gate is located within the first region; A first plug is formed on the substrate, the first plug being in physical contact with the substrate; as well as A second gate is formed on the substrate, the second gate being located within the second region, wherein the first metal layer includes a plug portion that physically contacts the doped region on one side of the second gate.
12. The method for fabricating a semiconductor device according to claim 11, characterized in that, Also includes: The pad is formed on the first plug, and the pad is formed together with the first metal layer and includes the same conductive material.
13. The method for fabricating a semiconductor device according to claim 12, characterized in that, The first gate and the first capacitor structure together form a memory cell.
14. The method for fabricating a semiconductor device according to claim 11, characterized in that, Also includes: Multiple second plugs are formed in the second region, and the multiple second plugs physically contact the first metal layer and the second metal layer respectively; as well as A metal interconnect layer is formed on the second plug, the metal interconnect layer being in physical contact with the second plug.
15. The method for fabricating a semiconductor device according to claim 11, characterized in that, The bottom surface of the second capacitor structure and the bottom surface of the first capacitor structure are not coplanar.
16. The method for fabricating a semiconductor device according to claim 11, characterized in that, The second capacitor structure and the first capacitor structure each include a bottom electrode layer, a capacitor dielectric layer, and a top electrode layer arranged in sequence, and the bottom electrode layer of the second capacitor structure is in physical contact with the second metal layer.
17. The method for fabricating a semiconductor device according to claim 16, characterized in that, The bottom surface of the bottom electrode layer of the second capacitor structure is higher than the bottom surface of the bottom electrode layer of the first capacitor structure.