Thread control method and device, processor and computer readable storage medium

Abstract

At least one embodiment of the present disclosure provides a thread control method and device, a processor, and a computer-readable storage medium. The thread control method includes: for multiple threads executed by a processor, obtaining the occupation status of the multiple threads on the physical registers in the processor; and in response to the occupation status satisfying the overflow threshold condition, selecting a target thread from the multiple threads, storing the data in at least part of the physical registers occupied by the target thread in an extended memory, and releasing the physical registers whose data are stored in the extended memory for use in other threads among the multiple threads except the target thread. The thread control method can enable multiple threads to share these physical registers under a reasonable number of physical registers, meeting the requirements of main frequency, power consumption, and multi-thread performance.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a thread control method and apparatus, a processor, and a computer-readable storage medium. Background Art

[0002] A modern multi-issue high-performance CPU (Central Processing Unit) includes at least one processor core, and each processor core includes multiple execution units to execute instructions. For example, the pipeline process of instruction execution includes five stages: instruction fetch (IF), decoding (ID), execution (EX), memory access (MEM), and write back (WB, Write Back, updating the result of instruction execution to the register).

[0003] In order to improve the parallelism of instruction execution in the processor, the processor can use simultaneous multithreading (SMT) technology, so that the pipeline structure (also referred to as "pipeline") used for instruction execution in the processor can support two or more (hardware) threads to execute simultaneously. For example, the SMT processor can be SMT2 (supporting up to two concurrent threads), SMT4 (supporting up to four concurrent threads) or SMT8 (supporting up to eight concurrent threads), etc. When a single-threaded processor is running, multiple execution units inside the processor may be idle due to pauses such as cache misses. For processors using SMT technology, even if a thread is paused, other threads can continue to use these hardware resources, which improves the utilization of hardware resources, avoids idling, and improves processor throughput and performance-power ratio.

[0004] In multithreading technology, physical registers are generally shared by multiple threads. The number of physical registers consumed (or occupied) by each thread is generally the number of logical registers of the thread, and there are also free running physical registers during the operation of the processor. Therefore, the number of physical registers actually required in multithreading technology is huge. However, due to the requirements of high main frequency and low power consumption, it is generally difficult to design a physical register stack that can store a large number of entries. This brings challenges to the sharing of physical registers under multithreading. Therefore, how to share these registers with a reasonable number of physical registers becomes a problem that needs to be solved. Summary of the invention

[0005] At least one embodiment of the present disclosure provides a thread control method, comprising: for multiple threads executed by a processor, obtaining the occupation status of the multiple threads on the physical registers in the processor; and in response to the occupancy status satisfying an overflow threshold condition, selecting a target thread from the multiple threads, storing data in at least a portion of the physical registers occupied by the target thread in an extended memory, and releasing the physical registers whose data are stored in the extended memory for use in other threads from the multiple threads except the target thread.

[0006] For example, according to the thread control method of at least one embodiment of the present disclosure, the overflow threshold condition includes a quantity threshold, wherein the quantity threshold is associated with a maximum number of physical registers in the processor that can be occupied by at least some of the multiple threads.

[0007] For example, according to the thread control method of at least one embodiment of the present disclosure, the quantity threshold indicates the maximum number of physical registers in the processor that can be occupied by at least some threads, and the occupancy status of multiple threads on the physical registers in the processor is obtained, including: counting the number of physical registers in the processor occupied by at least some threads.

[0008] For example, according to the thread control method of at least one embodiment of the present disclosure, the number of physical registers in the processor occupied by at least some threads is counted, including: counting the number of valid mappings of each thread in at least some threads, wherein the valid mapping indicates that one logical register corresponds to one valid physical register; and summing the counts as the number of physical registers in the processor occupied by at least some threads.

[0009] For example, according to the thread control method of at least one embodiment of the present disclosure, the quantity threshold indicates the maximum number of physical registers in the processor that can be occupied by some threads or all threads.

[0010] For example, according to at least one embodiment of the present disclosure, the thread control method further includes: in response to the number of physical registers in the processor occupied by at least some threads being greater than or equal to the maximum number, determining that the occupancy state meets the overflow threshold condition.

[0011] For example, according to the thread control method of at least one embodiment of the present disclosure, the overflow threshold condition includes a first time threshold, wherein the first time threshold indicates the longest time that the logical registers of at least some of the multiple threads are not in use, and obtaining the occupancy status of the physical registers in the processor by the multiple threads includes: obtaining the non-occupancy time of the logical registers of at least some of the threads.

[0012] For example, according to at least one embodiment of the present disclosure, the thread control method further includes: in response to obtaining that the non-occupied time of the logical registers of at least part of the threads is greater than or equal to the first time threshold, determining that the occupied state meets the overflow threshold condition.

[0013] For example, according to the thread control method of at least one embodiment of the present disclosure, the logical registers of at least some threads include multiple logical register groups, wherein obtaining the non-occupied time of the logical registers of at least some threads includes: obtaining the non-occupied time of the logical registers in a target logical register group among the multiple logical register groups, and wherein, in response to the occupancy state satisfying the overflow threshold condition, selecting a target thread among the multiple threads, and storing the data in at least some of the physical registers occupied by the target thread in the extended memory, including: in response to the non-occupied time of the logical registers in the target logical register group among the multiple logical register groups being greater than or equal to the first time threshold, selecting the corresponding thread as the target thread, and storing the data in at least some of the physical registers corresponding to the logical registers in the target logical register group of the target thread in the extended memory.

[0014] For example, the thread control method according to at least one embodiment of the present disclosure further includes: in response to the target thread needing to re-execute instructions, filling data from the extended memory into currently available physical registers in the processor.

[0015] For example, according to at least one embodiment of the present disclosure, the thread control method further includes: obtaining the time when the instruction is stopped dispatching, wherein the instruction is stopped dispatching in response to the occupancy state satisfying the overflow threshold condition; and in response to the time when the instruction is stopped dispatching being greater than or equal to a second time threshold, determining that the target thread needs to re-execute the instruction, wherein the second time threshold indicates the minimum time when the instruction corresponding to the target thread needs to be stopped dispatching.

[0016] For example, according to the thread control method of at least one embodiment of the present disclosure, the logical registers of the target thread include multiple logical register groups, wherein, in response to the target thread needing to re-execute instructions, the data are filled from the extended memory into the available physical registers, including: in response to the instruction needing to use the first logical register, only the data corresponding to each logical device in the logical register group where the first logical register is located is filled from the extended memory into the currently available physical register.

[0017] For example, according to the thread control method of at least one embodiment of the present disclosure, the extended memory includes multiple storage addresses, each storage address is dedicated to storing data corresponding to the logical register of a corresponding thread among the multiple threads.

[0018] For example, according to the thread control method of at least one embodiment of the present disclosure, a storage address is accessed through a thread number and a logical register number.

[0019] At least one embodiment of the present disclosure provides a thread control device, comprising: an acquisition module, configured to acquire, for multiple threads executed by a processor, the occupation status of the multiple threads on the physical registers in the processor; and a processing module, configured to select a target thread from the multiple threads in response to the occupation status satisfying an overflow threshold condition, store data in at least part of the physical registers occupied by the target thread into an extended memory, and release the physical registers whose data are stored in the extended memory for use in other threads from the multiple threads except the target thread.

[0020] For example, according to the thread control device of at least one embodiment of the present disclosure, the overflow threshold condition includes a quantity threshold, wherein the quantity threshold is associated with a maximum number of physical registers in the processor that can be occupied by at least some of the multiple threads.

[0021] For example, according to a thread control device of at least one embodiment of the present disclosure, the overflow threshold condition includes a first time threshold, wherein the first time threshold indicates the longest time that the logical registers of at least some of the multiple threads are not used, and the acquisition module includes: a time acquisition module, configured to acquire the non-occupied time of the logical registers of at least some of the threads.

[0022] For example, according to a thread control device of at least one embodiment of the present disclosure, the logical registers of at least some threads include multiple logical register groups, and the time acquisition module includes: a target logical register group time acquisition module, configured to acquire the non-occupied time of the logical registers in the target logical register group among the multiple logical register groups; and the processing module includes: a target thread selection unit, in response to the non-occupied time of the logical registers in the target logical register group among the multiple logical register groups being greater than or equal to the first time threshold, selecting the corresponding thread as the target thread; and an overflow storage control unit, configured to store data in at least some physical registers corresponding to the logical registers in the target logical register group of the target thread into the extended memory.

[0023] For example, according to at least one embodiment of the thread control device of the present disclosure, the processing module further includes: a filling storage control unit configured to fill data from the extended memory into currently available physical registers in the processor in response to the target thread needing to re-execute instructions.

[0024] For example, according to at least one embodiment of the thread control device of the present disclosure, the logical registers of the target thread include multiple logical register groups, and the filling storage control unit includes: a logical register group filling storage control unit, which is configured to fill only the data corresponding to each logical device in the logical register group where the first logical register is located from the extended memory to the currently available physical register in response to an instruction requiring the use of the first logical register.

[0025] For example, according to the thread control device of at least one embodiment of the present disclosure, the extended memory is arranged around the physical registers, and the data in at least part of the physical registers occupied by the target thread can be transmitted through a direct data channel between the extended memory and the physical registers.

[0026] At least one embodiment of the present disclosure provides a thread control device, comprising at least one processing unit and a memory; wherein the memory stores computer-readable instructions and is communicatively connected to at least one processing unit; and at least one processing unit is configured to execute the computer-readable instructions stored in the memory to implement the thread control method as described above.

[0027] At least one embodiment of the present disclosure provides a processor, including the thread control device as described above.

[0028] At least one embodiment of the present disclosure provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-readable instructions, and when a processor executes the computer-readable instructions, the thread control method described above is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments of the present disclosure are briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, and are not intended to limit the present disclosure.

[0030] Figure 1 A schematic diagram showing a pipeline of an exemplary processor core;

[0031] Figure 2 A schematic diagram showing a pipeline of an exemplary processor;

[0032] Figure 3 A schematic diagram showing an exemplary pipeline of a processor involving out-of-order execution and register renaming is shown;

[0033] Figure 4 A flowchart of a thread control method according to at least one embodiment of the present disclosure is shown;

[0034] Figure 5A schematic diagram of a thread control device according to at least one embodiment of the present disclosure is shown;

[0035] Figure 6 A schematic diagram showing another thread control device according to at least one embodiment of the present disclosure is shown;

[0036] 7A to 7E A logical register-physical register mapping table of four threads according to at least one embodiment of the present disclosure is shown;

[0037] Figure 8 A schematic diagram of an anomaly detection module according to at least one embodiment of the present disclosure is shown;

[0038] Fig. 9 A schematic diagram showing a logical register grouping according to at least one embodiment of the present disclosure is shown;

[0039] Fig.10 A schematic diagram showing storage of a thread in an extended memory according to at least one embodiment of the present disclosure is shown;

[0040] Fig.11 A schematic diagram showing another thread control device according to at least one embodiment of the present disclosure is shown;

[0041] Fig.12 A schematic diagram showing a computer-readable storage medium according to at least one embodiment of the present disclosure;

[0042] Fig.13 A schematic diagram of an electronic device according to at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0043] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with specific embodiments, it will be understood that it is not intended to limit the present disclosure to the described embodiments. On the contrary, it is intended to cover changes, modifications and equivalents included within the spirit and scope of the present disclosure as defined by the appended claims. It should be noted that the method operations described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of the two.

[0044] In order to enable those skilled in the art to better understand the present disclosure, the present disclosure is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0045] Note that the examples to be introduced below are only specific examples, and are not intended to limit the embodiments of the present disclosure to the specific shapes, hardware, connection relationships, operations, values, conditions, data, sequences, etc. shown and described. Those skilled in the art can apply the concepts of the present disclosure to construct more embodiments not mentioned in the present description by reading the present description.

[0046] The terms used in the present disclosure are those common terms currently widely used in the art in consideration of the functions of the present disclosure, but these terms may vary according to the intention of a person of ordinary skill in the art, precedents, or new technologies in the art. In addition, specific terms may be selected by the applicant, and in this case, their detailed meanings will be described in the detailed description of the present disclosure. Therefore, the terms used in the specification should not be understood as simple names, but rather as an overall description based on the meaning of the terms and the present disclosure.

[0047] Flowcharts are used in this disclosure to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously as required. At the same time, other operations may also be added to these processes, or one or more operations may be removed from these processes.

[0048] First, the abbreviations and related terms involved in this application are defined and explained.

[0049] Spill out refers to the process of storing data in physical registers into extended memory.

[0050] Fill in refers to the process of filling the data in the extended memory into the physical register.

[0051] It is understandable that the terms defined above are merely exemplary definitions in specific application scenarios to facilitate a better understanding of the present application, and the present disclosure is not limited thereto.

[0052] In order to improve the performance of the processor core, the processor core can use a pipeline approach, that is, the entire process of an instruction from being extracted, decoded, executed, and the result written back is divided into multiple pipeline stages, and an instruction can only be in one of the pipeline stages in one operation cycle; the processor core can run multiple instructions in different pipeline stages.

[0053] Figure 1 A schematic diagram of a pipeline of an exemplary processor core is shown, in which a dotted line with an arrow represents a redirected instruction flow.

[0054] like Figure 1As shown, the processor core (such as CPU core) of a single-core processor or a multi-core processor improves the instruction level parallelism through pipeline technology. The pipeline inside the processor core includes multiple pipeline stages. For example, after the program counters from various sources are fed into the pipeline and the next program counter (PC) is selected through the multiplexer (Mux), the instruction corresponding to the program counter must go through branch prediction, instruction fetch, instruction decoding, instruction dispatch and rename, instruction execution, instruction end, etc. Waiting queues are set between each pipeline stage as needed, and these queues are usually first-in-first-out (FIFO) queues. For example, after the branch prediction unit, a branch prediction (BP) FIFO queue is set to store branch prediction results; after the instruction fetch unit, an instruction cache (IC) FIFO is set to cache the fetched instructions; after the instruction decoding unit, a decoding (DE) FIFO is set to cache the decoded instructions; after the instruction dispatch and rename unit, a termination (RT) FIFO is set to cache the instructions waiting for confirmation after execution. At the same time, the pipeline of the processor core also includes an instruction queue to cache instructions waiting for the instruction execution unit to execute after instruction dispatch and renaming.

[0055] Figure 2 A schematic diagram of a pipeline of an exemplary processor is shown.

[0056] See also Figure 2 , each stage in the pipeline can input 4 instructions in parallel, for example, instructions 1-4 are processed in parallel, instructions 5-8 are processed in parallel, and instructions 9-12 are processed in parallel. Figure 1 In the conventional scalar pipeline shown, the average number of instructions executed per clock cycle is greater than 1, that is, its instruction-level parallelism is greater than 1.

[0057] For example, superscalar processors can further support out-of-order execution. Out-of-order execution refers to the technology that allows the CPU to send multiple instructions to the corresponding circuit units for processing separately without following the order specified by the program. Out-of-order execution involves many algorithms, which are basically designed based on reservation stations. The core idea of ​​reservation stations is to send the instructions after decoding to their respective reservation stations for storage according to their respective instruction types. If all the operands of the instruction are ready, out-of-order transmission can begin.

[0058] Figure 3 A schematic diagram of an exemplary pipeline of a processor involving out-of-order execution and register renaming is shown.

[0059] like Figure 3 As shown, in the processor, after each instruction (such as a branch instruction) is taken out from the instruction cache according to the program counter (PC) ("fetch"), the instruction is decoded ("decoded"); the decoded instruction is subjected to register renaming ("renaming"), and the instruction after register renaming is sent for out-of-order execution to remove the pseudo-correlation between instructions; then the instruction enters the instruction dispatch module, which determines when to dispatch the instruction to which execution unit for execution ("out-of-order scheduling"). For example, in different operation cycles, the instruction will be dispatched to different execution units (such as arithmetic logic unit (ALU), multiplication unit (MUL), division unit (DIV), load and storage unit (LSU), etc.) corresponding to different ports (such as port 0, port 1, port 2, port 3, etc.) for execution. While register renaming is being performed, the instruction will enter the instruction submission unit, which records the original instruction fetch order of the instructions processed in the pipeline. The instruction submission unit is used to submit instructions in the original instruction fetch order after the instructions are executed. At the same time, it will update the actual execution information of the branch instructions to the branch prediction unit.

[0060] As mentioned above, the possible pipeline conflicts of WAW (write after write) and WAR (read after write) can be solved by register renaming technology. This technology does not increase the number of general registers, but redefines the physical registers (PR) inside the processor. The registers defined in the instruction set are called architectural registers (AR). Physical registers actually exist in the processor, for example, they are called physical register files (PRF). The processor will dynamically map the architectural register AR to the physical register PR to solve the problem of WAW and WAR correlation; the processor completes the register renaming process through the architectural register mapping table and the physical register available list. When the processor renames the architectural register used in the current instruction, it needs to process both the source register and the destination register (both logical registers) in the instruction. For the source register, the processor will look up the architectural register mapping table to find the corresponding PR number (PRN). For the destination register, it needs to read a PR number from the physical register available list, establish a mapping relationship between the PR number and the destination register, and write it into the architectural register mapping table. If the free list is empty, the pipeline of the processor needs to pause and wait until an instruction retires and releases the PR. The architecture register mapping table is implemented, for example, by a hardware structure such as a storage device (eg, a cache or a register).

[0061] In addition, in order to improve the parallelism of instruction execution in the processor, the processor can also use simultaneous multithreading (SMT) technology. The pipeline structure of the processor for instruction execution (also referred to as "pipeline") can support two or more (hardware) threads to execute simultaneously, such as SMT2 (supporting up to two concurrent threads), SMT4 (supporting up to four concurrent threads) or SMT8 (supporting up to eight concurrent threads). In the pipeline of a processor that supports simultaneous multithreading technology, the computing resources in the processor are shared by multiple threads. For example, each thread can have its own independent logical register, but the multiple physical registers in the processor are shared by multiple threads; in the queues of various control functions of the pipeline, some can be shared by multiple threads, such as the instruction scheduling queue, and some can be statically divided among multiple threads, such as the instruction reordering queue. Simultaneous multithreading technology can use the parallelism between threads to improve the utilization of pipeline resources.

[0062] In addition, processors that use simultaneous multithreading (SMT) technology can work in SMT mode or single-thread mode. For example, in SMT mode, when one thread encounters a waiting state, other threads can continue to execute, which can effectively improve the utilization of hardware resources and enhance the multi-thread processing capability, overall performance and performance-power ratio of the CPU core.

[0063] In the present disclosure, an "operation cycle" may be, for example, a clock cycle or a machine cycle, or may be other time periods in a processor pipeline for completing an operation. The execution process of an instruction in each thread includes several stages, each of which completes a basic operation (e.g., instruction fetch, memory read, memory write, etc.), and the time required to complete a basic operation is called a machine cycle, also known as a CPU cycle.

[0064] The inventor of the present disclosure has noticed that in the existing multi-threading technology, a larger physical register stack is designed under multi-threading to meet the maximum design requirements, sacrificing the technical solution of frequency and area, or a fixed physical register stack is allocated to each thread, and sharing is not achieved, sacrificing the technical solution of performance. However, the technical solution of designing a larger physical register stack is easy to implement when the number of supported threads is small, but it will sacrifice the main frequency and power consumption under four threads, which will eventually affect the processor performance. Allocating a fixed physical register stack (i.e., a fixed number of registers) to each thread can solve the problem of low frequency, but four threads cannot achieve physical register sharing, which seriously affects the processor performance.

[0065] At least one embodiment of the present disclosure provides a thread control method and apparatus, a processor, and a computer-readable storage medium, which can enable multiple threads to share these physical registers even with a reasonable number of physical registers, thereby meeting the requirements of main frequency, power consumption, and multi-thread performance.

[0066] Figure 4 FIG. 4 is a flowchart of a thread control method 400 according to at least one embodiment of the present disclosure. Figure 4 The described thread control method 400 and additional aspects thereof may be implemented in a thread control device, electronic device, hardware structure, software structure, or a combination of hardware and software as described below.

[0067] See also Figure 4 , the thread control method 400 includes steps S410 to S420.

[0068] In step S410, for a plurality of threads executed by a processor, occupation status of the plurality of threads on physical registers in the processor is obtained.

[0069] In step S420, in response to the occupancy status satisfying the overflow threshold condition, a target thread among the multiple threads is selected, data in at least a portion of the physical registers occupied by the target thread are stored in the extended memory, and the physical registers whose data are stored in the extended memory are released for use by other threads among the multiple threads except the target thread.

[0070] For example, the processor here may be an SMT processor (eg, an SMT4 processor, an SMT8 processor, etc.), so that it can support multiple threads. The "target thread" refers to a thread as a description object, which may be any thread among the multiple threads.

[0071] It can be understood that the execution of instructions requires physical registers, and the “occupancy status” here can be used to indicate or characterize the situation of physical registers that are occupied and not released by a thread in a processor due to the thread in a previous operation cycle.

[0072] As described above, according to at least one embodiment of the present disclosure, the thread control method stores the data in the physical registers of some threads to the extended memory to release these physical registers for use by other threads based on the occupancy status of the physical registers in the processor meeting the overflow threshold condition. In this way, according to at least one embodiment of the present disclosure, the thread control method can enable multiple threads to share these physical registers under a reasonable number of physical registers, meeting the requirements of main frequency, power consumption and multi-thread performance.

[0073] Some exemplary additional aspects of the thread control method according to at least one embodiment of the present disclosure are described below.

[0074] For example, according to the thread control method of at least one embodiment of the present disclosure, the overflow threshold condition includes a quantity threshold, wherein the quantity threshold is associated with a maximum number of physical registers in the processor that can be occupied by at least some of the multiple threads.

[0075] In this way, according to at least one embodiment of the present disclosure, the thread control method can determine whether the occupancy state meets the overflow threshold condition by setting a quantity threshold.

[0076] For example, according to the thread control method of at least one embodiment of the present disclosure, the quantity threshold indicates the maximum number of physical registers in the processor that can be occupied by at least some threads, and the occupancy status of multiple threads on the physical registers in the processor is obtained, including: counting the number of physical registers in the processor occupied by at least some threads.

[0077] In this way, according to at least one embodiment of the present disclosure, the thread control method can determine whether the occupancy state meets the overflow threshold condition by setting a quantity threshold corresponding to the above maximum number.

[0078] For example, according to the thread control method of at least one embodiment of the present disclosure, the number of physical registers in the processor occupied by at least some threads is counted, including: counting the number of valid mappings of each thread in at least some threads, wherein the valid mapping indicates that one logical register corresponds to one valid physical register; and summing the counts as the number of physical registers in the processor occupied by at least some threads.

[0079] In this way, according to at least one embodiment of the present disclosure, the thread control method can obtain the occupancy status by counting the number of valid mappings of the thread.

[0080] For example, according to the thread control method of at least one embodiment of the present disclosure, the quantity threshold indicates the maximum ratio of physical registers in the processor that can be occupied by at least some threads, and the occupancy status of multiple threads on the physical registers in the processor is obtained, including: obtaining the ratio of physical registers in the processor occupied by at least some threads.

[0081] In this way, the thread control method according to at least one embodiment of the present disclosure can determine whether the occupancy state meets the overflow threshold condition by setting a threshold corresponding to the above ratio.

[0082] In some examples, obtaining the ratio of physical registers in a processor occupied by at least some threads may include the following steps: counting the number of physical registers in the processor occupied by at least some threads; and dividing the number by all physical registers of multiple threads of the processor.

[0083] In some examples, the quantity threshold may be set by setting the above-mentioned maximum number or maximum ratio, thereby ensuring the flexibility of setting the quantity threshold.

[0084] For example, according to the thread control method of at least one embodiment of the present disclosure, the quantity threshold indicates the maximum number of physical registers in the processor that can be occupied by some threads or all threads.

[0085] Thus, according to at least one embodiment of the present disclosure, the thread control method can achieve acquisition of occupancy status by setting a quantity threshold for all threads (mode one) or setting a quantity threshold for some threads (mode two).

[0086] In some examples, in an SMT4 processor, the above-mentioned mode 1 and mode 2 may be set, wherein the partial threads of mode 2 may be 2 threads (eg, thread 0 and thread 2, or thread 1 and thread 3, to name a few), or any other number of partial threads.

[0087] For example, according to a thread control method of at least one embodiment of the present disclosure, in response to the number of physical registers in the processor occupied by at least some threads being greater than or equal to the maximum number, it is determined that the occupancy state meets the overflow threshold condition.

[0088] In this way, according to at least one embodiment of the present disclosure, the thread control method can determine whether the occupancy state meets the overflow threshold condition through the obtained number and the maximum number.

[0089] For example, according to the thread control method of at least one embodiment of the present disclosure, in response to the ratio of physical registers in the processor occupied by at least part of the threads being greater than or equal to the maximum ratio, it is determined that the occupancy state meets the overflow threshold condition.

[0090] In this way, the thread control method according to at least one embodiment of the present disclosure can determine whether the occupancy state meets the overflow threshold condition by comparing the obtained ratio with the maximum ratio.

[0091] For example, according to the thread control method of at least one embodiment of the present disclosure, the overflow threshold condition includes a first time threshold, wherein the first time threshold indicates the longest time that the logical registers of at least some of the multiple threads are not in use, and obtaining the occupancy status of the physical registers in the processor by the multiple threads includes: obtaining the non-occupancy time of the logical registers of at least some of the threads.

[0092] Thus, the thread control method according to at least one embodiment of the present disclosure can determine whether the occupied state meets the overflow threshold condition by setting a time threshold. In this way, the thread control method according to at least one embodiment of the present disclosure can release the physical registers of the logical registers that have not been used for a long time for use by other threads.

[0093] For example, according to at least one embodiment of the present disclosure, the thread control method obtains the non-occupied time of the logical registers of at least some threads, including: counting the time that the instructions of at least some threads are not used after being dispatched.

[0094] Thus, according to at least one embodiment of the present disclosure, the thread control method can obtain the non-occupied time of the logical registers of at least some threads. Of course, the embodiment is not limited thereto, for example, the non-occupied time can also be obtained through other components or external indication information.

[0095] For example, according to at least one embodiment of the present disclosure, the thread control method further includes: in response to obtaining that the non-occupied time of the logical registers of at least part of the threads is greater than or equal to the first time threshold, determining that the occupied state meets the overflow threshold condition.

[0096] In this way, the thread control method according to at least one embodiment of the present disclosure can determine whether the occupied state meets the overflow threshold condition by comparing the above-mentioned or absent non-occupied time and the above-mentioned first time threshold.

[0097] For example, according to the thread control method of at least one embodiment of the present disclosure, the logical registers of at least some threads include multiple logical register groups, wherein obtaining the non-occupied time of the logical registers of at least some threads includes: obtaining the non-occupied time of the logical registers in a target logical register group among the multiple logical register groups, and wherein, in response to the occupancy state satisfying the overflow threshold condition, selecting a target thread among the multiple threads, and storing the data in at least some of the physical registers occupied by the target thread in the extended memory, including: in response to the non-occupied time of the logical registers in the target logical register group among the multiple logical register groups being greater than or equal to the first time threshold, selecting the corresponding thread as the target thread, and storing the data in at least some of the physical registers corresponding to the logical registers in the target logical register group of the target thread in the extended memory.

[0098] Thus, the thread control method according to at least one embodiment of the present disclosure stores the corresponding physical register data in the extended memory with the logical register group included in the logical register of the thread as the object. In this way, compared with storing the corresponding physical register data in the extended memory with all the logical registers of the thread as the object, the thread control method according to at least one embodiment of the present disclosure can store the physical register data in the extended memory in a finer granularity, avoid unnecessary occupation of physical registers, and thus further improve the performance of the processor.

[0099] For example, the thread control method according to at least one embodiment of the present disclosure further includes: in response to the target thread needing to re-execute instructions, filling data from the extended memory into currently available physical registers in the processor.

[0100] In this way, according to at least one embodiment of the present disclosure, the thread control method can resume execution of the target thread when the target thread needs to re-execute instructions.

[0101] For example, according to at least one embodiment of the present disclosure, the thread control method further includes: obtaining the time when the instruction is stopped dispatching, wherein the instruction is stopped dispatching in response to the occupancy state satisfying the overflow threshold condition; and in response to the time when the instruction is stopped dispatching being greater than or equal to a second time threshold, determining that the target thread needs to re-execute the instruction, wherein the second time threshold indicates the minimum time when the instruction corresponding to the target thread needs to be stopped dispatching.

[0102] Thus, according to at least one embodiment of the present disclosure, the thread control method can determine that the target thread needs to re-execute instructions by setting a time threshold. However, the embodiment is not limited thereto, for example, other components or external indication information can be used to determine that the target thread needs to re-execute instructions.

[0103] For example, according to the thread control method of at least one embodiment of the present disclosure, the logical registers of the target thread include multiple logical register groups, wherein, in response to the target thread needing to re-execute instructions, the data are filled from the extended memory into the available physical registers, including: in response to the instruction needing to use the first logical register, only the data corresponding to each logical device in the logical register group where the first logical register is located is filled from the extended memory into the currently available physical register.

[0104] Thus, the thread control method according to at least one embodiment of the present disclosure takes the logical register group included in the logical register of the thread as the object to fill the data corresponding to each logic unit from the extended memory into the currently available physical register. In this way, compared with taking all the logical registers of the thread as the object to fill the data corresponding to each logic unit from the extended memory into the currently available physical register, the thread control method according to at least one embodiment of the present disclosure can fill the data required by the instructions to be executed into the available physical registers in a finer granularity, avoid unnecessary occupation of physical registers, and thus further improve the performance of the processor.

[0105] For example, according to the thread control method of at least one embodiment of the present disclosure, the extended memory includes multiple storage addresses, each storage address is dedicated to storing data corresponding to the logical register of a corresponding thread among the multiple threads.

[0106] Thus, according to at least one embodiment of the present disclosure, the thread control method can set a dedicated storage location for the logic of each thread in the extended memory, realize dedicated storage of corresponding data, and avoid misses in data access.

[0107] In some examples, when storing data of a physical register of a certain logical register in the target thread in the extended memory, the data may be stored in a storage address dedicated to the logical register in the extended memory.

[0108] For example, according to the thread control method of at least one embodiment of the present disclosure, a storage address is accessed through a thread number and a logical register number.

[0109] In this way, the thread control method according to at least one embodiment of the present disclosure can achieve simple data access.

[0110] Corresponding to the thread control method 400 according to at least one embodiment of the present disclosure, at least one embodiment of the present disclosure further provides a thread control device.

[0111] Figure 5 A schematic diagram of a thread control device 500 according to at least one embodiment of the present disclosure is shown.

[0112] See also Figure 5 According to at least one embodiment of the present disclosure, a thread control device 500 includes an acquisition module 510 and a processing module 520 .

[0113] The acquisition module 510 is configured to acquire, for multiple threads executed by the processor, occupation states of the multiple threads on physical registers in the processor.

[0114] The processing module 520 is configured to select a target thread from among the multiple threads in response to the occupancy status satisfying an overflow threshold condition, store data in at least a portion of the physical registers occupied by the target thread into an extended memory, and release the physical registers whose data are stored in the extended memory for use in other threads from among the multiple threads except the target thread.

[0115] As described above, the thread control device according to at least one embodiment of the present disclosure stores the data in the physical registers of some threads to the extended memory to release these physical registers for use by other threads based on whether the occupation status of the physical registers in the processor meets the overflow threshold condition. In this way, the thread control device according to at least one embodiment of the present disclosure can enable multiple threads to share these physical registers under a reasonable number of physical registers, thereby meeting the requirements of main frequency, power consumption and multi-thread performance.

[0116] The additional aspects of the thread control device 500 according to at least one embodiment of the present disclosure may correspond to the additional aspects of the thread control method 400 according to at least one embodiment of the present disclosure. For example, the acquisition module 510 and the processing module 520 in the thread control device 500 may be modified or other modules may be added to implement the additional aspects of the thread control method 400 according to at least one embodiment of the present disclosure. Therefore, the technical effects of the additional aspects of the thread control method 400 according to at least one embodiment of the present disclosure may also be mapped to the additional aspects of the thread control device 500 according to at least one embodiment of the present disclosure, and will not be repeated here.

[0117] For example, according to the thread control device of at least one embodiment of the present disclosure, the overflow threshold condition includes a quantity threshold, wherein the quantity threshold is associated with a maximum number of physical registers in the processor that can be occupied by at least some of the multiple threads.

[0118] For example, according to a thread control device of at least one embodiment of the present disclosure, the overflow threshold condition includes a first time threshold, wherein the first time threshold indicates the longest time that the logical registers of at least some of the multiple threads are not used, and the acquisition module includes: a time acquisition module, configured to acquire the non-occupied time of the logical registers of at least some of the threads.

[0119] For example, according to a thread control device of at least one embodiment of the present disclosure, the logical registers of at least some threads include multiple logical register groups, and the time acquisition module includes: a target logical register group time acquisition module, configured to acquire the non-occupied time of the logical registers in the target logical register group among the multiple logical register groups; and the processing module includes: a target thread selection unit, in response to the non-occupied time of the logical registers in the target logical register group among the multiple logical register groups being greater than or equal to the first time threshold, selecting the corresponding thread as the target thread; and an overflow storage control unit, configured to store data in at least some physical registers corresponding to the logical registers in the target logical register group of the target thread into the extended memory.

[0120] For example, according to at least one embodiment of the thread control device of the present disclosure, the processing module further includes: a filling storage control unit configured to fill data from the extended memory into currently available physical registers in the processor in response to the target thread needing to re-execute instructions.

[0121] For example, according to at least one embodiment of the thread control device of the present disclosure, the logical registers of the target thread include multiple logical register groups, and the filling storage control unit includes: a logical register group filling storage control unit, which is configured to fill only the data corresponding to each logical device in the logical register group where the first logical register is located from the extended memory to the currently available physical register in response to an instruction requiring the use of the first logical register.

[0122] For example, according to the thread control device of at least one embodiment of the present disclosure, the extended memory is arranged around the physical registers, and the data in at least part of the physical registers occupied by the target thread can be transmitted through a direct data channel between the extended memory and the physical registers.

[0123] The following describes the above combination with an example application scenario. Figure 4 and Figure 5 It is understood that the example application scenarios described below are only examples and not limitations, and are intended to implement the above combination in specific application scenarios. Figure 4 and Figure 5 One or more aspects of the present invention, and the various aspects described below in conjunction with the example application scenario can be combined with the above Figure 4 and Figure 5 one or more aspects of a combination.

[0124] Figure 6 FIG. 6 is a schematic diagram of another thread control device 600 according to at least one embodiment of the present disclosure. It is understood that the thread control device 600 is only an exemplary thread control device shown in an example application scenario for ease of understanding, and each module therein can be combined, deleted, or added with other modules.

[0125] See also Figure 6 In order to realize the sharing of physical registers of multiple threads (four threads are used as an example below, but the embodiments of the present disclosure are not limited thereto), the thread control device 600 stores the data of the physical registers of a certain thread in the extended memory 606 through the exception detection module 602 (for example, the acquisition module 510 described above may be embodied therein) and the exception handling module 604 (for example, the processing module 520 described above may be corresponding thereto), and releases the physical registers of the thread for use by other threads. After a period of time, when the thread continues to execute instructions, the data is loaded from the extended memory 606 to the physical register file 608. It can be understood that the physical register file may include multiple physical registers. In this example scenario, the extended memory 606 is a temporary cache of the physical register file 608. In some examples, the extended memory 606 may be implemented by registers, static random access memory (SRAM), or a cache in a multiplexed processor architecture.

[0126] The exception detection module 602 detects that, for example, the total number of physical registers currently consumed by four threads reaches a certain threshold (for example, corresponding to the number threshold above), and needs to trigger an exception, and, for example, notifies the exception handling module 604 by generating an exception signal. The exception handling module 604 can, for example, load a microcode program from a microcode program memory 610 to handle the exception. In some examples, the microcode program memory 610 can be a read-only memory (ROM), and these microcode programs are generally fixed and immutable, so that the security of the microcode program can be guaranteed. Of course, the embodiment is not limited to this, and the microcode program memory 610 can be other memories that can store microcode programs.

[0127] The exception handling module 604 stores the data of the physical registers of a certain thread or several threads (such as the target thread described above) in the extended memory (i.e., Spill Out) through, for example, an arbitration algorithm, and releases the physical registers used by the thread. The released physical registers can be used by other threads.

[0128] During the exception handling process, the thread stops dispatching instructions, so that sufficient computing resources can be provided for the thread to be executed.

[0129] When the thread that stops dispatching instructions reaches a certain time, the thread dispatching will continue. At this time, the register data used by the thread is still stored in the extended memory and needs to be moved from the extended register to the physical register stack (i.e. Fill in), and then the thread instructions will continue to be executed.

[0130] The following describes the logical register-physical register mapping table of four threads.

[0131] 7A to 7E A logical register-physical register mapping table of four threads (thread 0 to thread 3) according to at least one embodiment of the present disclosure is shown.

[0132] In this example application scenario, the logic register is embodied as a vector logic register. However, the logic register may not necessarily be embodied as a vector logic register. 7A to 7E , vector logic registers are represented by the first letter v of vector, v0 represents a vector register with a data width of 512-bit, the lower 256-bit is represented by vL0 (vector low), and the higher 256-bit is represented by vH0 (vector high). Each thread has 31 vector logic registers, v0-v31 is divided into lower 256-bit registers (vL0-vL31) and higher 256-bit registers (vH0-vH31).

[0133] from 7A to 7E As can be seen in the figure, each thread has a logical register-physical register mapping table, and each logical register mapping consumes a physical register. For example, the vL0 register of thread 0 consumes the physical register numbered 8. When some physical registers of a thread are released through the Spill out mechanism, the physical register number in the mapping table will become Invalid, indicating that the physical register can be used by other threads, that is, it is available.

[0134] For example, if the physical registers of vL0-vL3 of thread 0 are released, the logical register-physical register mapping table of thread 0 will be changed from Fig. 7A becomes Fig. 7E , where physical registers 8, 9, 16, and 20 can be used by other threads after being released.

[0135] An example of an anomaly detection module is described below.

[0136] Figure 8 A schematic diagram of an anomaly detection module according to at least one embodiment of the present disclosure is shown.

[0137] In this example application scenario, the role of the exception detection module is, for example, to collect information, detect exceptions, and notify the instruction dispatch module to stop dispatching threads. When a thread stops dispatching for a period of time, the thread is notified to continue dispatching.

[0138] Combination Figure 6 and Figure 8 , the register mapping information can be obtained from the register mapping table 612, for example, and the instruction dispatch information 614 can be obtained from the instruction dispatch module. Register valid mapping means that one logical register corresponds to one valid physical register, and at this time, the register valid mapping counter 802 needs to count 1. The register valid mapping counter 802 can count the number of valid mappings of each thread and the number of physical registers consumed by all threads.

[0139] The threshold setting module 804 can set the threshold value of the number of physical registers in different modes. For example, in mode 1, it can be required that the total number of physical registers consumed by the four threads exceeds X before a Spill out exception is triggered, and the total number X (for example, corresponding to the maximum number above) can be set by the threshold setting module. For another example, in mode 2, it can be required that the total number of physical registers consumed by thread 0 and thread 2 reaches Y before a Spill out exception is triggered and / or it can be required that the total number of physical registers consumed by thread 1 and thread 3 reaches Z before a Spill out exception is triggered, and the total numbers Y and Z are set by the threshold setting module. In this way, setting the threshold value of the number of physical registers in different modes can provide a more flexible threshold setting method to adapt to different processor usage environments. For example, if it is detected that there are more programs for threads 0 and 2, and fewer programs for threads 1 and 3, the threshold Y can be set higher and / or the threshold Z can be set lower to favor threads 0 and 2, so that threads 0 and 2 can use more registers, thereby improving the performance of threads 0 and 2.

[0140] The threshold setting module 804 can also set a time threshold for stopping thread dispatch (eg, corresponding to the second time threshold mentioned above). In this way, the performance of the processor can be improved. For example, for threads with sparse instructions, the time for stopping dispatch can be controlled to be longer.

[0141] The comparator 806 may be responsible for comparing the actual consumption of the physical registers with the quantity threshold to determine the Spill out exception. In other aspects, the comparator may be responsible for comparing the actual consumption ratio of the physical registers with the quantity threshold set by the threshold, or may be responsible for comparing the time when the logical register is not used (not occupied) with the time threshold (for example, corresponding to the first time threshold above) to determine the Spill out exception, or the comparator may be responsible for comparing the time when the instruction is stopped from being dispatched with the time threshold (for example, corresponding to the second time threshold above) to determine the Fill in exception. The comparator 806 may determine based on the above comparison that the threshold condition is reached and report the exception type, that is, whether it is a Spill out exception (for example, corresponding to the above occupied state satisfying the overflow threshold condition) or a Fill in exception (for example, corresponding to the above target thread needing to re-execute instructions).

[0142] The arbitrator 808 may determine the thread number to be spilled out and the thread number to be stopped from being dispatched according to an arbitration algorithm. In some examples, the arbitration algorithm may include the least recently used algorithm (LRU), the least recently used algorithm (LFU), or the round robin algorithm (RH).

[0143] After the arbiter 808 sends out the Spill out signal and the stop dispatch signal, the second time counter 810 will be used to count the stop dispatch time. When the second time counter reaches a certain time threshold, the Spill out thread will be notified to continue executing instructions and the Fill in exception handler will be triggered.

[0144] An example of Fill in grouping of logic registers is described below.

[0145] When a thread's logical register is spilled out, if the thread re-executes instructions, it needs to fill in the logical register. Since each fill in of a logical register requires the consumption of a physical register, fill in is done in groups, and only one group of registers is filled in each time (for example, corresponding to the logical register group mentioned above). That is, fill in is done only when the logical register is used, and the group of registers is not filled in when the logical register is not used. In this way, compared with filling in all registers for a thread, filling in groups can provide fine-grained physical register consumption, for example, only a small number of registers that must be used are filled in, avoiding unnecessary occupation of physical registers, thereby further improving processor performance).

[0146] Fig. 9 A schematic diagram of logical register grouping according to at least one embodiment of the present disclosure is shown.

[0147] See also Fig. 9 , an exemplary grouping is: the lower 256-bits of vector registers v0-v15 are group A, the upper 256-bits of v0-v15 are group B, the lower 256-bits of v16-v31 are group C, and the upper 256-bits of v16-v31 are group D (the lower 256-bits of v0-v15 are vL0-vL15, and the lower 256-bits of v16-v31 are vL16-vL31).

[0148] When the logical registers of thread 0 have been spilled out to the extended memory, the exemplary instruction sequence executed at this time is as follows:

[0149] VADD VL0, VL1, VL2 (vector register addition VL0=VL1+VL2)

[0150] At this time, the vL0, vL1, and vL2 vector registers are used, and the vL0, vL1, and vL2 vector registers are located in group A. At this time, the logic registers of group A need to be filled in, while groups B, C, and D do not need to be filled in.

[0151] For another example, execute the following exemplary instruction sequence:

[0152] VADD VL0, VL1, VL16

[0153] At this time, the vL0, vL1, and vL16 vector registers are used, and the vL0, vL1, and vL16 vector registers involve groups A and C. At this time, the logic registers of groups A and C need to be filled in, while groups B and D do not need to be filled in.

[0154] It should be noted that the four logic register groups here are only exemplary, and can be divided into 8 groups, 16 groups or other numbers of logic register groups as needed.

[0155] The following is an example of an exception handling module.

[0156] See also Figure 6 After receiving the exception type from the exception detection module, the exception handling module 604 can give the corresponding exception program type to the microcode program memory to read the microcode program from the microcode program memory 610 and execute the corresponding microinstruction. For example, the exception type is divided into Spill out and Fill in exception types.

[0157] During the Spill Out process, the exception handling module can read the physical register data corresponding to the logical register in a thread into the exception handling module, and then store it in the extended memory. Generally speaking, the physical register is closer to the controller and the arithmetic unit inside the core, while the extended memory is far away from the physical register, and there is no direct data path between the physical register and the extended memory. In other aspects, the microinstructions can include instructions for releasing the physical register. Once the physical register is released, the corresponding position in its mapping table can be set to Invalid.

[0158] The process of Fill in can be considered as the opposite process of Spill out. For example, Fill in can be implemented through the above-mentioned Fill in grouping, while Spill out can be the Spill out of all registers of a certain type of a thread. For another example, Spill out can also be grouped similarly to Fill in grouping, such as the number of logical registers in each group of Spill out grouping is greater than the number of logical registers in each group of Fill in grouping.

[0159] The following is an example of expanding memory.

[0160] The extended memory is used to temporarily save the data of the thread spill out. The fixed address of the memory stores fixed data.

[0161] Fig.10 A schematic diagram showing storage of a thread in an extended memory according to at least one embodiment of the present disclosure is shown.

[0162] See also Fig.10 For example, the value of the vL0 logic register is dedicated to be stored at the location of address 0, the value of the vL1 logic register is dedicated to be stored at the location of address 1, and the value of the vL2 logic register is dedicated to be stored at the location of address 3. In this way, data access can be simplified compared to the random storage employed by, for example, a cache memory.

[0163] In other aspects, the memory can be read according to the thread number and the logical register number, thereby avoiding access misses. It can be understood that other threads can have similar structures in the extended memory.

[0164] An example of mode setting is described below.

[0165] Mode 1 and Mode 2 are mentioned above, and different mode thresholds are configurable. An exemplary description is given below.

[0166] Assuming that each thread consumes 80 physical registers (32 vL0-vL31, 32 vH0-vH31, 8 multimedia registers media0-media7 with a register width of 80 bits, and 8 temp registers) under four threads, four threads consume 320 registers. If each thread has 8 free running physical registers, the physical register stack requires a total of 352 items. However, the actual physical register stack has only 256 items or 192 items.

[0167] Taking a physical register stack with 256 entries as an example, mode 1 can be used: when the total number of physical registers effectively mapped by four threads reaches 248, a thread is triggered to spill out and the thread is stopped from being dispatched for a period of time, and then the thread is released and allowed to execute instructions again. The thread to spill out can be determined by the arbiter mentioned above.

[0168] If mode 2 is adopted: when the total number of valid mapped physical registers of two threads reaches, for example, 144, the Spill out of the two threads is triggered and dispatching of one thread is stopped for a period of time, and then the thread is released and allowed to execute instructions again.

[0169] If a physical register file of 192 entries is used as an example, two threads can be spilled out each time and dispatching of the two threads can be stopped for a period of time.

[0170] Mode setting can improve the utilization of physical registers, thereby improving the performance of multi-threading. For example, mode setting can allow physical registers to be used on threads that must be used, rather than being idle in the mapping table. For example, the execution of microinstructions (uops) of different threads can be detected through hardware logic, and then the information can be sent to the exception detection module, which decides to configure the corresponding mode. In other words, mode setting can be performed through dynamic configuration.

[0171] The following describes the need to Spill out logic registers that have not been used for a long time.

[0172] The exception detection module also has a function of detecting and processing registers that have not been used for a long time (for example, through a first time counter) according to the assigned information, and triggering a corresponding exception to Spill out the register.

[0173] For example, when executing a 256-bit register width program, the multimedia register program has not been used for a long time (this is just an example, does this multimedia register program have any special meaning), but the multimedia register is still mapped in the register mapping table. In this case, the multimedia register needs to be Spilled out to release the occupied physical register resources. For example, after executing a 512-bit register width program, only the 256-bit register width program is executed for a long time, and the high 256 registers of v0-v15 and the high low 256 registers of v16-v31 are not used (the 256-bit register width program only uses group A of the Fill in group). At this time, the registers of groups B, C, and D can be Spilled out to release the occupied physical register resources.

[0174] In this way, the utilization of physical registers is improved, thereby improving the performance of multi-threading. For example, some programs may only use a part of the registers (for example, a program that only supports the AVX2 instruction set will not use the high low of v16-v31 and the high of v0-v15). The registers need to be grouped, and there is no need to spill out the low of v0-v15. After all, frequent Spill out and Fill in will also affect performance.

[0175] In the above example application scenario, the thread control device 600 solves the problem of physical register sharing under multithreading. More specifically, if the number of items in the physical register stack is too large under multithreading, it will seriously reduce the processor's main frequency and increase the power consumption of the processor. The thread control device 600 reduces the number of physical registers used by extending the Spill out and Fill in mechanism of the memory, and at the same time enables the physical register resources to be shared. In addition, the thread control device 600 Spills out the registers that have not been used for a long time, releases the physical register resources, and improves the processor performance.

[0176] In other aspects, in the above example application scenario, a component similar to a memory can be used to expand the physical register file. For example, other storage components are used as backups of the physical register file and placed closer to the physical registers. There is a direct data channel between the physical register file and the expansion component, and instructions are used to realize data movement between the physical register and the expansion component.

[0177] Fig.11 FIG. 1 is a schematic diagram of another thread control device 1100 according to at least one embodiment of the present disclosure.

[0178] like Fig.11 As shown, the thread control device 1100 includes at least one processing unit 1120 and a memory 1110. The memory 1110 stores computer-readable instructions and is in communication with the processing unit 1120. The processing unit 1120 executes the computer-readable instructions stored in the memory 1110 to implement the thread control method and additional aspects thereof according to at least one embodiment of the present disclosure.

[0179] For example, the memory 1110 and the processing unit 1120 may communicate with each other directly or indirectly. Fig.11 As shown, the thread control device 1100 may further include a system bus 1130, and the memory 1110 and the processing unit 1120 may communicate with each other through the system bus 1130. For example, the processing unit 1120 may access the memory 1110 through the system bus 1130. For example, in other examples, the memory 1110 and the processing unit 1120 and other components may communicate through a network on chip (NOC) connection.

[0180] For example, the processing unit 1120 may control other components in the thread control device 1100 to perform desired functions. The processing unit 1120 may be a device having data processing capability and / or program execution capability, such as a central processing unit (CPU), a tensor processing unit (TPU), a network processor (NP), or a graphics processing unit (GPU), and may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0181] For example, the memory 1110 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc.

[0182] For example, one or more computer-readable instructions may be stored on the memory 1110, and the processing unit 1120 may execute the computer-readable instructions to implement various functions. Various applications and various data may also be stored in the computer-readable storage medium, such as instruction processing codes and various data used and / or generated by the application.

[0183] For example, when some computer instructions stored in the memory 1110 are executed by the processing unit 1120 , one or more steps in the thread control method described above can be performed.

[0184] For example, Fig.11 As shown, the thread control device 1100 may also include an input interface 1140 that allows an external device to communicate with the thread control device 1100. For example, the input interface 1140 may be used to receive instructions from an external computer device, from a user, etc. The thread control device 1100 may also include an output interface 1150 that interconnects the thread control device 1100 and one or more external devices. For example, the thread control device 1100 may output commands to the thread control device 1100 through the output interface 1150, etc.

[0185] It should be noted that the thread control device 1100 according to at least one embodiment of the present disclosure is illustrative rather than restrictive. According to actual application requirements, the thread control device 1100 may also include other conventional components or structures. For example, in order to realize the necessary functions of the thread control device, those skilled in the art may set other conventional components or structures according to specific application scenarios, and the embodiments of the present disclosure are not limited to this.

[0186] At least one embodiment of the present disclosure further provides a processor, such as an SMT processor, which includes a thread control device according to at least one embodiment of the present disclosure. The maximum number of threads that can be supported by the SMT processor can be, for example, 2, 4, 8, etc., and can be a single-core or multi-core processor. For example, the processor core can adopt a micro-architecture such as X86, ARM, RISC-V, etc., and can include a first-level or multi-level cache, which is not limited by the embodiments of the present disclosure.

[0187] At least one embodiment of the present disclosure also provides a computer-readable storage medium. Fig.12 A schematic diagram of a computer-readable storage medium 1200 is shown, in accordance with at least one embodiment of the present disclosure.

[0188] For example, Fig.12 As shown, the computer-readable storage medium 1200 stores computer-readable instructions 1210 , and when the computer-readable instructions 1210 are executed by a computer (including a processor), the thread control method and additional aspects thereof according to at least one embodiment of the present disclosure can be implemented.

[0189] For example, one or more computer-readable instructions may be stored on the computer-readable storage medium 1200. Some of the computer-readable instructions stored on the computer-readable storage medium 1200 may be, for example, instructions for implementing one or more steps in the above-mentioned thread control method.

[0190] For example, the computer-readable storage medium may include a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a compact disk read-only memory (CD-ROM), a flash memory, or any combination of the above computer-readable storage media, or other applicable storage media. For example, the computer-readable storage medium 1200 may include the memory 1110 in the above thread control device 1100.

[0191] At least some embodiments of the present disclosure also provide an electronic device. Fig.13 A schematic diagram of an electronic device 1300 is shown in accordance with at least one embodiment of the present disclosure.

[0192] The electronic device according to at least one embodiment of the present disclosure can be implemented as but not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc.

[0193] Fig.13 The electronic device 1300 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0194] For example, Fig.13 As shown, in some examples, the electronic device 1300 includes a processor 1301, which may include a processor of any of the above embodiments (e.g., an SMT processor), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1302 or a program loaded from a storage device 1308 to a random access memory (RAM) 1303. Various programs and data required for the operation of the computer system are also stored in the RAM 1303. The processor 1301, the ROM 1302, and the RAM 1303 are connected to each other via a bus 1304. An input / output (I / O) interface 1305 is also connected to the bus 1304.

[0195] For example, the following components may be connected to the I / O interface 1305: an input device 1306 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1307 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1308 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1309 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 1309 may allow the electronic device 1300 to communicate with other devices wirelessly or by wire to exchange data, performing communication processing via a network such as the Internet. The drive 1310 is also connected to the I / O interface 1305 as needed. Removable media 1311, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., are installed on the drive 1310 as needed, so that the computer program read therefrom can be installed into the storage device 1308 as needed. Although Fig.13 The electronic device 1300 is shown to include various devices, but it should be understood that it is not required to implement or include all of the devices shown. More or fewer devices may be implemented or included instead.

[0196] For example, the electronic device 1300 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 1309 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0197] In addition to the above exemplary descriptions, the following points need to be explained for this disclosure:

[0198] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to the general design.

[0199] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0200] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A thread control method, comprising: For a plurality of threads executed by a processor, obtaining occupation status of physical registers in the processor by the plurality of threads; as well as In response to the occupancy status satisfying an overflow threshold condition, a target thread among the multiple threads is selected, data in at least a portion of the physical registers occupied by the target thread is stored in an extended memory, and the physical registers in which the data is stored in the extended memory are released for use by other threads among the multiple threads except the target thread.

2. The thread control method according to claim 1, wherein: The overflow threshold condition includes a quantity threshold, wherein the quantity threshold is associated with a maximum quantity of physical registers in the processor that can be occupied by at least some of the plurality of threads.

3. The thread control method according to claim 2, wherein the quantity threshold indicates a maximum number of physical registers in the processor that can be occupied by at least part of the threads, and Obtaining occupation status of the multiple threads on the physical registers in the processor includes: The number of physical registers in the processor occupied by at least some of the threads is counted.

4. The thread control method according to claim 3, wherein: Counting the number of physical registers in the processor occupied by at least some of the threads includes: Counting the number of valid mappings for each of the at least some threads, wherein the valid mapping indicates that one logical register corresponds to one valid physical register; and The counts are summed up as the number of physical registers in the processor occupied by at least some of the threads.

5. The thread control method according to claim 3, wherein: The quantity threshold indicates a maximum number of physical registers in the processor that can be occupied by the part of threads or all threads.

6. The thread control method according to claim 3, further comprising: In response to the acquired number of physical registers in the processor occupied by at least part of the threads being greater than or equal to the maximum number, it is determined that the occupancy state satisfies an overflow threshold condition.

7. The thread control method according to claim 1, wherein: The overflow threshold condition includes a first time threshold, wherein the first time threshold indicates a maximum time that a logical register of at least some of the plurality of threads is not used, and Obtaining occupation status of the multiple threads on the physical registers in the processor includes: obtaining non-occupancy time of the logical registers of at least some of the threads.

8. The thread control method according to claim 7, further comprising: In response to obtaining that the non-occupancy time of the logical registers of the at least part of the threads is greater than or equal to a first time threshold, it is determined that the occupancy state meets an overflow threshold condition.

9. The thread control method according to claim 7, wherein: The logical registers of at least part of the threads include a plurality of logical register groups, The step of obtaining the non-occupied time of the logical registers of at least part of the threads includes: obtaining a non-occupied time of a logical register in a target logical register group among the plurality of logical register groups, and In response to the occupancy state satisfying the overflow threshold condition, selecting a target thread from the multiple threads, and storing data in at least a portion of the physical registers occupied by the target thread into the extended memory, comprises: In response to the non-occupancy time of the logical registers in the target logical register group among the multiple logical register groups being greater than or equal to the first time threshold, the corresponding thread is selected as the target thread, and the data in at least part of the physical registers corresponding to the logical registers in the target logical register group of the target thread are stored in the extended memory.

10. The thread control method according to any one of claims 1 to 9, further comprising: In response to the target thread needing to re-execute instructions, the data is filled from the extended memory into currently available physical registers in the processor.

11. The thread control method according to claim 10, further comprising: acquiring a time when the instruction is stopped from being dispatched, wherein the instruction is stopped from being dispatched in response to the occupancy state satisfying an overflow threshold condition; and In response to the time when the instruction is stopped from being dispatched being greater than or equal to a second time threshold, it is determined that the target thread needs to re-execute the instruction, wherein the second time threshold indicates a minimum time when the instruction corresponding to the target thread needs to be stopped from being dispatched.

12. The thread control method according to claim 10, wherein: The target thread's logical registers include a plurality of logical register groups. Wherein, in response to the target thread needing to re-execute instructions, filling the instructions from the extended memory into available physical registers includes: In response to the instruction needing to use a first logical register, only the data corresponding to each logic unit in the logical register group where the first logical register is located is filled from the extended memory into the currently available physical register.

13. The thread control method according to claim 10, wherein: The extended memory includes a plurality of storage addresses, each storage address being dedicated to storing data corresponding to a logic register of a corresponding thread among the plurality of threads.

14. A thread control device, comprising: An acquisition module is configured to acquire, for a plurality of threads executed by a processor, occupation states of physical registers in the processor by the plurality of threads; as well as The processing module is configured to select a target thread from the multiple threads in response to the occupancy state satisfying an overflow threshold condition, store data in at least a portion of the physical registers occupied by the target thread into an extended memory, and release the physical registers in which the data is stored in the extended memory for use in other threads from the multiple threads except the target thread.

15. The thread control device according to claim 14, wherein: The overflow threshold condition includes a first time threshold, wherein the first time threshold indicates a maximum time that a logical register of at least some of the multiple threads is not used, and the acquisition module includes: The time acquisition module is configured to acquire the non-occupied time of the logic registers of at least part of the threads.

16. The thread control device according to claim 15, wherein: The logical registers of at least part of the threads include a plurality of logical register groups, The time acquisition module comprises: a target logic register group time acquisition module configured to acquire a non-occupied time of a logic register in a target logic register group among the plurality of logic register groups; and The processing module comprises: a target thread selection unit, in response to a non-occupancy time of a logical register in a target logical register group among the plurality of logical register groups being greater than or equal to the first time threshold, selecting a corresponding thread as a target thread; and The overflow storage control unit is configured to store data in at least part of the physical registers corresponding to the logical registers in the target logical register group of the target thread into the extended memory.

17. The thread control device according to claim 14, wherein: The processing module also includes: The filling storage control unit is configured to fill the data from the extended memory into the currently available physical register in the processor in response to the target thread needing to re-execute instructions.

18. The thread control device according to claim 17, wherein: The logical register of the target thread includes a plurality of logical register groups, and the filling storage control unit includes: The logical register group filling storage control unit is configured to fill only the data corresponding to each logic unit in the logical register group where the first logical register is located from the extended memory into the currently available physical register in response to the instruction requiring the use of the first logical register.

19. The thread control device according to claim 14, wherein: The extended memory is arranged around the physical registers, and data in at least a portion of the physical registers occupied by the target thread can be transmitted through a direct data channel between the extended memory and the physical registers.

20. A thread control device, comprising at least one processing unit and a memory; wherein: The memory stores computer-readable instructions and is communicatively connected to the at least one processing unit; The at least one processing unit is configured to execute the computer-readable instructions stored in the memory to implement the thread control method according to any one of claims 1-13.

21. A processor, comprising the thread control device according to any one of claims 14-20.

22. A computer-readable storage medium, wherein: The computer-readable storage medium stores computer-readable instructions. When the processor executes the computer-readable instructions, the thread control method according to any one of claims 1 to 13 is implemented.

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