A phase-locked loop, radio frequency transceiver and communication device

Abstract

The application provides a phase-locked loop, a radio frequency transceiver and a communication device, and relates to the technical field of communication, and is used for reducing the power consumption of a communication device in a discontinuous working scene. The phase-locked loop is used for: outputting a first local oscillator signal in a first time period, the phase of the first local oscillator signal at the end moment of the first time period being a first phase; turning off the first local oscillator signal in a second time period; outputting a second local oscillator signal in a third time period, the first time period, the second time period and the third time period being three time periods in sequence, the second local oscillator signal having the same angular frequency as the first local oscillator signal, the phase of the second local oscillator signal at the start moment of the third time period being a second phase, the phase difference between the second phase and the first phase being equal to the product of the angular frequency and a time difference, the time difference being the difference between the start moment of the third time period and the end moment of the first time period. The phase-locked loop is applied to a communication device, and the power consumption of the communication device in a discontinuous working scene can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a phase-locked loop, a radio frequency transceiver and a communication device. BACKGROUND

[0002] In the wireless communication technology, especially in the fifth generation mobile communication, the power consumption of the wireless communication device becomes the main technical problem to be solved. Therefore, how to meet different working scenarios in the communication standard and optimize the working mode of the communication device to reduce the power consumption of the communication device is the main challenge at present. SUMMARY

[0003] The present application provides a phase-locked loop, a radio frequency transceiver and a communication device, which are used to reduce the power consumption of the communication device in the discontinuous working scenario.

[0004] To achieve the above-mentioned purpose, the embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, a phase-locked loop is provided, which is configured to: output a first local oscillator signal in a first time period, the phase of the first local oscillator signal at the end time of the first time period being a first phase; turn off the first local oscillator signal in a second time period; output a second local oscillator signal in a third time period, the first time period, the second time period and the third time period being three time periods in sequence, the second local oscillator signal having the same angular frequency as the first local oscillator signal, the phase of the second local oscillator signal at the start time of the third time period being a second phase, the phase difference between the second phase and the first phase being equal to the product of the angular frequency and a time difference, the time difference being the difference between the start time of the third time period and the end time of the first time period.

[0006] In the above technical solution, the first time period, the second time period and the third time period are three time periods in sequence, the phase-locked loop outputs the first local oscillator signal in the first time period and outputs the second local oscillator signal in the third time period, the phase difference between the second phase of the second local oscillator signal and the first phase of the first local oscillator signal is equal to the product of the angular frequency and the time difference, so as to ensure that the initial phases of the local oscillator signals of the phase-locked loop in the discontinuous working scenario are the same, and since the phase-locked loop does not output the local oscillator signal in the second time period, the power consumption is low, thereby reducing the power consumption of the communication device when the phase-locked loop is applied to the communication device, and realizing the consistency of the channel of the communication device.

[0007] In a possible implementation manner of the first aspect, the time interval in the first time period, the second time period and the third time period is one or more time slots or short time slots. In the above possible implementation manner, the initial phases of the local oscillator signals of the phase-locked loop in the discontinuous multiple time slots or short time slots are the same, and the power consumption is low.

[0008] In a possible implementation manner of the first aspect, the time slot includes 14 symbols or 12 symbols, and the short time slot includes 7 symbols, 6 symbols or 2 symbols. In the possible implementation manners, the number of symbols included in the time slot and the short time slot is provided, and when the phase-locked loop works in discontinuous time slots or short time slots, the accuracy of resource scheduling can be improved.

[0009] In a possible implementation manner of the first aspect, the phase-locked loop includes: a clock control circuit and a local oscillator signal output circuit; the clock control circuit is configured to output a frequency control word according to a reference clock and a feedback clock, and the feedback clock is used for feeding back a first local oscillator signal and a second local oscillator signal respectively; the local oscillator signal output circuit is configured to output the first local oscillator signal and the second local oscillator signal according to the frequency control word and the reference clock respectively; and the local oscillator signal output circuit is not operated in a second time period. In the possible implementation manner, the clock control circuit outputs the frequency control word in three time periods, and the local oscillator signal output circuit outputs the local oscillator signal according to the frequency control word in the first time period and the third time period, so that the initial phases of the local oscillator signals generated by the phase-locked loop in the discontinuous working scenario are the same, and the local oscillator signal output circuit is not operated in the second time period, so that the power consumption is low.

[0010] In a possible implementation manner of the first aspect, the clock control circuit includes: a clock selector and a Sigma-Delta modulator; the clock selector is configured to select one of the feedback clock and the reference clock to output to the Sigma-Delta modulator; and the Sigma-Delta modulator is configured to output the frequency control word according to the feedback clock and the reference clock. In the possible implementation manner, the initial phases of the local oscillator signals generated by the phase-locked loop in the discontinuous working scenario are the same, and the power consumption is low.

[0011] In a possible implementation manner of the first aspect, the local oscillator signal output circuit includes: a phase detector, a loop controller and a controlled oscillator which are coupled in sequence between a first node and a second node, and a feedback frequency divider coupled between the first node and the second node; the first node is coupled with an input end of the local oscillator signal output circuit, and the second node is coupled with an output end of the local oscillator signal output circuit. Optionally, the local oscillator signal output circuit further includes: a local oscillator generator coupled between the second node and the output end. In the possible implementation manner, a simple and effective local oscillator signal output circuit is provided.

[0012] In a possible implementation manner of the first aspect, the phase-locked loop is a digital phase-locked loop. Optionally, the phase detector comprises a time-to-digital converter, the loop controller comprises a digital loop controller, and the controlled oscillator comprises a digitally controlled oscillator. In the possible implementation manner, a simple and effective digital phase-locked loop is provided, which generates an initial phase of a local oscillator signal that is the same in a non-continuous working scenario, and has low power consumption.

[0013] In a possible implementation manner of the first aspect, the phase-locked loop is an analog phase-locked loop. Optionally, the phase detector comprises a frequency discriminator and a charge pump, the loop controller comprises an analog loop controller, and the controlled oscillator comprises a voltage-controlled oscillator. In the possible implementation manner, a simple and effective analog phase-locked loop is provided, which generates an initial phase of a local oscillator signal that is the same in a non-continuous working scenario, and has low power consumption.

[0014] In a possible implementation manner of the second aspect, the clock control circuit comprises a clock selector and a Sigma-Delta modulator; two input terminals of the clock selector are respectively two input terminals of the clock control circuit, an output terminal of the clock selector is coupled to an input terminal of the Sigma-Delta modulator, and an output terminal of the Sigma-Delta modulator is an output terminal of the clock control circuit.

[0015] In a possible implementation manner of the second aspect, the clock selector is configured to select one of the feedback clock and the reference clock to output to the Sigma-Delta modulator, and the Sigma-Delta modulator is configured to output the frequency control word according to the feedback clock or the reference clock.

[0016] In a possible implementation manner of the second aspect, the clock selector is configured to select one of the feedback clock and the reference clock to output to the Sigma-Delta modulator, and the Sigma-Delta modulator is configured to output the frequency control word according to the feedback clock or the reference clock.

[0017] In a possible implementation manner of the second aspect, the first time period, the second time period and the third time period are three time periods that are continuous in sequence, the clock selector is configured to output the feedback clock to the Sigma-Delta modulator in the first time period and the third time period, and output the reference clock to the Sigma-Delta modulator in the second time period; the Sigma-Delta modulator is configured to output the frequency control word according to the feedback clock in the first time period and the third time period, and output the frequency control word according to the reference clock in the second time period. In the second time period, the phase detector, the loop controller, the controlled oscillator, the local oscillator generator and the feedback frequency divider are closed.

[0018] In a possible implementation manner of the second aspect, the phase-locked loop is a digital phase-locked loop. Optionally, the phase detector comprises a time-to-digital converter, the loop controller comprises a digital loop controller, and the controlled oscillator comprises a digital controlled oscillator.

[0019] In a possible implementation manner of the second aspect, the phase-locked loop is a digital phase-locked loop. Optionally, the phase detector comprises a time-to-digital converter, the loop controller comprises a digital loop controller, and the controlled oscillator comprises a digital controlled oscillator.

[0020] In a third aspect, a radio frequency transceiver is provided, comprising: a transmitter comprising a digital-to-analog converter, a first analog processing circuit, a radio frequency modulator, a first phase-locked loop and an amplifier; wherein an output terminal of the digital-to-analog converter is coupled with an input terminal of the first analog processing circuit, an output terminal of the first analog processing circuit and an output terminal of the first phase-locked loop are coupled with two input terminals of the radio frequency modulator respectively, and an output terminal of the radio frequency modulator is coupled with an input terminal of the amplifier; the first phase-locked loop is the phase-locked loop provided in the first aspect, the second aspect or any of the possible implementation manners.

[0021] In a possible implementation manner of the third aspect, the transmitter transmits a signal in the first time period and the third time period, and closes the transmission of the signal in the second time period.

[0022] In a possible implementation manner of the third aspect, the radio frequency transceiver further comprises: a receiver comprising an analog-to-digital converter, a second analog processing circuit, a mixer, a second phase-locked loop and a low noise amplifier; wherein an output terminal of the low noise amplifier and an output terminal of the second phase-locked loop are coupled with two input terminals of the mixer, an output terminal of the mixer is coupled with an input terminal of the second analog processing circuit, and an output terminal of the second analog processing circuit is coupled with an input terminal of the analog-to-digital converter; the second phase-locked loop is the phase-locked loop provided in the first aspect or any of the possible implementation manners of the first aspect.

[0023] In a fourth aspect, a communication device is provided, which comprises a baseband circuit, a radio frequency transceiver and an antenna coupled in sequence, the radio frequency transceiver being the radio frequency transceiver provided in the third aspect or any possible implementation manner of the third aspect.

[0024] In a fifth aspect, a local oscillator signal output method is provided, which comprises: outputting a first local oscillator signal in a first time period, a phase of the first local oscillator signal at an end moment of the first time period being a first phase; turning off the first local oscillator signal in a second time period; outputting a second local oscillator signal in a third time period, the first time period, the second time period and the third time period being three time periods in sequence, the second local oscillator signal being the same as an angular frequency of the first local oscillator signal, a phase of the second local oscillator signal at a start moment of the third time period being a second phase, a phase difference between the second phase and the first phase being equal to a product of the angular frequency and a time difference, the time difference being a difference between the start moment of the third time period and the end moment of the first time period.

[0025] In a possible implementation manner of the fifth aspect, a time interval in the first time period, the second time period and the third time period is one or more time slots or short time slots.

[0026] In a possible implementation manner of the fifth aspect, the time slot comprises 14 symbols or 12 symbols.

[0027] In a possible implementation manner of the fifth aspect, the short time slot comprises 7 symbols, 6 symbols or 2 symbols.

[0028] In a possible implementation manner of the fifth aspect, the phase-locked loop comprises a clock control circuit and a local oscillator signal output circuit, and the method further comprises: the clock control circuit outputs the frequency control word according to the reference clock and a feedback clock; the local oscillator signal output circuit outputs the first local oscillator signal and the second local oscillator signal according to the frequency control word and the reference clock respectively; and the local oscillator signal output circuit does not work in the second time period.

[0029] In a possible implementation manner of the fifth aspect, the clock control circuit comprises a clock selector and a Sigma-Delta modulator, and the clock control circuit outputs the frequency control word according to the reference clock and a feedback clock, comprising: the clock selector selects one of the feedback clock and the reference clock to output to the Sigma-Delta modulator; and the Sigma-Delta modulator outputs the frequency control word according to the feedback clock and the reference clock.

[0030] It can be understood that any one of the above provided phase-locked loop, radio frequency transceiver, communication device and method contains the content of the phase-locked loop provided above, and therefore the beneficial effects that can be achieved can refer to the beneficial effects of the phase-locked loop provided above, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 is a state diagram of a phase-locked loop in a non-continuous working scenario;

[0032] Figure 2 is a schematic diagram of a non-continuous working scenario;

[0033] Figure 3 is a schematic diagram of another non-continuous working scenario;

[0034] Figure 4 is a structural schematic diagram of a radio frequency transceiver provided by the embodiment of the application;

[0035] Figure 5 is a state diagram of a phase-locked loop in a non-continuous working scenario provided by the embodiment of the application;

[0036] Figure 6 is a structural schematic diagram of a phase-locked loop provided by the embodiment of the application;

[0037] Figure 7 is a structural schematic diagram of another phase-locked loop provided by the embodiment of the application;

[0038] Figure 8 is a schematic diagram of a phase-locked loop in a working mode provided by the embodiment of the application;

[0039] Figure 9 is a schematic diagram of a phase-locked loop in another working mode provided by the embodiment of the application;

[0040] Figure 10 is a timing diagram of different signals in a phase-locked loop provided by the embodiment of the application;

[0041] Figure 11 is a structural schematic diagram of a digital phase-locked loop provided by the embodiment of the application;

[0042] Figure 12 is a structural schematic diagram of an analog phase-locked loop provided by the embodiment of the application. DETAILED DESCRIPTION

[0043] The making and using of various embodiments will now be discussed in detail below. It should be appreciated that numerous specific implementation details of the application will be discussed below with reference to one or more embodiments. However, such implementation details should not be construed to limit the scope of the application as described herein, but merely as an example of one implementation. Although specific embodiments have been illustrated and described herein, it should be appreciated that any arrangement which is calculated to achieve the same or similar result could be substituted for the specific embodiments shown. This disclosure is intended to cover any and all adaptations or variations of various embodiments. Therefore, it is manifestly intended that this application be limited only by the following claims.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0045] Circuits or other components can be described as or said to be "configured to" perform one or more tasks. In this context, "configured to" is used to mean that the circuit / component includes structure (e.g., circuitry) that performs the task(s) during operation. As such, the "configured to" can not refer to a structure being specifically adapted to perform the task(s), but that the structure is configured to perform the task(s) during operation. Accordingly, the "configured to" can include a structure that is not specifically adapted to perform the task(s) but that is capable of performing the task(s) during operation.

[0046] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the present application, "at least one" means one or more, and "multiple" means two or more. The "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects. "At least one of the following" or similar expressions means any combination of these items, including any combination of single item or multiple items. For example, at least one of a, b or c can represent a, b, c, a and b, a and c, b and c, or a, b and c, where a, b and c can be singular or plural.

[0047] The embodiments of the present application use "first" and "second" and the like to distinguish objects or functions or roles similar in name or function or role, and those skilled in the art can understand that "first" and "second" and the like do not limit the quantity and execution order. The word "coupled" is used to mean an electrical connection, including direct connection through a wire or connection end or indirect connection through other devices. Therefore, "coupled" should be regarded as a broad sense of electronic communication connection.

[0048] It should be noted that in the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design scheme described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or advantageous than other embodiments or design schemes. Rather, the use of "exemplary" or "for example" is intended to present relevant concepts in a concrete manner.

[0049] In a cellular communication standard, multiple non-continuous working scenarios are defined, i.e., multiple receiving operations or multiple sending operations of a communication device in a non-continuous working scenario are not continuous, but there is a certain idle period. For example, as shown in FIG. 1, three consecutive time slots (TS) are TS1, TS2 and TS3 respectively, and a communication device in a non-continuous working scenario can send service data in TS1 and TS3, and is in an idle state in TS2. Figure 1

[0050] The technical solution provided in the present application can be applied to a communication device including a phase-locked loop and supporting a non-continuous working scenario, which can be a base station and a terminal device. The communication device supporting a non-continuous working scenario can be a communication device that can be in a non-continuous working scenario, and multiple receiving operations or multiple sending operations of the communication device in the non-continuous working scenario are not continuous, but there is a certain idle period. Hereinafter, two non-continuous working scenarios in 5G NR communication are exemplarily described taking a cellular communication standard as an example.

[0051] The first one is a non-continuous working scenario based on symbol-based scheduling.

[0052] In the 5G NR communication standard, in order to adapt to different application scenarios, the scheduling of time-frequency resources by the physical layer is very flexible. In the scheduling of time domain resources, the system defines a symbol-based scheduling with a finer granularity than the traditional slot-based scheduling, which can also be referred to as mini-slot scheduling. Symbol-based scheduling allows only part of the symbols to transmit service data and the other part of the symbols to be in an idle state in a time slot. The symbol-based scheduling method can save time domain resources, and at the same time, for the ultra-reliable low-latency communication (URLLC) communication scenario which has a higher requirement on delay, the sampling symbol-based scheduling also helps to reduce the processing delay of service data.

[0053] Exemplarily, Figure 2 ​A structure diagram of a downlink data frame of a terminal device is shown, the terminal device sequentially receives signals of two time slots (TSs), denoted as TS1 and TS2, each of which includes 14 symbols (Ss), denoted as S1-S14. In each time slot, service data is transmitted on the symbols S1-S7, and the symbols S8-S14 are idle. That is, the terminal device performs a receiving operation in the time of the symbols S1-S7 in each time slot, and does not need to perform a receiving operation in the time of the symbols S8-S14.

[0054] It should be noted that the above Figure 2 takes 14 symbols in each time slot as an example to illustrate the application scenario of symbol-level scheduling, and the above Figure 2 does not limit the embodiments of the present application. In actual applications, the terminal device can also use other formats of downlink data frames, for example, each time slot can include 12 symbols, or each short time slot can include 7 symbols or only 2 symbols, and the embodiments of the present application do not make specific limitations.

[0055] The second is a non-continuous working scenario based on uplink coverage enhancement (UL coverage enhance).

[0056] The uplink coverage enhancement refers to that a receiving end uses multiple uplink time slot demodulation reference signals (DMRSs) for joint estimation to improve the reliability of terminal devices accessing the network in weak signal areas such as cell edges. In the scenario of uplink coverage enhancement, the DMRSs used for joint estimation can be allocated in multiple discontinuous time slots. For example, Figure 3 As shown in FIG. 2, in the three consecutive time slots denoted as TS1-TS3, the DMRS signals for uplink coverage enhancement are located in TS1 and TS3, respectively, TS1 and TS3 are discontinuous, and TS2 between TS1 and TS3 is an idle period.

[0057] In the above two working scenarios, the transmission of service data does not occur continuously, that is, there is an idle state between the transmission of multiple segments of service data. At the same time, the consistency of the communication channel by the communication device often has certain requirements, that is, the channel should be consistent in the effective communication period, and the insertion of the idle period should not affect the consistency of the channel. For the symbol-level scheduling shown in the first working scenario, the transmission channel of the signal should be ensured to be consistent in the time period of S1-S7 in TS1 and S1-S7 in TS2, so as to avoid the terminal device from performing channel estimation on each segment of the transmission signal, and reduce the load caused by the channel estimation operation. For the uplink coverage enhancement shown in the second working scenario, the port position of the sending end should present the same channel characteristics when the DMRS in TS1 and the DMRS in TS3 are sent, so as to ensure the correlation of the DMRS sent in multiple time slots, and thus improve the effectiveness of the uplink joint estimation.

[0058] For the non-continuous working scenario, it is required that the channel of the communication device is consistent in the effective communication period, that is, the insertion of the idle period should not affect the consistency of the channel. In the communication device, the transceiver (TCVR) is a key link for determining the channel characteristics. It is required that the channel of the communication device is consistent, and thus it is necessary to ensure that the initial phase of the local oscillator signal provided by the transceiver does not change in the entire communication process. At present, the method for maintaining the initial phase of the local oscillator signal is specifically as follows: it is ensured that the phase-locked loop providing the local oscillator signal is always in a stable working state in the entire communication process, so as to maintain the initial phase of the local oscillator signal by maintaining the working state of the phase-locked loop. For example, as shown in Figure 1 When the transceiver sends service data in TS1 and TS3 and is in an idle state in TS2, the phase-locked loop in the transceiver is always in a working state in the time period of TS1-TS3, that is, the phase-locked loop continuously outputs the local oscillator signal LO in the time period of TS1-TS3. However, when the communication device in the non-continuous working scenario enters the idle state, the communication device does not perform the sending or receiving operation, and at this time, maintaining the phase-locked loop in a stable working state will cause great power consumption. The structure of the transceiver is taken as an example for illustration.

[0059] The main function of the transceiver is to realize the frequency conversion between the baseband and the radio frequency, and to perform amplification, filtering and other operations on the signal. The structure of the transceiver is taken as an example for illustration.

[0060] Figure 4A structure diagram of a radio frequency transceiver is shown in the embodiments of the present application, which includes at least one transmitter (TX) and at least one receiver (RX) for signal transmission and reception respectively. Figure 4 The radio frequency transceiver includes one transmitter and one receiver as an example.

[0061] In the transmission direction, when the transmitter receives digital baseband data TX_BBI and TX_BBQ, a digital-to-analog converter (DAC) converts the digital baseband data into an analog baseband signal; an analog baseband processor (ABB) processes the analog baseband signal to filter out noise in the analog baseband signal, which can include image signals introduced by digital-to-analog conversion and quantization noise introduced by the DAC; a radio frequency modulator (MOD) mixes the filtered analog baseband signal to convert the analog baseband signal into a radio frequency signal TX_RF, which is amplified by an amplifier (AMP) and the like and then output to an antenna with a certain power, and radiated to the free space through the antenna.

[0062] In the receiving direction, the radio frequency signal RX_RF received by the antenna is processed by front-end devices such as filters and duplexers, and enters the radio frequency receiver, in which a low noise amplifier (LNA) amplifies the radio frequency signal RX_RF; a mixer (MIX) mixes the amplified radio frequency signal to convert the radio frequency signal into an analog baseband signal; the ABB performs low-pass filtering on the analog baseband signal to suppress out-of-band interference or noise, and avoid the sampling aliasing of an analog-to-digital converter (ADC) from deteriorating the signal-to-noise ratio; the ABB can also provide adjustable gain to adjust the amplitude of the analog baseband signal to obtain the desired signal strength at the input end of the ADC; the ADC converts the analog baseband signal into a digital baseband signal and transmits it to a digital signal processing module for further processing.

[0063] In the processing of the transmitter and the receiver, mixing processing is needed. In the transmitter, a radio frequency modulator MOD mixes the received analog baseband signal with a local oscillator signal TX LO generated by a transmit phase locked loop (TX-PLL) to convert the analog baseband signal into a radio frequency signal. In the receiver, a mixer MIX mixes the received radio frequency signal with a local oscillator signal RX LO generated by a receive phase locked loop (RX-PLL) to convert the radio frequency signal into an analog baseband signal.

[0064] Wherein, the influence of the radio frequency transceiver on the channel characteristics can be represented by a transfer function. In the direction of the transmitter, an ideal transmitter satisfies the following formula (1-1); wherein, Re{} is a real function, i.e. taking the real part of a complex value; A TX represents the gain of the transmitter, i.e. the amplitude of the signal strength adjustment of the transmitter; S TX_BB represents the digital baseband signal; S TX_RF represents the radio frequency signal; S TX_LO represents the local oscillator signal of the transmitter.

[0065] S TX_RF = A TX · Re{S TX_BB · S TX_LO} (1-1)

[0066] Wherein, S TX_BB is represented by a complex signal as the following formula (1-2), and is represented by a polar coordinate as the following formula (1-3); S TX_LO is a complex single tone signal, satisfying the following formula (1-4); wherein, A TX_BB (t) represents the amplitude of the analog baseband signal, θ TX_BB (t) represents the phase of the analog baseband signal, ω C represents the angular frequency of the local oscillator signal, represents the phase of the local oscillator signal.

[0067] S TX_BB (t) = S TX_BBI (t) + j· S TX_BBQ (t) (1-2)

[0068]

[0069] Since an ideal local oscillator signal is a complex single tone signal, its initial phase does not change with time, and thus the signal processing of the transmitter can be represented as the following formula (5).

[0070]

[0071] According to equation (1-5), after the processing of the transmitter, the analog baseband signal is shifted to the carrier frequency ω C At the same time, the amplitude and phase of the signal are also adjusted by the transmitter. If only looking at the processing of the useful signal, stripping away the operation of carrier frequency shifting, the ideal transmitter's processing of the useful signal S' TX_RF can be represented as equation (1-6), H TX satisfies equation (1-7).

[0072] S′ TX_RF = S TX_BB · H TX (1-6)

[0073]

[0074] The above H TX can be called the equivalent transfer function of the transmitter, which can be used to reflect the influence of the transmitter on the signal, i.e., changing the amplitude and phase of the signal. From equation (1-7), it can be seen that the initial phase of the transmitter's local oscillator (TX LO) signal is the main source of the transmitter's influence on the phase of the signal.

[0075] Similar to the signal processing of the transmitter, in the direction of the receiver, the processing of the signal by the receiver can be represented by the equivalent transfer function H RX of the receiver, H RX satisfies equation (1-8).

[0076]

[0077] Similar to the equivalent transfer function H TX of the transmitter, A RX in equation (1-8) represents the processing of the amplitude of the received signal by the receiver, represents the processing of the phase of the received signal by the receiver. is the initial phase of the receiver's local oscillator (RX LO) signal. From equation (1-8), it can be seen that the initial phase of the receiver's local oscillator signal is the main source of the receiver's influence on the phase of the signal.

[0078] Therefore, the channel of the communication device in the discontinuous working scenario described above requires consistency, that is, the transmitter equivalent transfer function or the receiver equivalent transfer function representing the characteristics of the radio frequency transceiver does not change at any time point, that is, the processing characteristics of the radio frequency transceiver for signals are not changed. Based on this, for the discontinuous working scenario in the cellular communication system, the embodiment of the present application provides a phase-locked loop, a radio frequency transceiver and a communication device, which can ensure that the initial phase of the local oscillator signal is unchanged in the effective communication time period, so as to ensure that the equivalent transfer function of the transmitter or the receiver does not change, that is, the channel characteristics provided by the radio frequency transceiver are consistent.

[0079] The phase-locked loop provided by the embodiment of the present application has a first working mode and a second working mode. The phase-locked loop works in the first working mode to output the local oscillator signal. The phase-locked loop works in the second working mode to maintain the initial phase of the local oscillator signal and does not output the local oscillator signal. The first working mode can be referred to as a normal working mode, and the second working mode can be referred to as an idle state or a phase maintaining mode.

[0080] The phase-locked loop is introduced and described by taking the working process of the phase-locked loop in three time periods in sequence as an example. As shown in Figure 5 , the three time periods in sequence include a first time period T1, a second time period T2 and a third time period T3. The phase-locked loop is configured to: output a first local oscillator signal LO1 in the first time period T1, the phase of the first local oscillator signal LO1 at the end time of the first time period T1 is a first phase; turn off the first local oscillator signal LO1 in the second time period T2, which can also be referred to as being in an idle state or not outputting the local oscillator signal in the second time period T2; output a second local oscillator signal LO2 in the third time period T3, the second local oscillator signal LO2 has the same angular frequency as the first local oscillator signal LO1, the phase of the second local oscillator signal LO2 at the start time of the third time period T3 is a second phase, and the phase difference between the second phase and the first phase is equal to the product of the angular frequency and a time difference, the time difference is the difference between the start time of the third time period T3 and the end time of the first time period T1. That is, the phase-locked loop works in the first working mode in the first time period T1 and the second time period T2, and works in the second working mode in the second time period T2.

[0081] As shown in Figure 5 , if the start time of the first time period T1 is represented as t0, the end time is represented as t1, the start time of the third time period T3 is represented as t2, and the instantaneous phase of the first local oscillator signal LO1 at the time t0 is (that is, the initial phase of the first local oscillator signal LO1 is ), then the instantaneous phase of the first local oscillator signal LO1 at any time satisfies the following formula (2-1), ω Cω1 represents the angular frequency of the first local signal LO1. Therefore, the instantaneous phase of the first local signal LO1 at the time t1 is and satisfies the formula (2-2), the instantaneous phase at the time t2 is and satisfies the formula (2-3). Therefore, it is ensured that the instantaneous phase of the second local signal LO2 at the time t2 is that is, the phase difference between the second phase of the second local signal LO2 and the first phase of the first local signal LO1 is equal to ω C times (t2-t1).

[0082]

[0083] It should be noted that the phase difference can be in the range of 0 to 2π (2π = 360°), and when the product of ω C is greater than 2π, the product can be expressed as N is an integer, and at this time can be considered as the phase difference between the second phase and the first phase. For example, when the product of ω C is 400° (i.e., 2π+40°), the phase difference between the second phase and the first phase can be considered as 40°.

[0084] Optionally, the time intervals of the above three time periods can be one or more time slots or short time slots, for example, the time intervals of the above three time periods can all be time slots, or the time intervals of the three time periods are all short time slots, or the time intervals of one or two of the three time periods are time slots and the time interval of the other time period is a short time slot. Among them, the time slot can include different numbers of symbols, and the short time slot can also include different numbers of symbols, for example, one time slot can include 14 symbols or 12 symbols, and one short time slot includes 7 symbols, 6 symbols or 2 symbols. The number of symbols included in any two of the above three time periods can be the same or different. The number of symbols included in the time slot and the short time slot is not limited in the embodiments of the present application.

[0085] Specifically, as Figure 6As shown, the phase-locked loop comprises: a clock control circuit 1 and a local oscillator signal output circuit 2. The clock control circuit 1 is configured to receive a reference clock CLK_REF and a feedback clock CLK_DIV, and output a frequency control word NDIV, the feedback clock being configured to feedback a clock of a first local oscillator signal in a first time period and a clock of a second local oscillator signal in a third time period. The local oscillator signal output circuit 2 is configured to output the first local oscillator signal and the second local oscillator signal in the first time period and the third time period respectively according to the frequency control word NDIV and the reference clock CLK_REF; wherein the local oscillator signal output circuit 2 is not working in a second time period.

[0086] In the embodiments of the present application, for the first time period, the second time period and the third time period which are continuous in sequence, the phase-locked loop can output the first local oscillator signal in the first time period and the second local oscillator signal in the third time period, and a phase difference between a second phase of the second local oscillator signal and a first phase of the first local oscillator signal is equal to a product of the angular frequency and the time difference, so as to ensure that the initial phase of the local oscillator signal output by the phase-locked loop in the discontinuous time period is unchanged. In addition, the phase-locked loop is in an idle state in the second time period and does not output the local oscillator signal, so as to save power consumption, and further reduce the power consumption of the communication device when the phase-locked loop is applied to the communication device.

[0087] Further, as shown in Figure 7 The local oscillator signal output circuit 2 comprises: a phase detector (PD) 21, a loop controller (LCT) 22 and a controllable oscillator (OSC) 23 which are coupled in sequence between a first node and a second node, and a feedback frequency divider 24 coupled between the first node and the second node; wherein the first node is coupled with an input end of the local oscillator signal output circuit 2, and the second node is coupled with an output end of the local oscillator signal output circuit 2. Optionally, the local oscillator signal output circuit 2 can further comprise: a local oscillator generator (LOG) 25 coupled between the second node and the output end.

[0088] The phase detector 21 is configured to detect a phase difference between the reference clock CLK_REF and the feedback clock CLK_DIV, and output a detection signal according to the phase difference, the detection signal can be a voltage signal or a current signal. Assuming that the phase of the reference clock CLK_REF is θ REF (t), the phase of the feedback clock is θ DIV (t), and the conversion gain of the phase detector 21 is K PD , then the detection signal E PD(t) satisfies the following equation (2-4).

[0089] E PD (t) = K PD · [θ REF (t) - θ DIV (t)] (2-4)

[0090] The loop controller 22 can also be referred to as a loop filter, and is configured to output a control signal according to a detection signal output by the phase detector 21. The detection signal output by the phase detector 21 can be a voltage signal. The loop controller 22 can be a proportional controller or a proportional-integral controller. Assuming that the loop controller 22 is a proportional-integral controller, the control signal V CTRL (t) output by the loop controller 22 satisfies the following equation (2-5), K I and K P are a proportional gain and an integral gain of the loop controller 22, respectively.

[0091]

[0092] The controlled oscillator 23 is configured to output a local oscillation signal according to the control signal output by the loop controller 22. The local oscillation signal output by the controlled oscillator 23 can be directly used as a local oscillation signal (e.g., a first local oscillation signal or a third local oscillation signal) of the phase-locked loop, or the frequency or amplitude of the local oscillation signal can be processed and then used as a local oscillation signal of the phase-locked loop. Assuming that the control signal output by the loop controller 22 is V CTRL (t) and the conversion gain of the controlled oscillator 23 is K V , the local oscillation signal f OSC (t) output by the controlled oscillator 23 satisfies the following equation (2-6), f0represents the frequency of the control signal V CTRL (t) = 0.

[0093] f OSC (t) = f0+ K V · V CTRL (t) (2-6)

[0094] The feedback frequency divider 24 is configured to divide the local oscillation signal output by the controlled oscillator 23 according to a first frequency control word, to output a feedback clock CLK_DIV. The first frequency control word can also be referred to as a division ratio. Assuming that the division ratio is N DIV , the frequency f DIV (t) of the feedback clock CLK_DIV and the frequency f OSC(t) satisfies the following equation (2-7).

[0095]

[0096] The local oscillator generator 25 is configured to perform further processing on the local oscillator signal output by the feedback frequency divider 24, which can include frequency division processing, frequency multiplication processing, or quadrature processing, etc., and the embodiments of the present application do not make specific limitations thereon.

[0097] Further, as shown in Figure 7 , the clock control circuit 1 includes a clock multiplexer (CMUX) 11 and a Sigam-Delta modulator (SDM) 12. The clock multiplexer 11 is configured to output the feedback clock CLK_DIV to the SDM 12 (i.e., select the feedback clock CLK_DIV as the working clock CLK_SDM of the SDM 12) in the first time period and the third time period, and output the reference clock CLK_REF to the SDM 12 (i.e., select the reference clock CLK_REF as the working clock CLK_SDM of the SDM 12) in the second time period. The SDM 12 is configured to output the frequency division ratio N DIV in the first time period and the third time period according to the second frequency control word FCW and the feedback clock CLK_DIV, and output the frequency division ratio N DIV in the second time period according to the second frequency control word FCW and the reference clock CLK_REF.

[0098] The phase-locked loop can be a fractional-N phase-locked loop, and the SDM 12 is configured to implement the fractional-N function of the phase-locked loop. Assuming that the frequency of the first local oscillator signal or the third local oscillator signal is f LO , the frequency of the reference clock CLK_REF is f REF , and the second frequency control word is N FCW , then N FCW satisfies the following equation (2-8). If N FCW is an integer, the phase-locked loop can not include the SDM 12, and the feedback frequency divider 24 directly implements frequency division according to the frequency division ratio N DIV , in which case the frequency division ratio N DIV is equal to N FCW .

[0099]

[0100] If N FCW is a fraction, the frequency control word N FCWThis is converted into an integer frequency division sequence that can be processed by the feedback frequency divider 24. Assume the second frequency control word N... FCW This indicates that N satisfies formula (2-9). FCW_INTG and N FCW_FRAC N FCW If N contains the integer part and the fractional part, then N FCW After processing by SDM 12, the output shows a series of variations within the range of N. FCW_INTG The nearest integer sequence, i.e., the frequency division ratio N DIV It satisfies formula (2-10). N DIV The range of variation depends on the type of SDM 12.

[0101] N FCW =N FCW_INTG +N FCW_FRAC (2-9)N DIV ∈N FCW_INTG +{…,-2,-1,0,1,2,…}(2-10)

[0102] As shown in formula (2-10), after processing by SDM 12, the feedback divider 24 receives an integer division ratio that varies within a certain range. However, over a long period, the average value of the division ratio received by the feedback divider 24 is the desired second frequency control word, i.e., N. FCW It satisfies formula (2-11).

[0103] N FCW =MEAN{N DIV [i]} (2-11)

[0104] After introducing the specific structure of this phase-locked loop, the following is based on... Figure 7 The operating states of each device in the phase-locked loop under different operating simulations are described in detail. Figure 8 A schematic diagram of the operating states of each device in the phase-locked loop when it is in the first operating mode is shown. The phase detector 21, loop controller 22, controlled oscillator 23, feedback divider 24, local oscillator generator 25, clock selector 11 and SDM 12 are all in the operating state, and the clock selector 11 selects the feedback clock CLK_DIV to output to the SDM 12. Figure 9 The diagram shows the operating states of the various components of the phase-locked loop in the second operating mode, where the phase detector 21, loop controller 22, controlled oscillator 23, feedback divider 24 and local oscillator generator 25 are all off (i.e. not working), the clock selector 11 and SDM 12 are in the working state, and the clock selector 11 selects the reference clock CLK_REF and outputs it to the SDM 12.

[0105] Corresponding to the aboveFigure 8 and Figure 9 The operating status of each device is shown. Figure 10 The timing diagrams shown are for several signals involved in the phase-locked loop under different operating modes. These signals include the reference clock CLK_REF, the feedback clock CLK_DIV, the clock received by SDM12 CLK_SDM, and the division ratio N. DIV It should be noted that, Figure 10 The three consecutive time periods are represented as T1, T2 and T3. The phase-locked loop is in the first working mode in T1 and T3 and in the second working mode in T2. Figure 10 Lieutenant General Frequency Division Ratio N DIV The corresponding integer sequence is represented as N[0], N[1], N[2], ..., N

[16] . This integer sequence is only an example and does not constitute a limitation on the embodiments of this application.

[0106] The operating state of each device in the aforementioned phase-locked loop can be controlled by a processor or a controller. For example, taking the controller controlling the operating state of each device in the phase-locked loop as an example, combined with... Figure 10 The control process of the controller during time periods T1-T3 is described below. Specifically, during time period T1, the controller turns on the phase detector 21, loop controller 22, controlled oscillator 23, feedback divider 24, local oscillator generator 25, clock selector 11, and SDM 12, and controls clock selector 11 to select the feedback clock CLK_DIV output, so that the feedback clock CLK_DIV is used as the working clock of SDM 12; during time period T2, the controller controls clock selector 11 to select the reference clock CLK_REF output, so that the reference clock CLK_REF is used as the working clock of SDM 12, and after the switching is completed, the controller turns off the phase detector 21, loop controller 22, controlled oscillator 23, feedback divider 24, and local oscillator generator 25; during time period T3, the controller turns on the phase detector 21, loop controller 22, controlled oscillator 23, feedback divider 24, local oscillator generator 25, clock selector 11, and SDM 12. SDM 12 is activated and controls clock selector 11 to select the feedback clock CLK_DIV output, so that the feedback clock CLK_DIV is used as the operating clock of SDM 12. During the above process, SDM 12 can continuously and stably output the division ratio N. DIV This ensures that the initial phase of the local oscillator signal output circuit 2 in the phase-locked loop remains unchanged during non-continuous time periods.

[0107] Further, the phase-locked loop is a digital phase-locked loop, which can be a digital fractional-N PLL. In the digital fractional-N PLL, the phase detector 21, the loop controller 22 and the controlled oscillator 23 can be digital circuits for processing or generating digital signals. Specifically, the phase detector 21 is a digital phase detector, which can include a time-to-digital converter (TDC), for example; the loop controller 22 is a digital loop controller; and the controlled oscillator 23 is a digital controlled oscillator (DCO). In one possible embodiment, in combination with Figure 7 As shown in FIG. 2, the digital fractional-N PLL includes a time-to-digital converter 21, a digital loop controller 22, a digital controlled oscillator 23 and a local oscillator generator 25 coupled in series between a first node and an output terminal, a feedback divider 24 coupled between the first node and a second node, and a clock selector 11 and an SDM 12. Figure 11 As shown in FIG. 2, the digital fractional-N PLL includes a time-to-digital converter 21, a digital loop controller 22, a digital controlled oscillator 23 and a local oscillator generator 25 coupled in series between a first node and an output terminal, a feedback divider 24 coupled between the first node and a second node, and a clock selector 11 and an SDM 12.

[0108] Alternatively, the phase-locked loop is an analog phase-locked loop, which can be an analog fractional-N PLL. In the analog fractional-N PLL, the phase detector 21, the loop controller 22 and the controlled oscillator 23 can be analog circuits for processing or generating analog signals. Specifically, the phase detector 21 includes an analog phase detector, which can include a phase-frequency detector (PFD) and a charge pump (CP), for example; the loop controller 22 is an analog loop controller (ALCT); and the controlled oscillator 23 is a voltage controlled oscillator (VCO). In one possible embodiment, in combination with Figure 7 As shown in FIG. 2, the digital fractional-N PLL includes a time-to-digital converter 21, a digital loop controller 22, a digital controlled oscillator 23 and a local oscillator generator 25 coupled in series between a first node and an output terminal, a feedback divider 24 coupled between the first node and a second node, and a clock selector 11 and an SDM 12. Figure 12 As shown in FIG. 2, the digital fractional-N PLL includes a time-to-digital converter 21, a digital loop controller 22, a digital controlled oscillator 23 and a local oscillator generator 25 coupled in series between a first node and an output terminal, a feedback divider 24 coupled between the first node and a second node, and a clock selector 11 and an SDM 12.

[0109] It should be noted that the specific structures of the digital phase-locked loop and the analog phase-locked loop shown above are merely exemplary and do not limit the specific structures of the digital phase-locked loop and the analog phase-locked loop. For example, the digital phase detector in the digital phase-locked loop can also be other digital circuits having the same function as the time-to-digital converter, and the analog phase detector in the analog phase-locked loop can also be other digital circuits having the same function as the analog phase detector composed of the frequency discriminator and the charge pump, and the embodiments of the present application do not make specific limitations thereto.

[0110] Based on this, the embodiments of the present application further provide a radio frequency transceiver, the structure of the radio frequency transceiver is as shown in Figure 4 The radio frequency transceiver includes at least one transmitter, the transmitter includes any one of the phase-locked loops provided above, which can be referred to as a first phase-locked loop; and / or, at least one receiver, the receiver includes any one of the phase-locked loops provided above, which can be referred to as a second phase-locked loop. Figure 4 The radio frequency transceiver includes one transmitter and one receiver as an example.

[0111] Optionally, the transmitter further includes a digital-to-analog converter, a first analog processing circuit, a radio frequency modulator, a first phase-locked loop, and an amplifier; wherein the output end of the digital-to-analog converter is coupled with the input end of the first analog processing circuit, the output end of the first analog processing circuit and the output end of the first phase-locked loop are respectively coupled with two input ends of the radio frequency modulator, and the output end of the radio frequency modulator is coupled with the input end of the amplifier. Further, at least one transmitter closes the output of the transmission signal in the second time period.

[0112] Optionally, the receiver further includes an analog-to-digital converter, a second analog processing circuit, a mixer, a second phase-locked loop, and a low-noise amplifier; wherein the output end of the low-noise amplifier and the output end of the second phase-locked loop are coupled with two input ends of the mixer, the output end of the mixer is coupled with the input end of the second analog processing circuit, and the output end of the second analog processing circuit is coupled with the input end of the analog-to-digital converter.

[0113] It should be noted that the specific description of the phase-locked loop, the transmitter, and the receiver can be referred to the description above, and the embodiments of the present application will not be repeated here.

[0114] Further, when the at least one transmitter comprises multiple transmitters, the multiple transmitters can share one first phase-locked loop or each of the multiple transmitters comprises one first phase-locked loop. When the at least one receiver comprises multiple receivers, the multiple receivers can share one second phase-locked loop or each of the multiple receivers comprises one second phase-locked loop. When the radio frequency transceiver comprises both a transmitter and a receiver, the transmitter and the receiver can share one phase-locked loop or each of the transmitter and the receiver comprises a different phase-locked loop. In practical applications, whether to share a phase-locked loop can be determined by a person skilled in the art according to actual conditions, and embodiments of the present application do not make specific limitations in this regard.

[0115] In another aspect of the present application, a communication device is also provided, which can be a base station or a terminal device. The communication device comprises a baseband circuit, a radio frequency transceiver and an antenna which are coupled in sequence. The radio frequency transceiver is the radio frequency transceiver provided above.

[0116] In another aspect of the present application, a local oscillator signal output method is also provided, which is applied in a phase-locked loop. The method comprises: outputting a first local oscillator signal in a first time period, a phase of the first local oscillator signal at an end time of the first time period is a first phase; turning off the first local oscillator signal in a second time period; outputting a second local oscillator signal in a third time period, the first time period, the second time period and the third time period are three time periods which are continuous in sequence, the second local oscillator signal has the same angular frequency as the first local oscillator signal, a phase of the second local oscillator signal at a start time of the third time period is a second phase, a phase difference between the first phase and the second phase is equal to a product of the angular frequency and a time difference, the time difference is a difference between the start time of the third time period and the end time of the first time period.

[0117] Optionally, the time period in the first time period, the second time period and the third time period is a time slot or a short time slot. In one example, the time slot comprises 14 symbols or 12 symbols. In another example, the short time slot comprises 7 symbols, 6 symbols or 2 symbols.

[0118] Further, the phase-locked loop comprises a clock control circuit and a local oscillator signal output circuit. The method further comprises: the clock control circuit outputs the frequency control word according to the reference clock and a feedback clock, the feedback clock is used for feeding back the first local oscillator signal and the second local oscillator signal respectively; the local oscillator signal output circuit outputs the first local oscillator signal and the second local oscillator signal according to the frequency control word and the reference clock respectively; wherein, the local oscillator signal output circuit does not work in the second time period.

[0119] Further, the clock control circuit comprises a clock selector and a Sigma-Delta modulator.

[0120] Correspondingly, the clock control circuit outputs the frequency control word according to the reference clock and the feedback clock, including: the clock selector selects one of the feedback clock and the reference clock to output to the Sigma-Delta modulator; the Sigma-Delta modulator outputs the frequency control word according to the feedback clock and the reference clock.

[0121] It should be noted that the specific description of each step described above can refer to the related description in the foregoing description, and the embodiments of the present application will not be repeated here.

[0122] In the embodiments of the present application, for the first time period, the second time period and the third time period which are continuous in sequence, the phase-locked loop can output the first local oscillator signal in the first time period, and output the second local oscillator signal in the third time period, and the phase difference between the second phase of the second local oscillator signal and the first phase of the first local oscillator signal is equal to the product of the angular frequency and the time difference, so as to ensure that the initial phase of the local oscillator signal output by the phase-locked loop in the non-continuous time period is unchanged. In addition, the phase-locked loop is in an idle state in the second time period and does not output the local oscillator signal, so as to save power consumption, and further reduce the power consumption of the communication device when the phase-locked loop is applied to the communication device.

[0123] In several embodiments provided in the present application, it should be understood that the different circuits or units disclosed can be implemented in other manners. For example, the above described device embodiments are merely schematic, and the division of the circuit or unit is merely a logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0124] The units described as separate components may or may not be physically separate, and the components shown as units may be one physical unit or multiple physical units, that is, may be located in one place, or may be distributed in multiple different places. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0125] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0126] Finally, it should be noted that the above only describes specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any changes or replacements within the technical scope disclosed by the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A phase-locked loop, characterized in that, The phase-locked loop is used for: The first local oscillator signal is output during the first time period, and the phase of the first local oscillator signal at the end of the first time period is the first phase. The first local oscillator signal is turned off during the second time period; The second local oscillator signal is output in the third time period. The first time period, the second time period, and the third time period are three consecutive time periods. The second local oscillator signal has the same angular frequency as the first local oscillator signal. The phase of the second local oscillator signal at the beginning of the third time period is the second phase. The phase difference between the second phase and the first phase is equal to the product of the angular frequency and the time difference. The time difference is the difference between the beginning of the third time period and the end of the first time period. The phase-locked loop includes: a clock control circuit and a local oscillator signal output circuit; The clock control circuit is used to output a frequency control word according to a reference clock and a feedback clock, wherein the feedback clock is used to feed back the first local oscillator signal and the second local oscillator signal respectively. The local oscillator signal output circuit is used to output the first local oscillator signal and the second local oscillator signal respectively according to the frequency control word and the reference clock; The local oscillator signal output circuit does not operate during the second time period.

2. The phase-locked loop according to claim 1, characterized in that, The time intervals in the first time period, the second time period, and the third time period are one or more time slots or short time slots.

3. The phase-locked loop according to claim 2, characterized in that, The time slot includes 14 symbols or 12 symbols.

4. The phase-locked loop according to claim 2, characterized in that, The short time slot includes 7 symbols, 6 symbols, or 2 symbols.

5. The phase-locked loop according to claim 1, characterized in that, The clock control circuit includes: a clock selector and a Sigm-Delta modulator; The clock selector is used to select one of the feedback clock and the reference clock to output to the Sigam-Delta modulator; The Sigam-Delta modulator is used to output the frequency control word according to the feedback clock and the reference clock.

6. The phase-locked loop according to claim 1 or 5, characterized in that, The local oscillator signal output circuit includes: a phase detector, a loop controller, and a controlled oscillator connected in series between the first node and the second node, and a feedback frequency divider connected between the first node and the second node; The first node is coupled to the input terminal of the local oscillator signal output circuit, and the second node is coupled to the output terminal of the local oscillator signal output circuit.

7. The phase-locked loop according to claim 6, characterized in that, The phase-locked loop is a digital phase-locked loop.

8. The phase-locked loop according to claim 7, characterized in that, The phase detector includes a time-to-digital converter, the loop controller includes a digital loop controller, and the controlled oscillator includes a numerically controlled oscillator.

9. The phase-locked loop according to claim 6, characterized in that, The phase-locked loop is a simulated phase-locked loop.

10. The phase-locked loop according to claim 9, characterized in that, The phase detector includes a frequency and phase detector and a charge pump, the loop controller includes an analog loop controller, and the controlled oscillator includes a voltage-controlled oscillator.

11. The phase-locked loop according to claim 6, characterized in that, The local oscillator signal output circuit further includes a local oscillator generator coupled between the second node and the output terminal.

12. A radio frequency transceiver, characterized in that, The radio frequency transceiver includes: A transmitter includes a digital-to-analog converter, a first analog processing circuit, an radio frequency modulator, a first phase-locked loop, and an amplifier; wherein the output terminal of the digital-to-analog converter is coupled to the input terminal of the first analog processing circuit, the output terminal of the first analog processing circuit and the output terminal of the first phase-locked loop are respectively coupled to the two input terminals of the radio frequency modulator, and the output terminal of the radio frequency modulator is coupled to the input terminal of the amplifier. The first phase-locked loop is the phase-locked loop according to any one of claims 1-11.

13. The radio frequency transceiver according to claim 12, characterized in that, The transmitter transmits signals during the first time period and the third time period, and turns off the transmission signal during the second time period.

14. The radio frequency transceiver according to claim 12 or 13, characterized in that, The radio frequency transceiver also includes: A receiver comprising: an analog-to-digital converter, a second analog processing circuit, a mixer, a second phase-locked loop, and a low-noise amplifier; wherein the output terminal of the low-noise amplifier and the output terminal of the second phase-locked loop are coupled to the two input terminals of the mixer, the output terminal of the mixer is coupled to the input terminal of the second analog processing circuit, and the output terminal of the second analog processing circuit is coupled to the input terminal of the analog-to-digital converter; The second phase-locked loop is the phase-locked loop according to any one of claims 1-11.

15. A communication device, characterized in that, The communication device includes a baseband circuit, a radio frequency transceiver, and an antenna coupled in sequence, wherein the radio frequency transceiver is the radio frequency transceiver described in any one of claims 12-14.

16. A method for outputting a local oscillator signal, characterized in that, The method includes: The first local oscillator signal is output during the first time period, and the phase of the first local oscillator signal at the end of the first time period is the first phase. The first local oscillator signal is turned off during the second time period; The second local oscillator signal is output in the third time period. The first time period, the second time period, and the third time period are three consecutive time periods. The second local oscillator signal has the same angular frequency as the first local oscillator signal. The phase of the second local oscillator signal at the beginning of the third time period is the second phase. The phase difference between the second phase and the first phase is equal to the product of the angular frequency and the time difference. The time difference is the difference between the beginning of the third time period and the end of the first time period. The phase-locked loop includes a clock control circuit and a local oscillator signal output circuit, and the method further includes: The clock control circuit outputs a frequency control word based on the reference clock and the feedback clock, and the feedback clock is used to feed back the first local oscillator signal and the second local oscillator signal respectively. The local oscillator signal output circuit outputs the first local oscillator signal and the second local oscillator signal respectively according to the frequency control word and the reference clock; The local oscillator signal output circuit does not operate during the second time period.

17. The method according to claim 16, characterized in that, The time intervals in the first time period, the second time period, and the third time period are one or more time slots or short time slots.

18. The method according to claim 17, characterized in that, The time slot includes 14 symbols or 12 symbols.

19. The method according to claim 17, characterized in that, The short time slot includes 7 symbols, 6 symbols, or 2 symbols.

20. The method according to claim 16, characterized in that, The clock control circuit includes a clock selector and a Sigm-Delta modulator. The clock control circuit outputs a frequency control word based on the reference clock and the feedback clock, including: The clock selector selects one of the feedback clock and the reference clock and outputs it to the Sigam-Delta modulator; The Sigm-Delta modulator outputs the frequency control word based on the feedback clock and the reference clock.

Images