A method for constructing an analysis library, a method for designing a layout, a system and a storage medium

Abstract

The present invention relates to the field of chip design, and in particular to an analysis library construction method, a design layout method, a system and a storage medium. The analysis library construction method provided by the present invention comprises the following steps: providing standard cells in the design process of the design layout; selecting standard cells to be adjacently set and detecting bad pixel values ​​when the standard cells are adjacent based on a neural network model; collecting bad pixel values ​​to obtain a standard cell analysis library of the standard cells. The present invention uses a neural network model to quickly analyze the bad pixel values ​​when various preset standard cells are adjacently set, and sets the standard cell combination and its corresponding bad pixel value set as a standard cell analysis library. The fast analysis and processing capability of the neural network model is used for analysis, so that the time required to construct the standard cell analysis library is relatively short. At the same time, searching and consulting the standard cell analysis library can quickly and efficiently obtain the bad pixel values ​​when different standard cells are adjacently set.

Description

[Technical field]

[0001] The present invention relates to the field of chip design, and in particular to an analysis library construction method, a design layout method, a system and a storage medium. [Background technology]

[0002] At present, the business model of the semiconductor industry is divided into wafer foundry (FAB) and pure design company (FABLESS). Usually, FABLESS designs the chip and then relies on FAB to realize the production of the chip. The chip design and manufacturing are separated. Of course, when designing the chip, the constraints of the design rules (Design Rule) provided by the manufacturing end will be taken into account, but basically the information exchange between the two sides is limited. With the continuous evolution of process nodes, the integration of devices is getting higher and higher, and the manufacturing difficulty is getting greater and greater. Considering the design rules on the design side cannot guarantee that the manufacturing side can get a good yield. If some stubborn process defects can be fully considered during chip design, the pressure of the process stage can be greatly reduced.

[0003] In the chip lithography design process, there are pre-designed standard cells with specific functions and interfaces that are used and repeated many times. These standard cells can include logic gates, triggers, memory cells, etc. These standard cells represent the basic functional areas in the chip and can be repeatedly arranged throughout the chip to build complex circuits and systems. In chip design, designers can implement the various functions required by the chip by designing standard cells with different functions for layout. This modular design approach can improve design efficiency and simplify the entire chip design process.

[0004] After layout design, bad pixels may occur when standard cells are adjacent to each other. If, during layout, it is known in advance which standard cells are more likely to cause lithography bad pixels when adjacent to each other, the adjacency of such standard cells can be avoided as much as possible during the layout process while keeping other major indicators unaffected.

[0005] However, due to the huge number of standard cells and the huge number of combinations between standard cells, the existing technology cannot quickly and efficiently analyze the bad pixel values ​​between adjacent standard cells, and thus cannot reduce the process bad pixels of chip design by adjusting the settings of standard cells during chip design layout. [Summary of the invention]

[0006] In order to be able to quickly and efficiently obtain the bad pixel values ​​when standard cells are adjacent to each other during layout design in a chip design process, and to reduce the bad pixels in a chip design layout, the present invention provides an analysis library construction method, which comprises the following steps: providing a standard cell and a surrounding environment of a design layout in a design process, setting the surrounding environment adjacent to the standard cell, detecting the bad pixel generation value of the standard cell, filtering the standard cell without bad pixels, and obtaining the remaining standard cells with bad pixels after filtering; selecting the filtered standard cells to be adjacently set and layout to obtain a design layout, providing a neural network model obtained by training according to a photolithography process, obtaining a mask layout corresponding to the design layout by inputting the design layout into the neural network model, obtaining a photoresist profile by simulating the mask layout, checking the bad pixels existing in the photoresist profile by a preset photolithography rule checking program, and obtaining the bad pixel values ​​between the standard cells in the design layout; and collecting the bad pixel values ​​to obtain a standard cell analysis library of the standard cells.

[0007] Preferably, the boundaries of the standard cells are defined based on the lithography influence range of the design layout, and the filtered standard cells are divided into categories according to the boundary shapes of the standard cells; representative standard cells are selected in each category of the standard cells, and the representative standard cells of different categories are selected to be arranged adjacently and the bad pixel values ​​when the standard cells are adjacent are detected based on a neural network model; the bad pixel values ​​are collected and input into a standard cell analysis library.

[0008] In order to solve the above technical problems, the present invention also provides a method for designing a layout, comprising the following steps:

[0009] Provides a standard cell analysis library, sets the standard cell according to the layout algorithm of the design layout to obtain the design layout, and obtains the bad pixel value of the standard cell through the standard cell analysis library.

[0010] A first bad pixel threshold is set. When the bad pixel value of the standard cell is greater than the first bad pixel threshold, the standard cell is reset through a layout algorithm to obtain a new design layout. When the bad pixel value of the standard cell of the new design layout is less than or equal to the first bad pixel threshold, the new design layout is output.

[0011] Preferably, the steps in the layout algorithm include global layout and detailed layout, at least one of the global layout and the detailed layout obtains the bad pixel value of the standard cell through a standard cell analysis library, and when the bad pixel value of the standard cell is greater than a first bad pixel threshold, the standard cell is reset through the global layout and / or detailed layout to obtain a new design layout.

[0012] Preferably, the bad pixel value of the standard cell is obtained through the standard cell analysis library in both the global layout and the detailed layout. When the bad pixel value of the standard cell is greater than the first bad pixel threshold, the standard cell is reset through the global layout and the detailed layout to obtain a new design layout.

[0013] Preferably, the design layout is detected based on the neural network model to obtain the bad pixel value of the design layout; according to the bad pixel value of the design layout, the layout of the standard cells in the design layout is adjusted to obtain a new design layout.

[0014] Preferably, a second bad pixel threshold is set, and when the bad pixel value of the design layout is greater than the second bad pixel threshold, the layout of the standard cells in the design layout is adjusted; the adjusted design layout is re-layouted in detail to obtain a new design layout; the new design layout is iterated, and the bad pixel value of the new design layout is obtained through the neural network model, and when the bad pixel value is less than or equal to the second bad pixel threshold, the new design layout is output.

[0015] In order to solve the above technical problems, the present invention also provides a design layout system, comprising:

[0016] The analysis library module is used to provide standard cells of the design layout during the design process, select the adjacent settings of the standard cells and detect the bad pixel values ​​when the standard cells are adjacent based on the neural network model, and collect the bad pixel values ​​to obtain the standard cell analysis library of the standard cells.

[0017] The layout module is used to set the standard cells according to the layout algorithm of the design layout to obtain the design layout, and obtain the bad pixel value of the standard cells through the standard cell analysis library; set the first bad pixel threshold, when the bad pixel value of the standard cell is greater than the first bad pixel threshold, reset the standard cell through the layout algorithm to obtain a new design layout; when the bad pixel value of the standard cell of the new design layout is less than or equal to the first bad pixel threshold, output the new design layout.

[0018] The present invention also provides a storage medium, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the design layout method is implemented.

[0019] Compared with the prior art, the analysis library component method, design layout method, system and storage medium of the present invention have the following advantages:

[0020] 1. The analysis library construction method provided by the present invention comprises the following steps: providing standard cells in the design process of the design layout; selecting adjacent settings of standard cells and detecting bad pixel values ​​when the standard cells are adjacent based on a neural network model; and collecting bad pixel values ​​to obtain a standard cell analysis library of the standard cells.

[0021] With the continuous improvement of chip scale, integration and process technology, the scale of standard cells required for chip design is huge, and the number of adjacent combination settings between corresponding standard cells is also more. The present invention uses a neural network model to quickly analyze the bad pixel values ​​of various preset standard cells when they are adjacently set, and sets the standard cell combination and its corresponding bad pixel value set as a standard cell analysis library. The fast analysis and processing capability of the neural network model is used for analysis, so that the time required to construct the standard cell analysis library is shorter. At the same time, searching and consulting the standard cell analysis library can quickly and efficiently obtain the bad pixel values ​​of different standard cells when they are adjacently set.

[0022] 2. The analysis library construction method provided by the present invention also includes providing a surrounding environment in the design process of the design layout, setting the surrounding environment adjacent to the standard unit, detecting the bad pixel value generated by the standard unit, filtering the standard units without bad pixels, and obtaining the remaining standard units with bad pixels after filtering.

[0023] The present invention first filters the standard cells, and uses the most commonly used surrounding environment to adjacently place each standard cell. If no bad pixels are generated in this situation, it can be considered that there is a high probability that no potential bad pixels will be generated when it is adjacent to other standard cells during layout. In this way, only the problem of the remaining standard cells being adjacent to each other is considered, thereby reducing the number of standard cell combinations that need to be adjacently analyzed when constructing a standard cell analysis library, and reducing the time required to construct the standard cell analysis library.

[0024] 3. The analysis library construction method provided by the present invention further includes defining the boundaries of the standard cells based on the lithography influence range of the design layout, and classifying the filtered standard cells according to the boundary shapes of the standard cells.

[0025] A representative standard cell is selected in each category of the standard cell, the representative standard cells of different categories are selected to be arranged adjacently, and the bad pixel values ​​when the standard cells are adjacent are detected based on a neural network model.

[0026] The present invention analyzes the lithographic performance produced when different standard cells are adjacent, but the boundary morphology and proximity of the standard cells can be used as a class to participate in the subsequent lithographic performance analysis after the standard cells are adjacent. The present invention analyzes the boundaries of the filtered standard cells, classifies them according to the boundaries, selects representatives from each class to perform adjacent settings and analyzes their bad pixel values, thereby further reducing the number of combinations of standard cell adjacent analysis and reducing the time required to build a standard cell analysis library.

[0027] 4. The present invention also provides a design layout method, which first provides a standard cell analysis library, then sets the standard cells according to the layout algorithm of the design layout to obtain the design layout, and obtains the bad pixel value of the standard cell through the standard cell analysis library; sets a first bad pixel threshold, and when the bad pixel value of the standard cell is greater than the first bad pixel threshold, resets the standard cell through the layout algorithm to obtain a new design layout; when the bad pixel value of the standard cell of the new design layout is less than or equal to the first bad pixel threshold, outputs the new design layout.

[0028] By introducing the standard cell analysis library in the process of setting standard cells in the layout algorithm, the bad pixel situation of the standard cells after layout can be judged, so as to adjust the setting position of the standard cells according to the bad pixel situation, so as to reduce the bad pixels of the design layout obtained after layout.

[0029] 5. The steps in the layout algorithm of the present invention include global layout and detailed layout. At least one of the global layout and the detailed layout obtains the bad pixel value of the standard cell through the standard cell analysis library. When the bad pixel value of the standard cell is greater than the first bad pixel threshold, the standard cell is reset through the global layout and / or detailed layout to obtain a new design layout.

[0030] The present invention obtains bad pixel values ​​of standard cells through a standard cell analysis library in both the global layout and detailed layout processes of a layout algorithm, and then adjusts and optimizes the standard cell positions to obtain a layout result with fewer bad pixels. The optimized global layout result is further optimized and adjusted in the detailed layout, and a design layout with fewer bad pixels is obtained by adjusting the standard cell position layout multiple times.

[0031] 6. After obtaining the optimized and adjusted design layout through the standard cell analysis library, the present invention detects the design layout based on the neural network model to obtain the bad pixel value of the design layout; according to the bad pixel value of the design layout, the layout of the standard cells in the design layout is adjusted to obtain a new design layout, so that the bad pixels of the new design layout can be further reduced.

[0032] 7. The present invention also sets a second bad pixel threshold. When the bad pixel value of the obtained design layout is greater than the second bad pixel threshold, the layout of the standard cells in the design layout is adjusted and then the detailed layout is re-performed to obtain a new design layout. The process is iterated in a loop until the bad pixel value of the design layout is less than or equal to the second bad pixel threshold. Therefore, the present invention can obtain a design layout that meets the bad pixel value requirements according to actual needs.

[0033] 8. The present invention also provides a design layout system, which has the same beneficial effects as the above-mentioned design layout method, and will not be elaborated here.

[0034] 9. The present invention also provides a storage medium on which a computer program is stored. When the computer program is executed, it implements the above-mentioned design layout method and has the same beneficial effects as the above-mentioned design layout method, which will not be elaborated here.

Brief Description of the Drawings

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0036] Figure 1 It is a flowchart of the steps of a method for constructing an analysis library provided in the first embodiment of the present invention.

[0037] Figure 2 It is a flowchart of step S2 in a method for constructing an analysis library provided in the first embodiment of the present invention.

[0038] Figure 3 It is a flowchart of step S1 in a method for constructing an analysis library provided in the first embodiment of the present invention.

[0039] Figure 4 It is an example diagram of a standard unit provided by the first embodiment of the present invention.

[0040] Figure 5 The second embodiment of the present invention provides a method for designing a layout. Figure 1 .

[0041] Figure 6 The second embodiment of the present invention provides a method for designing a layout. Figure 2 .

[0042] Figure 7 It is a structural schematic diagram of a design layout system provided by the third embodiment of the present invention.

[0043] Figure 8 It is a schematic diagram of the structure of a storage medium provided by the fourth embodiment of the present invention.

[0044] Description of the accompanying drawings:

[0045] 1. Design the layout system; 2. Storage media;

[0046] 101, analysis library module; 102, layout module; 201, memory; 202, processor; 203, computer program;

[0047] 301. Standard cell A; 302. Standard cell B; 303. Standard cell C. [Specific implementation method]

[0048] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and implementation examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0049] In chip design, designers can implement various functions required by the chip by designing standard cells with different functions and laying them out. This modular design method can improve design efficiency and simplify the entire chip design process.

[0050] After layout design, bad pixels may occur when standard cells are adjacent to each other. If, during layout, it is known in advance which standard cells are more likely to cause lithography bad pixels when adjacent to each other, the adjacency of such standard cells can be avoided as much as possible during the layout process while keeping other major indicators unaffected.

[0051] However, due to the huge number of standard cells and the huge number of combinations between standard cells, the existing technology cannot quickly and efficiently analyze the bad pixel values ​​between adjacent standard cells, and thus cannot reduce the process bad pixels of chip design by adjusting the settings of standard cells during chip design layout.

[0052] See also Figure 1 In order to solve the above problems, the first embodiment of the present invention provides a method for constructing an analysis library, and the method for constructing an analysis library comprises the following steps:

[0053] S1: Provides standard cells in the design process of the design layout.

[0054] S2: Select the standard cell adjacent setting and detect the bad pixel value when the standard cells are adjacent based on the neural network model.

[0055] S3: Collect bad pixel values ​​to obtain a standard cell analysis library of standard cells.

[0056] With the continuous improvement of chip scale, integration and process technology, the scale of standard cells required for chip design is huge, and the number of adjacent combination settings between corresponding standard cells is also more. The present invention uses a neural network model to quickly analyze the bad pixel values ​​of various preset standard cells when they are adjacently set, and sets the standard cell combination and its corresponding bad pixel value set as a standard cell analysis library. The fast analysis and processing capability of the neural network model is used for analysis, so that the time required to construct the standard cell analysis library is shorter. At the same time, searching and consulting the standard cell analysis library can quickly and efficiently obtain the bad pixel values ​​of different standard cells when they are adjacently set.

[0057] It should be noted that the design layout of a chip refers to the process of converting the logical structure and function of a circuit into a pattern that is actually formed on the surface of the chip during the chip design process. It is similar to a blueprint or drawing of a chip, describing the geometry, arrangement, and interconnection of the circuit. The design layout is usually presented in the form of a two-dimensional plane, which contains the position and layout of each component and / or standard unit (such as transistors, resistors, capacitors, etc.) in the circuit. It reflects information at all levels of the chip, including the wiring of the circuit, the shape and size of the components and / or standard units, the position and arrangement of the pins, and the connection method with other components and / or standard units.

[0058] The process of designing a design layout can usually be summarized into the following steps:

[0059] Circuit design: At the beginning of chip design, designers use circuit design tools to design circuit logic according to requirements and specifications. This includes selecting and designing individual components and / or standard units in the circuit, such as transistors, resistors, capacitors, etc.

[0060] Layout design: After the circuit design is completed, the designer will carry out layout design. Layout design is to plan and arrange the positions of various components and / or standard cells in the circuit on the chip surface to maximize the performance, power consumption, size and other requirements. This stage needs to consider the interconnection and pin positions between components and / or standard cells.

[0061] Wiring design: After the layout design is completed, the designer will carry out wiring design. Wiring design is to plan and route the interconnection lines between various components and / or standard cells to establish the transmission path of the signal in the circuit. This stage needs to consider factors such as signal delay, noise, power consumption, etc., while meeting the design rules and constraints.

[0062] Optimization and verification: After completing the wiring design, the designer will optimize and verify it. By using design verification tools and simulation tools, the design layout is verified to ensure that the functional correctness and performance of the circuit meet the requirements. If necessary, electromagnetic compatibility analysis, power consumption analysis and other steps will be performed.

[0063] Generate layout: Finally, designers use professional layout generation tools to convert the design layout into the specific format required for chip manufacturing. This includes generating data files at various levels, such as mask files, exposure files, etc., for use in subsequent chip manufacturing process steps.

[0064] It can be understood that in step S1, the standard cells required for designing the layout are obtained through the standard cell library. The standard cell library is an important component in chip design, which contains library elements of commonly used logic gates, memory cells and other functional units. The standard cells in the standard cell library are designed to have standardized sizes and ports to facilitate combination and connection in chip design. These standard cells are usually composed of digital logic gates, triggers, latches, multiplexers, adders, etc. According to different chip design requirements, the standard cell library will provide multiple different component types and variants to adapt to different design scenarios.

[0065] See also Figure 3 It can be understood that step S1 of the analysis library construction method provided in the first embodiment also includes the following steps:

[0066] S11: providing a surrounding environment during the design process of the design layout, setting the surrounding environment adjacent to the standard cell, detecting the bad pixel generation value of the standard cell, filtering the standard cells without bad pixels, and obtaining the remaining standard cells with bad pixels after filtering.

[0067] The present invention first filters the standard cells, and sets the standard cells adjacent to the surrounding environment. If no bad pixels are generated in this situation, it can be considered that there is a high probability that no potential bad pixels will be generated when the standard cells are adjacent to other standard cells during layout. In this way, only the problem of the remaining standard cells being adjacent to each other is considered, thereby reducing the number of standard cell combinations that need to be analyzed adjacently when constructing a standard cell analysis library, and reducing the time required to construct the standard cell analysis library.

[0068] It should be noted that the surrounding environment in chip design usually refers to other components, circuits or systems that are closely connected to a specific chip or chip module. It not only includes specific components, but also involves power supply, signal transmission, clock, temperature and other aspects related to these components. Therefore, the surrounding environment includes various specific components, circuits and systems, as well as environmental factors related to them. These components can be power supply systems, clock circuits, sensors, packaging and connectors, etc., which have close interactions and influences with the chip.

[0069] It can be understood that the surrounding environment in step S11 is some commonly used surrounding environments in chip design, and specifically may include the following surrounding environments:

[0070] Clock gate environment: Arrange other related standard units around the clock driving unit to ensure stable transmission of the clock signal and avoid timing problems and clock offset.

[0071] Power / ground environment: Place standard cells that need to be connected to each other to provide stable power and ground connections in adjacent locations to reduce power noise and electrical problems.

[0072] Data path environment: Connect the data path-related standard cells in the circuit to each other and place them in close locations to shorten the signal transmission path and reduce latency.

[0073] Input / output environment: Place input / output units or standard units related to input / output in adjacent locations so that they can be connected to other input / output interfaces and external circuits. By properly designing the surrounding environment, the possibility of adjacent bad points can be effectively reduced, the circuit layout can be optimized, and the performance and reliability of the circuit can be improved.

[0074] It can be understood that step S1 also includes the steps of:

[0075] S12: defining the boundaries of the standard cells based on the lithography influence range of the design layout, and classifying the filtered standard cells according to the boundary shapes of the standard cells.

[0076] S13: Select a representative standard cell in each category of the standard cell, select representative standard cells of different categories to be adjacent to each other, and detect bad pixel values ​​when the standard cells are adjacent to each other based on a neural network model.

[0077] It should be noted that the lithography influence range of a chip refers to the minimum size or spacing that can be achieved by lithography technology during the chip manufacturing process. Lithography is a process that transfers the design pattern to the surface of a chip, which is processed using photoresist and photolithography masks. The lithography machine coats the photoresist on the surface of the chip, then transmits light through the pattern on the photolithography mask for irradiation, and finally removes part of the photoresist through development to form a pattern on the chip. The boundaries of the standard cell need to be determined based on the lithography influence range to ensure that the size of the standard cell is not smaller than the capability of lithography. The boundaries of the standard cell should take into account the resolution of the lithography machine and the performance of the photoresist to ensure that the required circuit structure can be accurately and reliably formed during the manufacturing process.

[0078] Understandably, see Figure 4 In this embodiment, standard cells A301, B302 and C303 are listed, and standard cells A301 and B302 are arranged adjacent to each other, and standard cells B302 and C303 are arranged adjacent to each other. The boundaries of standard cells A301 and C303 are close and they are classified as the same type of standard cells.

[0079] In this embodiment, the lithographic performance generated when different standard cells are adjacent is analyzed. However, some standard cells have similar boundary morphologies among the standard cells. They can be used as a class to participate in the subsequent lithographic performance analysis of the adjacent standard cells. The present invention analyzes the boundaries of the filtered standard cells, classifies them according to the boundaries, selects representatives from each class to perform adjacent settings and analyzes their bad pixel values, thereby further reducing the number of combinations of standard cell adjacent analysis and reducing the time required to build a standard cell analysis library.

[0080] See also Figure 2 It can be understood that step S2 also includes the following steps:

[0081] S21: Select standard cells and set up the layout adjacent to each other to obtain a design layout.

[0082] S22: Provide a neural network model trained according to the photolithography process, and obtain a mask layout corresponding to the design layout by inputting the design layout into the neural network model.

[0083] S23: Obtaining a photoresist profile through mask layout simulation.

[0084] S24: Check the bad pixels existing in the photoresist outline through a preset photolithography rule checking program to obtain the bad pixel values ​​between the standard cells in the design layout.

[0085] It can be understood that in the process of simulation application, the neural network model in step S23 adopts a mechanism of seamless connection with the current OPC tool, so that it can be directly run on the OPC platform, that is, the neural network model is seamlessly embedded in the OPC tool. In the practical use of the OPC tool, since the size of the full chip design layout is very large and cannot be directly processed, the general practice in the industry is to divide the entire chip into many small slices. This neural network model will adopt the same slice division as the OPC tool during simulation. The slice operation size of this neural network model is smaller than the slice operation size of the normal OPC tool. In practice, the slices of the OPC tool will continue to be divided into smaller slices, that is, this neural network model is based on the slices of smaller size during operation, and then the results are spliced ​​together to obtain a sliced ​​result, so that it can be connected with the normal OPC tool results.

[0086] The chip is usually composed of multiple levels of materials and structures, each of which has specific functions and effects. The process of training the neural network model in step S22 is to randomly select a slice in the same layer of the chip design layout, input the mask layout of the slice into the neural network model based on the selected slice, and obtain the corresponding photoresist profile. The trained neural network model is applied to all slices in the same layer of the design layout, and finally the photoresist profile of the design layout is calculated.

[0087] In this embodiment, the photoresist profile corresponding to the design layout can be directly obtained through the neural network model, which greatly improves the speed of obtaining the photoresist profile. At the same time, due to the rapid feedback capability of the neural network model in the lithography simulation, the lithography simulation of the entire design layout can be realized through the neural network model, and the photoresist profile of all positions of the design layout can be obtained. Then, the photoresist profile can be checked through the lithography rule check program, and the bad pixel value of the entire design layout can be checked, that is, the number of bad pixels in the design layout can be obtained.

[0088] It should be noted that Optical Proximity Correction (OPC) is a tool or algorithm used in the chip manufacturing process. It is used to check and optimize chip design to solve the impact and defects introduced by lithography technology. The lithography rule checker is a tool or algorithm used to solve the problems and defects introduced by lithography technology. It plays an important role in improving lithography quality and optimizing chip design in the chip manufacturing process.

[0089] The first embodiment of the present invention reduces the number of standard cells that need to be detected by filtering, boundary clustering and representative combination of standard cells. At the same time, through the rapid feedback capability of the neural network model in the lithography simulation, the photoresist profile corresponding to the design layout can be quickly obtained. The bad pixel value of the design layout can be obtained by detecting the photoresist profile. Due to the rapid feedback capability of the neural network model, this embodiment can detect a huge number of standard cell combinations, and then obtain a standard cell analysis library. The standard cell analysis library can realize the rapid acquisition of bad pixel values ​​when different standard cells are set adjacent to each other.

[0090] See also Figure 5 In order to solve the above problems, the second embodiment of the present invention further provides a layout design method, which includes the following steps:

[0091] K1: Provide the standard cell analysis library of the first embodiment described above.

[0092] K2: Set the standard cells according to the layout algorithm of the design layout to obtain the design layout, and obtain the bad pixel value of the standard cell through the standard cell analysis library.

[0093] K3: Provide a preset first bad pixel threshold. When the bad pixel value of the standard cell is greater than the first bad pixel threshold, the standard cell is iteratively set through the layout algorithm to obtain a new design layout. When the bad pixel value of the standard cell of the new design layout is less than or equal to the first bad pixel threshold, the new design layout is output.

[0094] This second embodiment introduces a standard cell analysis library in the process of setting standard cells by the layout algorithm, so as to judge the bad pixel situation of the standard cells after layout, and adjust the setting position of the standard cells according to the bad pixel situation, so as to reduce the bad pixels of the design layout obtained after layout.

[0095] See also Figure 6 It can be understood that the layout algorithm in step K2 of this embodiment includes the following steps:

[0096] K21: Global layout.

[0097] K22: Detailed layout.

[0098] In step K2, in at least one of the global layout and detailed layout of the layout algorithm, a bad pixel value of the standard cell is obtained through a standard cell analysis library. When the bad pixel value of the standard cell is greater than a first bad pixel threshold, the standard cell is reset through the global layout and / or detailed layout to obtain a new design layout.

[0099] It can be understood that the second embodiment obtains the bad pixel value of the standard cell through the standard cell analysis library in both the global layout and detailed layout processes of the layout algorithm, and then adjusts and optimizes the standard cell position to obtain a layout result with fewer bad pixels. The optimized global layout result is further optimized and adjusted in the detailed layout, and a design layout with fewer bad pixels is obtained by adjusting the standard cell position layout multiple times.

[0100] It should be noted that the layout algorithm of chip design usually includes two stages: global layout and detailed layout.

[0101] Global layout: In the global layout stage, the design tool will make a preliminary layout of each standard unit on the chip according to the design specifications and constraints to achieve the goals of reducing delay, minimizing area, and reducing power consumption. The global layout aims to determine the approximate location of each standard unit, while considering the overall layout style and chip structure, in preparation for the subsequent detailed layout.

[0102] Detailed layout: In the detailed layout stage, the design tool will optimize and refine the preliminary layout results obtained by the global layout. Detailed layout is mainly based on the global layout to further optimize the performance of the circuit, including reducing signal transmission delay, reducing circuit power consumption, optimizing wiring length, etc. This stage usually considers more detailed constraints and limitations of chip physical implementation to achieve the final layout design goals. Through the design of the two stages of global layout and detailed layout, the design tool can effectively optimize the performance of the chip design and ensure that the final layout meets the design requirements and constraints.

[0103] Please refer to Figure 5 and Figure 6It can be understood that the second embodiment further includes step K4, which specifically includes the following steps:

[0104] K41: Detect the design layout based on the neural network model and obtain the bad pixel value of the design layout.

[0105] K42: Set the second bad pixel threshold. When the bad pixel value of the obtained design layout is greater than the second bad pixel threshold, adjust the layout of the standard cells in the design layout and then re-perform detailed layout to obtain a new design layout.

[0106] K43: This process is iterated repeatedly until the bad pixel value of the design layout is less than or equal to the second bad pixel threshold.

[0107] It should be noted that adjusting the design layout can locally fine-tune the layout results. Such fine-tuning methods are very mature in current layout tools. For example, cell flip, cell shift, cell permutation, filler insertion, etc. can all be used to fine-tune the layout results to resolve the bad points found by the neural network model.

[0108] According to the bad pixel value of the design layout, the layout of the standard cells in the design layout is adjusted to obtain a new design layout, so that the bad pixels of the new design layout can be further reduced, so that the present invention can obtain a design layout that meets the bad pixel value requirements according to actual needs.

[0109] See also Figure 7 In order to solve the above technical problems, the third embodiment of the present invention further provides a design layout system 1, comprising:

[0110] The analysis library module 101 is used to provide standard cells required for designing layout, select adjacent settings of standard cells and detect bad pixel values ​​when standard cells are adjacent based on a neural network model, and collect bad pixel values ​​to obtain a standard cell analysis library of standard cells.

[0111] The layout module 102 is used to set the standard cells according to the layout algorithm of the design layout to obtain the design layout, and obtain the bad pixel value of the standard cells through the standard cell analysis library; set the first bad pixel threshold, when the bad pixel value of the standard cell is greater than the first bad pixel threshold, reset the standard cell through the layout algorithm to obtain a new design layout; when the bad pixel value of the standard cell of the new design layout is less than or equal to the first bad pixel threshold, output the new design layout.

[0112] A design layout system 1 provided by the present invention has the same beneficial effects as the above-mentioned design layout method, which will not be described in detail here.

[0113] See also Figure 8The fourth embodiment of the present invention further provides a storage medium 2, which includes a memory 201, a processor 202, and a computer program 203 stored in the memory 201 and executable on the processor 202. When the processor 202 executes the computer program 203, the above-mentioned design layout method is implemented. The storage medium 2 has the same beneficial effects as the above-mentioned design layout method, which will not be elaborated herein.

[0114] It can be understood that according to the embodiments disclosed in the present invention, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments of the present disclosure include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication part, and / or installed from a removable medium. When the computer program is executed by the central processing unit (CPU), the above functions defined in the method of the present application are executed. It should be noted that the computer-readable medium described in the present application can be a computer-readable signal medium or a computer-readable storage medium or a combination of the above two. Computer-readable storage media, for example, include but are not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or a combination of the above. More specific examples of computer-readable storage media may include but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or a suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, apparatus, or device. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or a suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to: wireless, wire, optical cable, RF, etc., or a suitable combination of the above.

[0115] The computer program code for performing the operation of the present application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and also conventional procedural programming languages ​​such as "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on the remote computer, or completely on the remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through a variety of networks including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., using an Internet service provider to connect through the Internet).

[0116] In the embodiments provided by the present invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B according to A does not mean determining B only according to A, and B can also be determined according to A and / or other information.

[0117] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in a suitable manner. Those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0118] In various embodiments of the present invention, it should be understood that the size of the serial numbers of the above-mentioned processes does not mean the necessary order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0119] The flow chart and block diagram in the accompanying drawings of the present invention illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which is determined based on the functions involved. It should be particularly noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs a specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0120] Compared with the prior art, the analysis library component method, design layout method, system and storage medium of the present invention have the following advantages:

[0121] 1. The analysis library construction method provided by the present invention comprises the following steps: providing standard cells of a design layout in a design process; selecting adjacent settings of standard cells and detecting bad pixel values ​​when the standard cells are adjacent based on a neural network model; and collecting bad pixel values ​​to obtain a standard cell analysis library of the standard cells.

[0122] With the continuous improvement of chip scale, integration and process technology, the scale of standard cells required for chip design is huge, and the number of adjacent combination settings between corresponding standard cells is also more. The present invention uses a neural network model to quickly analyze the bad pixel values ​​of various preset standard cells when they are adjacently set, and sets the standard cell combination and its corresponding bad pixel value set as a standard cell analysis library. The fast analysis and processing capability of the neural network model is used for analysis, so that the time required to construct the standard cell analysis library is shorter. At the same time, searching and consulting the standard cell analysis library can quickly and efficiently obtain the bad pixel values ​​of different standard cells when they are adjacently set.

[0123] 2. The analysis library construction method provided by the present invention also includes providing the surrounding environment of the design layout during the design process, setting the surrounding environment adjacent to the standard unit, detecting the bad pixel values ​​of the standard unit, filtering the standard units without bad pixels, and obtaining the remaining standard units with bad pixels after filtering.

[0124] The present invention first filters the standard cells, and uses the most commonly used surrounding environment to adjacently place each standard cell. If no bad pixels are generated in this situation, it can be considered that there is a high probability that no potential bad pixels will be generated when it is adjacent to other standard cells during layout. In this way, only the problem of the remaining standard cells being adjacent to each other is considered, thereby reducing the number of standard cell combinations that need to be adjacently analyzed when constructing a standard cell analysis library, and reducing the time required to construct the standard cell analysis library.

[0125] 3. The analysis library construction method provided by the present invention further includes defining the boundaries of the standard cells based on the lithography influence range of the design layout, and classifying the filtered standard cells according to the boundary shapes of the standard cells.

[0126] A representative standard cell is selected in each category of the standard cell, the representative standard cells of different categories are selected to be arranged adjacently, and the bad pixel values ​​when the standard cells are adjacent are detected based on a neural network model.

[0127] The present invention analyzes the lithographic performance produced when different standard cells are adjacent, but the boundary morphology and proximity of the standard cells can be used as a class to participate in the subsequent lithographic performance analysis after the standard cells are adjacent. The present invention analyzes the boundaries of the filtered standard cells, classifies them according to the boundaries, selects representatives from each class to perform adjacent settings and analyzes their bad pixel values, thereby further reducing the number of combinations of standard cell adjacent analysis and reducing the time required to build a standard cell analysis library.

[0128] 4. The present invention also provides a design layout method, which first provides a standard cell analysis library, then sets the standard cells according to the layout algorithm of the design layout to obtain the design layout, and obtains the bad pixel value of the standard cell through the standard cell analysis library; sets a first bad pixel threshold, and when the bad pixel value of the standard cell is greater than the first bad pixel threshold, resets the standard cell through the layout algorithm to obtain a new design layout; when the bad pixel value of the standard cell of the new design layout is less than or equal to the first bad pixel threshold, outputs the new design layout.

[0129] By introducing the standard cell analysis library in the process of setting standard cells in the layout algorithm, the bad pixel situation of the standard cells after layout can be judged, so as to adjust the setting position of the standard cells according to the bad pixel situation, so as to reduce the bad pixels of the design layout obtained after layout.

[0130] 5. The steps in the layout algorithm of the present invention include global layout and detailed layout. At least one of the global layout and the detailed layout obtains the bad pixel value of the standard cell through the standard cell analysis library. When the bad pixel value of the standard cell is greater than the first bad pixel threshold, the standard cell is reset through the global layout and / or detailed layout to obtain a new design layout.

[0131] The present invention obtains bad pixel values ​​of standard cells through a standard cell analysis library in both the global layout and detailed layout processes of a layout algorithm, and then adjusts and optimizes the standard cell positions to obtain a layout result with fewer bad pixels. The optimized global layout result is further optimized and adjusted in the detailed layout, and a design layout with fewer bad pixels is obtained by adjusting the standard cell position layout multiple times.

[0132] 6. After obtaining the optimized and adjusted design layout through the standard cell analysis library, the present invention detects the design layout based on the neural network model to obtain the bad pixel value of the design layout; according to the bad pixel value of the design layout, the layout of the standard cells in the design layout is adjusted to obtain a new design layout, so that the bad pixels of the new design layout can be further reduced.

[0133] 7. The present invention also sets a second bad pixel threshold. When the bad pixel value of the obtained design layout is greater than the second bad pixel threshold, the layout of the standard cells in the design layout is adjusted and then the detailed layout is re-performed to obtain a new design layout. The process is iterated in a loop until the bad pixel value of the design layout is less than or equal to the second bad pixel threshold. Therefore, the present invention can obtain a design layout that meets the bad pixel value requirements according to actual needs.

[0134] 8. The present invention also provides a design layout system, which has the same beneficial effects as the above-mentioned design layout method, and will not be elaborated here.

[0135] 9. The present invention also provides a storage medium on which a computer program is stored. When the computer program is executed, it implements the above-mentioned design layout method and has the same beneficial effects as the above-mentioned design layout method, which will not be elaborated here.

[0136] The above is a detailed introduction to an analysis library construction method, a design layout method, a system and a storage medium disclosed in an embodiment of the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for a person skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and the scope of application. In summary, the content of this specification should not be understood as a limitation on the present invention, and any modifications, equivalent substitutions and improvements made within the principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for constructing an analysis library, characterized in that: The following steps are involved: Provide a standard unit and a surrounding environment in a design process of a design layout, set the surrounding environment adjacent to the standard unit, detect the bad point generation value of the standard unit, filter the standard unit without bad points, and obtain the remaining standard units with bad points after filtering; select the filtered standard units to be adjacently set and layout to obtain a design layout, provide a neural network model obtained by training according to a photolithography process, obtain a mask layout corresponding to the design layout by inputting the design layout into the neural network model, obtain a photoresist profile by simulating the mask layout, check the bad points existing in the photoresist profile by a preset photolithography rule checking program, and obtain the bad point values ​​between the standard units in the design layout; The bad pixel values ​​are collected to obtain a standard cell analysis library of the standard cell.

2. A method for constructing an analysis library according to claim 1, characterized in that: Defining the boundary of the standard cell based on the lithography influence range of the design layout, and classifying the filtered standard cells according to the boundary shapes of the standard cells; Selecting a representative standard cell in each category of the standard cells, selecting the representative standard cells of different categories to be arranged adjacently, and detecting bad pixel values ​​when the standard cells are adjacent based on a neural network model; The bad pixel values ​​are collected and input into the standard cell analysis library.

3. A design layout method, characterized in that: The following steps are involved: Providing a standard unit analysis library as claimed in any one of claims 1 to 2; Setting the standard cells according to the layout algorithm of the design layout to obtain the design layout, and obtaining the bad pixel value of the standard cells through the standard cell analysis library; Setting a first bad pixel threshold, when the bad pixel value of the standard cell is greater than the first bad pixel threshold, resetting the standard cell by the layout algorithm to obtain a new design layout; When the bad pixel value of the standard cell of the new design layout is less than or equal to the first bad pixel threshold, the new design layout is output.

4. A design layout method as claimed in claim 3, characterized in that: The steps in the layout algorithm include global layout and detailed layout. At least one of the global layout and the detailed layout obtains the bad pixel value of the standard cell through the standard cell analysis library. When the bad pixel value of the standard cell is greater than the first bad pixel threshold, the standard cell is reset through the global layout and / or the detailed layout to obtain a new design layout.

5. A design layout method as claimed in claim 4, characterized in that: In both the global layout and the detailed layout, the bad pixel value of the standard cell is obtained through the standard cell analysis library. When the bad pixel value of the standard cell is greater than the first bad pixel threshold, the standard cell is reset through the global layout and the detailed layout to obtain a new design layout.

6. A design layout method as claimed in claim 5, characterized in that: Detecting the design layout based on the neural network model to obtain a bad pixel value of the design layout; According to the bad pixel value of the design layout, the layout of the standard cells in the design layout is adjusted to obtain a new design layout.

7. A design layout method as claimed in claim 6, characterized in that: Setting a second bad pixel threshold, and when the bad pixel value of the design layout is greater than the second bad pixel threshold, adjusting the layout of the standard cell in the design layout; Re-layout the adjusted design layout to obtain a new design layout; Iterate the new design layout, obtain the bad pixel value of the new design layout through the neural network model, and output the new design layout when the bad pixel value is less than or equal to the second bad pixel threshold.

8. A design layout system, characterized in that: include: An analysis library module is used to provide standard cells in a design process of a design layout, select adjacent settings of the standard cells and detect bad pixel values ​​when the standard cells are adjacent based on a neural network model, and collect the bad pixel values ​​to obtain a standard cell analysis library of the standard cells; A layout module, used for setting standard cells according to a layout algorithm of a design layout to obtain a design layout, and obtaining a bad pixel value of the standard cell through the standard cell analysis library; Setting a first bad pixel threshold, when the bad pixel value of the standard cell is greater than the first bad pixel threshold, resetting the standard cell by the layout algorithm to obtain a new design layout; When the bad pixel value of the standard unit of the new design layout is less than or equal to the first bad pixel threshold, the new design layout is output.

9. A storage medium comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, a design layout method according to any one of claims 3 to 7 is implemented.

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