Pixel circuit, detection method and display device

Abstract

Embodiments of the present disclosure provide a pixel circuit, a detection method and a display device, and relate to the technical field of display, which are used for repairing the pixel circuit in time to reduce the manufacturing cost of the display device. The driving sub-circuit is configured to control the conduction of the second node and the third node in response to the electric potential of the first node in the first stage. The first sub-circuit is configured to transmit the first signal received at the first signal end to the node coupled with the first sub-circuit in response to the scan signal received by the at least one scan signal end in the first stage. The detection sub-circuit is coupled with the other one of the second node and the third node, the second scan signal end and the data signal end. The detection sub-circuit is configured to transmit the signal received at the node coupled with the detection sub-circuit to the data signal end in response to the second scan signal received at the second scan signal end in the first stage. The pixel circuit is used in a display panel.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a pixel circuit, a detection method and a display device. BACKGROUND

[0002] With the development of display technology, display devices (such as mobile phones, notebook computers or tablet computers, etc.) are increasingly applied to people's lives. Among them, the organic light-emitting diode (Organic Light-Emitting Diode, OLED for short) display device has the advantages of active light-emitting, wide viewing angle, high contrast, fast response speed, low power consumption, ultra-thin, etc., and therefore receives widespread attention. SUMMARY

[0003] Embodiments of the present disclosure aim to provide a pixel circuit, a detection method and a display device, which can repair the pixel circuit in time to reduce the preparation cost of the display device.

[0004] To achieve the above-mentioned purpose, embodiments of the present disclosure provide the following technical solutions:

[0005] In one aspect, a pixel circuit is provided. The pixel circuit includes a driving sub-circuit, a first sub-circuit, a data writing sub-circuit and a detection sub-circuit. The driving sub-circuit is coupled with a first node, a second node and a third node; the driving sub-circuit is configured to, in the first stage, control the conduction of the second node and the third node in response to the potential of the first node; the first sub-circuit is coupled with one of the second node and the third node, a first signal terminal and at least one scanning signal terminal; the data writing sub-circuit is coupled with the first node, a first scanning signal terminal and a data signal terminal; the first sub-circuit is coupled with the first signal terminal and the scanning signal terminal; the first sub-circuit is further coupled with one of the second node and the third node; the first sub-circuit is configured to, in the first stage, transmit a first signal received at the first signal terminal to a first target node in response to a scanning signal received by the scanning signal terminal; wherein the first target node is the node of the second node and the third node coupled with the first sub-circuit; the detection sub-circuit is coupled with a second scanning signal terminal and the data signal terminal; the detection sub-circuit is further coupled with the other of the second node and the third node; the detection sub-circuit is configured to, in the first stage, transmit a signal received at a second target node to the data signal terminal in response to a second scanning signal received at the second scanning signal terminal; wherein the second target node is the node of the second node and the third node coupled with the detection sub-circuit.

[0006] In the pixel circuit, the first signal can be transmitted to the data signal end through the first sub-circuit, the driving sub-circuit and the detection sub-circuit. In this way, by detecting the current size at the data signal end, the driving sub-circuit can be detected to determine whether the driving sub-circuit is damaged and whether there is a difference among all the driving sub-circuits, so that the pixel circuit can be repaired in time, the influence on the subsequent process of the pixel circuit is reduced, and the preparation cost of the display device is reduced.

[0007] In some embodiments, the detection sub-circuit is coupled with the second node, and the first sub-circuit includes a first reset sub-circuit and a second light emitting sub-circuit. The first reset sub-circuit is coupled with a first initialization signal end, a fourth node and a first reset signal end; the first reset sub-circuit is configured to, in the first stage, transmit a first initialization signal received at the first initialization signal end to the fourth node in response to a first reset signal received at the first reset signal end; the fourth node is configured to be coupled with an anode of a light emitting device; the second light emitting sub-circuit is coupled with the third node, a second light emitting signal end and the fourth node; the second light emitting sub-circuit is configured to, in the first stage, transmit the received first initialization signal at the fourth node to the third node in response to a second light emitting signal received at the second light emitting signal end; the driving sub-circuit is configured to, in the first stage, transmit the received first initialization signal at the third node to the second node in response to the potential of the first node; and the detection sub-circuit is configured to, in the first stage, transmit the received first initialization signal at the third node to the data signal end in response to a second scan signal received at the second scan signal end.

[0008] In some embodiments, the detection stage further includes a second stage, and the pixel circuit further includes a first light emitting sub-circuit. The first light emitting sub-circuit is coupled with a first voltage signal end, a first light emitting signal end and the second node; the first light emitting sub-circuit is configured to, in the second stage, transmit a first voltage signal received at the first voltage signal end to the second node in response to a first light emitting signal received at the first light emitting signal end; and the detection sub-circuit is further configured to, in the second stage, transmit the received first voltage signal at the second node to the data signal end in response to a second scan signal received at the second scan signal end.

[0009] In some embodiments, the detection sub-circuit is coupled with the third node, and the first sub-circuit includes a first light emitting sub-circuit. The first light emitting sub-circuit is coupled with a first voltage signal terminal, a first light emitting signal terminal, and the second node; the first light emitting sub-circuit is configured to, in the first stage, transmit a first voltage signal received at the first voltage signal terminal to the second node in response to a first light emitting signal received at the first light emitting signal terminal; the driving sub-circuit is configured to, in the first stage, transmit the first voltage signal received at the second node to the third node in response to the potential of the first node; and the detection sub-circuit is configured to, in the first stage, transmit the first voltage signal received at the second node to the data signal terminal in response to a second scan signal received at a second scan signal terminal.

[0010] In some embodiments, the detection stage further includes a second stage, and the pixel circuit further includes a first reset sub-circuit and a second light emitting sub-circuit. The first reset sub-circuit is coupled with a first initialization signal terminal, a fourth node, and a first reset signal terminal; the fourth node is configured to be coupled with an anode of the light emitting device; the first reset sub-circuit is configured to, in the second stage, transmit a first initialization signal received at the first initialization signal terminal to the fourth node in response to a first reset signal received at the first reset signal terminal; the second light emitting sub-circuit is coupled with the third node, a second light emitting signal terminal, and the fourth node; the second light emitting sub-circuit is configured to, in the second stage, transmit the first initialization signal received at the fourth node to the third node in response to a second light emitting signal received at the second light emitting signal terminal; and the detection sub-circuit is further configured to, in the second stage, transmit the first initialization signal received at the third node to the data signal terminal in response to a second scan signal received at a second scan signal terminal.

[0011] In some embodiments, the detection sub-circuit includes a first transistor. A first electrode of the first transistor is coupled with the data signal terminal, a second electrode is coupled with another of the second node and the third node, and a control electrode is coupled with the second scan signal terminal.

[0012] In some embodiments, the driving sub-circuit includes a second transistor. A first electrode of the second transistor is coupled with the second node, a second electrode is coupled with the third node, a first control electrode is coupled with the first node, and a second control electrode is coupled with the third node.

[0013] In some embodiments, the detection stage further comprises a third stage, and the pixel circuit further comprises a second reset sub-circuit. The second reset sub-circuit is coupled with a second initialization signal terminal, the first node and a second reset signal terminal; the second reset sub-circuit is configured to, in the third stage, transmit a second initialization signal received at the second initialization signal terminal to the first node in response to a second reset signal received at the second reset signal terminal; and the data writing sub-circuit is configured to, in the third stage, transmit the second initialization signal received at the first node to the data signal terminal in response to a first scan signal received at the first scan signal terminal.

[0014] In another aspect, a detection method of a pixel circuit is provided. The detection method is used to detect the pixel circuit of any of the above embodiments. The detection stage comprises a first stage; in the first stage, a first sub-circuit transmits a first signal received at a first signal terminal to a node coupled with the first sub-circuit in response to a scan signal received at the at least one scan signal terminal; a driving sub-circuit transmits the first signal received at the node coupled with the first sub-circuit to a node coupled with a detection sub-circuit under the control of the first node; and the detection sub-circuit transmits the first signal received at the node coupled with the detection sub-circuit to a data signal terminal in response to a second scan signal received at a second scan signal terminal.

[0015] The detection method of the pixel circuit has the same structure and beneficial technical effects as the pixel circuit provided in some of the above embodiments, and will not be described here again.

[0016] In some embodiments, the detection sub-circuit is coupled with a second node; in the first stage, a first reset sub-circuit transmits a first initialization signal received at a first initialization signal terminal to a fourth node in response to a first reset signal received at a first reset signal terminal, a second light emitting sub-circuit transmits the first initialization signal received at the fourth node to a third node in response to a second light emitting signal received at a second light emitting signal terminal, the driving sub-circuit transmits the first initialization signal received at the third node to the second node in response to the potential at the first node, and the detection sub-circuit transmits the first initialization signal at the second node to the data signal terminal in response to a second scan signal received at a second scan signal terminal.

[0017] In some embodiments, the detection stage further comprises a second stage; in the second stage, a first light emitting sub-circuit transmits a first voltage signal received at a first voltage signal terminal to a second node in response to a first light emitting signal received at a first light emitting signal terminal, and the detection sub-circuit transmits the potential at the second node to the data signal terminal in response to a second scan signal received at a second scan signal terminal.

[0018] In some embodiments, the detection sub-circuit and the third node are coupled; in the first stage, the first light-emitting sub-circuit transmits the first voltage signal received at the first voltage signal terminal to the second node in response to the first light-emitting signal received at the first light-emitting signal terminal, the driving sub-circuit transmits the first voltage signal received at the second node to the third node in response to the electric potential at the first node, and the detection sub-circuit transmits the first voltage signal received at the third node to the data signal terminal in response to the second scan signal received at the second scan signal terminal.

[0019] In some embodiments, the detection stage further comprises a second stage; in the second stage, the first reset sub-circuit transmits the first initialization signal received at the first initialization signal terminal to the fourth node in response to the first reset signal received at the first reset signal terminal, the second light-emitting sub-circuit transmits the electric potential at the fourth node to the third node in response to the second light-emitting signal received at the second light-emitting signal terminal, and the detection sub-circuit transmits the electric potential at the third node to the data signal terminal in response to the second scan signal received at the second scan signal terminal.

[0020] In some embodiments, the detection stage further comprises a third stage; in the third stage, the second reset sub-circuit transmits the second initialization signal received at the second initialization signal terminal to the first node in response to the second reset signal received at the second reset signal terminal, and the data writing sub-circuit transmits the second initialization signal received at the first node to the data signal terminal in response to the first scan signal received at the first scan signal terminal.

[0021] In another aspect, a display device is provided. The display device comprises the pixel circuit according to any one of the above embodiments.

[0022] The display device has the same structure and beneficial technical effects as the pixel circuit provided in some of the above embodiments, and will not be described again here. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0024] Figure 1 A structural diagram of a display device according to some embodiments;

[0025] Figure 2Another configuration diagram of a display device according to some embodiments;

[0026] Figure 3 A configuration diagram of a display panel including a substrate and a pixel circuit according to some embodiments;

[0027] Figure 4 A configuration diagram of a display panel including a substrate and a pixel circuit according to some embodiments;

[0028] Figure 5 A configuration diagram of a pixel circuit according to some embodiments; Figure 4 A cross-sectional view along the section line A-A;

[0029] Figure 6 A configuration diagram of a pixel circuit according to some embodiments;

[0030] Figure 7 A configuration diagram of a pixel circuit according to some embodiments;

[0031] Figure 8 A configuration diagram of a pixel circuit including a transistor and a capacitor according to some embodiments;

[0032] Figure 9 A configuration diagram of a pixel circuit including a transistor and a capacitor according to some embodiments;

[0033] Figure 10 A timing diagram of a pixel circuit according to some embodiments;

[0034] Figure 11 A timing diagram of a pixel circuit according to some embodiments;

[0035] Figure 12 A configuration diagram of a transistor included in a pixel circuit according to some embodiments;

[0036] Figure 13 A configuration diagram of a transistor included in a pixel circuit according to some embodiments;

[0037] Figure 14 A configuration diagram of a transistor included in a pixel circuit according to some embodiments;

[0038] Figure 15 A configuration diagram of a transistor included in a pixel circuit according to some embodiments;

[0039] Figure 16 A configuration diagram of a transistor included in a pixel circuit according to some embodiments;

[0040] Figure 17Another structural diagram of the pixel circuit according to some embodiments, in which transistors are turned on or turned off;

[0041] Figure 18 Another structural diagram of the pixel circuit according to some embodiments. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. It should be apparent that the described embodiments are only a part of the embodiments of the present disclosure, and not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0043] Unless otherwise required by context, the term "comprise" and other forms of the term "comprise", such as "comprises" and "comprising", and the like, are used in an open, inclusive and non-limiting sense, that is, as "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate a particular feature, structure, material, or characteristic that is included in at least one embodiment or example of the present disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics described can be included in any suitable way in any one or more embodiments or examples.

[0044] Hereinafter, the terms "first", "second", etc. are used only for the purpose of description, and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0045] In describing some embodiments, "coupled" and "connected," along with their derivatives, can be used. It should be understood that these terms are not intended as synonyms for each other. Rather, "connected" can be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" can be used to indicate that two or more elements are in either physical or electrical contact with each other, even at a remote location from each other. The term "coupled" as used herein encompasses the case where one or more intervening elements can exist. The embodiments disclosed herein are not necessarily limited to the details of the embodiments described.

[0046] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C." Both of these phrases include the following combinations: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A and B and C.

[0047] "A and / or B" includes the following three combinations: A alone, B alone, and a combination of A and B.

[0048] As used herein, the term "if' can, depending on the context, optionally be interpreted as meaning "when," or "while," or "in response to determining," or "in response to detecting." Likewise, the phrase "if it is determined" or "if [a stated condition or event] is detected" can, depending on the context, optionally be interpreted as meaning "upon determining," or "in response to determining," or "upon detecting," or "in response to detecting [the stated condition or event]."

[0049] The use of "adapted to" or "configured to," as used herein, means open and inclusive language that does not exclude additional devices or steps not explicitly described.

[0050] Additionally, the use of "based on" means open and inclusive language that does not exclude additional conditions or values not explicitly stated.

[0051] As used herein, "about," "approximately," or "around" includes the recited value and the average value within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art considering the measurement being discussed and the error in measurement associated with the particular quantity being measured (i.e., the limitations of the measurement system).

[0052] As used herein, "parallel," "perpendicular," "equal" include the recited condition and conditions approximating the recited condition within an acceptable deviation range, as determined by one of ordinary skill in the art taking into account the measurement at issue and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where near parallel can have an acceptable deviation range of, for example, within 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where near perpendicular can also have an acceptable deviation range of, for example, within 5°. "Equal" includes absolute equality and near equality, where near equality can have an acceptable deviation range of, for example, a difference between the two that is less than or equal to 5% of either.

[0053] It should be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0054] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the circular features can be shown in the drawings. It will be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions can be made. These implementation-specific decisions can include, for example, manufacturing or processing tolerances, variations from manufacturing or processing tolerances, and other factors that can affect the cost, performance, and / or other aspects of the implementation. As such, the exemplary embodiments are not to be construed as limited to the specific illustrative examples contained herein but are to be accorded the broadest scope consistent with the principles and novel features disclosed herein. For example, the shapes of the regions illustrated in the drawings can not exactly reflect the shapes of the regions in an actual device, and are merely intended to be illustrative of the regions. Thus, the shapes of the regions illustrated in the drawings are not intended to limit the scope of the exemplary embodiments.

[0055] In embodiments of the present disclosure, the capacitor can be a capacitor device fabricated separately by a process, for example, by fabricating a special capacitor electrode, each capacitor electrode of the capacitor can be implemented by a metal layer, a semiconductor layer (for example, doped polysilicon), etc. The capacitor can also be a parasitic capacitor between transistors, or implemented by the transistor itself and other devices, lines, or by using the parasitic capacitor between the lines of the circuit itself.

[0056] In the circuit provided by the embodiments of the present disclosure, the first node, the second node, and the third node are not actual components, but are convergence points of relevant electrical connections in a circuit diagram, that is, these nodes are nodes equivalent to the convergence points of relevant electrical connections in a circuit diagram.

[0057] The "low level" of the pixel circuit provided in the embodiments of the present disclosure refers to a level capable of turning on the operated transistor included therein, and correspondingly, the "high level" refers to a level incapable of turning on the operated transistor included therein (i.e., the transistor is turned off).

[0058] The control electrode of each transistor provided in the embodiments of the present disclosure is the gate of the transistor, the first electrode is one of the source and the drain of the transistor, and the second electrode is the other of the source and the drain of the transistor. Since the source and the drain of the transistor can be symmetrical in structure, the source and the drain of the transistor can be indistinguishable in structure, that is, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure can be indistinguishable in structure. For example, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode of the transistor is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode of the transistor is the source.

[0059] As shown in Figure 1 and Figure 2 , some embodiments of the present disclosure provide a display device 1000, which can be any device displaying anything whether moving (e.g., video) or fixed (e.g., still image) and whether text or image.

[0060] For example, the display device 1000 can be any product or component having a display function, such as a television, a notebook computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, an in-vehicle display, a flight display, etc.

[0061] In some examples, as shown in Figure 1 , the display device 1000 can be a portable display product. For example, the display device 1000 can be a mobile phone as shown in Figure 1 .

[0062] In yet other examples, as shown in Figure 2 , the display device 1000 can be a wearable device. For example, the display device 1000 can be a watch as shown in Figure 2 .

[0063] In some embodiments, as shown in Figure 3 , the display device 1000 includes a display panel 100, a driving circuit board 200, a housing 300, and a cover plate 400.

[0064] The display panel 100 has a light-emitting side 100A and a non-light-emitting side 100B. The light-emitting side 100A refers to the side of the display panel 100 that can emit light. Figure 3 The upper side of the display panel 100), the non-light-emitting side 100B refers to the side opposite to the light-emitting side 100A. Figure 3 (Lower side of the central display panel 100).

[0065] The driving circuit board 200 is located on the non-light-emitting side of the display panel 100 and is connected to the display panel 100 to provide light-emitting signals to the display panel 100.

[0066] The housing 300 can be a box-shaped structure with an opening. The display panel 100 and the driving circuit board 200 can be disposed inside the housing 300. The cover plate 400 is disposed on the light-emitting side of the display panel 100 and is located at the opening of the housing 300.

[0067] like Figure 3 As shown, the longitudinal section of the housing 300 can be, for example, U-shaped. The display panel 100 and the drive circuit board 200 are disposed inside the housing 300, and the cover plate 400 is disposed at the opening of the housing 300.

[0068] The aforementioned display panel 100 comes in various types, and can be selected and configured according to actual needs.

[0069] For example, the display panel 100 described above may be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, an active matrix organic light-emitting diode (AMOLED) display panel, a liquid crystal display (LCD) display panel, or a mini / micro light-emitting display (MLED) display panel, etc. The embodiments disclosed herein do not impose specific limitations.

[0070] The following description uses the above-mentioned display panel 100 as an OLED display panel as an example to illustrate some embodiments of this disclosure.

[0071] In some embodiments, such as Figure 4 and Figure 5 As shown, the display panel 100 includes a substrate 10 and a plurality of sub-pixels 20.

[0072] The material used by the substrate 10 can include a polymer resin or glass. Exemplarily, the substrate 10 can be flexible, and the material used by the substrate 10 includes one of a polymer resin such as Polyethersulfone (PES), Polyarylate (PAR), Polyetherimide (PEI), Polyethylene Naphthalate Two Formic Acid GlycolEster (PEN), Polyethylene Terephthalate (PET), Polyphenyl Sulfide Granula (PPS), Polyimide (PI), Polycarbonate (PC), and Cellulose Acetate Propionate (CAP). Exemplarily, the substrate 10 can be rigid, and include a glass material containing SiO2 as a main component.

[0073] As shown in Figure 4 The plurality of sub-pixels 20 are arranged on the substrate 10, and the plurality of sub-pixels 20 can be arranged in multiple rows and multiple columns, for example. Each row of sub-pixels 20 includes at least two sub-pixels 20 arranged along a first direction X, and each column of sub-pixels 20 includes at least two sub-pixels 20 arranged along a second direction Y. The first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are perpendicular.

[0074] The plurality of sub-pixels 20 can include a first sub-pixel with a first color, a second sub-pixel with a second color, and a third sub-pixel with a third color. The first color, the second color, and the third color are three primary colors. For example, the first color is red, the second color is blue, and the third color is green, which are not limited in the embodiments of the present disclosure.

[0075] In some embodiments, as shown in Figure 4 and Figure 5 Each sub-pixel 20 includes a pixel circuit 21 and a light emitting device 22 arranged on the substrate 10. The pixel circuit 21 includes a plurality of transistors 211 and a storage capacitor 212 (Capacitor, C).

[0076] The transistor used in the circuit provided by the embodiments of the present disclosure can be a thin film transistor, a field effect transistor or other switching devices with the same characteristics, and the embodiments of the present disclosure are described by taking a thin film transistor as an example.

[0077] For example, the transistor 211 is an oxide thin film transistor, which has a high carrier mobility and can improve the response speed of the transistor 211.

[0078] As shown in FIG. 1, the transistor 211 includes an active region 2111, a source 2112, a drain 2113 and a gate 2114, and the source 2112 and the drain 2113 are in contact with the active region 2111. The storage capacitor 212 includes two opposite plates. Figure 5 It should be noted that the source 2112 and the drain 2113 can be interchanged, that is, 2112 in the above description represents the drain, and 2113 represents the source.

[0079] Figure 5 It should be noted that the source 2112 and the drain 2113 can be interchanged, that is, 2112 in the above description represents the drain, and 2113 represents the source.

[0080] The structure of the pixel circuit 21 can include various structures, which can be selected and arranged according to actual needs. For example, the structure of the pixel circuit 21 can include a “2T1C”, “3T1C”, “6T1C”, “7T1C”, “6T2C” or “7T2C” structure. Among them, “T” represents the transistor 211, the number before “T” represents the number of transistors 211, and “C” represents the storage capacitor 212, and the number before “C” represents the number of storage capacitors 212.

[0081] As shown in FIG. 1, the light emitting device 22 includes a first electrode 221, a light emitting functional layer 222 and a second electrode 223. The first electrode 221 can be electrically connected to the source 2112 or the drain 2113 of the transistor 211 as a driving transistor, Figure 5 for example. The material of the first electrode 221 includes indium tin oxide (English: Indium Tin Oxide, ITO) or silver (Ag). The material of the second electrode includes aluminum (Al), Ag or magnesium (Mg). Figure 5 It should be noted that the first electrode 221 is the anode of the light emitting device 22, and the second electrode 223 is the cathode of the light emitting device 22; or the first electrode 221 is the cathode of the light emitting device 22, and the second electrode 223 is the anode of the light emitting device 22. Hereinafter, the first electrode 221 is taken as the anode of the light emitting device 22, and the second electrode 223 is taken as the cathode of the light emitting device 22 as an example to illustrate the embodiments of the present disclosure.

[0082]

[0083] ​​Exemplarily, as shown in Figure 5 The second electrode 223 (cathode) is an integral layer structure.

[0084] The light-emitting functional layer 222 can include only a light-emitting layer, or can further include at least one of an electron transporting layer (ETL), an electron injection layer (EIL), a hole transporting layer (HTL), and a hole injection layer (HIL) in addition to the light-emitting layer.

[0085] In some embodiments, as shown in Figure 5 The display panel 100 further includes an encapsulation layer 30. The encapsulation layer 30 is disposed on the side of the plurality of sub-pixels 20 away from the substrate 10, and is configured to encapsulate the light-emitting device 22 and improve the service life of the light-emitting device 22. The encapsulation layer 30 can be an encapsulation film or an encapsulation substrate, and the specific form is not limited in the embodiments of the present disclosure.

[0086] Exemplarily, the encapsulation layer 30 can include one encapsulation film, or two or more encapsulation films stacked. For example, as shown in Figure 5 The encapsulation layer 30 includes a first inorganic encapsulation layer 31, a first organic encapsulation layer 32, and a second inorganic encapsulation layer 33 stacked in a direction perpendicular to and away from the substrate 10. The materials of the first inorganic encapsulation layer 31 and the second inorganic encapsulation layer 33 include any one or more of silicon nitride, silicon oxynitride, or silicon oxide. The material of the first organic encapsulation layer 32 includes a polymer resin, such as polyimide.

[0087] In some embodiments, the pixel circuit 21 includes a driving sub-circuit 201 and a data writing sub-circuit 202.

[0088] In some examples, as shown in Figure 6 and Figure 7 The driving sub-circuit 201 is coupled to the first node N1, the second node N2, and the third node N3. The driving sub-circuit 201 is configured to control the conduction and the cutoff of the second node N2 and the third node N3 in response to the potential of the first node N1.

[0089] Exemplarily, as shown in Figure 8 and Figure 9As shown, the driving sub-circuit 201 includes a second transistor (driving transistor) T2, the first electrode of the second transistor T2 is connected with the second node N2, and the second electrode is connected with the third node N3. The first control electrode is connected with the first node N1, and the second control electrode is connected with the third node N3. In this way, the drain current of the second transistor T2 is small, which is beneficial to improve the performance of the second transistor T2. The first control electrode is one of the top gate and the bottom gate of the second transistor, and the second control electrode is the other one of the top gate and the bottom gate.

[0090] In some examples, as shown in Figure 8 and Figure 9 As shown, the data writing sub-circuit 202 is coupled with the first node N1, the first scan signal end GATE1 and the data signal end DATA.

[0091] For example, the data writing sub-circuit 202 includes a third transistor T3, the first electrode of the third transistor T3 is connected with the data signal end DATA, the second electrode is connected with the first node N1, and the control electrode is connected with the data signal end DATA.

[0092] In some embodiments, the pixel circuit 21 has a detection stage, and the pixel circuit 21 needs to be detected in the detection stage to determine whether the pixel circuit 21 meets the design requirements. The detection stage is located after the preparation of the pixel circuit 21 and before the preparation of the light emitting device 22.

[0093] Generally, the data signal end DATA is connected with a detection device (for example, a current sensor), and the current value at the data signal end DATA is detected to determine whether the pixel circuit 21 meets the requirements. If the current value at the data signal end DATA is less than or equal to a preset value, the requirements are met. The preset value can be selected according to the actual situation. For example, if the requirements of the pixel circuit 21 are high, the preset value can be small, and if the requirements of the pixel circuit 21 are low, the preset value can be large.

[0094] In the related art, the driving sub-circuit cannot be detected in the detection stage, which leads to the inability to determine whether the driving sub-circuit is damaged and the inability to determine whether all the driving sub-circuits are different, and the pixel circuit cannot be repaired in time, thereby affecting the subsequent process (for example, the preparation of the light emitting device) of the pixel circuit, and further leading to a high preparation cost of the display panel.

[0095] In order to solve the above technical problems, as shown in the drawings, some embodiments of the present disclosure provide a pixel circuit 21, which has a detection stage, as shown in Figure 10 and Figure 11 As shown, the detection stage includes a first stage P1.

[0096] As shown in Figure 12 andFigure 13 As shown in FIG. 2, the driving sub-circuit 201 is configured to, in the first phase P1, control the conduction of the second node N2 and the third node N3 in response to the potential of the first node N1.

[0097] On this basis, as shown in FIG. 2, the pixel circuit 21 further comprises a first sub-circuit 203 and a detection sub-circuit 204. Figure 6 Figure 7 As shown in FIG. 2, the pixel circuit 21 further comprises a first sub-circuit 203 and a detection sub-circuit 204.

[0098] The first sub-circuit 203 is coupled with the first signal terminal V1 and the scanning signal terminal, and further coupled with one of the second node N2 and the third node N3. The first sub-circuit 203 is configured to, in the first phase P1, transmit the first signal received at the first signal terminal V1 to a first target node in response to the scanning signal received by the at least one scanning signal terminal. The first target node is the node of the second node N2 and the third node N3 coupled with the first sub-circuit 203.

[0099] The driving sub-circuit 201 is configured to, in the first phase P1, control the conduction of the second node N2 and the third node N3 in response to the potential of the first node N1.

[0100] The detection sub-circuit 204 is coupled with the second scanning signal terminal GATE2 and the data signal terminal DATA, and further coupled with the other of the second node N2 and the third node N3.

[0101] Exemplarily, as shown in FIG. 2, the detection sub-circuit 204 comprises a first transistor T1, the first electrode of the first transistor T1 is coupled with the data signal terminal DATA, the second electrode is coupled with the other of the second node N2 and the third node N3, and the control electrode is coupled with the second scanning signal terminal GATE2. Figure 8 Figure 9 In addition, as shown in FIG. 2, the detection sub-circuit 204 is configured to, in the first phase P1, transmit the signal received at a second target node to the data signal terminal DATA in response to the second scanning signal received at the second scanning signal terminal GATE2. The second target node is the node of the second node N2 and the third node N3 coupled with the detection sub-circuit 204.

[0102] In addition, as shown in FIG. 2, the detection sub-circuit 204 is configured to, in the first phase P1, transmit the signal received at a second target node to the data signal terminal DATA in response to the second scanning signal received at the second scanning signal terminal GATE2. The second target node is the node of the second node N2 and the third node N3 coupled with the detection sub-circuit 204. Figure 12 Figure 13 In addition, as shown in FIG. 2, the detection sub-circuit 204 is configured to, in the first phase P1, transmit the signal received at a second target node to the data signal terminal DATA in response to the second scanning signal received at the second scanning signal terminal GATE2. The second target node is the node of the second node N2 and the third node N3 coupled with the detection sub-circuit 204.

[0103] ​​​In this way, the first signal can pass through the first sub-circuit 203, the driving sub-circuit 201 and the detection sub-circuit 204 to the data signal end DATA. In this way, by detecting the current at the data signal end DATA, the driving sub-circuit 201 can be detected to determine whether the driving sub-circuit 201 is damaged and whether there is a difference between all the driving sub-circuits 201, so as to repair the pixel circuit 21 in time, reduce the influence on the subsequent process of the pixel circuit 21, and reduce the preparation cost of the display device.

[0104] It can be understood that in some embodiments, the detection sub-circuit 204 is kept normally closed in one display frame period, so as to reduce the risk of affecting the display of the display panel 100 by the detection sub-circuit 204.

[0105] In some embodiments, as shown in Figure 6 and Figure 7 , the pixel circuit 21 further includes a first light emitting sub-circuit 205, a first reset sub-circuit 206 and a second light emitting sub-circuit 207.

[0106] In some examples, as shown in Figure 6 and Figure 7 , the first light emitting sub-circuit 205 is coupled with the first voltage signal end VDD, the first light emitting signal end EM1 and the second node N2.

[0107] Exemplarily, as shown in Figure 8 and Figure 9 , the first light emitting sub-circuit 205 includes a fourth transistor T4, the first electrode of the fourth transistor T4 is coupled with the first voltage signal end VDD, the second electrode is coupled with the second node N2, and the control electrode is coupled with the first light emitting signal end EM1.

[0108] In some examples, as shown in Figure 8 and Figure 9 , the first reset sub-circuit 206 is coupled with the first initialization signal end VINIT1, the fourth node N4 and the first reset signal end RESET1. The fourth node N4 is configured to be coupled with the anode of the light emitting device 22.

[0109] Exemplarily, as shown in Figure 8 and Figure 9 , the first reset sub-circuit 206 includes a fifth transistor T5, the first electrode of the fifth transistor T5 is coupled with the first initialization signal end VINIT1, the second electrode is coupled with the fourth node N4, and the control electrode is coupled with the first reset signal end RESET1.

[0110] In this way, under the control of the first reset signal end RESET1, the first initialization signal received by the first initialization signal end VINIT1 can be transmitted to the fourth node N4 through the first reset sub-circuit 206, so that the fourth node N4 can be initialized, and the problem that the potential of the previous image frame remaining in the fourth node N4 affects the display image of the next image frame can be improved, thereby improving the brightness uniformity of the display panel 100.

[0111] On this basis, as shown in Figures 6-9 , the cathode of the light-emitting device 22 is coupled with the second voltage signal end VSS. Among them, the level output by the second voltage signal end VSS is lower than the high level output by the first voltage signal end VDD.

[0112] In some examples, as shown in Figure 8 and Figure 9 , the second light-emitting sub-circuit 207 is coupled with the third node N3, the second light-emitting signal end EM2 and the fourth node N4.

[0113] Exemplarily, as shown in Figure 8 and Figure 9 , the second light-emitting sub-circuit 207 includes a sixth transistor T6, the first pole of the sixth transistor T6 is coupled with the third node N3, the second pole is coupled with the fourth node N4, and the control pole is coupled with the second light-emitting signal end EM2.

[0114] In some embodiments, as shown in Figure 6 , the detection sub-circuit 204 is coupled with the second node N2. The first sub-circuit 203 includes the first reset sub-circuit 206 and the second light-emitting sub-circuit 207 described above. At this time, the first signal end V1 includes the first initialization signal end VINIT1, the first target node is the third node N3, and the second target node is the second node N2.

[0115] Among them, as shown in Figure 10 and Figure 12 , the first reset sub-circuit 206 is configured to, in the first stage P1, in response to the first reset signal received at the first reset signal end RESET1, transmit the first initialization signal received at the first initialization signal end VINIT1 to the fourth node N4.

[0116] The second light-emitting sub-circuit 207 is configured to, in the first stage P1, in response to the second light-emitting signal received at the second light-emitting signal end, transmit the received first initialization signal at the fourth node N4 to the third node N3.

[0117] The driving sub-circuit 201 is configured to, in the first stage P1, in response to the potential of the first node N1, transmit the received first initialization signal at the third node N3 to the second node N2.

[0118] The detection sub-circuit 204 is configured to, in the first stage P1, transmit the first initialization signal received at the second node N2 to the data signal end DATA in response to the second scan signal received at the second scan signal end GATE2.

[0119] In this way, the first initialization signal can be transmitted to the data signal end DATA through the first reset sub-circuit 206, the second light-emitting sub-circuit 207, the driving sub-circuit 201 and the detection sub-circuit 204. In this way, by detecting the current size at the data signal end DATA, the driving sub-circuit 201 can be detected to determine whether the driving sub-circuit 201 is damaged and whether there is a difference among all the driving sub-circuits 201, so that the pixel circuit 21 can be repaired in time, the influence on the subsequent process of the pixel circuit 21 is reduced, and the preparation cost of the display device is reduced.

[0120] On the basis of the above embodiment, as shown in Figure 10 and Figure 14 The detection stage further includes a second stage P2, and the first light-emitting sub-circuit 205 is configured to, in the second stage P2, transmit the first voltage signal received at the first voltage signal end VDD to the second node N2 in response to the first light-emitting signal received at the first light-emitting signal end EM1. At this time, the detection sub-circuit 204 is further configured to, in the second stage P2, transmit the first voltage signal received at the second node N2 to the data signal end DATA in response to the second scan signal received at the second scan signal end GATE2.

[0121] In this way, the first voltage signal can be transmitted to the data signal end DATA through the first light-emitting sub-circuit 205 and the detection sub-circuit 204. In this way, by detecting the current size at the data signal end DATA, the first light-emitting sub-circuit 205 can be detected to determine whether the first light-emitting sub-circuit 205 is damaged and whether there is a difference among all the first light-emitting sub-circuits 205, so that the pixel circuit 21 can be repaired in time, the influence on the subsequent process of the pixel circuit 21 is reduced, and the preparation cost of the display device is reduced.

[0122] In other embodiments, as shown in Figure 7 The detection sub-circuit 204 is coupled with the third node N3, and the first sub-circuit 203 includes the first light-emitting sub-circuit 205. At this time, the first signal end V1 includes the first voltage signal end VDD, the first target node is the second node N2, and the second target node is the third node N3.

[0123] Among them, as shown in Figure 11 and Figure 13As shown, the first light emitting sub-circuit 205 is configured to, in the first phase P1, in response to the first light emitting signal received at the first light emitting signal end EM1, transmit the first voltage signal received at the first voltage signal end VDD to the second node N2.

[0124] The driving sub-circuit 201 is configured to, in the first phase P1, in response to the potential of the first node N1, transmit the received first voltage signal at the second node N2 to the third node N3.

[0125] The detection sub-circuit 204 is configured to, in the first phase P1, in response to the second scanning signal received at the second scanning signal end GATE2, transmit the first voltage signal received at the third node N3 to the data signal end DATA.

[0126] In this way, the first voltage signal can be transmitted to the data signal end DATA through the first light emitting sub-circuit 205, the driving sub-circuit 201 and the detection sub-circuit 204. In this way, by detecting the current size at the data signal end DATA, the driving sub-circuit 201 can be detected to determine whether the driving sub-circuit 201 is damaged and whether there is a difference among all the driving sub-circuits 201, so as to repair the pixel circuit 21 in time, reduce the influence on the subsequent process of the pixel circuit 21, and reduce the preparation cost of the display device.

[0127] On the basis of the above embodiment, as shown in Figure 11 and Figure 15 The detection phase further includes a second phase P2.

[0128] At this time, the first reset sub-circuit 206 is configured to, in the second phase P2, in response to the first reset signal received at the first reset signal end RESET1, transmit the first initialization signal received at the first initialization signal end VINIT1 to the fourth node N4.

[0129] The second light emitting sub-circuit 207 is configured to, in the second phase P2, in response to the second light emitting signal received at the second light emitting signal end EM2, transmit the first initialization signal received at the fourth node N4 to the third node N3.

[0130] The detection sub-circuit 204 is further configured to, in the second phase P2, in response to the second scanning signal received at the second scanning signal end GATE2, transmit the first initialization signal received at the third node N3 to the data signal end DATA.

[0131] In this way, the first initialization signal can be transmitted to the data signal end DATA through the first reset sub-circuit 206, the second light-emitting sub-circuit 207 and the detection sub-circuit 204. In this way, by detecting the current size at the data signal end DATA, the first reset sub-circuit 206 and the second light-emitting sub-circuit 207 can be detected to determine whether the first reset sub-circuit 206 and the second light-emitting sub-circuit 207 are damaged, and whether there is a difference between all the first reset sub-circuit 206 and the second light-emitting sub-circuit 207, so as to repair the pixel circuit 21 in time, reduce the influence on the subsequent process of the pixel circuit 21, and reduce the preparation cost of the display device.

[0132] In some embodiments, as shown in Figure 6 and Figure 7 , the pixel circuit 21 further includes a second reset sub-circuit 208.

[0133] In some examples, as shown in Figure 6 and Figure 7 , the second reset sub-circuit 208 is coupled with the second initialization signal end VINIT2, the first node N1 and the second reset signal end RESET2.

[0134] Exemplarily, as shown in Figure 8 and Figure 9 , the second reset sub-circuit 208 includes a seventh transistor T7, the first electrode of the seventh transistor T7 is coupled with the second initialization signal end VINIT2, the second electrode is coupled with the first node N1, and the control electrode is coupled with the second reset signal end RESET2.

[0135] In this way, under the control of the second reset signal end RESET2, the second initialization signal received by the second initialization signal end VINIT2 can be transmitted to the first node N1 through the second reset sub-circuit 208, so that the first node N1 can be initialized, and the problem that the potential of the previous image frame remaining in the first node N1 affects the display image of the next image frame can be improved, thereby improving the brightness uniformity of the display panel 100.

[0136] As shown in Figure 10 , Figure 11 , Figure 16 and Figure 17 , the detection stage further includes a third stage P3, wherein the second reset sub-circuit 208 is configured to, in the third stage P3, transmit the second initialization signal received at the second initialization signal end VINIT2 to the first node N1 in response to the second reset signal received at the second reset signal end RESET2.

[0137] At this time, the data write sub-circuit 202 is configured to, in the third stage P3, in response to the first scan signal received at the first scan signal end GATE1, transmit the second initialization signal received at the first node N1 to the data signal end DATA.

[0138] In this way, the second initialization signal can be transmitted to the data signal end DATA through the second reset sub-circuit 208 and the data write sub-circuit 202. In this way, by detecting the current size at the data signal end DATA, the data write sub-circuit 202 can be detected to determine whether the data write sub-circuit 202 is damaged and whether there is a difference between all data write sub-circuits 202, so that the pixel circuit 21 can be repaired in time, the influence on the process after the pixel circuit 21 is reduced, and the preparation cost of the display device is reduced.

[0139] In some embodiments, as shown in Figure 6 and Figure 7 The pixel circuit 21 further includes a storage sub-circuit 209, which is coupled with the first node N1 and the third node N3. The storage sub-circuit 209 is configured to store the potential of the third node N3.

[0140] In some examples, as shown in Figure 8 and Figure 9 The storage sub-circuit 209 includes a first storage capacitor 2091, a first plate of the first storage capacitor 2091 is coupled with the first node N1, and a second plate is coupled with the third node N3.

[0141] In other examples, as shown in Figure 18 The storage sub-circuit 209 includes a second storage capacitor 2092 and a third storage capacitor 2093.

[0142] The first plate of the second storage capacitor 2092 is coupled with the first node N1, and the second plate is coupled with the fifth node N5.

[0143] The first plate of the third storage capacitor 2093 is coupled with the fifth node N5, and the second plate is coupled with the third node N3.

[0144] In addition, the pixel circuit 21 further includes a third reset sub-circuit 210, which is coupled with a third initialization signal end VINIT3, a fifth node N5 and a third reset signal end RESET3.

[0145] Exemplarily, as shown in Figure 18 The third reset sub-circuit 210 includes an eighth transistor T8, a first electrode of the eighth transistor T8 is connected with the third initialization signal end VINIT3, a second electrode is connected with the fifth node N5, and a control electrode is connected with the third reset signal end RESET3.

[0146] The operation of the pixel circuit 21 in the detection stage will be described in detail below in conjunction with a timing diagram. The following embodiments are based on the assumption that each of the transistors described above is N-type. As shown in Figure 10 and Figure 11 the detection stage includes a first phase P1, a second phase P2, and a third phase P3.

[0147] As shown in Figure 12 and Figure 13 the first phase P1;

[0148] The first sub-circuit 203 transmits the first signal received at the first signal terminal V1 to the node coupled with the first sub-circuit 203 in response to the scan signal received at the at least one scan signal terminal. Under the control of the first node N1, the driving sub-circuit 201 transmits the first signal received at the node coupled with the first sub-circuit 203 to the node coupled with the detection sub-circuit 204. The detection sub-circuit 204 transmits the first signal received at the node coupled with the detection sub-circuit 204 to the data signal terminal DATA in response to the second scan signal received at the second scan signal terminal GATE2.

[0149] In this way, the first signal can be transmitted to the data signal terminal DATA through the first sub-circuit 203, the driving sub-circuit 201, and the detection sub-circuit 204. In this way, by detecting the size of the current at the data signal terminal DATA, the driving sub-circuit 201 can be detected to determine whether the driving sub-circuit 201 is damaged and whether there is a difference among all the driving sub-circuits 201, so that the pixel circuit 21 can be repaired in time, the impact on the subsequent process of the pixel circuit 21 is reduced, and the manufacturing cost of the display device is reduced.

[0150] In some embodiments, as shown in Figure 12 the detection sub-circuit 204 is coupled with the second node N2. In the first phase P1;

[0151] The first reset sub-circuit 206 transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the fourth node N4 in response to the first reset signal received at the first reset signal terminal RESET1, the second light-emitting sub-circuit 207 transmits the first initialization signal received at the fourth node N4 to the third node N3 in response to the second light-emitting signal received at the second light-emitting signal terminal EM2, the driving sub-circuit 201 transmits the first initialization signal received at the third node N3 to the second node N2 in response to the potential at the first node N1, and the detection sub-circuit 204 transmits the first initialization signal at the second node N2 to the data signal terminal DATA in response to the second scan signal received at the second scan signal terminal GATE2.

[0152] In this way, the first signal can be transmitted to the data signal end DATA through the first reset sub-circuit 206, the second light-emitting sub-circuit 207, the driving sub-circuit 201 and the detection sub-circuit 204. In this way, by detecting the current size at the data signal end DATA, the driving sub-circuit 201 can be detected to determine whether the driving sub-circuit 201 is damaged and whether there is a difference among all the driving sub-circuits 201, so that the pixel circuit 21 can be repaired in time, the influence on the subsequent process of the pixel circuit 21 is reduced, and the preparation cost of the display device is reduced.

[0153] Exemplarily, as shown in Figure 10 and Figure 12 , each sub-circuit in the pixel circuit 21 includes a transistor 211 or a storage capacitor 212. In the first stage P1, the first reset signal, the second light-emitting signal and the second scanning signal are all 1, and the first light-emitting signal, the first scanning signal and the second reset signal are all 0. Wherein, "0" represents low level, and "1" represents high level.

[0154] In this case, the first reset signal end RESET1, the second light-emitting signal end EM2 and the second scanning signal end GATE2 input high level, and the fifth transistor T5, the sixth transistor T6 and the first transistor T1 are all turned on. The first light-emitting signal end EM1, the first scanning signal end GATE1 and the second reset signal end RESET2 input low level, and the fourth transistor T4, the third transistor T3 and the seventh transistor T7 are all turned off.

[0155] The first initialization signal received at the first initialization signal end VINIT1 is transmitted to the fourth node N4 through the fifth transistor T5, the first initialization signal received at the fourth node N4 is transmitted to the third node N3 through the sixth transistor T6, the first initialization signal received at the third node N3 is transmitted to the second node N2 through the second transistor T2, and the first initialization signal at the second node N2 is transmitted to the data signal end DATA through the first transistor T1.

[0156] As shown in Figure 10 and Figure 14 , in the second stage P2;

[0157] The first light-emitting sub-circuit 205 transmits the first voltage signal received at the first voltage signal end VDD to the second node N2 in response to the first light-emitting signal received at the first light-emitting signal end EM1, and the detection sub-circuit 204 transmits the potential at the second node N2 to the data signal end DATA in response to the second scanning signal received at the second scanning signal end GATE2.

[0158] In this way, the first voltage signal can be transmitted to the data signal end DATA through the first light-emitting sub-circuit 205 and the detection sub-circuit 204. In this way, by detecting the current size at the data signal end DATA, the first light-emitting sub-circuit 205 can be detected to determine whether the first light-emitting sub-circuit 205 is damaged and whether there is a difference among all the first light-emitting sub-circuits 205, so that the pixel circuit 21 can be repaired in time, the influence on the subsequent process of the pixel circuit 21 is reduced, and the preparation cost of the display device is reduced.

[0159] Exemplarily, as shown in FIG. 2, each sub-circuit in the pixel circuit 21 includes a transistor 211 or a storage capacitor 212. In the second phase P2, the first light-emitting signal and the second scanning signal are both 1, and the first reset signal, the second light-emitting signal, the first scanning signal, and the second reset signal are all 0. Figure 10 Figure 14 In this case, the first light-emitting signal end EM1 and the second scanning signal end GATE2 input high level, and the fourth transistor T4 and the first transistor T1 are both turned on. The first reset signal end RESET1, the second light-emitting signal end EM2, the first scanning signal end GATE1, and the second reset signal end RESET2 input low level, and the fifth transistor T5, the sixth transistor T6, the third transistor T3, and the seventh transistor T7 are all cut off.

[0160] The first voltage signal received at the first voltage signal end VDD is transmitted to the second node N2 through the fourth transistor T4, and the first voltage signal received at the second node N2 is transmitted to the data signal end DATA through the first transistor T1.

[0161] In some other embodiments, as shown in FIG. 3, the detection sub-circuit 204 and the third node N3 are coupled. In the first phase P1;

[0162] In the first phase P1, the first light-emitting signal end EM1 and the second scanning signal end GATE2 input high level, and the fourth transistor T4 and the first transistor T1 are both turned on. The first reset signal end RESET1, the second light-emitting signal end EM2, the first scanning signal end GATE1, and the second reset signal end RESET2 input low level, and the fifth transistor T5, the sixth transistor T6, the third transistor T3, and the seventh transistor T7 are all cut off. Figure 13 The first light-emitting sub-circuit 205 transmits the first voltage signal received at the first voltage signal end to the second node N2 in response to the first light-emitting signal received at the first light-emitting signal end EM1, the driving sub-circuit 201 transmits the first voltage signal received at the second node N2 to the third node N3 in response to the potential at the first node N1, and the detection sub-circuit 204 transmits the first voltage signal received at the third node N3 to the data signal end DATA in response to the second scanning signal received at the second scanning signal end GATE2.

[0163]

[0164] ​​In this way, the first voltage signal can be transmitted to the data signal end DATA through the first light-emitting sub-circuit 205, the driving sub-circuit 201 and the detection sub-circuit 204. In this way, by detecting the current size at the data signal end DATA, the driving sub-circuit 201 can be detected to determine whether the driving sub-circuit 201 is damaged and whether there is a difference among all the driving sub-circuits 201, so that the pixel circuit 21 can be repaired in time, the influence on the subsequent process of the pixel circuit 21 is reduced, and the preparation cost of the display device is reduced.

[0165] Exemplarily, as shown in Figure 11 and Figure 13 , each sub-circuit in the pixel circuit 21 includes a transistor 211 or a storage capacitor 212. In the first stage P1, the first light-emitting signal and the second scanning signal are both 1, and the first reset signal, the second light-emitting signal, the first scanning signal and the second reset signal are all 0.

[0166] In this case, the first light-emitting signal end EM1 and the second scanning signal end GATE2 input high level, and the fourth transistor T4 and the first transistor T1 are turned on. The first reset signal end RESET1, the second light-emitting signal end EM2, the first scanning signal end GATE1 and the second reset signal end RESET2 input low level, and the fifth transistor T5, the sixth transistor T6, the third transistor T3 and the seventh transistor T7 are all cut off.

[0167] The first voltage signal received at the first voltage signal end VDD is transmitted to the second node N2 through the fourth transistor T4, the first voltage signal received at the second node N2 is transmitted to the third node N3 through the second transistor T2, and the first voltage signal received at the third node N3 is transmitted to the data signal end DATA through the first transistor T1.

[0168] As shown in Figure 11 and Figure 15 , in the second stage P2;

[0169] The first reset sub-circuit 206 transmits the first initialization signal received at the first initialization signal end VINIT1 to the fourth node N4 in response to the first reset signal received at the first reset signal end RESET1, the second light-emitting sub-circuit 207 transmits the potential at the fourth node N4 to the third node N3 in response to the second light-emitting signal received at the second light-emitting signal end EM2, and the detection sub-circuit 204 transmits the potential at the third node N3 to the data signal end DATA in response to the second scanning signal received at the second scanning signal end GATE2.

[0170] In this way, the first initialization signal can be transmitted to the data signal end DATA through the first reset sub-circuit 206, the second light-emitting sub-circuit 207 and the detection sub-circuit 204. In this way, by detecting the current size at the data signal end DATA, the first reset sub-circuit 206 and the second light-emitting sub-circuit 207 can be detected to determine whether the first reset sub-circuit 206 and the second light-emitting sub-circuit 207 are damaged, and whether there is a difference between all the first reset sub-circuits 206 and the second light-emitting sub-circuits 207, so that the pixel circuit 21 can be repaired in time, the influence on the subsequent process of the pixel circuit 21 is reduced, and the preparation cost of the display device is reduced.

[0171] Exemplarily, as shown in Figure 11 and Figure 15 , each sub-circuit in the pixel circuit 21 includes a transistor 211 or a storage capacitor 212. In the second stage P2, the first reset signal, the second light-emitting signal and the second scan signal are all 1, and the first light-emitting signal, the first scan signal and the second reset signal are all 0.

[0172] In this case, the first reset signal end RESET1, the second light-emitting signal end EM2 and the second scan signal end GATE2 input high level, and the fifth transistor T5, the sixth transistor T6 and the first transistor T1 are all turned on. The first light-emitting signal end EM1, the first scan signal end GATE1 and the second reset signal end RESET2 input low level, and the fourth transistor T4, the third transistor T3 and the seventh transistor T7 are all turned off.

[0173] The first initialization signal received at the first initialization signal end VINIT1 is transmitted to the fourth node N4 through the fifth transistor T5, the first initialization signal received at the fourth node N4 is transmitted to the third node N3 through the sixth transistor T6, and the first initialization signal received at the third node N3 is transmitted to the data signal end DATA through the first transistor T1.

[0174] In some embodiments, as shown in Figure 10 , Figure 11 , Figure 16 and Figure 17 , the detection stage further includes a third stage P3.

[0175] In the third stage P3;

[0176] The second reset sub-circuit 208 transmits the second initialization signal received at the second initialization signal end VINIT2 to the first node N1 in response to the second reset signal received at the second reset signal end RESET2; and the data writing sub-circuit 202 transmits the second initialization signal received at the first node N1 to the data signal end DATA in response to the first scan signal received at the first scan signal end GATE1.

[0177] In this configuration, the second initialization signal can be transmitted to the data signal terminal DATA via the second reset sub-circuit 208 and the data writing sub-circuit 202. By detecting the current at the data signal terminal DATA, the data writing sub-circuit 202 can be monitored to determine if it is damaged and to identify any discrepancies among all data writing sub-circuits 202. This allows for timely repair of the pixel circuit 21, reducing the impact on subsequent processes and lowering the manufacturing cost of the display device.

[0178] For example, such as Figure 10 , Figure 11 , Figure 16 and Figure 17 As shown, each sub-circuit in pixel circuit 21 includes a transistor 211 or a storage capacitor 212. In the third stage P3, the second reset signal and the first scan signal are both 1, and the first reset signal, the second light emission signal, the second scan signal, and the first light emission signal are all 0.

[0179] In this configuration, the second reset signal terminal RESET2 and the first scan signal terminal GATE1 are both at high levels, and the third transistor T3 and the seventh transistor T7 are both turned on. The first reset signal terminal RESET1, the second light emission signal terminal EM2, the second scan signal terminal GATE2, and the first light emission signal terminal EM1 are all at low levels, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the first transistor T1 are all turned off.

[0180] The second initialization signal received at the second initialization signal terminal VINIT2 is transmitted to the first node N1 through the seventh transistor T7, and the second initialization signal received at the first node N1 is transmitted to the data signal terminal DATA through the third transistor T3.

[0181] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0182] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A pixel circuit, characterized in that, The detection stage comprises a first stage; The pixel circuit comprises: a driving sub-circuit coupled to the first node, the second node and the third node; the driving sub-circuit is configured to, in the first stage, control the conduction of the second node and the third node in response to the potential of the first node; a data writing sub-circuit coupled to the first node, a first scan signal terminal and a data signal terminal; a first sub-circuit coupled to a first signal terminal and a scan signal terminal; the first sub-circuit is further coupled to one of the second node and the third node; the first sub-circuit is configured to, in the first stage, transmit a first signal received at the first signal terminal to a first target node in response to a scan signal received at the scan signal terminal; wherein the first target node is the node of the second node and the third node coupled to the first sub-circuit; a detection sub-circuit coupled to a second scan signal terminal and the data signal terminal; the detection sub-circuit is further coupled to the other of the second node and the third node; the detection sub-circuit is configured to, in the first stage, transmit a signal received at a second target node to the data signal terminal in response to a second scan signal received at the second scan signal terminal; wherein the second target node is the node of the second node and the third node coupled to the detection sub-circuit.

2. The pixel circuit of claim 1, wherein, The detection sub-circuit is coupled to the second node, and the first sub-circuit comprises: a first reset sub-circuit coupled to a first initialization signal terminal, a fourth node and a first reset signal terminal; the first reset sub-circuit is configured to, in the first stage, transmit a first initialization signal received at the first initialization signal terminal to the fourth node in response to a first reset signal received at the first reset signal terminal; wherein the fourth node is configured to be coupled to an anode of a light emitting device; a second light emitting sub-circuit coupled to the third node, a second light emitting signal terminal and the fourth node; the second light emitting sub-circuit is configured to, in the first stage, transmit the received first initialization signal at the fourth node to the third node in response to a second light emitting signal received at the second light emitting signal terminal; The driving sub-circuit is configured to, in the first stage, transmit the received first initialization signal at the third node to the second node in response to the potential of the first node; The detection sub-circuit is configured to, in the first stage, transmit the received first initialization signal at the third node to the data signal terminal in response to the second scan signal received at the second scan signal terminal.

3. The pixel circuit of claim 2, wherein, The detection stage further comprises a second stage, and the pixel circuit further comprises: a first light emitting sub-circuit coupled to a first voltage signal terminal, a first light emitting signal terminal and the second node; the first light emitting sub-circuit is configured to, in the second stage, transmit a first voltage signal received at the first voltage signal terminal to the second node in response to a first light emitting signal received at the first light emitting signal terminal; The detection sub-circuit is further configured to, in the second stage, in response to a second scan signal received at a second scan signal terminal, transmit the first voltage signal received at the second node to the data signal terminal.

4. The pixel circuit of claim 1, wherein, The detection sub-circuit is coupled with the third node, and the first sub-circuit comprises: A first light emitting sub-circuit is coupled with a first voltage signal terminal, a first light emitting signal terminal and the second node; the first light emitting sub-circuit is configured to, in the first stage, in response to a first light emitting signal received at the first light emitting signal terminal, transmit the first voltage signal received at the first voltage signal terminal to the second node; The driving sub-circuit is configured to, in the first stage, in response to the potential of the first node, transmit the first voltage signal received at the second node to the third node; The detection sub-circuit is configured to, in the first stage, in response to a second scan signal received at a second scan signal terminal, transmit the first voltage signal received at the second node to the data signal terminal.

5. The pixel circuit of claim 4, wherein, The detection stage further comprises a second stage, and the pixel circuit further comprises: A first reset sub-circuit is coupled with a first initialization signal terminal, a fourth node and a first reset signal terminal; wherein the fourth node is configured to be coupled with an anode of the light emitting device; the first reset sub-circuit is configured to, in the second stage, in response to a first reset signal received at the first reset signal terminal, transmit a first initialization signal received at the first initialization signal terminal to the fourth node; A second light emitting sub-circuit is coupled with the third node, a second light emitting signal terminal and the fourth node; the second light emitting sub-circuit is configured to, in the second stage, in response to a second light emitting signal received at the second light emitting signal terminal, transmit the first initialization signal received at the fourth node to the third node; The detection sub-circuit is further configured to, in the second stage, in response to the second scan signal received at the second scan signal terminal, transmit the first initialization signal received at the third node to the data signal terminal.

6. The pixel circuit according to any one of claims 1 to 5, characterized by, The detection sub-circuit comprises: A first transistor; a first pole of the first transistor is coupled with the data signal terminal, a second pole is coupled with another of the second node and the third node, and a control pole is coupled with the second scan signal terminal.

7. The pixel circuit according to any one of claims 1 to 5, characterized by, The driving sub-circuit comprises: A second transistor; a first pole of the second transistor is coupled with the second node, a second pole is coupled with the third node, a first control pole is coupled with the first node, and a second control pole is coupled with the third node.

8. The pixel circuit according to any one of claims 1 to 5, characterized by, The detection stage further comprises a third stage, The pixel circuit further comprises: A second reset sub-circuit is coupled with a second initialization signal terminal, the first node and a second reset signal terminal; the second reset sub-circuit is configured to, in the third stage, in response to a second reset signal received at the second reset signal terminal, transmit a second initialization signal received at the second initialization signal terminal to the first node; The data writing sub-circuit is configured to, in the third stage, in response to a first scan signal received at the first scan signal terminal, transmit a second initialization signal received at the first node to the data signal terminal.

9. A method of detecting a pixel circuit, characterized by, The detection stage comprises a first stage. In the first stage, the first sub-circuit transmits a first signal received at the first signal terminal to a node coupled to the first sub-circuit in response to a scan signal received at the scan signal terminal. The driving sub-circuit transmits the first signal received at the node coupled to the first sub-circuit to a node coupled to the detection sub-circuit under the control of the first node. The detection sub-circuit transmits the first signal received at the node coupled to the detection sub-circuit to the data signal terminal in response to a second scan signal received at the second scan signal terminal.

10. The detection method according to claim 9, characterized in that, The detection sub-circuit is coupled to the second node. In the first stage, the first reset sub-circuit transmits a first initialization signal received at the first initialization signal terminal to the fourth node in response to a first reset signal received at the first reset signal terminal, the second light emitting sub-circuit transmits the first initialization signal received at the fourth node to the third node in response to a second light emitting signal received at the second light emitting signal terminal, the driving sub-circuit transmits the first initialization signal received at the third node to the second node in response to the potential at the first node, and the detection sub-circuit transmits the first initialization signal at the second node to the data signal terminal in response to a second scan signal received at the second scan signal terminal.

11. The detection method according to claim 10, characterized in that, The detection stage further comprises a second stage. In the second stage, the first light emitting sub-circuit transmits a first voltage signal received at the first voltage signal terminal to the second node in response to a first light emitting signal received at the first light emitting signal terminal, and the detection sub-circuit transmits the potential at the second node to the data signal terminal in response to a second scan signal received at the second scan signal terminal.

12. The detection method of claim 9, wherein, The detection sub-circuit is coupled to the third node. In the first stage, the first light emitting sub-circuit transmits a first voltage signal received at the first voltage signal terminal to the second node in response to a first light emitting signal received at the first light emitting signal terminal, the driving sub-circuit transmits the first voltage signal received at the second node to the third node in response to the potential at the first node, and the detection sub-circuit transmits the first voltage signal received at the third node to the data signal terminal in response to a second scan signal received at the second scan signal terminal.

13. The detection method of claim 12, wherein, The detection stage further comprises a second stage. In the second stage, the first reset sub-circuit transmits a first initialization signal received at the first initialization signal terminal to the fourth node in response to a first reset signal received at the first reset signal terminal, the second light emitting sub-circuit transmits the potential at the fourth node to the third node in response to a second light emitting signal received at the second light emitting signal terminal, and the detection sub-circuit transmits the potential at the third node to the data signal terminal in response to a second scan signal received at the second scan signal terminal.

14. The detection method according to any one of claims 9 to 13, characterized in that, The detection stage further comprises a third stage. In the third stage, the second reset sub-circuit transmits a second initialization signal received at a second initialization signal terminal to the first node in response to a second reset signal received at a second reset signal terminal; The data writing sub-circuit transmits the second initialization signal received at the first node to the data signal terminal in response to a first scan signal received at a first scan signal terminal.

15. A display device comprising: The pixel circuit includes any one of the pixel circuits according to claims 1-8.

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