Method for determining stage transmission connection of display panel and display panel

Abstract

The application provides a display panel and a cascade connection determination method of the display panel. The method comprises the following steps: obtaining cascade information of the display panel, obtaining a pre-stored cascade mode library, and determining a target cascade mode corresponding to the cascade information from the cascade mode library; determining a target phase difference corresponding to the target cascade mode; rearranging an initial order of original clock signal input of the display panel according to a DRD architecture according to a set rule to obtain a target order of clock signal input; when it is determined that the target phase difference and the target order do not match, determining a target trigger gate row corresponding to a current gate row based on the target order, and controlling the current gate row to be connected with the target trigger gate row. The application re-arranges the output order of the clock signal after selecting the target cascade mode, and then realizes the target cascade, solves the cascade limitation of the DRD architecture, and has the technical effect that the cascade design can be selected or optimized to be more optimal according to actual requirements.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of stage transmission control of display panels, in particular to a stage transmission connection determination method of a display panel and the display panel. BACKGROUND

[0002] At present, a liquid crystal display realizes the purpose of lighting display by scanning pixels row by row. With the gradual development of display technology, in order to reduce the cost and improve the display requirements, the general DRD architecture and the DLG display mode are charged and discharged in the way of row-by-row scanning.

[0003] The difference between the DLG mode and the Normal mode is that the original one-by-one opening of a row is changed to the way of opening two rows one by one for backward scanning. The DLG mode is that when two rows are opened at the same time, the pixels input by the Data are of the same color group, otherwise, display abnormalities occur and the DLG mode cannot be realized. The DRD architecture is to drive by using double Geta lines to reduce the number of Data, so as to achieve the purpose of reducing the cost. By combining the advantages of the two technologies, the DLG under the DRD architecture has strong competitiveness, but if the DLG mode is realized under the DRD architecture, it is necessary to ensure that the pixels input by the Data are of the same color resistance when two rows are opened.

[0004] However, due to the arrangement position of the clock signal of the DRD+DLG mode, the stage transmission is limited to a multiple of 4, thereby there is a risk of display abnormalities; and due to the stage transmission being limited in several specific ways, the stage transmission selection is greatly limited. SUMMARY

[0005] In order to solve the technical problem of driving abnormalities caused by the above-mentioned stage transmission limitation, the embodiments of the present application provide at least a stage transmission connection determination method of a display panel and the display panel.

[0006] In a first aspect, the embodiments of the present application provide a stage transmission connection determination method of a display panel, applied to a display panel of a double-gate stage driving DRD architecture, comprising:

[0007] obtaining stage transmission information of the display panel, and obtaining a pre-stored stage transmission mode library, and determining a target stage transmission mode corresponding to the stage transmission information from the stage transmission mode library;

[0008] determining a target phase difference corresponding to the target stage transmission mode, the target phase difference representing a stage transmission interval;

[0009] rearranging an initial order of original clock signal input of the display panel according to the DRD architecture in a set rule to obtain a target order of the clock signal input;

[0010] When it is determined that the target phase difference does not match the target order, a target trigger gate row corresponding to a current gate row is determined based on the target order, and the current gate row is connected to the target trigger gate row so that a phase difference between the target trigger gate row and the current gate row matches the target phase difference.

[0011] In an optional implementation, the target transmission mode corresponding to the transmission information is determined from the transmission mode library, including:

[0012] An information attribute of the transmission information is determined, and the transmission attribute represents a characteristic of the transmission information.

[0013] The preset transmission mode is generated based on the information attribute, and a transmission mode in the transmission mode library is matched with the preset transmission mode.

[0014] When the preset transmission mode matches the transmission mode in the transmission mode library, a corresponding target transmission mode is determined.

[0015] In an optional implementation, the target phase difference corresponding to the target transmission mode is determined, including:

[0016] A pull-up trigger value and a pull-down trigger value corresponding to the target transmission mode are determined.

[0017] A target phase difference is determined according to the pull-up trigger value and the pull-down trigger value, and the target phase difference includes a pull-up target phase difference and a pull-down target phase difference.

[0018] In an optional implementation, two gate rows are scanned simultaneously when the display panel is driven to scan.

[0019] The initial order of the original clock signal input of the display panel is rearranged according to a set rule to obtain a target order of the clock signal input according to the DRD architecture, including:

[0020] In the display panel, a plurality of groups of adjacent data lines of the same color group are determined.

[0021] A gate row corresponding to each group of adjacent data lines is determined as a simultaneous scanning group, and the initial order of the original clock signal input is rearranged according to a set rule based on the simultaneous scanning group to obtain a target order of the clock signal input.

[0022] In an optional implementation, the initial order of the original clock signal input is rearranged according to a set rule based on the simultaneous scanning group to obtain a target order of the clock signal input, including:

[0023] determine adjacent the simultaneous scanning groups as gate groups, and acquire a wiring sequence corresponding to a gate row pair in the gate groups;

[0024] adjust a wiring sequence corresponding to each simultaneous scanning group in the gate groups as adjacent wiring to obtain a target wiring sequence;

[0025] rearrange an initial sequence of the original clock signal input according to a set rule based on the target wiring sequence to obtain a target sequence of the clock signal input.

[0026] In an optional implementation, the determining that the target phase difference does not match the target sequence includes:

[0027] determining an original trigger gate row corresponding to a current gate row based on the stage transmission information;

[0028] determining an up pull trigger phase difference and a down pull trigger phase difference between the original trigger gate row and the current gate row based on the target sequence;

[0029] determining that the target phase difference does not match the target sequence when the up pull trigger phase difference does not match the up pull target phase difference;

[0030] and / or,

[0031] determining that the target phase difference does not match the target sequence when the down pull trigger phase difference does not match the down pull target phase difference.

[0032] In an optional implementation, the determining that the target phase difference does not match the target sequence includes:

[0033] acquiring a stage transmission limit of the DRD architecture, the stage transmission limit representing a constraint condition of the DRD architecture;

[0034] determining that the target phase difference does not match the target sequence when it is determined that the stage transmission limit does not match a multiple of the target phase difference.

[0035] In an optional implementation, the target trigger gate row includes an up pull trigger gate row and a down pull trigger gate row.

[0036] The determining a target trigger gate row corresponding to a current gate row based on the target sequence includes:

[0037] determining an up pull trigger gate row corresponding to the current gate row after moving the current gate row upward by a number of gate rows corresponding to the up pull trigger phase difference according to the target sequence;

[0038] determining a pull-down trigger gate row corresponding to the current gate row according to the target sequence.

[0039] In an alternative embodiment, the control of the connection of the current gate row and the target trigger gate row so as to match the phase difference between the target trigger gate row and the current gate row with the target phase difference comprises:

[0040] controlling the connection of the current gate row and the pull-up trigger gate row so as to match the pull-up trigger phase difference between the pull-up trigger gate row and the current gate row with the pull-up target phase difference;

[0041] controlling the connection of the current gate row and the pull-down trigger gate row so as to match the pull-down trigger phase difference with the pull-down target phase difference.

[0042] In a second aspect, the embodiments of the present application provide a display panel, comprising: a plurality of gate rows and a level transmission connection module, wherein each gate row is provided with two gate lines;

[0043] The level transmission connection module is configured to acquire level transmission information of the display panel, acquire a pre-stored level transmission mode library, and determine a target level transmission mode corresponding to the level transmission information from the level transmission mode library; determine a target phase difference corresponding to the target level transmission mode, the target phase difference representing a level transmission interval; rearrange an initial order of an original clock signal of the display panel according to a set rule based on the DRD architecture to obtain a target order of a target clock signal; when it is determined that the target phase difference does not match the target order, determine a target trigger gate row corresponding to a current gate row based on the target order, and control the connection of the current gate row and the target trigger gate row so as to match the phase difference between the target trigger gate row and the current gate row with the target phase difference.

[0044] The above technical solutions provided by the embodiments of the present application have the following advantages compared with the prior art: the method provided by the embodiments of the present application rearranges the output order of the clock signal after selecting the target level transmission mode, and then realizes the target level transmission, solves the level transmission limitation of the DRD architecture, and has the technical effect of selecting or optimizing to a more optimal level transmission design according to actual needs. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows, the drawings herein are incorporated into the description and form a part of the description, the drawings show the embodiments consistent with the present application, and are used to illustrate the technical solutions of the present application together with the description. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor.

[0046] Figure 1a A display panel level transmission relationship chain representation intention provided in the prior art scenario;

[0047] Figure 1b A display panel level transmission relationship access structure schematic diagram provided in the prior art scenario;

[0048] Figure 1c Another display panel level transmission relationship chain representation intention provided in the prior art scenario;

[0049] Figure 1d Another display panel level transmission relationship access structure schematic diagram provided in the prior art scenario;

[0050] Figure 2 A display panel DLG mode level transmission waveform diagram provided in the prior art scenario;

[0051] Figure 3 A display panel level transmission connection determination method flowchart provided in the embodiments of the present application;

[0052] Figure 4 Another display panel level transmission connection determination method flowchart provided in the embodiments of the present application;

[0053] Figure 5 A display panel level transmission relationship chain representation intention provided in the embodiments of the present application;

[0054] Figure 6 A display panel level transmission relationship access structure schematic diagram provided in the embodiments of the present application;

[0055] Figure 7 Another display panel level transmission relationship chain representation intention provided in the embodiments of the present application;

[0056] Figure 8 Another display panel level transmission relationship access structure schematic diagram provided in the embodiments of the present application;

[0057] Figure 9A structural schematic diagram of a display panel provided by an embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0059] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0060] The term "and / or" herein only describes an association relationship, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of multiple or any combination of at least two of multiple, for example, including at least one of A, B and C can mean including any one or more elements selected from the set consisting of A, B and C.

[0061] It is found through research that when the TFT-LCD is working, the liquid crystal in the single pixel of the display area changes in transmittance after the pixel is subjected to an external voltage, the color is transmitted accordingly, all the pixels arranged in an array in the display area are switched frame by frame to realize dynamic display. The pixel control is performed in a row-by-row scanning manner to charge and discharge, with the gradual development of display technology, in order to reduce the cost and improve the display requirements, the DRD architecture and the DLG display mode are adopted.

[0062] Figure 1a and Figure 1b are respectively a level transmission relationship chain table and a level transmission relationship access structure diagram of a Normal DRD mode in a prior art scenario, and Figure 1c and Figure 1dCompared with the cascade relationship link list and the cascade relationship access structure diagram in the DRD+DLG mode, the difference between the DLG mode and the Normal mode is that the two rows are opened in turn to scan backward instead of opening one row in turn. Whether the DLG mode is applicable depends on whether the pixels to which the Data data are input are of the same color group when the two rows are opened at the same time, otherwise, display abnormalities cannot be realized, and the DLG mode cannot be driven to display. The DRD architecture is driven by double Geta lines to reduce the amount of Data data, so as to reduce the cost.

[0063] The DLG in the DRD architecture has strong competitiveness by comprehensively combining the advantages of the two technologies, but if the DLG mode is realized in the DRD architecture, it is necessary to ensure that the pixels to which the Data data are input are of the same color group when the two rows are opened, and it is necessary to change the input order of the original clock signal CK (12345678…→13245768…) to meet the requirements.

[0064] Reference Figure 1c and Figure 1d The input order of the clock signal CK needs to be changed (12345678…→13245768…) when the DRD+DLG mode is driven, and the cascade number needs to meet the multiple of 4, otherwise the Figure 2 The display model of the Q point provided will appear in two different forms, and there is a risk of display abnormalities. According to the Figure 1a and Figure 1c As shown in the Normal mode to the DLG mode switching, taking the-4+6 cascade number as an example, the cascade relationship of the first to the thirteenth rows is presented. Taking the sixth row as an example, the current clock signal CK in the DLG mode is CK7, the up pull trigger (Carry-4) is CK3, so the up pull trigger phase difference is 4, and the down pull trigger (Carry+6) is CK11, so the down pull trigger phase difference is 4, and thus the cascade mode is equivalent to-4+4 at this time. Therefore, the-4+6 cascade has Figure 2 two Q point forms in the middle. By analogy, the Q point will appear in two forms under the non-4 multiple cascade in the DRD+DLG mode, which will affect the Gout output, and there is a risk of display abnormalities. According to the cascade reasoning under different modes, the cascade is limited to-4+4, -4+8, -8+4, and-8+8, and among them, the-4+4, -8+4, and-8+8 cascades are limited to 4H or less for the clock signal CK, which leads to the problems of large Q point flicker and low Vmax, and greatly limits the cascade selection.

[0065] Based on the above research, in order to solve the cascade limitation, the application provides a cascade connection determination method of a display panel, which changes the arrangement order of the clock signal CK, re-scans the scanning rows, breaks the limitation problem that the cascade receives the multiple of 4, and realizes the selection or optimization to a more optimal cascade design according to the actual demand.

[0066] For the purpose of facilitating the understanding of the embodiments of the present application, further explanation and description will be made in specific embodiments in conjunction with the accompanying drawings, which do not constitute a limitation to the embodiments of the present application.

[0067] Figure 3 A flowchart of a level transmission connection determination method of a display panel is provided for the embodiments of the present application. The method is applied to a display panel of a double-gate level driving (DRD) architecture. According to the embodiments of the present application, the level transmission connection determination method of the display panel comprises the following steps. Figure 3 According to the provided diagram, the steps of the level transmission connection determination method of the display panel specifically comprise:

[0068] S301, obtaining level transmission information of the display panel, and obtaining a pre-stored level transmission mode library, and determining a target level transmission mode corresponding to the level transmission information from the level transmission mode library.

[0069] The present application is applied to the process of driving the display panel of the DRD level transmission. By reordering the clock signals, adjusting the level transmission number position, and performing row-by-row scanning according to the ordered scanning sequence, the clock signals corresponding to the pull-up trigger unit and the pull-down trigger unit of each driving unit are compared, and the level transmission number value is calculated according to the phase difference. It is judged whether the level transmission number value matches the set level transmission number, and then the purpose of setting any level transmission number according to the demand is achieved, breaking the limitation of the level transmission.

[0070] The level transmission information mentioned here can be understood as level transmission data, such as display panel size, working frequency, or working temperature factor data. The level transmission mode library mentioned here can be understood as a database storing various level transmission modes. By selecting the appropriate level transmission mode from the level transmission mode library according to the different level transmission information.

[0071] Further, in the process of driving the display panel, according to the different level transmission information, a suitable level transmission mode is selected from the database storing a plurality of level transmission modes as a target level transmission mode, which provides a reference mode for the next level transmission data operation.

[0072] S302, determining a target phase difference corresponding to the target level transmission mode, the target phase difference representing a level transmission distance.

[0073] The target phase difference mentioned here can be understood as the time difference between the clock signal and the pull-up level transmission unit, or the time difference between the clock signal and the pull-down level transmission unit.

[0074] Further, after determining the target level transmission mode, the difference between the clock signal and the level transmission unit is calculated according to the size of the level transmission mode as the target phase difference, which provides a reference for the next step of inferring whether the level transmission data is successful.

[0075] S303, rearrange the initial order of the original clock signal input of the display panel according to the DRD architecture according to the set rule to obtain the target order of the clock signal input.

[0076] The set rule mentioned here can be understood as a rule for reordering the input order of the clock signal according to the difference of the target cascade mode.

[0077] Further, in the pixel array of the display panel, the input order of the original clock signal of the driving row pixel unit is first reordered, and the clock signal is rearranged according to the difference of the target cascade mode to obtain the target order of the clock signal. The target order and the target cascade mode are one-to-one corresponding through the set rule, so as to ensure that the input order of the clock signal meets the set requirement of the cascade number.

[0078] S304, when it is determined that the target phase difference and the target order do not match, determining the target trigger gate row corresponding to the current gate row based on the target order, and controlling the current gate row and the target trigger gate row to be connected, so that the phase difference between the target trigger gate row and the current gate row matches the target phase difference.

[0079] The current gate row mentioned here can be understood as the current driving pixel row. Each gate row has two cascade data lines, which are connected to the cascade ports of other pixel rows. The target trigger gate row mentioned here can be understood as the adjacent gate row having a cascade relationship with the current cascade gate row, which is the last cascade row of the current gate row and the next gate row of the current gate row.

[0080] Further, by calculating the phase difference corresponding to the target order of the current gate row and comparing it with the target phase difference, when the target phase difference and the target order do not match, the current gate row is calculated through the cascade mode to obtain the target trigger gate row matching the cascade relationship with the adjacent current gate row, and the current gate row and the target trigger gate row are directly connected to realize the cascade control under the target cascade mode.

[0081] The embodiment of the application provides a display panel level transmission connection determination method, which comprises the following steps: obtaining level transmission information of a display panel; obtaining a pre-stored level transmission mode library; and determining a target level transmission mode corresponding to the level transmission information from the level transmission mode library; determining a target phase difference corresponding to the target level transmission mode, wherein the target phase difference represents a level transmission interval; rearranging an initial order of original clock signal input of the display panel according to a DRD architecture and a set rule to obtain a target order of clock signal input; when it is determined that the target phase difference and the target order do not match, determining a target trigger gate line corresponding to a current gate line based on the target order, and connecting the current gate line and the target trigger gate line to make the phase difference between the target trigger gate line and the current gate line match the target phase difference. The output order of the clock signal is rearranged after the target level transmission mode is selected, and then the target level transmission is realized, so that the level transmission limitation of the DRD architecture is solved, and the technical effect of selecting or optimizing a more optimal level transmission design according to actual requirements is achieved.

[0082] Figure 4 The flowchart of another display panel level transmission connection determination method provided by the embodiment of the application is shown. Figure 4 The embodiment is introduced on the basis of the above embodiment. According to the Figure 4 The steps of the display panel level transmission connection determination method provided by the embodiment are specifically shown in the diagram.

[0083] S401, determining an information attribute of the level transmission information, wherein the level transmission attribute represents the characteristics of the level transmission information.

[0084] S402, generating a preset level transmission mode based on the information attribute, and matching the preset level transmission mode with a level transmission mode in the level transmission mode library.

[0085] S403, determining a target level transmission mode corresponding to the preset level transmission mode when the preset level transmission mode matches the level transmission mode in the level transmission mode library.

[0086] The level transmission information mentioned herein can be understood as level transmission data. The level transmission attribute mentioned herein can be understood as a data factor affecting the level transmission, such as a display panel size, a working frequency or a working temperature and the like. The level transmission mode library mentioned herein can be understood as a database storing various level transmission modes, and a suitable level transmission mode is selected from the level transmission mode library according to different level transmission information. For example, the level transmission mode can be set as a-4+4 mode, a-4+6 mode, a-4+8 mode, an-8+8 mode and the like.

[0087] Further, in the display panel driving process, according to different level transmission information, a preset level transmission mode is first set, and a suitable level transmission mode is selected from a database storing a plurality of level transmission modes and compared with the preset level transmission mode, and when the two match, the selected level transmission mode is taken as a target level transmission mode to provide a reference mode for the next level transmission data operation.

[0088] S404, determine the pull-up trigger value and the pull-down trigger value corresponding to the target level transmission mode.

[0089] S405, determine the target phase difference according to the pull-up trigger value and the pull-down trigger value, the target phase difference includes the pull-up target phase difference and the pull-down target phase difference.

[0090] The pull-up trigger value mentioned here can be understood as the difference between the scan value of the clock signal corresponding to the current gate row and the scan value of the clock signal corresponding to the pull-up gate row which is level transmitted by the current gate row. The pull-up target phase difference mentioned here can be understood as the phase difference between the position of the current gate row and the position of the pull-up gate row which is level transmitted by the current gate row.

[0091] Further, according to the target level transmission mode, the clock signal value corresponding to the scan of the current gate row is obtained first, and then the pull-up trigger value of the pull-up unit corresponding to the level transmission relationship of the current gate row is deduced, and the pull-down trigger value corresponding to the level transmission relationship of the pull-down unit is deduced. The pull-up target phase difference is obtained by calculating the difference between the clock signal value scanned by the current gate row and the pull-up trigger value, and the pull-down target phase difference is obtained by calculating the difference between the clock signal value scanned by the current gate row and the pull-down trigger value. Thus, the target phase difference under the current level transmission mode is determined, which provides a reference for verifying whether the level transmission is stable in the target level transmission mode.

[0092] For example, when the target level transmission mode is set to -4+6, the clock signal value scanned by the current gate row is detected as CK7, and the corresponding pull-up value is detected as CK4. Then, the pull-up target phase difference is -4. After checking, the pull-down trigger value is CK13, and the pull-down target phase difference is calculated as 6, which meets the level transmission requirement of -4+6.

[0093] S406, determine the adjacent data lines of the multiple groups of the same color groups in the display panel.

[0094] Here, the display panel simultaneously scans two gate rows during driving and scanning. The adjacent data lines mentioned here can be understood as the data lines connected to the same clock signal in a level transmission unit.

[0095] S407, determine the gate row corresponding to each group of adjacent data lines as a simultaneous scanning group, and rearrange the initial order of the original clock signal input based on the simultaneous scanning group according to the set rule, to obtain the target order of the clock signal input.

[0096] Further, the input order of the clock signal corresponding to the simultaneous scanning group connected by the adjacent data line is reordered, and the reordering is performed according to a set rule, so that the input order of the clock signal in the target level transmission mode in the DRD architecture Normal mode is obtained, and the input order of the clock signal in the DLG mode is rearranged, so that the input order of the clock signal in the DLG mode in the DRD architecture is obtained.

[0097] In a possible example scenario, Figure 5 and Figure 6 A schematic diagram of a -4+6 level transmission mode relationship chain table and -4+6 level transmission relationship access of a display panel provided by the embodiment of the application. By Figure 5 and Figure 6 The diagram provided is that the order of the clock signal is reordered from 1, 2, 3, 4, 5,..., to obtain a new clock signal input order: 13245768.... The input order of the clock signal converted to the DLG mode is rearranged, and the arrangement rule is that 1, 2, 3, 4, 5, 6, 7, 8... is first arranged in groups of four, and the middle exchange is changed to 13245768.... Then 2468 is replaced by 1357, and the arrangement order of the clock signal in the DLG mode is obtained: 13135757.... And a new clock signal input order is obtained. According to Figure 5 The gate lines of the display panel are connected in the order, and according to the selected -4+6 level transmission mode, 4 cells are pulled up directly above and 6 cells are pulled down directly below for the current gate line, and then the connection relationship in the level transmission mode shown in Figure 6 is obtained.

[0098] S408, the adjacent simultaneous scanning group is determined as a gate group, and the wiring order corresponding to the gate line in the gate group is obtained.

[0099] S409, the wiring order corresponding to each simultaneous scanning group in the gate group is adjusted to an adjacent wiring, and a target wiring order is obtained.

[0100] S410, the initial order of the original clock signal input is rearranged according to a set rule based on the target wiring order, and a target order of the clock signal input is obtained.

[0101] The adjacent wiring mentioned here can be understood as that the same clock signal connects two adjacent scanning lines.

[0102] Further, the set simultaneous scanning group is regarded as a gate group, that is, the same clock signal connects two scanning groups, and the adjacent wiring connection is performed on the gate group, and the clock signal is reordered according to the current wiring order, so that the target order is obtained.

[0103] In one possible example scenario, Figure 7 and Figure 8 This is a schematic diagram illustrating a -4+6 level transmission relationship chain list and a -4+6 level transmission relationship access method for a display panel, provided as an embodiment of this application. (Through...) Figure 7 and Figure 8 The provided diagram shows that, while maintaining the original clock signal sequence of 1, 2, 3, 4, 5..., the input sequence of the clock signal in DLG mode is rearranged. The arrangement rule is to first group 1, 2, 3, 4, 5, 6, 7, 8... into groups of four, swapping the middle two to obtain the sequence: 13245768... Then, 2468 is replaced with 1357, resulting in the clock signal sequence in DLG mode: 13135757... Swapping the middle two gives the input sequence: 11335577..., thus obtaining the new clock signal input sequence. Figure 7 The gate rows of the display panel are connected sequentially. The scan clock signal uses rows 12 as a simultaneous scan group and rows 34 as a simultaneous scan group. Without changing the gate row cascade connection lines, the positions of the cascade units are changed to multiples of 4, with the middle two cascade units cross-connected to the gate lines of the AA area cascade, thus obtaining... Figure 8 The connection relationship is shown in the cascading transmission mode.

[0104] S411. Determine the original trigger gate row corresponding to the current gate row based on the stage transmission information.

[0105] S412. Determine the pull-up trigger phase difference and pull-down trigger phase difference between the original trigger gate row and the current gate row based on the target order.

[0106] S413. When the pull-up trigger phase difference and the pull-up target phase difference do not match, determine that the target phase difference and the target order do not match.

[0107] S414. When the phase difference of the pull-down trigger does not match the phase difference of the pull-down target, determine that the target phase difference does not match the target order.

[0108] The pull-up trigger phase difference mentioned here can be understood as the difference between the clock signal of the current gate row and the clock signal of the cascade pull-up unit. Similarly, the pull-down trigger phase difference can be understood as the difference between the clock signal of the current gate row and the clock signal of the cascade pull-down unit.

[0109] Further, the original = trigger gate row is obtained according to the pull-up gate row and the pull-down gate row connected to the current gate row, the phase difference between the scan clock signal corresponding to the current gate row and the 2 gate rows connected in cascade is calculated according to the target order, and the pull-up trigger phase difference and the pull-down trigger phase difference are obtained. By comparing the pull-up trigger phase difference with the target phase difference, it is determined whether the cascade gate row connected to the current gate row meets the requirement of the target cascade mode. If the pull-up trigger phase difference does not match the pull-up target phase difference or the pull-down trigger phase difference does not match the pull-down target phase difference, it is indicated that the current cascade mode does not meet the cascade requirement of the display panel, and it is further determined that the currently selected cascade mode is not suitable, thereby providing a reference basis for reselecting a suitable cascade mode from the cascade mode library in the next step.

[0110] S415, obtain a cascade limit of the DRD architecture, the cascade limit representing a constraint condition of the DRD architecture.

[0111] S416, when it is determined that the cascade limit does not match the multiple of the target phase difference, it is determined that the target phase difference does not match the target order.

[0112] The cascade limit mentioned here can be understood as a limit condition for driving and displaying the display panel under the DRD architecture, for example, the size, working temperature or working frequency or display multiple of the display panel.

[0113] Further, the cascade limit for driving and displaying the display panel is obtained according to the limitation of the DRD architecture itself, for example, the multiple of 4 or the multiple of 2, and then it is determined whether the target phase difference matches the target order according to whether the limited cascade limit matches the multiple of the target phase difference. For example, when it is determined that the multiple of 2 is required in the DRD architecture, when the -4+8 cascade mode is selected, the constraint condition of the corresponding cascade mode is the multiple of 4, which does not match the multiple of 2, and then it is obtained that -4+8 does not meet the multiple of 2.

[0114] In a possible example scenario, Figure 5 and Figure 7 The clock signal input order linked list of the 2 cascade mode is obtained. According to the clock signal input order linked list of the 2 cascade mode, Figure 5The provided diagram takes-4+6 level transmission as an example. When switched to the DLG mode, the CK input sequence is the same as the existing scheme: 13135757…, which presents the level transmission relationship of the first to the thirteenth rows. Taking the sixth row as an example, the clock signal CK of the current gate row in the DLG mode is CK7, the clock signal value of the up pull trigger (Carry-4) unit is CK3, so the up pull trigger phase difference is 4, the clock signal value of the down pull trigger (Carry+6) unit is CK1, so the down pull trigger phase difference is 6, so the level transmission mode is still equivalent to-4+6 at this time, and the rest of the rows are the same. Therefore, the scheme is no longer limited to multiples of 4 for level transmission at this time, which improves the design space of the product, solves the level transmission limitation problem, and improves the product performance.

[0115] Similarly, according to Figure 7 The provided diagram takes-4+6 level transmission as an example. When switched to the DLG mode, the CK input sequence is the same as the existing scheme: 13135757…, which presents the level transmission relationship of the first to the thirteenth rows. Taking the sixth row as an example, the clock signal CK of the current gate row in the DLG mode is CK7, the clock signal value of the up pull trigger (Carry-4) unit is CK3, so the up pull trigger phase difference is 4, the clock signal value of the down pull trigger (Carry+6) unit is CK1, so the down pull trigger phase difference is 6, so the level transmission mode is still equivalent to-4+6 at this time, and the rest of the rows are the same. Therefore, the scheme is no longer limited to multiples of 4 for level transmission at this time, which improves the design space of the product, solves the level transmission limitation problem, and improves the product performance.

[0116] Since the CK input sequence does not need to be changed, when switched to the DLG mode, only 12345678… is changed to 11335577…, which presents the level transmission relationship of the first to the thirteenth rows. Taking the sixth row as an example, the clock signal CK of the current gate row in the DLG mode is CK7, the clock signal value of the up pull trigger (Carry-4) unit is CK3, so the up pull trigger phase difference is 4, the clock signal value of the down pull trigger (Carry+6) unit is CK1, so the down pull trigger phase difference is 6, so the level transmission mode is still equivalent to-4+6 at this time, and the rest of the rows are the same. Therefore, the scheme is no longer limited to multiples of 4 for level transmission at this time.

[0117] The target trigger gate row includes an up pull trigger gate row and a down pull trigger gate row.

[0118] S417, moving the current gate row by the up pull trigger phase difference corresponding number of gate rows in the target sequence to determine the up pull trigger gate row corresponding to the current gate row.

[0119] S418, moving the current gate row by the down pull trigger phase difference corresponding number of gate rows in the target sequence to determine the down pull trigger gate row corresponding to the current gate row.

[0120] S419, control the current gate row and the up pull trigger gate to be connected, so that the up pull trigger phase difference between the up pull trigger gate row and the current gate row matches the up pull target phase difference.

[0121] S420, control the current gate row and the down pull trigger gate to be connected, so that the up pull trigger phase difference between the up pull trigger gate row and the current gate row matches the up pull target phase difference.

[0122] Further, the connection lines of the gate rows are re-adjusted according to the rearrangement of the clock signals. According to the rearrangement of the new clock signals, the pull-up trigger phase difference and the pull-down trigger phase difference corresponding to the target level transmission mode are calculated, the corresponding pull-up trigger gate row and the pull-down trigger gate row are found, and the current gate row is connected with the pull-up trigger gate row and the pull-down trigger gate row, so that the pull-up trigger phase difference between the pull-up trigger gate row and the current gate row matches the pull-up target phase difference, and the pull-up trigger phase difference between the pull-up trigger gate row and the current gate row matches the pull-up target phase difference.

[0123] In a possible example scenario, Figure 6 and Figure 8 is a level transmission relationship connection diagram. According to Figure 6 the diagram provided, after the clock signals are reordered in the Figure 5 -4+6 level transmission, for example, the gate row of the current clock signal CK1 is moved up by 4 units according to the pull-up trigger phase difference 4 to obtain CK9, and the level transmission connection is performed, and the pull-down trigger gate row is found by moving down by 6 units, and the connection between the right side of the gate row and the AA area is kept unchanged to obtain a new level transmission connection diagram.

[0124] Similarly, in the Figure 8 -4+6 level transmission, for example, the gate row is moved up by 4 units according to the pull-up trigger phase difference 4 to obtain CK9, and the level transmission connection is performed, and the pull-down trigger gate row is found by moving down by 6 units, and the connection between the right side of the gate row and the AA area is kept unchanged to obtain a new level transmission connection diagram. Figure 7

[0125] Optionally, according to the rearrangement of the clock signals and the connection mode of the connection lines of the gate rows in the present application, -6+4, -2+4 and -4+2 can also be implemented according to the set requirements. The same design mode, specific implementation mode and steps will not be repeated here.

[0126] Figure 9 is a structure diagram of a display panel provided in an embodiment of the present application. According to Figure 9 the diagram provided, the display panel includes a plurality of gate rows and a level transmission connection module 100, wherein two gate lines are arranged for each gate row;

[0127] ​The stage transmission connection module 100 is configured to acquire stage transmission information of the display panel, acquire a pre-stored stage transmission mode library, and determine a target stage transmission mode corresponding to the stage transmission information from the stage transmission mode library; determine a target phase difference corresponding to the target stage transmission mode, the target phase difference representing a stage transmission interval; rearrange an initial order of an original clock signal of the display panel according to a DRD architecture according to a set rule to obtain a target order of a target clock signal; when it is determined that the target phase difference and the target order do not match, determine a target trigger gate row corresponding to a current gate row based on the target order, and control the current gate row and the target trigger gate row to be connected, so that a phase difference between the target trigger gate row and the current gate row matches the target phase difference.

[0128] The display panel 1000 provided by the embodiment can be a display panel 1000 as shown in Figure 9 The display panel 1000 provided by the embodiment can be a display panel 1000 as shown in Figures 3-8 The display panel 1000 provided by the embodiment can be a display panel 1000 as shown in Figures 3-8 The display panel 1000 provided by the embodiment can be a display panel 1000 as shown in Figures 3-8 The display panel 1000 provided by the embodiment can be a display panel 1000 as shown in

[0129] Finally, it should be noted that: the above-described embodiments are merely specific implementations of the present application, used to illustrate the technical solutions of the present application, rather than limit the same, the protection scope of the present application is not limited thereto, although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art within the technical range disclosed by the present application, they can still modify or easily think of changes to the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications, changes or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, all should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for determining the cascading connection of a display panel, characterized in that, Display panels used in dual-gate level driven DRD architectures include: Obtain the cascading information of the display panel and obtain a pre-stored cascading method library, and determine the target cascading method corresponding to the cascading information from the cascading method library; Determine the target phase difference corresponding to the target transmission method, wherein the target phase difference characterizes the transmission interval; According to the DRD architecture, the initial order of the original clock signal input to the display panel is rearranged according to the set rules to obtain the target order of the clock signal input. When it is determined that the target phase difference does not match the target order, the target trigger gate row corresponding to the current gate row is determined based on the target order, and the current gate row is connected to the target trigger gate row so that the phase difference between the target trigger gate row and the current gate row matches the target phase difference.

2. The method according to claim 1, characterized in that, Determining the target cascading method corresponding to the cascading information from the cascading method library includes: Determine the information attributes of the hierarchical information, wherein the information attributes characterize the characteristics of the hierarchical information; A preset transmission method is generated based on the information attributes, and the preset transmission method is matched with the transmission methods in the transmission method library. When the preset transmission method matches the transmission method in the transmission method library, the corresponding target transmission method is determined.

3. The method according to claim 2, characterized in that, Determining the target phase difference corresponding to the target transmission mode includes: Determine the pull-up trigger value and pull-down trigger value corresponding to the target transmission method; The target phase difference is determined based on the pull-up trigger value and the pull-down trigger value, and the target phase difference includes the pull-up target phase difference and the pull-down target phase difference.

4. The method according to claim 1, characterized in that, The display panel scans two gate rows simultaneously during driving scanning; The step of rearranging the initial order of the original clock signal inputs to the display panel according to the DRD architecture based on a set rule to obtain the target order of the clock signal inputs includes: Multiple adjacent data lines of the same color group are identified in the display panel; Each group of adjacent data lines is defined as a simultaneous scan group, and the initial order of the original clock signal input is rearranged according to a set rule based on the simultaneous scan group to obtain the target order of the clock signal input.

5. The method according to claim 4, characterized in that, The process of rearranging the initial order of the original clock signal inputs according to a set rule based on the simultaneous scanning group to obtain the target order of the clock signal inputs includes: The adjacent simultaneous scanning groups are determined as gate groups, and the wiring sequence corresponding to the gate row in the gate group is obtained; The wiring order corresponding to each simultaneous scanning group in the gate group is adjusted to be adjacent wiring to obtain the target wiring order; Based on the target wiring sequence, the initial order of the original clock signal input is rearranged according to a set rule to obtain the target order of the clock signal input.

6. The method according to claim 3, characterized in that, The determination that the target phase difference does not match the target order includes: Based on the cascade information, determine the original trigger gate row corresponding to the current gate row; Based on the target order, determine the pull-up trigger phase difference and the pull-down trigger phase difference between the original trigger gate row and the current gate row; When the pull-up trigger phase difference does not match the pull-up target phase difference, it is determined that the target phase difference does not match the target order. And / or, When the pull-down trigger phase difference does not match the pull-down target phase difference, it is determined that the target phase difference does not match the target order.

7. The method according to claim 1, characterized in that, The determination that the target phase difference does not match the target order includes: Obtain the cascading constraints of the DRD architecture, whereby the cascading constraints characterize the constraints of the DRD architecture; When it is determined that the transmission limit does not match the multiple of the target phase difference, it is determined that the target phase difference does not match the target order.

8. The method according to claim 6, characterized in that, The target trigger gate row includes: a pull-up trigger gate row and a pull-down trigger gate row; Determining the target trigger gate row corresponding to the current gate row based on the target order includes: After moving the current gate row upwards by the number of gate rows corresponding to the pull-up trigger phase difference according to the target order, the pull-up trigger gate row corresponding to the current gate row is determined. After moving the current gate row downwards by the number of gate rows corresponding to the pull-down trigger phase difference according to the target order, the pull-down trigger gate row corresponding to the current gate row is determined.

9. The method according to claim 8, characterized in that, The step of controlling the connection between the current gate row and the target trigger gate row to match the phase difference between the target trigger gate row and the current gate row with the target phase difference includes: The current gate row is connected to the pull-up trigger gate row so that the pull-up trigger phase difference between the pull-up trigger gate row and the current gate row matches the pull-up target phase difference; The current gate row is connected to the pull-down trigger gate row so that the pull-down trigger phase difference and the pull-down target phase difference are matched.

10. A display panel, comprising: Multiple gate rows and cascade connection modules, wherein each gate row is provided with two gate lines; The cascading connection module is used to acquire cascading information of the display panel and a pre-stored cascading mode library, and determine the target cascading mode corresponding to the cascading information from the cascading mode library; determine the target phase difference corresponding to the target cascading mode, the target phase difference representing the cascading spacing; rearrange the initial order of the original clock signal of the display panel according to a set rule based on the DRD architecture to obtain the target order of the clock signal input; when it is determined that the target phase difference does not match the target order, determine the target trigger gate row corresponding to the current gate row based on the target order, and control the current gate row to connect with the target trigger gate row so that the phase difference between the target trigger gate row and the current gate row matches the target phase difference.

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