Gate driving circuit and display panel

Abstract

This application discloses a gate driving circuit and a display panel. The gate driving circuit includes a shift register, which includes a pull-up module, a pull-down module, and a compatibility control module. By adding a compatibility control module connected to the pull-up module to the shift register, the pull-up module provides a corresponding gate driving signal to the gate driving line at low refresh rates, and the pull-up module and the compatibility control module jointly provide a corresponding gate driving signal to the gate driving line at high refresh rates. This can improve the driving capability of the gate driving signal in the gate driving line as the refresh rate increases, thereby controlling the consistency of the charging rate at different refresh rates under the drive of the compatibility control line, and thus enabling the same or similar display quality and reliability to be presented at different refresh rates.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a gate driving circuit and a display panel. BACKGROUND

[0002] With the development of display panels, the requirement for refresh rate is higher and higher, and with the higher and higher refresh rate, the requirement for display taste is also improved synchronously, but the driving under different refresh rates in the same display panel needs to be compatible.

[0003] However, different refresh rates will also lead to different charging rates, which will cause the same display panel to present different display qualities due to different charging rates under different refresh rates, and the reliability under different refresh rates is also inconsistent. SUMMARY

[0004] The present application provides a gate driving circuit and a display panel to alleviate the technical problem of inconsistent charging rates under different refresh frequencies.

[0005] In a first aspect, the present application provides a gate driving circuit for a display panel, the gate driving circuit comprising a shift register, the shift register comprising a pull-up module, a pull-down module and a compatibility control module, a control end of the pull-up module being connected with a pull-up node, one end of the pull-up module being connected with a first transmission line, the other end of the pull-up module being connected with a gate driving line; a control end of the pull-down module being connected with a pull-down control line, one end of the pull-down module being connected with a second transmission line, the other end of the pull-down module being connected with the gate driving line; the compatibility control module being connected with a compatibility control line and the pull-up module; wherein the pull-up module provides a corresponding gate driving signal for the gate driving line under a low refresh rate; and the pull-up module and the compatibility control module jointly provide a corresponding gate driving signal for the gate driving line under a high refresh rate.

[0006] In some embodiments, each input end of the compatibility control module is connected with one end of the pull-up module, each output end of the compatibility control module is connected with the other end of the pull-up module, each first control end of the compatibility control module is connected with a compatibility control line, and each second control end of the compatibility control module is connected with the pull-up node.

[0007] In some embodiments, the compatibility control module comprises at least one compatibility control unit, an input end of each compatibility control unit is connected with one end of the pull-up module, an output end of each compatibility control unit is connected with the other end of the pull-up module, a first control end of each compatibility control unit is connected with a compatibility control line, and a second control end of each compatibility control unit is connected with the pull-up node.

[0008] In some embodiments, the compatible control unit comprises a first transistor and a second transistor, a first electrode of the first transistor is connected with one end of the pull-up module, a gate electrode of the first transistor is connected with the compatible control line; a first electrode of the second transistor is connected with a second electrode of the first transistor, a gate electrode of the second transistor is connected with a control end of the pull-up module, a second electrode of the second transistor is connected with the other end of the pull-up module.

[0009] In some embodiments, the pull-up module comprises a pull-up transistor, a first electrode of the pull-up transistor is connected with the first electrode of the first transistor, a gate electrode of the pull-up transistor is connected with the gate electrode of the second transistor, a second electrode of the pull-up transistor is connected with the second electrode of the second transistor, and a channel type of the pull-up transistor is the same as a channel type of the second transistor.

[0010] In some embodiments, as the refresh rate increases, the number of compatible control units of the first transistor in the on state also increases.

[0011] In some embodiments, the refresh rate is divided into a high refresh rate and a low refresh rate, and the compatible control module comprises one compatible control unit; wherein, under the high refresh rate, the first transistor in the compatible control unit is in the on state; and under the low refresh rate, the first transistor in the compatible control unit is in the off state.

[0012] In some embodiments, the compatible control unit of the first transistor in the off state is used to reduce the leakage current of the pull-up node under the low refresh rate.

[0013] In some embodiments, the compatible control module is used to reduce the leakage current of the pull-up node under the low refresh rate and improve the charging rate under the high refresh rate.

[0014] In a second aspect, the present application provides a display panel, comprising the above-mentioned gate drive circuit.

[0015] The gate drive circuit and the display panel provided by the present application increase the compatible control module connected with the pull-up module in the shift register, the pull-up module provides the corresponding gate drive signal for the gate drive line under the low refresh rate, and the pull-up module and the compatible control module jointly provide the corresponding gate drive signal for the gate drive line under the high refresh rate, which can improve the driving ability of the gate drive signal in the gate drive line as the refresh rate increases, thereby controlling the consistency of the charging rate under different refresh rates under the driving of the compatible control line, and further enabling the same or similar display quality and reliability under different refresh rates. BRIEF DESCRIPTION OF DRAWINGS

[0016] The technical solutions and other beneficial effects of the present application will be apparent from the following detailed description of specific embodiments of the present application, combined with the accompanying drawings.

[0017] Figure 1 A schematic diagram of a pattern of leakage horizontal lines in the related art.

[0018] Figure 2 A schematic diagram of a structure of a gate driving circuit in the related art.

[0019] Figure 3 A principle block diagram of a gate driving circuit provided by an embodiment of the present application.

[0020] Figure 4 A principle block diagram of a compatibility control module provided by an embodiment of the present application.

[0021] Figure 5 A circuit principle diagram of a gate driving circuit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person skilled in the art without any creative work fall within the scope of protection of the present application.

[0023] In addition, the terms “first”, “second” are only used for description purpose, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features, so that the features with “first” and “second” can explicitly or implicitly include one or more of the features, and in the description of the present application, the meaning of “multiple” is two or more, unless otherwise explicitly and specifically limited.

[0024] With the development of display panels, the requirement for refresh rate is getting higher and higher, 60Hz→120Hz→144Hz→165Hz→240Hz→288Hz→360Hz, and so on, and there is also a display panel with an ultra-high refresh rate of 500Hz.

[0025] With the increasing of refresh rate, the requirement of display taste is also increasing, but the driving under different refresh rates in the same display panel generally needs to be compatible, for example, 360Hz refresh rate needs to be compatible with 60Hz refresh rate specification taste, which brings difficulties to design and debugging. For example, the same display panel will also cause different charging rates due to different refresh rates. Taking a 27-inch full high definition (FHD) display panel as an example, the charging rate under 60Hz refresh rate can reach more than 99%, and the charging rate under 360Hz refresh rate is only 80%. If the charging design and debugging are based on 60Hz refresh rate, it will cause insufficient charging under 360Hz refresh rate, thereby causing reliability problems such as roughness, impure color and charging leakage risk. If the charging design and debugging are based on 360Hz refresh rate, it can meet the charging requirements under 360Hz refresh rate, but overcharging will occur under 60Hz refresh rate, and there will still be problems such as roughness, insufficient overdrive (OD), and the longer leakage time under 60Hz refresh rate will also cause the problem of leakage horizontal lines (such as Figure 1

[0026] In the traditional technology, the roughness caused by the difference between light and heavy loads is generally improved by using horizontal line overdrive voltage (Line OD). The debugging schemes under low refresh rate and high refresh rate are different, and multiple sets of timing and multiple sets of overdrive (OD) data corresponding to each other need to be used in the timing controller (TCON) to improve the above problems, but this will increase the debugging difficulty and the cost of the timing controller.

[0027] Figure 2 FIG. 1 is a structural schematic diagram of a gate drive circuit in the related art. The gate drive circuit includes a shift register or a plurality of cascaded shift registers. The shift register includes a pull-up module 10 and a pull-down module 20. A control end of the pull-up module 10 is connected with a pull-up node Q. One end of the pull-up module 10 is connected with a first transmission line. The other end of the pull-up module 10 is connected with a gate drive line. A control end of the pull-down module 20 is connected with a pull-down control line. One end of the pull-down module 20 is connected with a second transmission line. The other end of the pull-down module 20 is connected with the gate drive line.

[0028] The first transmission line is used to transmit a first clock signal CK or a second clock signal XCK. The second transmission line is used to transmit a low potential signal VSS. The gate drive line is used to transmit a gate drive signal, for example, an Nth gate drive signal G(N). The pull-down control line is used to transmit a pull-down control signal, for example, an (N+1)th gate drive signal G(N+1).

[0029] ​The pull-up module 10 comprises a pull-up transistor T21, a gate of the pull-up transistor T21 is connected with the pull-up node Q, a first electrode of the pull-up transistor T21 is connected with the first clock signal CK or the second clock signal XCK, and a second electrode of the pull-up transistor T21 outputs the Nth gate drive signal G(N).

[0030] It should be noted that the first electrode can be one of the source electrode and the drain electrode, and the second electrode can be the other of the source electrode and the drain electrode. For example, when the first electrode is the source electrode, the second electrode is the drain electrode; or when the first electrode is the drain electrode, the second electrode is the source electrode.

[0031] The pull-down module 20 comprises a first pull-down transistor T31, a first electrode of the first pull-down transistor T31 is connected with the low potential signal VSS, a gate of the first pull-down transistor T31 is connected with the (N+1)th gate drive signal G(N+1), and a second electrode of the first pull-down transistor T31 outputs the Nth gate drive signal G(N).

[0032] The shift register can further comprise a pull-up control transistor T11, a first electrode of the pull-up control transistor T11 is connected with the (N-1)th gate drive signal G(N-1), a gate of the pull-up control transistor T11 is connected with the (N-1)th stage transfer signal ST(N-1), and a second electrode of the pull-up control transistor T11 is connected with the pull-up node Q.

[0033] The shift register can further comprise a cascade transistor T22, a first electrode of the cascade transistor T22 is connected with the first clock signal CK or the second clock signal XCK, a gate of the cascade transistor T22 is connected with the pull-up node Q, and a second electrode of the cascade transistor T22 outputs the Nth stage transfer signal ST(N).

[0034] The shift register can further comprise a bootstrap capacitor Cbt, one end of the bootstrap capacitor Cbt is connected with the pull-up node Q, and the other end of the bootstrap capacitor Cbt is connected with the second electrode of the pull-up transistor T21.

[0035] The shift register can further comprise a second pull-down transistor T41, a first electrode of the second pull-down transistor T41 is connected with the pull-up node Q, a gate of the second pull-down transistor T41 is connected with the (N+1)th gate drive signal G(N+1), and a second electrode of the second pull-down transistor T41 is connected with the low potential signal VSS.

[0036] The shift register may also include an inverter INV, a first pull-down sustaining transistor T42, and a second pull-down sustaining transistor T32. The input of the inverter INV is connected to the pull-up node Q, and the output of the inverter INV is connected to the gates of the first pull-down sustaining transistor T42 and the second pull-down sustaining transistor T32. The first terminal of the first pull-down sustaining transistor T42 is connected to the pull-up node Q, and the second terminal of the first pull-down sustaining transistor T42 is connected to a low-level signal VSS. The first terminal of the second pull-down sustaining transistor T32 is connected to the gate drive line, and the second terminal of the second pull-down sustaining transistor T32 is connected to a low-level signal VSS.

[0037] It should be noted that the transistors described above can be either N-channel or P-channel transistors in different embodiments. Figure 2 The example is based on the premise that all transistors are N-channel thin-film transistors.

[0038] Based on this, this embodiment provides a gate driving circuit, which includes a shift register. Please refer to [link to relevant documentation]. Figures 3 to 5 ,like Figure 3 As shown, the shift register includes a pull-up module 10, a pull-down module 20, and a compatibility control module 30. The control terminal of the pull-up module 10 is connected to the pull-up node Q, one end of the pull-up module 10 is connected to the first transmission line CSL1, and the other end of the pull-up module 10 is connected to the gate drive line GL. The control terminal of the pull-down module 20 is connected to the pull-down control line XCL, one end of the pull-down module 20 is connected to the second transmission line CSL2, and the other end of the pull-down module 20 is connected to the gate drive line GL. The compatibility control module 30 is connected to the compatibility control line JRL and the pull-up module 10. The pull-up module 10 provides the corresponding gate drive signal to the gate drive line GL at low refresh rates. The pull-up module 10 and the compatibility control module 30 jointly provide the corresponding gate drive signal to the gate drive line GL at high refresh rates.

[0039] It is understood that the gate drive circuit provided in this embodiment, by adding a compatibility control module 30 connected to the pull-up module 10 in the shift register, allows the pull-up module 10 to provide the corresponding gate drive signal to the gate drive line GL at low refresh rates. The pull-up module 10 and the compatibility control module 30 jointly provide the corresponding gate drive signal to the gate drive line GL at high refresh rates. This can improve the driving capability of the gate drive signal in the gate drive line GL as the refresh rate increases, thereby controlling the consistency of the charging rate at different refresh rates under the drive of the compatibility control line JRL, and thus enabling the same or similar display quality and reliability to be presented at different refresh rates.

[0040] It should be noted that the compatibility control module 30 is used to reduce the leakage current of the pull-up node Q at the low refresh rate, and to increase the charging rate at the high refresh rate. The structure of the pull-up module 10 and the pull-down module 20 and the connection relationship thereof can be referred to the related description in the Figure 2 .

[0041] For example, the highest refresh rate is 360Hz, the high refresh rate refers to the refresh rate greater than or equal to 120Hz, and the low refresh rate refers to the refresh rate less than 120Hz. It can be understood that with the change of the highest refresh rate, the high refresh rate and the low refresh rate can also be adaptively adjusted.

[0042] Specifically, each input end of the compatibility control module 30 is connected with one end of the pull-up module 10, each output end of the compatibility control module 30 is connected with the other end of the pull-up module 10, each first control end of the compatibility control module 30 is connected with a compatibility control line JRL, and each second control end of the compatibility control module 30 is connected with the pull-up node Q.

[0043] The first transmission can also selectively transmit a high potential signal (VGH). The compatibility control line JRL is used to transmit a compatibility control signal VGV.

[0044] In one embodiment, as shown in Figure 4 , the compatibility control module 30 includes at least one compatibility control unit 31, the input end of each compatibility control unit 31 is connected with one end of the pull-up module 10, the output end of each compatibility control unit 31 is connected with the other end of the pull-up module 10, the first control end of each compatibility control unit 31 is connected with a compatibility control line JRL, and the second control end of each compatibility control unit 31 is connected with the pull-up node Q.

[0045] It should be noted that with the increase of the refresh rate, the number of compatibility control units 31 can also increase, which is beneficial to further increase the charging rate at the high refresh rate, so as to better realize the consistency of the charging rate at different refresh rates.

[0046] In one embodiment, as shown in Figure 5 , the compatibility control unit 31 includes a first transistor and a second transistor, the first pole of the first transistor is connected with one end of the pull-up module 10, the gate of the first transistor is connected with the compatibility control line JRL; the first pole of the second transistor is connected with the second pole of the first transistor, the gate of the second transistor is connected with the control end of the pull-up module 10, and the second pole of the second transistor is connected with the other end of the pull-up module 10.

[0047] It should be noted that, as the refresh rate increases, the number of compatible control units 31 of the first transistor in the on state also increases, which is conducive to further increasing the charging rate under high refresh rate, so as to better realize the consistency of the charging rate under different refresh rates. Wherein, when the first transistor is in the off state, the second transistor can play a role similar to the bootstrap capacitor Cbt, therefore, the compatible control unit 31 of the first transistor in the off state can be used to reduce the leakage current of the pull-up node Q under low refresh rate.

[0048] Wherein, the channel type of the pull-up transistor T21 is the same as that of the second transistor, for example, both can be N-channel transistors or P-channel transistors, so as to realize the synchronous conduction of the two, thereby facilitating to enhance the driving capability of the gate driving signal in the gate driving line GL, and further facilitating to improve the charging rate.

[0049] In one of the embodiments, the refresh rate can be high refresh rate and low refresh rate, and the compatible control module 30 includes a compatible control unit 31; wherein, under high refresh rate, the first transistor in the compatible control unit 31 is in the on state; under low refresh rate, the first transistor in the compatible control unit 31 is in the off state.

[0050] It should be noted that, under high refresh rate, the first transistor is in the on state, and the pull-up transistor T21 is also in the on state synchronously, so that the first transistor and the pull-up transistor T21 can jointly transmit the signal in the first transmission line CSL1, thereby facilitating to enhance the driving capability of the gate driving signal in the gate driving line GL under high refresh rate, and further facilitating to improve the charging rate.

[0051] Wherein, Figure 5 The structures not described in the above description can refer to the description of the corresponding structures in the above Figure 2 The description of the corresponding structures in the above

[0052] In one of the embodiments, the application provides a display panel, which includes the above-mentioned gate driving circuit.

[0053] It can be understood that, since the display panel provided by the embodiment includes the gate drive circuit described above, the compatible control module 30 connected with the pull-up module 10 can also be added in the shift register, the pull-up module 10 provides the corresponding gate drive signal for the gate drive line GL at the low refresh rate, and the pull-up module 10 and the compatible control module 30 jointly provide the corresponding gate drive signal for the gate drive line GL at the high refresh rate, so that the driving capability of the gate drive signal in the gate drive line GL can be improved along with the increase of the refresh rate, thereby the consistency of the charging rate at different refresh rates is controlled under the driving of the compatible control line JRL, and then the same or similar display quality and reliability at different refresh rates can be presented.

[0054] It should be noted that the display panel described above can be a liquid crystal display panel or a self-luminous display panel that can be applied.

[0055] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0056] The gate drive circuit and the display panel provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples in this paper, and the above description of the embodiments is only used to help understand the technical solutions and the core ideas of the present application; the ordinary skilled in the art should understand that the technical solutions recorded in the above embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A gate driving circuit for a display panel, characterized by, The gate drive circuit comprises a shift register, and the shift register comprises: a pull-up module, a control end of the pull-up module being connected with a pull-up node, one end of the pull-up module being connected with a first transmission line, and the other end of the pull-up module being connected with a gate drive line; a pull-down module, a control end of the pull-down module being connected with a pull-down control line, one end of the pull-down module being connected with a second transmission line, and the other end of the pull-down module being connected with the gate drive line; a compatibility control module, the compatibility control module being connected with a compatibility control line and the pull-up module; wherein the pull-up module provides a corresponding gate drive signal for the gate drive line under a low refresh rate, and the pull-up module and the compatibility control module jointly provide a corresponding gate drive signal for the gate drive line under a high refresh rate.

2. The gate drive circuit according to claim 1, characterized by Each input end of the compatibility control module is connected with one end of the pull-up module, each output end of the compatibility control module is connected with the other end of the pull-up module, each first control end of the compatibility control module is connected with one compatibility control line, and each second control end of the compatibility control module is connected with the pull-up node.

3. The gate drive circuit according to claim 2, characterized by The compatibility control module comprises at least one compatibility control unit, an input end of each compatibility control unit is connected with one end of the pull-up module, an output end of each compatibility control unit is connected with the other end of the pull-up module, a first control end of each compatibility control unit is connected with one compatibility control line, and a second control end of each compatibility control unit is connected with the pull-up node.

4. The gate drive circuit according to claim 3, characterized by The compatibility control unit comprises: a first transistor, a first pole of the first transistor being connected with one end of the pull-up module, and a gate of the first transistor being connected with the compatibility control line; a second transistor, a first pole of the second transistor being connected with a second pole of the first transistor, a gate of the second transistor being connected with a control end of the pull-up module, and a second pole of the second transistor being connected with the other end of the pull-up module.

5. The gate drive circuit according to claim 4, characterized in that The pull-up module comprises a pull-up transistor, a first pole of the pull-up transistor being connected with the first pole of the first transistor, a gate of the pull-up transistor being connected with the gate of the second transistor, a second pole of the pull-up transistor being connected with the second pole of the second transistor, and a channel type of the pull-up transistor being the same as a channel type of the second transistor.

6. The gate drive circuit according to claim 4, characterized by With the increase of the refresh rate, the number of the compatibility control units of the first transistor in the on state also increases.

7. The gate drive circuit according to claim 5, characterized by The refresh rate is divided into a high refresh rate and a low refresh rate, and the compatibility control module comprises one compatibility control unit; wherein under the high refresh rate, the first transistor in the compatibility control unit is in the on state, and under the low refresh rate, the first transistor in the compatibility control unit is in the off state.

8. The gate drive circuit according to claim 7, characterized by The compatibility control unit of the first transistor in the off state is used to reduce the leakage current of the pull-up node under the low refresh rate.

9. The gate drive circuit according to any one of claims 1 to 8, characterized by The compatibility control module is used to reduce the leakage current of the pull-up node under the low refresh rate and to improve the charging rate under the high refresh rate.

10. A display panel, characterized by, The display panel comprises the gate drive circuit as claimed in any of claims 1-9.

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