Display control circuit, method, display substrate and display device

Abstract

The present application provides a display control circuit, method, display substrate and display device. The display control circuit includes: at least two groups of shift register circuits and pixel circuits, wherein the at least two groups of shift register circuits include a first shift register and a second shift register, and the pixel circuit includes an initialization subcircuit, a storage subcircuit, a driving subcircuit and a data writing subcircuit. The control end of the initialization subcircuit is connected to the first output end of the first shift register, and the control end of the data writing subcircuit is connected to the first output end of the second shift register, and a shielding subcircuit is designed in at least one shift register.

Description

Technical Field

[0001] The present application belongs to the field of display control technology, and in particular relates to a display control circuit, method, display substrate and display device. Background Art

[0002] Partial refresh refers to refreshing a dynamic area of ​​the screen (such as animation) at a high frequency and a static area (such as text) at a low frequency, thereby reducing power consumption. Currently, partial refresh technology is mostly used in LTPO (Low Temperature Polycrystalline Oxide) pixel circuits, but using partial refresh technology in LTPO pixel circuits has the problem of high cost. Summary of the Invention

[0003] The embodiments of the present application provide a display control circuit, method, display substrate and display device, which can realize local refresh based on the LTPS pixel circuit, thereby reducing the implementation cost of the local refresh technology.

[0004] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by practice of the present application.

[0005] According to a first aspect of an embodiment of the present application, a display control circuit is provided, comprising:

[0006] At least two groups of shift register circuits, including a first group of shift register circuits and a second group of shift register circuits; the first group of shift register circuits includes a plurality of first shift registers arranged in cascade connection, and the second group of shift register circuits includes a plurality of second shift registers arranged in cascade connection;

[0007] A pixel circuit, comprising an initialization subcircuit, a storage subcircuit, a driving subcircuit, and a data writing subcircuit, wherein the initialization subcircuit is connected to a first node, the storage subcircuit is connected to the first node and the second node respectively, the data writing subcircuit is connected to the second node, and the driving subcircuit is connected to the first node;

[0008] The control end of the initialization subcircuit is connected to the first output end of the first shift register, and the control end of the data writing subcircuit is connected to the first output end of the second shift register; the first shift register and the second shift register include a shift register subcircuit, and at least one of the first shift register and the second shift register further includes a shielding subcircuit, and the shielding subcircuit is connected to the shift register subcircuit;

[0009] The shift register subcircuit is used to output a cascade signal based on an input signal;

[0010] The output end of the shielding subcircuit serves as the first output end, and is used to output a control signal based on the shielding signal. When the shielding signal is at a first level, the control signal is at a first level. When the shielding signal is at a second level, the control signal is the same as the cascade signal, wherein the first level is different from the second level.

[0011] In some embodiments, the pixel circuit further includes a compensation subcircuit, wherein a first terminal of the compensation subcircuit is connected to the first node and is used to write a compensation voltage to the first node, a second terminal is connected to the output terminal of the driving subcircuit, and a control terminal is connected to the first output terminal of the second shift register;

[0012] The first shift register and the second shift register include the masking subcircuit, and the control signal output by the masking subcircuit is a row scanning signal.

[0013] In some embodiments, the first shift register and the second shift register are driven by bilateral driving.

[0014] In some embodiments, the at least two groups of shift register circuits further include a third group of shift register circuits, wherein the third group of shift register circuits includes a plurality of third shift registers arranged in cascade;

[0015] The initialization subcircuit includes a first subcircuit and a second subcircuit, wherein the first subcircuit has an input terminal for receiving an initialization voltage signal, an output terminal connected to a third node, and a control terminal connected to the output terminal of the third shift register; the second subcircuit has an input terminal connected to the third node, an output terminal connected to the first node, and a control terminal connected to the first output terminal of the first shift register;

[0016] The second sub-circuit is further configured to write a compensation voltage to the first node during a compensation phase.

[0017] In some embodiments, the first shift register includes the shielding subcircuit, and the control signal output by the shielding subcircuit is a light emitting control signal;

[0018] The shift register sub-circuit in the second shift register is further configured to output a row scanning signal to the control terminal of the data writing sub-circuit.

[0019] In some embodiments, the first shift register and the second shift register include the masking subcircuit;

[0020] The control signal output by the shielding sub-circuit in the first shift register is a light-emitting control signal;

[0021] The control signal output by the masking sub-circuit in the second shift register is a row scanning signal.

[0022] In some embodiments, the driving mode of the first shift register and the third shift register is unilateral driving, and the driving mode of the second shift register is bilateral driving.

[0023] In some embodiments, the pixel circuit further includes a compensation subcircuit, wherein a first terminal of the compensation subcircuit is connected to the first node and is used to write a compensation voltage to the first node, a second terminal is connected to the output terminal of the driving subcircuit, and a control terminal is connected to the first output terminal of the second shift register;

[0024] The second shift register includes a shielding subcircuit, and the control signal output by the shielding subcircuit is a row scanning signal;

[0025] The initialization sub-circuit is respectively connected to the first output end of the first shift register and the first output end of the second shift register of the previous level, and is used to write the initialization voltage to the first node under the control of the control signal output from the first output end of the first shift register and the control signal output from the first output end of the second shift register of the previous level.

[0026] In some embodiments, the initialization subcircuit includes a third subcircuit and a fourth subcircuit, the input end of the third subcircuit is used to receive the initialization voltage signal, the output end is connected to the input end of the fourth subcircuit, and the output end of the fourth subcircuit is connected to the first node;

[0027] The control end of one of the third sub-circuit and the fourth sub-circuit is connected to the first output end of the first shift register, and the control end of the other sub-circuit is connected to the first output end of the second shift register of the previous stage.

[0028] In some embodiments, the initialization subcircuit includes a third subcircuit and a fourth control subcircuit, the input end of the third subcircuit is used to receive an initialization voltage signal, the output end is connected to the first node, and the control end is connected to the output end of the fourth subcircuit, the input end of the fourth subcircuit is connected to the first output end of the second shift register of the previous level, and the control end is connected to the first output end of the first shift register.

[0029] In some embodiments, the driving mode of the first shift register is single-side driving or double-side driving, and the driving mode of the second shift register is double-side driving.

[0030] In some embodiments, the at least two groups of shift register circuits further include a third group of shift register circuits, a fourth group of shift register circuits, and a fifth group of shift register circuits, the third group of shift register circuits includes a plurality of third shift registers arranged in cascade connection, the fourth group of shift register circuits includes a plurality of fourth shift registers arranged in cascade connection, and the fifth group of shift register circuits includes a plurality of fifth shift registers arranged in cascade connection;

[0031] The data writing subcircuit includes a fifth subcircuit and a sixth subcircuit, wherein the fifth subcircuit has an input end for receiving a data voltage signal, an output end connected to the second node, and a control end connected to the first output end of the second shift register; and the sixth subcircuit has an input end for receiving an initialization voltage signal, an output end connected to the second node, and a control end connected to the output end of the third shift register.

[0032] The initialization subcircuit includes a seventh subcircuit, an eighth subcircuit, and a ninth subcircuit, wherein the seventh subcircuit has an input end for receiving an initialization voltage signal, an output end connected to the fourth node, and a control end connected to the output end of the fourth shift register; the eighth subcircuit has an input end connected to the fourth node, an output end connected to the third node, and a control end connected to the output end of the fifth shift register; the ninth subcircuit has an input end connected to the third node, an output end connected to the first node, and a control end connected to the first output end of the first shift register;

[0033] The first shift register includes a shielding subcircuit, and the control signal output by the shielding subcircuit is a light-emitting control signal;

[0034] The eighth sub-circuit is further configured to write a light-emitting control voltage from the fourth node to the light-emitting element during a light-emitting phase;

[0035] The ninth sub-circuit is further configured to write a compensation voltage to the first node during a compensation phase.

[0036] In some embodiments, the transistors in the pixel circuit are all low-temperature polysilicon transistors.

[0037] According to a second aspect of an embodiment of the present application, there is provided a display substrate, comprising:

[0038] a substrate, and

[0039] As described in the first aspect, the display control circuit is arranged on one side of the base substrate.

[0040] According to a third aspect of an embodiment of the present application, a display control method is provided, which is applied to the display substrate according to the second aspect, and the method includes:

[0041] determining a first display area and a second display area of ​​the display substrate;

[0042] Writing a first level into a shielding signal input terminal of a shielding sub-circuit in a shift register corresponding to the first display area;

[0043] A second level is written into the shielding signal input terminal of the shielding sub-circuit in the shift register corresponding to the second display area, wherein the first level is different from the second level.

[0044] According to a fourth aspect of an embodiment of the present application, a display device is provided, comprising the display substrate as described in the second aspect.

[0045] In the present application, at least two groups of shift register circuits and pixel circuits are provided in the display control circuit, wherein the at least two groups of shift register circuits include a first shift register and a second shift register, and the pixel circuit includes an initialization subcircuit, a storage subcircuit, a drive subcircuit, and a data write subcircuit. The control end of the initialization subcircuit is connected to the first output end of the first shift register, and the control end of the data write subcircuit is connected to the first output end of the second shift register. In addition, a shielding subcircuit is designed in at least one of the shift registers. The above display control circuit design can achieve partial refresh based on the LTPS pixel circuit, reducing the implementation cost of the partial refresh technology.

[0046] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings are incorporated into and constitute a part of the specification, illustrating embodiments consistent with the present application and, together with the specification, explaining the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0048] Figure 1 An exemplary circuit block diagram of a display control circuit in an embodiment of the present application is shown;

[0049] Figure 2 shows a circuit structure diagram of an LTPS 7T1C pixel circuit in the related art;

[0050] Figure 3 Shown is a circuit structure diagram of an LTPS 7T1C pixel circuit capable of full-screen low-frequency refresh;

[0051] Figure 4The circuit structure diagram of the LTPS 8T1C pixel circuit capable of full-screen low-frequency refresh is shown;

[0052] Figure 5 Shown Figure 1 An exemplary circuit structure diagram of a shift register including a shielding subcircuit;

[0053] Figure 6 Shown Figure 5 The timing diagram of the shift register in normal output;

[0054] Figure 7 Shown Figure 5 Timing diagram of the shift register when masking the output;

[0055] Figure 8 Shown Figure 5 Shift register driver Figure 4 The circuit structure diagram of the 8T1C pixel circuit;

[0056] Figure 9 Shown Figure 5 Shift register driver Figure 4 Timing diagram of 8T1C pixel circuit;

[0057] Figure 10 Shown Figure 1 An exemplary detailed schematic diagram of a control circuit is shown in FIG.

[0058] Figure 11 Shown Figure 10 An exemplary circuit structure diagram of a pixel circuit;

[0059] Figure 12 Shown for driving Figure 11 An exemplary timing diagram of a pixel circuit;

[0060] Figure 13 Shown Figure 11 An exemplary arrangement diagram of a control circuit is shown in FIG.

[0061] Figure 14 Shown for driving Figure 11 Another exemplary timing diagram of a pixel circuit;

[0062] Figure 15 Shown Figure 1 Another exemplary detailed schematic diagram of the control circuit is shown in FIG.

[0063] Figure 16 Shown Figure 15 An exemplary circuit structure diagram of a pixel circuit;

[0064] Figure 17 Shown Figure 15 An exemplary arrangement diagram of a control circuit is shown in FIG.

[0065] Figure 18 Shown for driving Figure 16 An exemplary timing diagram of a pixel circuit;

[0066] Figure 19 Shown Figure 1 Another exemplary detailed schematic diagram of the control circuit is shown in FIG.

[0067] Figure 20 Shown Figure 19 An exemplary circuit structure diagram of a pixel circuit;

[0068] Figure 21 Shown for driving Figure 16 Another exemplary timing diagram of a pixel circuit;

[0069] Figure 22 Shown for driving Figure 20 An exemplary timing diagram of a pixel circuit;

[0070] Figure 23 Shown Figure 1 Another exemplary detailed schematic diagram of the control circuit is shown in FIG.

[0071] Figure 24 Shown Figure 23 An exemplary circuit structure diagram of a pixel circuit;

[0072] Figure 25 Shown Figure 23 Another exemplary circuit structure diagram of a pixel circuit;

[0073] Figure 26 Shown Figure 23 Another exemplary circuit structure diagram of a pixel circuit;

[0074] Figure 27 Shown for driving Figure 23 An exemplary timing diagram of a pixel circuit;

[0075] Figure 28 Shown Figure 23 An exemplary arrangement diagram of a control circuit is shown in FIG.

[0076] Figure 29 Shown Figure 1 Another exemplary detailed schematic diagram of the control circuit is shown in FIG.

[0077] Figure 30 Shown Figure 29 An exemplary circuit structure diagram of a pixel circuit;

[0078] Figure 31 A schematic structural diagram of a display substrate in an embodiment of the present application is shown;

[0079] Figure 32 A flow chart of a display control method in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0080] The following describes exemplary embodiments of the present application in more detail with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0081] Unless otherwise defined, the technical or scientific terms used in this application should have the usual meanings understood by people with ordinary skills in the field to which this application belongs. The "first", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.

[0082] It should also be noted that the source and drain of the transistors used in the embodiments of the present application may be symmetrical in structure, so the source and drain may be physically identical. In the embodiments of the present application, in order to distinguish the transistors, except for the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other as the second electrode, so the first electrode and the second electrode of all or part of the transistors in the embodiments of the present application can be interchanged as needed.

[0083] In order to keep the following description of the embodiments of the present application clear and concise, the present application omits detailed descriptions of some known functions and known components.

[0084] The exemplary embodiments of the present application are described in detail below with reference to the accompanying drawings, but the present application is not limited to these specific embodiments.

[0085] Figure 1 FIG. 1 shows an exemplary circuit block diagram of a display control circuit in an embodiment of the present application. Figure 1As shown, the display control circuit includes: at least two groups of shift register circuits, including a first group of shift register circuits and a second group of shift register circuits; the first group of shift register circuits includes a plurality of first shift registers 11 arranged in cascade, and the second group of shift register circuits includes a plurality of second shift registers 12 arranged in cascade; the pixel circuit 13 includes an initialization subcircuit 130, a storage subcircuit 131, a driving subcircuit 132 and a data writing subcircuit 133, the initialization subcircuit 130 is connected to the first node N1, the storage subcircuit 131 is respectively connected to the first node N1 and the second node N2, the data writing subcircuit 133 is connected to the second node N2, and the driving subcircuit 132 is connected to the first node N1; wherein the control end of the initialization subcircuit 130 is connected to the first output of the first shift register 11 The first shift register 11 and the second shift register 12 include a shift register sub-circuit, and at least one of the first shift register 11 and the second shift register 12 further includes: a shielding sub-circuit, which is connected to the shift register sub-circuit; the shift register sub-circuit is used to output a cascade signal (carry) based on an input signal (such as GSTV or the carry output by the previous shift register sub-circuit); the output end of the shielding sub-circuit serves as a first output end, and is used to output a control signal based on the shielding signal (SU1 or SU2). When the shielding signal is at a first level, the control signal is at a first level. When the shielding signal is at a second level, the control signal is the same as the cascade signal.

[0086] In some embodiments, the display control circuit may be applied to a display substrate, such as an active-matrix organic light-emitting diode (AMOLED) display substrate.

[0087] In some embodiments, the light-emitting element EL may be a light-emitting diode, which may be, for example, an organic light-emitting diode (OLED) or a quantum dot organic light-emitting diode (QLED), etc., and the present invention is not limited thereto. The light-emitting element EL may use light-emitting materials of different colors to emit light of different colors, thereby performing color display.

[0088] In some embodiments, the initialization sub-circuit 130 is used to write an initialization voltage to the first node N1, the data writing sub-circuit 133 is used to write a data voltage from the second node N2 to the storage sub-circuit 131, and the driving sub-circuit 132 is used to drive the light-emitting element EL to emit light under the control of the voltage of the first node N1.

[0089] It should be noted that the pixel circuit 13 is an LTPS (Low Temperature Poly-Silicon) pixel circuit. The transistors in the pixel circuit are all P-type thin film transistors, which implements the local refresh technology at a low cost.

[0090] It can be understood that for the first-stage shift register sub-circuit in the shift register circuit, since there is no previous-stage shift register sub-circuit outputting a cascade signal, the input signal GSTV needs to be written into it. For other-stage shift register sub-circuits, the cascade signal output by the previous-stage shift register sub-circuit can be used as GSTV to achieve driving.

[0091] It should also be noted that in the embodiments of the present application, the first level may be an active level that turns on the transistor, and the second level may be an inactive level that turns off the transistor. For example, if the transistor is a P-type thin-film transistor, the first level is high, turning off the P-type thin-film transistor, and the second level is low, turning on the P-type thin-film transistor. When the shielding signal is high, the control signal is also high, and the shielding effect of the shielding subcircuit is effective, at which point the corresponding display area will be refreshed at a low frequency. When the second level is low, the control signal is the same as the cascade signal, the shielding effect of the shielding subcircuit is not effective, and the corresponding display area will refresh normally.

[0092] Figure 2 The circuit structure diagram of the LTPS 7T1C pixel circuit in the related art is shown. All transistors in this circuit are P-type low-temperature polysilicon transistors. Figure 2 As shown, the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are controlled by a group of Gate GOA circuits. Reset is generally the Gate GOA signal of the previous row, that is, when data is written to the current row, the first node N1 and the fourth node N4 of the next row are reset. The fifth transistor T5 and the sixth transistor T6 are controlled by a group of EM GOA. In this circuit architecture, to ensure that the screen does not flicker at low frequencies, the second node N2 and the fourth node N4 need to be reset during the frame hold phase. However, because the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 share a group of Gate GOA circuits, when the second node N2 and the fourth node N4 are reset, the second transistor T2 is also turned on, which is equivalent to another data write. Therefore, this circuit architecture cannot switch from high frequency to low frequency.

[0093] Figure 3 The circuit structure diagram of the LTPS 7T1C pixel circuit that can refresh the entire screen at a low frequency is shown. Figure 3As shown, the fourth transistor T4 and the seventh transistor T7 are controlled by a group of EM GOA circuits, the first transistor T1 and the second transistor T2 are controlled by a group of Gate GOA circuits, and the fifth transistor T5 and the sixth transistor T6 are controlled by a group of EM GOA circuits. In this circuit architecture, when the second node N2 and the fourth node N4 are reset during the frame hold phase, the second transistor T2 is turned off, which can solve the problem of screen flicker at low frequencies. Therefore, this circuit architecture can achieve low-frequency refresh of the entire screen area.

[0094] Figure 4 The circuit structure diagram of the LTPS 8T1C pixel circuit that can refresh the entire screen at a low frequency is shown. Figure 4 As shown, by adding an eighth transistor T8 to the circuit and connecting it to the second node N2, the hysteresis of the third transistor T3 can be improved. The second node N2 is reset by the initialization voltage Vinit3. The seventh and eighth transistors T7 and T8 are controlled by a set of EM GOA circuits. The first, second, and fourth transistors T1 and T2 are controlled by a set of Gate GOA circuits. The fifth and sixth transistors T5 and T6 are also controlled by a set of EM GOA circuits. This circuit architecture can also achieve low-frequency refresh rates across the entire screen.

[0095] Figure 3 The LTPS 7T1C pixel circuit shown and Figure 4 The LTPS 8T1C pixel circuit shown can achieve low-frequency refresh for the entire screen, but cannot achieve low-frequency refresh for a localized area. To achieve local refresh, the embodiment of the present application adds a shielding subunit to the GOA circuit. The shielding subunit shields data writing in a certain area, thereby achieving low-frequency refresh for that area. Figure 5 Shown Figure 1 An exemplary circuit structure diagram of a shift register including a shielding subcircuit is shown in FIG. Figure 5As shown, taking the shift register as the first shift register as an example, the shift register includes a shift register sub-circuit 110 and a shielding sub-circuit 111, wherein the shift register sub-circuit 110 can be a Gate The GOA circuit includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a second capacitor C2, and a third capacitor C3. A first electrode of the ninth transistor T9 is used to receive a GSTV signal, a second electrode is connected to a fifth node N5, and a gate is used to receive a GCK signal. A first electrode of the tenth transistor T10 is connected to a sixth node N6, a second electrode is used to receive a GCK signal, and a gate is connected to the fifth node N5. A first electrode of the eleventh transistor T11 is used to receive a VGL signal, a second electrode is connected to a sixth node N6, and a gate is used to receive a GCK signal. A first end of the second capacitor C2 is used to receive a VGH signal, and a second end is connected to the sixth node N6. A gate of the twelfth transistor T12 is connected to the sixth node N6, a first electrode is used to receive a VGH signal, and a second electrode is respectively connected to the first end of the third capacitor C3 and the first electrode of the thirteenth transistor T13, serving as a gate. The output end of GOA outputs the cascade signal; the second electrode of the thirteenth transistor T13 is used to output the GCB signal, and the gate is connected to the seventh node N7; the first electrode of the fourteenth transistor T14 is used to receive the VGH signal, the second electrode is connected to the first electrode of the fifteenth transistor T15 via the eighth node N8, and the gate is connected to the sixth node N6; the second electrode of the fifteenth transistor T15 is connected to the fifth node N5, and the gate is used to receive the GCB signal; the first electrode of the sixteenth transistor T16 is connected to the fifth node N5, the second electrode is connected to the seventh node N7, and the gate is used to receive the VGL signal.

[0096] The shielding subcircuit 111 (Shielding Unit, SU) may include a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, a twentieth transistor T20, a twenty-first transistor T21, a twenty-second transistor T22, a fourth capacitor C4, and a fifth capacitor C5. The gate of the seventeenth transistor T17 is connected to the sixth node N6, the first electrode is used to receive the VGH signal, the second electrode is respectively connected to the first end of the fourth capacitor C4 and the first electrode of the eighteenth transistor T18, and serves as the output end of the shielding subcircuit 111 to output the control signal Gout; the second electrode of the eighteenth transistor T18 is used to output the GCB signal, and the gate is connected to the sixth node N6. The ninth node N9 is connected to the ninth node N9; the first electrode of the nineteenth transistor T19 is used to receive the VGH signal, the second electrode is connected to the ninth node N9 via the first electrode and the second electrode of the twentieth transistor T20, and the gate is connected to the sixth node N6; the gate of the twentieth transistor T20 is used to receive the GCB signal; the first electrode of the twenty-first transistor T21 is connected to the seventh node N7, the second electrode is connected to the ninth node N9 via the fifth capacitor C5, and the gate is used to receive the VGL signal; the first electrode of the twenty-second transistor T22 is used to receive the shielding signal SU, the second electrode is connected to the ninth node N9, and the gate is connected to the second electrode of the twenty-first transistor T21.

[0097] Among them, GSTV is the row drive clock signal, carry is the cascade signal, Gout is the control signal, GCK is the first gate clock signal, GCB is the second gate clock signal, VGH is the high level, VGL is the low level. For P-type low-temperature polysilicon crystals, VGH is the voltage for closing the gate, and VGL is the voltage for opening the gate.

[0098] It can be understood that in the above-described shift register circuit, the shift register subcircuit 110 is responsible for outputting the cascade signal carry to the next-stage shift register subcircuit, and the shield subcircuit 111 is responsible for outputting the control signal Gout to the display area. The cascade signal and the control signal do not interfere with each other. In certain areas, the shield signal is controlled to the first level, turning off the second transistor T2 and the fourth transistor T4 in the pixel circuit, thereby maintaining a low refresh rate in these areas.

[0099] The shift register circuit described above adds a 6T2C shielding subcircuit 111 to the 8T2C shift register subcircuit 110. In implementation, shielding subcircuit 111 is not limited to a 6T2C circuit design; more thin-film transistors and capacitors can be added to enhance output capability or improve functionality. Shift register subcircuit 110 is also not limited to an 8T2C circuit; shielding subcircuit 111 can also be added to 12T3C, 16T3C, and other circuits.

[0100] Figure 6 Shown Figure 5 The timing diagram of the shift register in normal output. Figure 6 SU is the shielding signal, such as Figure 6 As shown, when GSTV is at a low level, GCK is at a low level, and GCB is at a high level, for the shift register sub-circuit, the ninth transistor T9 and the eleventh transistor T11 are turned on, the sixth node N6 and the seventh node N7 are set to a low level, and then the twelfth transistor T12 and the thirteenth transistor T13 are turned on. At this time, the carry signal is at a high level; and for the shielding sub-circuit, the sixth node N6 is set to a low level, the sixteenth transistor T16 is turned on, the Gout signal is at a high level, the seventh node N7 is set to a low level, the seventeenth transistor T17 is turned on, the seventh node N7 is set to a low level, the twenty-second transistor T22 is turned on, and the shielding signal SU is written to the ninth node N9. Because the shielding signal is at a low level at this time, the eighteenth transistor T18 is turned on, GCB is output, and GCB is high, so the Gout signal is still at a high level.

[0101] Figure 7 Shown Figure 5 The timing diagram of the shift register in the shielded output. Figure 7 As shown, when GSTV is high, GCK is high, and GCB is low, for the shift register sub-circuit, the ninth transistor T9 and the eleventh transistor T11 are turned off, the seventh node N7 and the fifth node N5 maintain the state of the previous moment, which is low, so the tenth transistor T10 is turned on, GCK is written to the sixth node N6, which is high, and the twelfth transistor T12 is turned off. The seventh node N7 is low, which can turn on the thirteenth transistor T13 and output GCB. At this time, the carry signal is low. For the shielding sub-circuit, the sixth node N6 is high, the seventeenth transistor T17 is turned off, the seventh node N7 is low, the twenty-second transistor T22 is turned on, and the shielding signal SU is written. At this time, the level of SU determines whether the eighteenth transistor T18 is turned on. If SU is low, as shown in FIG. Figure 6 As shown, the eighteenth transistor T18 is normally turned on, and the GCB output, that is, Gout, is low level; if SU is high level, then Figure 7 As shown, the eighteenth transistor T18 is turned off, and Gout relies on the fourth capacitor C4 to maintain the state of the previous moment and outputs a high level to achieve a shielding function.

[0102] If a partial refresh design is performed based on the LTPS 8T1C pixel circuit, a shielding subcircuit is added to the shift register subcircuit, and the resulting circuit structure is as follows: Figure 8As shown. If the second transistor T2, the fourth transistor T4 and the first transistor T1 are still controlled by the same set of GOA circuits, the first node N1 of the next row is refreshed while the current row is reset. In this case, two phenomena may occur depending on the area where the low-frequency refresh area is located. The first is that if the upper half of the screen is a high-frequency refresh area and the lower half of the screen is a low-frequency refresh area, and the first node N1 of the first row of the low-frequency refresh area is refreshed, a bright line may appear at the boundary between high and low refresh. The second is that if the upper half of the screen is a low-frequency refresh area and the lower half of the screen is a high-frequency refresh area, since no data is written to the low-frequency refresh area, the first node N1 of the first row of the high-frequency refresh area will not be refreshed, and the screen may be abnormal. Reference Figure 9 In the timing diagram shown, SU is shielded during row n, but the refresh of the first node N1 in row n is determined by the data written to row n-1 and cannot be shielded. Therefore, in the design of local refresh for LTPS pixel circuits, the key point is to prevent any correlation between the upstream and downstream rows, or to shield this correlation through special design.

[0103] Through the design of the display control circuit of the embodiment of the present application, local refresh can be achieved based on the LTPS pixel circuit, reducing the implementation cost of the local refresh technology. At the same time, by using different groups of shift registers to control the data writing of the second node and the refresh of the first node, the data writing of this row will not affect the refresh of the first node N1 of the next row, thereby ensuring the normal display of the picture during the local refresh process.

[0104] Figure 10 Shown Figure 1 An exemplary detailed schematic diagram of the control circuit is shown in FIG. Figure 10 As shown, the pixel circuit also includes a compensation sub-circuit 134, a first end of the compensation sub-circuit 134 is connected to the first node N1, and is used to write a compensation voltage to the first node N1, a second end is connected to the output end of the driving sub-circuit 132, and a control end is connected to the first output end of the second shift register 12; the first shift register 11 and the second shift register 12 include a shielding sub-circuit, and the control signal output by the shielding sub-circuit is a row scanning signal.

[0105] Figure 11 Shown Figure 10 An exemplary circuit structure diagram of a pixel circuit in FIG. Figure 10 and Figure 11In some embodiments, the initialization subcircuit 130 may include a first transistor T1, the storage subcircuit 131 may include a first capacitor Cst, the compensation subcircuit 134 may include a second transistor T2, the driving subcircuit 132 may include a third transistor T3, and the data writing subcircuit 133 may include a fourth transistor T4. In a specific implementation, the pixel circuit 13 may further include a first light-emitting control subcircuit (not shown) and a second light-emitting control subcircuit (not shown). The first light-emitting control subcircuit includes a fifth transistor T5, and the second light-emitting control subcircuit includes a sixth transistor T6. The initialization subcircuit 130 may further include a seventh transistor T7, and the data writing subcircuit 133 may further include an eighth transistor T8. The gate of the first transistor T1 is controlled by the first shift register 11, the gates of the second transistor T2 and the fourth transistor T4 are controlled by the second shift register 12, the gates of the fifth transistor T5 and the sixth transistor T6 may be controlled by the shift register EM1, and the gates of the seventh transistor T7 and the eighth transistor T8 may be controlled by the shift register EM2.

[0106] It should be noted that Figure 10 The sub-circuits of the pixel circuit are not limited to the above-mentioned design, and the number of thin film transistors may be reduced, or the output capability of each sub-circuit may be enhanced by adding more thin film transistors and capacitors.

[0107] Figure 12 Shown for driving Figure 11 An exemplary timing diagram of the pixel circuit in FIG. Figure 12 As shown, at the nth row, the shielding signal SU2 of the shielding sub-circuit of the second shift register is switched to a high level, which can shield the data writing of the nth row, and the shielding signal SU1 of the shielding sub-circuit of the first shift register can be switched to a high level 1H in advance (H is the time required for the data signal to refresh a row of pixels), thereby shielding the refresh of the first node N1 of the nth row, thereby ensuring the normal display of the picture at the junction of the high-frequency refresh area and the low-frequency refresh area.

[0108] Figure 13 Shown Figure 11 An exemplary arrangement diagram of the control circuit is shown in FIG. Figure 13 As shown, the first shift register (Gate1+SU1) and the second shift register (Gate2+SU2) can be driven in a double-sided manner, while the shift registers EM1 and EM2 can be driven in a single-sided manner. This design can reduce the size of the bezel. In other embodiments, the four shift registers can also be driven in a double-sided manner. Although this solution increases the size of the bezel, it can ensure improved uniformity of display brightness.

[0109] Figure 14Shown for driving Figure 11 Another exemplary timing diagram of the pixel circuit in FIG. Figure 14 As shown, Figure 11 The driving principle of the middle pixel circuit is as follows: the shielding signal SU1 and the shielding signal SU2 are set to a high level at the beginning of the nth row, and are maintained at a low level before the n-1th row. If the base frequency is 120Hz, the control signal and the cascade signal before the n-1th row are the same, the shielding effect does not take effect, and each frame is refreshed. Therefore, the refresh frequency before the n-1th row is 120Hz; starting from the nth row, the control signal is high, the shielding effect takes effect, which is equivalent to refreshing one frame and maintaining one frame. Therefore, the refresh frequency starting from the nth row is 60Hz.

[0110] Figure 15 Shown Figure 1 Another exemplary detailed schematic diagram of the control circuit is shown in FIG. Figure 15 As shown, the at least two groups of shift register circuits further include a third group of shift register circuits, which includes a plurality of cascaded third shift registers 14. The initialization subcircuit includes a first subcircuit 1301 and a second subcircuit 1302. The first subcircuit 1301 has an input terminal for receiving an initialization voltage signal Vinit1, an output terminal connected to a third node N3, and a control terminal connected to the output terminal of the third shift register 14. The second subcircuit 1302 has an input terminal connected to the third node N3, an output terminal connected to a first node N1, and a control terminal connected to the first output terminal of the first shift register 11. The second subcircuit 1302 is further configured to write a compensation voltage to the first node during the compensation phase. The first shift register 11 includes a shielding subcircuit 111, the control signal output by the shielding subcircuit 111 being a light-emitting control signal. The shift register subcircuit 120 in the second shift register 12 is further configured to output a row scan signal to the control terminal of the data writing subcircuit 133.

[0111] Figure 16 Shown Figure 15 An exemplary circuit structure diagram of a pixel circuit in FIG. Figure 15 and Figure 16In some embodiments, the first subcircuit 1301 may include a first transistor T1, the second subcircuit 1302 may include a second transistor T2, the storage subcircuit 131 may include a first capacitor Cst, the driving subcircuit 132 may include a third transistor T3, and the data writing subcircuit 133 may include a fourth transistor T4. In a specific implementation, the pixel circuit 13 may further include a first light-emission control subcircuit (not shown) and a second light-emission control subcircuit (not shown). The first light-emission control subcircuit includes a fifth transistor T5, and the second light-emission control subcircuit includes a sixth transistor T6. The initialization subcircuit 130 may further include a seventh transistor T7, and the data writing subcircuit 133 may further include an eighth transistor T8. The gate of the first transistor T1 is controlled by the third shift register 14, the gate of the second transistor T2 is controlled by the first shift register 11, and the gate of the fourth transistor T4 is controlled by the second shift register 12. The gates of the fifth and sixth transistors T5 and T6 may be controlled by the shift register EM1, and the gates of the seventh and eighth transistors T7 and T8 may be controlled by the shift register EM2.

[0112] It can be understood that if the initialization voltage signal Vinit1 is to achieve the refresh of the first node N1, the first transistor T1 and the second transistor T2 need to be turned on at the same time. Under the architecture of this pixel circuit, the data writing of this row will not affect the next row. Since the first transistor T1 and the second transistor T2 are controlled by different shift registers, when the second transistor T2 is shielded, the initialization voltage signal Vinit1 cannot be reset to the first node N1. Therefore, the gate of the first transistor T1 does not need to add a shielding sub-circuit control.

[0113] Figure 17 Shown Figure 15 An exemplary arrangement diagram of the control circuit is shown in FIG. Figures 15 to 17 EM4+SU corresponds to the first shift register 11, Gate corresponds to the second shift register 12, and EM3 corresponds to the third shift register 14. The driving mode of the first shift register and the third shift register is unilateral driving, and the driving mode of the second shift register is bilateral driving.

[0114] Figure 18 Shown for driving Figure 16 An exemplary timing diagram of the pixel circuit in FIG. Figure 18 As shown, in the nth row, the shielding signal SU of the shielding sub-circuit of the first shift register is switched to a high level, which can shield the refresh of the first node N1 of the nth row, thereby ensuring the normal display of the picture at the junction of the high-frequency refresh area and the low-frequency refresh area.

[0115] Figure 19 Shown Figure 1 Another exemplary detailed schematic diagram of the control circuit is shown in FIG. Figure 19 As shown, the at least two groups of shift register circuits further include a third group of shift register circuits, which includes multiple cascaded third shift registers 14. The initialization subcircuit 130 includes a first subcircuit 1301 and a second subcircuit 1302. The first subcircuit 1301 has an input terminal for receiving an initialization voltage signal, an output terminal connected to a third node N3, and a control terminal connected to the output terminal of the third shift register 14. The second subcircuit 1302 has an input terminal connected to the third node N3, an output terminal connected to a first node N1, and a control terminal connected to the first output terminal of the first shift register 11. The second subcircuit 1302 is further configured to write a compensation voltage to the first node N1 during the compensation phase. The first shift register 11 and the second shift register 12 include shielding subcircuits. The shielding subcircuit 111 in the first shift register 11 outputs a control signal that is a light-emitting control signal, while the shielding subcircuit 121 in the second shift register 12 outputs a row scan signal.

[0116] Figure 20 Shown Figure 19 An exemplary circuit structure diagram of a pixel circuit in FIG. Figure 20 and Figure 16 The pixel circuit architecture is the same as that of FIG. 1 , except that a shielding subcircuit is added to the second shift register 12 to implement shielding control of the gate of the fourth transistor T4. Figure 21 Shown for driving Figure 16 Another exemplary timing diagram of the pixel circuit in FIG. Figure 22 Shown for driving Figure 20 An exemplary timing diagram of a pixel circuit in FIG. Figure 21 and Figure 22 It can be seen that, through this design, in the hold frame phase of the low-frequency refresh area, the data voltage will not refresh the second node N2, but Figure 16 In the holding frame phase, the data voltage will be refreshed to the second node N2, affecting the source potential of the third transistor T3, so Figure 20 The circuit structure shown may have more advantages in low-frequency display effects, but it will inevitably lead to an increase in the border.

[0117] Figure 23 Shown Figure 1 Another exemplary detailed schematic diagram of the control circuit is shown in FIG. Figure 23As shown, the pixel circuit 13 also includes a compensation sub-circuit 134, a first end of the compensation sub-circuit 134 is connected to the first node N1, and is used to write a compensation voltage to the first node N1, a second end is connected to the output end of the driving sub-circuit 132, and a control end is connected to the first output end of the second shift register 12; the second shift register 12 includes a shielding sub-circuit 121, and the control signal output by the shielding sub-circuit 121 is a row scan signal; the initialization sub-circuit 130 is respectively connected to the first output end of the first shift register 11 and the first output end of the second shift register 12' of the previous stage, and is used to write an initialization voltage to the first node N1 under the control of the control signal output from the first output end of the first shift register 11 and the control signal output from the first output end of the second shift register 12' of the previous stage.

[0118] In some embodiments, the initialization subcircuit 130 includes a third subcircuit 1303 and a fourth subcircuit 1304, the input end of the third subcircuit 1303 is used to receive the initialization voltage signal, the output end is connected to the input end of the fourth subcircuit 1304, and the output end of the fourth subcircuit 1304 is connected to the first node N1; wherein, the control end of one of the third subcircuit 1303 and the fourth subcircuit 1304 is connected to the first output end of the first shift register 11, and the control end of the other is connected to the first output end of the second shift register 12' of the previous level.

[0119] Figure 24 and Figure 25 Shown Figure 23 Two exemplary circuit structure diagrams of pixel circuits in FIG. Figure 24 As shown, the third sub-circuit 1303 may include a first transistor T1, the fourth sub-circuit 1304 may include a ninth transistor T9, the storage sub-circuit 131 may include a first capacitor Cst, the compensation sub-circuit 134 may include a second transistor T2, the driving sub-circuit 132 may include a third transistor T3, and the data writing sub-circuit 133 may include a fourth transistor T4. In a specific implementation, the pixel circuit 13 may further include a first light-emitting control sub-circuit (not shown) and a second light-emitting control sub-circuit (not shown), the first light-emitting control sub-circuit including a fifth transistor T5, the second light-emitting control sub-circuit including a sixth transistor T6, the initialization sub-circuit 130 may further include a seventh transistor T7, and the data writing sub-circuit 133 may further include an eighth transistor T8. The gate of the first transistor T1 is controlled by the second shift register 12' of the previous level, the gate of the second transistor T2 and the gate of the fourth transistor T4 are controlled by the second shift register 12, the gate of the ninth transistor T9 is controlled by the first shift register 11, the gate of the fifth transistor T5 and the gate of the sixth transistor T6 are controlled by the shift register M1, and the gate of the seventh transistor T7 and the gate of the eighth transistor T8 are controlled by the shift register M2.

[0120] Figure 25 and Figure 24 The difference is that the ninth transistor T9 is respectively arranged at the source or drain of the first transistor T1. Figure 25 The third sub-circuit 1303 includes a ninth transistor T9, and the fourth sub-circuit 1304 includes a first transistor T1.

[0121] In some embodiments, the initialization subcircuit 130 includes a third subcircuit 1303 and a fourth control subcircuit 1304, the input end of the third subcircuit 1303 is used to receive the initialization voltage signal, the output end is connected to the first node N1, the control end is connected to the output end of the fourth subcircuit 1304, the input end of the fourth subcircuit 1304 is connected to the first output end of the second shift register 12' of the previous level, and the control end is connected to the first output end of the first shift register 11.

[0122] Figure 26 Shown Figure 23 Another exemplary circuit structure diagram of the pixel circuit in FIG. Figure 26 As shown, the third sub-circuit 1303 may include a first transistor T1 , the fourth sub-circuit 1304 may include a ninth transistor T9 , and the gate of the first transistor T1 is controlled by the ninth transistor T9 . Figure 26 and Figure 24 The difference is that the ninth transistor T9 is arranged at the gate of the first transistor T1.

[0123] The three aforementioned pixel circuits each add a ninth transistor T9 to the drain, source, and gate of the first transistor T1 to control whether the initialization voltage Vinit1 is written into the first transistor T1. In these three circuit architectures, the first transistor T1, the second transistor T2, and the fourth transistor T4 are controlled by the second shift register 12, and whether the first node N1 is refreshed is controlled by the ninth transistor T9. In the low-frequency refresh region, the ninth transistor can be turned off to ensure that the first node N1 is not refreshed.

[0124] Figure 27 Shown for driving Figure 23 An exemplary timing diagram of the pixel circuit in FIG. Figure 27 As shown, in the nth row, the shielding signal SU of the shielding sub-circuit of the second shift register is switched to a high level, and the signal output by the first shift register is switched to a high level 1H in advance, which can shield the refresh of the first node N1 of the nth row and the data writing of the second node N2, thereby ensuring the normal display of the picture at the junction of the high-frequency refresh area and the low-frequency refresh area.

[0125] Figure 28 Shown Figure 23 An exemplary arrangement diagram of the control circuit is shown in FIG. Figures 23 to 28 EM3 corresponds to the first shift register, Gate+SU corresponds to the second shift register, EM1 corresponds to the shift register connected to the fifth transistor T5 and the sixth transistor T6, and EM2 corresponds to the shift register connected to the seventh transistor T7 and the eighth transistor T8. The first shift register is driven by bilateral drive, the second shift register is driven by bilateral drive, and the shift registers M1 and M2 are driven by unilateral drive. Of course, other drive modes can also be used. To ensure uniform brightness of the screen display, the second shift register must be driven by bilateral drive, while the other shift registers can be driven by bilateral drive in one group and unilateral drive in the other two groups according to actual needs.

[0126] Figure 29 Shown Figure 1 Another exemplary detailed schematic diagram of the control circuit is shown in FIG. Figure 29 As shown, the at least two groups of shift register circuits further include a third group of shift register circuits, a fourth group of shift register circuits and a fifth group of shift registers, the third group of shift register circuits includes a plurality of third shift registers 14 arranged in cascade, the fourth group of shift register circuits includes a plurality of fourth shift registers 15 arranged in cascade, and the fifth group of shift register circuits includes a plurality of fifth shift registers 16 arranged in cascade; the data writing sub-circuit 133 includes a fifth sub-circuit 1331 and a sixth sub-circuit 1332, the input end of the fifth sub-circuit 1331 is used to receive the data voltage signal Vdata, the output end is connected to the second node N2, and the control end is connected to the first output end of the second shift register 12, the input end of the sixth sub-circuit 1332 is used to receive the initialization voltage signal Vinit3, the output end is connected to the second node N2, and the control end is connected to the output end of the third shift register 14; the initialization sub-circuit 130 includes a seventh sub-circuit 1307, a sixth sub-circuit 1308, and a seventh sub-circuit 1309. The eighth sub-circuit 1308 and the ninth sub-circuit 1309, the seventh sub-circuit 1307 has an input end connected to the initialization voltage signal Vinit2, an output end connected to the fourth node N4, and a control end connected to the output end of the fourth shift register 15, the eighth sub-circuit 1308 has an input end connected to the fourth node N4, an output end connected to the third node N3, and a control end connected to the output end of the fifth shift register 16, the ninth sub-circuit 1309 has an input end connected to the third node N3, an output end connected to the first node N1, and a control end connected to the first output end of the first shift register 11; the first shift register 11 includes a shielding sub-circuit 111, and the control signal output by the shielding sub-circuit 111 is a light-emitting control signal; the eighth sub-circuit 1308 is further used to write a light-emitting control voltage from the fourth node N4 to the light-emitting element during the light-emitting phase; the ninth sub-circuit 1309 is further used to write a compensation voltage to the first node N1 during the compensation phase.

[0127] Figure 30Shown Figure 29 An exemplary circuit structure diagram of a pixel circuit in FIG. Figure 30 As shown, the fifth sub-circuit 1331 may include a fourth transistor T4, the sixth sub-circuit 1332 may include an eighth transistor T8, the storage sub-circuit 131 may include a first capacitor Cst, the driving sub-circuit 132 may include a third transistor T3, the seventh sub-circuit 1307 may include a seventh transistor T7, the eighth sub-circuit 1308 may include a sixth transistor T6, and the ninth sub-circuit 1309 may include a second transistor T2. In a specific implementation, the pixel circuit 13 may further include a light-emitting control sub-circuit (not shown), which includes a fifth transistor T5. The gate of the second transistor T2 is controlled by the first shift register 11, the gate of the fourth transistor T4 is controlled by the second shift register 12, and the gates of the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all controlled by different shift registers.

[0128] It can be understood that by controlling the fifth transistor T5 and the sixth transistor T6 by different shift registers, the second transistor T2, the sixth transistor T6, and the seventh transistor T7 can be set to be turned on at the same time in the timing, and the first node N1 can be reset by the initialization voltage Vinit2. In addition, the seventh transistor T7 and the eighth transistor T8 are also controlled by different shift registers to prevent the seventh transistor T7 and the eighth transistor T8 from being turned on at the same time, causing the initialization voltage Vinit2 and the initialization voltage Vinit3 to be short-circuited. This circuit architecture can also achieve the first row of the low-frequency refresh area without refreshing the first node N1. The pixel circuit has fewer thin-film transistors, but a larger number of shift registers.

[0129] It should be noted that the pixel circuit in this application can be designed based on a low-frequency LTPS 8T1C pixel circuit or a low-frequency LTPS 7T1C pixel circuit. Those skilled in the art can also design based on other low-frequency LTPS pixel circuits according to actual needs.

[0130] Figure 31 FIG. 2 is a schematic diagram showing a structure of a display substrate 20 in an embodiment of the present application. Figure 31 As shown, the display substrate 20 includes a base substrate 200 and a display control circuit 100 provided in any of the above embodiments. The display control circuit 100 is disposed on one side of the base substrate 20. The display control circuit 100 may include shift register circuits 1-n and a pixel circuit 13. The shift register circuits 1-n are connected to the pixel circuit 13, and the pixel circuit 13 is connected to the light-emitting element EL to control the light emission of the light-emitting element EL.

[0131] Figure 32FIG. 1 shows a flow chart of a display control method according to an embodiment of the present application. Figure 32 As shown, the display control method is applied to the display substrate provided above, and the method may include the following steps:

[0132] Step S101, determining a first display area and a second display area of ​​a display substrate;

[0133] Step S102, writing a first level into the shielding signal input terminal of the shielding sub-circuit in the shift register corresponding to the first display area;

[0134] Step S103 : writing a second level into the shielding signal input terminal of the shielding sub-circuit in the shift register corresponding to the second display area, wherein the first level is different from the second level.

[0135] The first display area refers to a display area that needs to be refreshed at a low frequency, and the second display area refers to a display area that needs to be refreshed at a high frequency. The specific positions and numbers of the first display area and the second display area on the display substrate are not limited in this embodiment.

[0136] Assume that the shift register corresponding to the first display area is in the nth row. Before the nth row, the shielding signal written into the shielding subcircuit is the second level (for example, a low level). At the nth row, the shielding signal written into the shielding subcircuit is switched to the first level (for example, a high level), thereby achieving high-frequency refresh of the second display area and low-frequency refresh of the first display area.

[0137] by Figure 12 For example, in the nth row, the shielding signal SU2 of the shielding sub-circuit of the second shift register is switched to a high level, which can shield the data writing of the nth row. The shielding signal SU1 of the shielding sub-circuit of the first shift register can be switched to a high level 1H in advance to shield the refresh of the first node N1 of the nth row, thereby ensuring the normal display of the picture at the junction of the high-frequency refresh area and the low-frequency refresh area.

[0138] by Figure 18 For example, in the nth row, the shielding signal SU of the shielding sub-circuit of the first shift register is switched to a high level, which can shield the refresh of the first node N1 of the nth row, thereby ensuring the normal display of the picture at the junction of the high-frequency refresh area and the low-frequency refresh area.

[0139] In addition, the present application also provides a display device, including the above-mentioned display substrate 20. For example, the display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, wearable device, etc., and the embodiments of the present application are not limited thereto.

[0140] In addition, it should be understood by those skilled in the art that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure is limited to these examples. Within the context of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of different aspects of one or more embodiments of the present disclosure as described above, which are not provided in detail for the sake of simplicity.

[0141] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of this disclosure.

Claims

1. A display control circuit, characterized in that: include: At least two groups of shift register circuits, including a first group of shift register circuits and a second group of shift register circuits; the first group of shift register circuits includes a plurality of first shift registers arranged in cascade connection, and the second group of shift register circuits includes a plurality of second shift registers arranged in cascade connection; A pixel circuit, comprising an initialization subcircuit, a storage subcircuit, a driving subcircuit, and a data writing subcircuit, wherein the initialization subcircuit is connected to a first node, the storage subcircuit is connected to the first node and the second node respectively, the data writing subcircuit is connected to the second node, and the driving subcircuit is connected to the first node; The control end of the initialization subcircuit is connected to the first output end of the first shift register, and the control end of the data writing subcircuit is connected to the first output end of the second shift register; the first shift register and the second shift register include a shift register subcircuit, and at least one of the first shift register and the second shift register further includes a shielding subcircuit, and the shielding subcircuit is connected to the shift register subcircuit; The shift register subcircuit is configured to output a cascade signal based on an input signal; The output end of the shielding subcircuit serves as the first output end, and is used to output a control signal based on the shielding signal. When the shielding signal is at a first level, the control signal is at the first level. When the shielding signal is at a second level, the control signal is the same as the cascade signal. The first level is different from the second level. The pixel circuit also includes a compensation subcircuit, a first end of the compensation subcircuit is connected to the first node for writing a compensation voltage to the first node, a second end is connected to the output end of the driving subcircuit, and a control end is connected to the first output end of the second shift register.

2. The display control circuit according to claim 1, wherein: The first shift register and the second shift register include the masking subcircuit, and the control signal output by the masking subcircuit is a row scanning signal.

3. The display control circuit according to claim 2, wherein: The first shift register and the second shift register are driven in a double-sided driving manner.

4. The display control circuit according to claim 1, wherein: The second shift register includes a shielding subcircuit, and the control signal output by the shielding subcircuit is a row scanning signal; The initialization sub-circuit is respectively connected to the first output end of the first shift register and the first output end of the second shift register of the previous level, and is used to write an initialization voltage to the first node under the control of the control signal output from the first output end of the first shift register and the control signal output from the first output end of the second shift register of the previous level.

5. The display control circuit according to claim 4, wherein: The initialization subcircuit includes a third subcircuit and a fourth subcircuit, wherein the input end of the third subcircuit is used to receive the initialization voltage signal, the output end is connected to the input end of the fourth subcircuit, and the output end of the fourth subcircuit is connected to the first node; The control end of one of the third sub-circuit and the fourth sub-circuit is connected to the first output end of the first shift register, and the control end of the other sub-circuit is connected to the first output end of the second shift register of the previous stage.

6. The display control circuit according to claim 4, wherein: The initialization subcircuit includes a third subcircuit and a fourth subcircuit, the input end of the third subcircuit is used to receive an initialization voltage signal, the output end is connected to the first node, and the control end is connected to the output end of the fourth subcircuit, the input end of the fourth subcircuit is connected to the first output end of the second shift register of the previous level, and the control end is connected to the first output end of the first shift register.

7. The display control circuit according to any one of claims 4 to 6, characterized in that: The driving mode of the first shift register is single-side driving or double-side driving, and the driving mode of the second shift register is double-side driving.

8. The display control circuit according to any one of claims 1 to 6, characterized in that: The transistors in the pixel circuit are all low-temperature polysilicon transistors.

9. A display substrate, characterized in that: include: a substrate, and The display control circuit according to any one of claims 1 to 8, wherein the display control circuit is arranged on one side of the base substrate.

10. A display control method, characterized in that: Applied to the display substrate according to claim 9, the method comprises: determining a first display area and a second display area of ​​the display substrate; Writing a first level into a shielding signal input terminal of a shielding sub-circuit in a shift register corresponding to the first display area; A second level is written into the shielding signal input terminal of the shielding sub-circuit in the shift register corresponding to the second display area, wherein the first level is different from the second level.

11. A display device, characterized in that: The display substrate according to claim 10 is included.

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