A non-volatile 1.5T floating gate FLASH memory

Abstract

The present invention provides a non-volatile 1.5T floating gate type FLASH memory. The memory includes a substrate, a gate transistor, a programming operation function area, an erasing operation function area and a source and drain area. The gate transistor is composed of a selection gate, a bottom dielectric layer and a top dielectric layer. The bottom dielectric layer is thinner and is conducive to low voltage reading operation; the programming operation function area includes a floating gate, a control gate-floating gate inter-gate dielectric layer and a control gate. The gate-to-gate coupling rate of the control gate and the floating gate of this structure is high, about 0.55-0.6; the erasing operation function area includes an erase gate, a floating gate and a top dielectric layer. The top erase gate covers the tip part above the floating gate. The gate-to-gate coupling rate of the erase gate and the floating gate of this structure is about 0.05, which is conducive to the tip tunneling efficient erasing operation of the memory working state. The flash memory cell structure has the advantages of high density, high reliability, low power consumption and efficient operation.

Description

Technical Field

[0001] The invention belongs to the technical field of high-end memory, and in particular relates to a non-volatile 1.5T floating gate FLASH memory. Background Art

[0002] In recent years, embedded memory technology has been evolving and innovating with the development of consumer electronics, industrial electronics, and automotive electronics. Among them, embedded SRAM and embedded flash memory dominate the market. Embedded flash memory is programmable, non-volatile, and on-chip embedded, and can provide functions such as code and data storage, backup storage, system startup, and information storage. Integrating embedded flash memory into microcontroller (MCU) products to achieve its programmability can reduce the total cost and time of system development and innovate the supply chain. Such system-level design mainly includes: storage units, hard macro storage arrays, and peripheral circuits and soft macros. Systematic design.

[0003] At present, for automotive MCU applications, embedded flash memory requires robust quality and reliability, with zero failure rate under harsh temperature conditions. Such high reliability requirements determine that NOR Flash is the best choice for automotive MCU. The present invention is based on a 55nm CMOS mass production platform, adopts a new split-gate floating gate structure, and considers logic compatibility, power consumption, cost, reliability, process controllability, memory density and chip size, making NOR Flash suitable for code storage and parameter setting in automotive MCU.

[0004] In system-level design, the storage unit determines the overall electrical performance and data reliability. The storage unit of a device that is competitive in the automotive MCU market should have the following advantages: (1) a low single read voltage (Vdd); (2) low power consumption in read mode and program / erase mode; (3) high reliability. The erase and write endurance should be ≥100K, and the data retention capacity should be ≥10 years @125℃; (4) compatible with logic; (5) small unit size and fewer masks required;

[0005] Among embedded memories, NOR Flash is a niche storage. After 2006, its market gradually shrank with the demise of feature phones, and the market space continued to decline until 2015. Since 2018, it has been widely used in the fields of Internet of Things, wearable devices, 5G, and automotive due to its "in-chip execution" feature, and the market size has gradually recovered. Driven by applications in downstream fields, the NOR Flash market has regained its growth momentum and entered a new growth period. In summary, the downward trend in the market space for NOR Flash has become history, and the development of emerging fields is bringing new opportunities for NOR Flash. A memory with larger storage space, lower operating power consumption, faster erase and write, read speed, longer data retention time, stronger erase and write endurance, and stronger anti-interference ability is the current research goal.

[0006] With the development of integrated circuits, the processing speed limit of computer systems based on the von Neumann architecture is increasingly limited by memory read bandwidth and transmission delay. The memory data access speed cannot keep up with the CPU data processing speed, resulting in an increasingly serious memory wall problem. Embedded flash memory in automotive MCU applications often requires: low power consumption and low voltage operation, automotive-grade reliability, sufficient working bandwidth, process reliability, CMOS logic compatibility, and high safety standards. The above comprehensive performance requirements are extremely challenging for embedded flash memory technology. Summary of the invention

[0007] In order to solve the problems existing in the prior art, the present invention provides a non-volatile 1.5T floating gate FLASH memory and a manufacturing method thereof, which can realize code storage with high density, high reliability, low power consumption and high operating efficiency.

[0008] The present invention provides a novel 1.5T floating gate FLASH memory, comprising a substrate, a gate transistor, a programming operation function area, an erasing operation function area and a source and drain area;

[0009] The gate transistor is manufactured on the substrate, and comprises a bottom dielectric layer, a selection gate and a top dielectric layer; the selection gate is located between the bottom dielectric layer and the top dielectric layer;

[0010] The functional area for programming operation is manufactured between the bottom dielectric layer and the top dielectric layer, and includes a first inter-gate dielectric layer, a floating gate, a second inter-gate dielectric layer and a control gate;

[0011] The first intergate dielectric layer is located on a single-side sidewall of the select gate, the floating gate is located on a side of the first intergate dielectric layer away from the select gate, the second intergate dielectric layer is located on a side of the floating gate away from the select gate, and the control gate is located on a side of the second intergate dielectric layer away from the select gate;

[0012] The floating gate half-covers the second inter-gate dielectric layer, and the second inter-gate dielectric layer half-covers the control gate;

[0013] The functional area for erase operation includes an erase gate, a floating gate and a top dielectric layer; the head of the floating gate is covered by the top dielectric layer and the erase gate;

[0014] Preferably, the bottom dielectric layer has a thickness between 20 and 150 angstroms, the top dielectric layer has a thickness between 100 and 200 angstroms, and the second dielectric layer has a thickness between 100 and 150 angstroms;

[0015] Preferably, the selection gate, floating gate, control gate and erase gate are made of polysilicon; the bottom dielectric layer and the top dielectric layer are made of silicon oxide; the first inter-gate dielectric layer and the second inter-gate dielectric layer are made of silicon oxide-silicon nitride-silicon oxide; and the substrate is made of silicon;

[0016] Preferably, the top tip angle of the floating gate is 30-60 degrees;

[0017] Preferably, the source region and the drain region are respectively arranged on two sides of the substrate, wherein the source region is close to the control gate, and the drain region is close to the selection gate;

[0018] Preferably, the floating gate and the second inter-gate dielectric layer are both L-shaped structures, the floating gate has a sharp corner at the end of the top dielectric layer, and the sharp corner is covered by the top dielectric layer and the erase gate; more specifically, the distance between the sharp corner of the floating gate and the substrate is greater than the distance between the side of the select gate close to the top dielectric layer and the substrate; the distance between the side of the select gate close to the top dielectric layer and the substrate is equal to the distance between the control gate and the substrate; the height of the floating gate close to the select gate is greater than the height of the floating gate close to the control gate;

[0019] Preferably, during the programming operation of the memory, a 1V voltage is applied to the selection gate, a 4.5V pulse voltage is applied to the source, and a 0V voltage is applied to the substrate. At this time, the voltage difference generates a transverse electric field to accelerate the electrons to become hot electrons; the drain voltage is 0.3V, and a 7-8V pulse voltage is applied to the control gate and the erase gate at the same time. At this time, the longitudinal bias voltage pulls the hot electrons from the source side into the floating gate; after 8-10μs programming time, the channel hot carriers are pulled from the source side into the floating gate under the action of the transverse and longitudinal electric fields;

[0020] When the memory is erased, an 8-12V pulse high voltage is applied to the erase gate, and the gate, source, substrate, drain, and control gate are selected to be 0V at the same time. At this time, the electrons in the floating gate are pulled out under the action of the strong electric field of the erase gate; after 2-8ms of erase time, the electrons in the floating gate are pulled into the erase gate in the area where the tip electric field is concentrated, realizing block erasure;

[0021] When the memory is in a read operation, a 1-1.5V turn-on voltage is applied to the select gate, the source and substrate are at 0V, the drain voltage is <0.8V, and the control gate and erase gate are at 1.2-1.5V at the same time;

[0022] More specifically, the currents of the memory in the programming and erasing states are Id0 and Id1 respectively, where Id0 <Id1。

[0023] The present invention also provides a novel method for manufacturing a 1.5T floating gate FLASH memory, comprising the following steps:

[0024] Step 1: Growth of the select gate oxide layer, select gate and sidewalls. After thin film deposition, ion implantation, photolithography and etching processes, the oxide layer thickness is 20-150 angstroms, the select gate thickness is 1000 angstroms, and the silicon nitride sidewall thickness is 130 angstroms.

[0025] Step 2: Preparation of ONO dielectric layer, floating gate, silicon nitride barrier layer and source region. After ONO and floating gate poly deposition, ion implantation, thin film deposition, photolithography, etching and ion implantation, an ONO dielectric layer of about 100 angstroms, a 200 angstrom "L-shaped" floating gate poly and a silicon nitride barrier layer are finally formed. 5e14,20keV As is implanted into the source region and activated by annealing at 950°C.

[0026] Step 3: Preparation of ONO dielectric layer and control gate. After removing silicon nitride, ONO and control gate poly film deposition, ion implantation, etching and annealing repair processes, a 110 angstrom ONO dielectric layer and a control gate poly layer flush with the select gate height are finally obtained. At this time, the floating gate tip is higher than the control gate and the select gate.

[0027] Step 4: Generation of oxide layer and erase gate: After thin film deposition, photolithography and etching processes, a 100 angstrom oxide layer and a 500 angstrom erase gate poly are generated.

[0028] Step 5: LDD, drain region, silicon nitride sidewall, and main structure of memory cell are formed. The main structure of the memory cell is formed by oxide film deposition, photolithography, etching, LDD ion implantation (three times), silicon nitride sidewall deposition, drain region ion implantation (three times), and annealing activation.

[0029] Step 6: The contact and interconnection processes are the same as the conventional processes.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] The present invention proposes that the top corner of the floating gate is wrapped by the erase gate, the ECR theoretical value is 0.05, it has a lower erase voltage, and the concentrated electric field at the top corner enables it to have high-efficiency erase. The floating gate of the present invention adopts an "L-type", which has a large overlapping area with the control gate, the CGR is about 0.55-0.6, and the erase efficiency is high.

[0032] The preparation process of the memory of the present invention can first make SG, the gate oxide thickness of SG is relatively thin, and a lower Vdd of 1.5V is achieved, and low power consumption reading is achieved. In summary, the novel floating gate memory of the present invention has the advantages of high density, high efficiency, low power consumption and high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a cross-sectional schematic diagram of the FLASH memory of the present invention;

[0034] Figure 2 Schematic diagram of programming and erasing mechanism of FLASH memory of the present invention, wherein (a) is programming mechanism, (b) is erasing mechanism, and (c) is reading mechanism;

[0035] Figure 3 A cross-sectional schematic diagram of the manufacturing process of the FLASH memory of the present invention;

[0036] Figure 4 I is the FLASH memory of the present invention BL -V CG curve;

[0037] Markings in the figure: 1, substrate; 2, source region; 3, drain region; 4, bottom silicon oxide dielectric layer; 5, selection gate; 6, first ONO dielectric layer; 7, floating gate; 8, second ONO dielectric layer; 9, control gate; 10, top silicon oxide dielectric layer; 11, erase gate; 12, silicon nitride dielectric layer. DETAILED DESCRIPTION

[0038] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0039] Figure 1 A cross-sectional schematic diagram of a floating gate flash memory shown in the present invention;

[0040] The memory is located on a Si substrate 1, and includes: a source region 2, a drain region 3, a bottom silicon oxide dielectric layer 4, a polysilicon selection gate 5, a first ONO dielectric layer 6 between the selection gate and the floating gate, a floating gate 7, a second ONO dielectric layer 8 between the control gate and the floating gate, a control gate 9, a top silicon oxide dielectric layer 10, and a top erase gate 11.

[0041] The second ONO dielectric layer 8 is located between the polysilicon control gate 9 and the floating gate 7 and has a thickness between 100 and 150 angstroms.

[0042] The first ONO dielectric layer 6 is located between the polysilicon select gate 5 and the floating gate 7 .

[0043] The top erase gate 11 is located on the top silicon oxide dielectric layer 10 and has a thickness between 50 and 150 angstroms.

[0044] The bottom silicon oxide dielectric layer 4 is located on the substrate 1 and is in contact with the floating gate 7 and the polysilicon selection gate 5 respectively.

[0045] The control gate 9 is half-covered by the floating gate 7; the floating gate 7 is an "L-shaped" structure, including a longitudinal arm and a transverse arm perpendicular to each other, the top of the longitudinal arm has a sharp angle structure, and the bottom is connected to one end of the transverse arm; the other end of the transverse arm faces away from the polysilicon selection gate 5. The top sharp angle of the longitudinal arm is half-covered by the top silicon oxide dielectric layer 10 and the top erase gate 11. Specifically, the top sharp angle of the longitudinal arm is 30-60 degrees.

[0046] The top silicon oxide dielectric layer 10 is located on the top of the polysilicon selection gate 5, the first ONO dielectric layer 6 between the selection gate and the floating gate, the floating gate 7, the second ONO dielectric layer 8 between the control gate and the floating gate, and the control gate 9, and has a thickness between 100-200 angstroms.

[0047] The thin thickness of the bottom silicon oxide dielectric layer of the selection transistor can support low-voltage reading, which plays a key role in reducing device power consumption. The upper tip of the floating gate is covered by the top erase gate. This structure is conducive to the efficient erasing operation of the tip tunneling in the working state of the memory. Compared with the traditional stacked gate structure, the new memory proposed in the present invention can increase the overlapping area of ​​the control gate and the floating gate while reducing the size, thereby greatly improving the control gate-floating gate inter-gate coupling rate and improving the memory operation efficiency. In addition, the independent top erase gate in the present invention can realize the separation of the charge movement channels of the programming and erasing processes, reduce the voltage that the control gate needs to withstand, and reduce the loss of the inter-gate dielectric layer while shortening the gate length of the control gate and reducing the thickness of the inter-gate dielectric layer, thereby increasing the reliability of the device operation.

[0048] Figure 2(a)-(c) are schematic diagrams of programming and erasing mechanisms of a novel 1.5T floating gate FLASH storage cell structure shown in the present invention;

[0049] In the programming operation, 1V is applied to the select gate, and the voltages of the source and substrate 1 are 4.5V (pulse) and 0V respectively. This voltage difference generates a transverse electric field to accelerate the electrons to become hot electrons. The drain voltage is 0.3V, and the control gate and erase gate 11 voltages are both 7V (pulse). At this time, the longitudinal bias voltage pulls the hot electrons from the source side into the floating gate. The programming time is 10μs, and the channel hot carriers are pulled from the source side into the floating gate under the action of the transverse and longitudinal electric fields.

[0050] In the erasing operation, the erase gate 11 applies a high voltage of 8V (pulse), and the select gate, source, substrate 1, drain, and control gate are all at 0V. At this time, the electrons in the floating gate are pulled out under the action of the strong electric field of the erase gate 11. The erasing time is 2ms, and the electrons in the floating gate are pulled into the erase gate 11 in the area where the tip electric field is concentrated, realizing block erasing.

[0051] In the read operation, the select gate applies a 1.2V turn-on voltage, the source and substrate 1 voltages are 0V, the drain voltage is 0.8V, and the control gate and erase gate 11 voltages are both 1.2V. The currents of the memory in the programming / erasing state are Id0 / Id1, where Id0<7uA and Id1>7uA are required to distinguish the two states.

[0052] Figure 3 A cross-sectional schematic diagram of a main manufacturing process of a floating gate flash memory shown in the present invention;

[0053] A bottom silicon oxide dielectric layer 4 and a 1000 angstrom polysilicon gate are formed on the silicon substrate 1 by, for example, a deposition process and ion implanted, and then a hard mask layer is deposited. Subsequently, the hard mask layer, the 500 angstrom polysilicon gate and the bottom silicon oxide dielectric layer 4 are sequentially etched by an etching process to form a 1500 angstrom middle polysilicon selection gate 5. Subsequently, a 120 angstrom first silicon oxide-silicon nitride-silicon oxide dielectric layer 6 between gates can be formed on the polysilicon selection gate 5 by, for example, a deposition process, and then etched and annealed at 900 degrees Celsius for repair.

[0054] The polysilicon floating gate 7 is formed by, for example, a deposition process and an ion implantation process is performed.

[0055] A 750 angstrom silicon nitride dielectric layer 12 is formed by, for example, a deposition process.

[0056] The silicon nitride dielectric layer 12, the 200 angstrom polysilicon floating gate 7 and the 100 angstrom inter-gate first silicon oxide-silicon nitride-silicon oxide dielectric layer 6 are etched in sequence by etching process. The silicon nitride dielectric layer is then removed to form the sidewall of the gate transistor. On the right side of the silicon substrate 1, N-type (or P-type) doping is performed by ion implantation ((5e14, 20keV As implantation and 950°C annealing repair)) to form the source region 2. The specific N-type or P-type doping is determined by the device design.

[0057] A 110 angstrom inter-gate second silicon oxide-silicon nitride-silicon oxide dielectric layer 8 is formed by chemical vapor deposition.

[0058] The polysilicon gate is deposited by a deposition process and then etched and patterned to form a control gate 9 flush with the select gate. At this time, the tip of the floating gate is higher than the control gate and the select gate.

[0059] Subsequently, a top silicon oxide dielectric layer 10 with a thickness of 100 angstroms is formed by chemical vapor deposition, and a top erase gate 11 with a thickness of 500 angstroms is formed by a deposition process and a chemical mechanical polishing process.

[0060] A lightly doped drain region is preferentially formed by oxide film deposition, photolithography, etching and three ion implantations (the first one is 3e14, 2keV As implantation; the second one is 2e13, 35keV BF2 implantation; the third one is 2.5e13, 20keV B implantation), and then a drain region 3 is finally formed on the left side of the silicon substrate 1 by silicon nitride sidewall deposition, three ion implantations (the first one is 2e13, 25keV P implantation; the second one is 1.8e15, 20keV As implantation; the third one is 8.7e14, 5keV P implantation) and 1065°C annealing activation;

[0061] Finally, contact holes, metal layers and through holes are formed through deposition, photolithography and etching processes to realize external connection of the storage unit.

[0062] Conduct electrical testing based on the device tape-out results, such as Figure 4 As shown, the device undergoes the above programming and erasing operations and reads I BL -V CG From the curve, we can see that the device has realized basic programming and erasing functions, and the corresponding storage window is around 6V.

[0063] In summary, the novel flash memory cell of the present invention has the technical advantages of small size, high operating efficiency, low power consumption and high reliability.

Claims

1. A non-volatile 1.5T floating gate FLASH memory, comprising a substrate, a gate transistor, a programming operation function area, an erasing operation function area, a source area, and a drain area; Features: The gate transistor is manufactured on the substrate, and comprises a bottom dielectric layer, a selection gate and a top dielectric layer; the selection gate is located between the bottom dielectric layer and the top dielectric layer; The functional area for programming operation is manufactured between the bottom dielectric layer and the top dielectric layer, and includes a first inter-gate dielectric layer, a floating gate, a second inter-gate dielectric layer and a control gate; The first intergate dielectric layer is located on a single-side sidewall of the select gate, the floating gate is located on a side of the first intergate dielectric layer away from the select gate, the second intergate dielectric layer is located on a side of the floating gate away from the select gate, and the control gate is located on a side of the second intergate dielectric layer away from the select gate; The floating gate half-covers the second inter-gate dielectric layer, and the second inter-gate dielectric layer half-covers the control gate; The functional area for erasing operation includes an erase gate, a floating gate and a top dielectric layer; the head of the floating gate is covered by the top dielectric layer and the erase gate, wherein the head of the floating gate has a sharp corner and the floating gate is an L-shaped structure.

2. The FLASH memory according to claim 1, characterized in that: The thickness of the bottom dielectric layer is between 20-150 angstroms, the thickness of the top dielectric layer is between 100-200 angstroms; and the thickness of the second dielectric layer is between 100-150 angstroms.

3. The FLASH memory according to claim 1, characterized in that: The selection gate, floating gate, control gate and erase gate are made of polysilicon; the bottom dielectric layer and the top dielectric layer are made of silicon oxide; the first inter-gate dielectric layer and the second inter-gate dielectric layer are made of silicon oxide-silicon nitride-silicon oxide; and the substrate is made of silicon.

4. The FLASH memory according to claim 1, characterized in that: The top tip angle of the floating gate is 30-60 degrees.

5. The FLASH memory according to claim 1, characterized in that: The source region and the drain region are respectively arranged at two sides of the substrate, wherein the source region is close to the control gate, and the drain region is close to the selection gate.

6. The FLASH memory according to claim 1, characterized in that: The second inter-gate dielectric layer is an L-shaped structure.

7. The FLASH memory according to claim 6, characterized in that: The distance between the tip corner of the floating gate and the substrate is greater than the distance between the side of the select gate close to the top dielectric layer and the substrate.

8. The FLASH memory according to claim 6, characterized in that: The height of the floating gate close to the selection gate is greater than the height of the floating gate close to the control gate.

9. The FLASH memory according to any one of claims 1 to 8, characterized in that: When the memory is programmed, a 1V voltage is applied to the select gate, a 4.5V pulse voltage is applied to the source, and a 0V voltage is applied to the substrate. At this time, the voltage difference generates a transverse electric field to accelerate the electrons to become hot electrons; the drain voltage is 0.3V, and a 7-8V pulse voltage is applied to the control gate and the erase gate at the same time. At this time, the longitudinal bias voltage pulls the hot electrons from the source side into the floating gate; after 8-10μs programming time, the channel hot carriers are pulled from the source side into the floating gate under the action of the transverse and longitudinal electric fields; When the memory is erased, an 8-12V pulse high voltage is applied to the erase gate, and the gate, source, substrate, drain, and control gate are all 0V at the same time. At this time, the electrons in the floating gate are pulled out under the action of the strong electric field of the erase gate. After 2-8 ms of erasing time, the electrons in the floating gate are pulled into the erase gate in the area where the tip electric field is concentrated, achieving block erasing; When the memory is read, a 1-1.5 V turn-on voltage is applied to the select gate, the source and substrate are at 0 V, the drain voltage is <0.8 V, and the control gate and erase gate are at 1.2-1.5 V at the same time.

10. The FLASH memory according to claim 9, characterized in that: The current of the memory in programming and erasing state is Id0 and Id1 respectively, where Id0 <Id1。

Images