Packaging structure and method of a kA single tube type SiC power semiconductor module

Abstract

The application belongs to the technical field of semiconductor, and discloses a packaging structure of a kiloampere single-tube SiC power semiconductor module, mainly including SiC chips, a ceramic substrate, a bottom plate, power and signal terminals, integrated gate / Kelvin source resistors, a shell and other components. The packaging structure improves the electric heating performance of the multi-chip parallel connection, reduces the size of the power module, breaks through the limitation of the number of parallel SiC chips, greatly improves the current capacity and power density of the existing SiC power semiconductor module, and is especially suitable for 1.7kV-6.5kV single-tube power semiconductor modules for high-power occasions such as rail transit traction and flexible DC power transmission. In addition, the packaging structure is compatible with traditional welding, bonding, potting and other processes, the preparation method is mature, and is suitable for large-scale popularization and application in actual engineering.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and particularly relates to a packaging structure and method for a kiloampere-level single-tube SiC power semiconductor module. Background Technology

[0002] High-capacity power semiconductor modules, as key components of power electronic equipment, are widely used in high-power applications such as rail transit, wind power generation, and flexible DC transmission. Currently, silicon (Si)-based power semiconductor modules are gradually approaching their material theoretical limits, becoming a major bottleneck for improving equipment performance. As a representative of wide-bandgap power semiconductors, silicon carbide (SiC) has comprehensive performance advantages over Si, including higher voltage ratings, lower switching losses, and higher operating junction temperatures, showing broad application prospects. Limited by the current rating of a single chip, high-capacity SiC power semiconductor modules are typically composed of multiple chips connected in parallel. However, the current ratings of existing commercially available 1.7kV–6.5kV high-capacity SiC power semiconductor modules are usually low (less than 1000A), making it difficult to meet the demands of high-power applications.

[0003] Currently, there are no commercially available single-transistor SiC power semiconductor modules with a current capacity exceeding 1000A (kiloampere level), and their corresponding packaging structures are also lacking. Existing commercial single-transistor Si IGBT power semiconductor modules suffer from drawbacks such as large size, low power density, and poor dynamic and static current sharing and heat dissipation performance, making them unsuitable for high-speed switching SiC chips. Therefore, this invention proposes a novel packaging structure for 1.7kV–6.5kV kiloampere-level single-transistor SiC power semiconductor modules, filling a technological gap in this field.

[0004] Based on the above analysis, the problems and shortcomings of the existing technology are as follows:

[0005] 1) Currently, there are no commercially available 1.7kV to 6.5kV kiloampere-level single-tube SiC power semiconductor modules on the market, and their corresponding packaging structures are also in a blank stage.

[0006] 2) Existing commercial kiloampere-level single-tube Si IGBT module packaging structures have disadvantages such as large size, low power density, poor dynamic and static current sharing performance and heat dissipation performance, and are not suitable for high-speed switching SiC chips. Summary of the Invention

[0007] To address the problems existing in the prior art, the present invention provides a packaging structure for a kiloampere-level single-tube SiC power semiconductor module.

[0008] This invention is implemented as follows: a packaging structure for a kiloampere-level single-tube SiC power semiconductor module, the packaging structure comprising:

[0009] 1. Multiple source power terminals and drain power terminals are distributed on multiple power DBC substrates to provide power output and input for the module;

[0010] 2. Multiple parallel SiC chips located on DBC substrates with the same or different power, each chip is connected to the corresponding source power terminal through its own power source bonding line, and connected to the corresponding drain power terminal through the drain copper region;

[0011] 3. The signal DBC substrate has Kelvin source signal terminals, gate signal terminals and Kelvin drain signal terminals for receiving and transmitting module control signals;

[0012] 4. Base plate, which is fixedly connected to the power DBC substrate and signal DBC substrate mentioned above, is used to effectively conduct the heat generated by the SiC chip and ensure the high reliability of the module.

[0013] 5. The outer casing, together with the potting silicone gel, encapsulates and protects all the above components, ensuring electrical insulation, providing mechanical support, preventing external contamination, and enabling long-term reliable operation of the module;

[0014] Specifically, the SiC power semiconductor module's packaging structure includes a total of 6 power DBC substrates, where each power DBC substrate can arrange n parallel SiC chips, where n≥6, and the entire SiC power semiconductor module contains a total of 6*n (≥36) parallel SiC chips.

[0015] Furthermore, the power DBC substrate includes a drain, a power source, a Kelvin source, and a gate copper region. The drain copper region is U-shaped, with its opening encompassing a rectangular power source copper region. Parallel SiC chips are evenly spaced on the drain copper region (n / 2 chips on each side), symmetrical about the vertical center line of the U. The gate and Kelvin source copper regions are also U-shaped, with their openings facing opposite directions to the drain copper region, and they encompass the entire drain-source copper region.

[0016] Furthermore, each SiC chip's gate pad is connected in series with an integrated gate resistor via bonding wires. Multiple sets of split gate copper regions connected to the integrated gate resistor can be arranged on two straight lines or on the same straight line, and are electrically interconnected through long bonding wires with continuous landing points. Additionally, when the Kelvin circulating current is large, each SiC chip's Kelvin source bonding wire needs to be connected in series with a Kelvin source resistor, and its layout is consistent with that of the integrated gate resistor.

[0017] Furthermore, the power source bonding lines of each parallel SiC chip are bonded in opposite directions (180° out of phase) to the gate and Kelvin source bonding lines, thereby decoupling the drive circuit and the power circuit, minimizing the influence of common source parasitic inductance, and fully leveraging the high switching speed advantage of SiC chips.

[0018] Furthermore, the common drain busbar of each parallel SiC chip current branch on the power DBC substrate is located at the vertical center line of the drain copper region, and the common source busbar is located near the center of the power source copper region. At the same time, the length and angle of the power source bonding line of each parallel SiC chip are precisely adjusted to improve the static current sharing performance of multi-chip linkage.

[0019] Furthermore, the drain and source power terminals are symmetrically arranged and placed at the common drain and common source junctions of the two power DBC substrates, thereby forming a "sub-single tube" structure.

[0020] Furthermore, arranging the single "sub-transistor" at predetermined intervals can form three "sub-transistors". Further, the gate, Kelvin source, and Kelvin drain signal terminals are placed on three identical signal DBC substrates. Both the signal DBC substrate and the power DBC substrate have a three-layer structure: an upper copper layer, a ceramic layer, and a lower copper layer, and are all connected to the base plate. Even further, the drive circuits of all parallel SiC chips are connected to the gate and Kelvin source signal terminals via copper leads or bonding wires, forming an electrical interconnection of the drive circuits. Simultaneously, the Kelvin drain signal terminal and its DBC substrate are also connected to the drain copper region of the power DBC substrate via bonding wires.

[0021] Furthermore, the SiC chips in the kiloampere-level single-tube SiC power semiconductor module packaging structure can be all SiC MOSFET chips, or a combination of SiC MOSFET chips and SiC SBD chips in a ratio such as 2:1 or 1:1.

[0022] Another object of the present invention is to provide a packaging method for a kiloampere-level single-tube SiC power semiconductor module, comprising the following steps:

[0023] S101, the SiC chip is welded or sintered to the power DBC substrate with the integrated gate / Kelvin source resistor;

[0024] S102, performs wire bonding on the gate, Kelvin source, and power source bonding wires of the SiC chip;

[0025] S103, respectively weld the drain and source power terminals and the gate, Kelvin source and Kelvin drain signal terminals to the power DBC substrate and the signal DBC substrate, and at the same time weld or sinter the power DBC substrate and the signal DBC substrate to the base plate.

[0026] S104, perform wire bonding on the interconnect bonding lines between DBC substrates;

[0027] S105, assembles the SiC power semiconductor module housing and performs potting encapsulation;

[0028] Based on the above technical solutions and the technical problems solved, please analyze the advantages and positive effects of the technical solution to be protected by this invention from the following aspects:

[0029] First, the packaging structure proposed in this invention is an innovative packaging structure formed by precisely adjusting, optimizing, and completely reconstructing the existing kiloampere-level single-tube Si IGBT power semiconductor module structure, and is especially suitable for high-speed switching SiC chips. Compared with existing Si IGBT modules, this packaging structure not only achieves a smaller size and higher power density, but also has superior dynamic and static current sharing and heat dissipation performance.

[0030] 1. High current capacity: The proposed packaging structure contains 6 parallel DBC substrates, each of which can accommodate n SiC chips (n≥6). Therefore, the entire module contains a total of 6*n (≥36) parallel SiC chips, which breaks through the limitation of the number of parallel chips in existing commercial SiC power semiconductor modules and greatly improves the current capacity of the module (≥1000A).

[0031] 2. Small package size and high power density: By utilizing the small size of SiC chips and combining a compact chip layout design with optimized copper areas on the DBC substrate, the size of the power semiconductor module is reduced, effectively improving the power density of the module.

[0032] 3. Low power loss: By employing Kelvin connections and reverse bonding technology, the drive circuit and power circuit are decoupled, fully leveraging the high switching speed advantage of SiC chips and reducing switching losses. Simultaneously, large-scale parallel connection of chips also helps reduce the conduction losses of the power semiconductor module.

[0033] 4. Excellent dynamic and static current sharing performance: In terms of power circuit design, symmetrical current paths and parasitic inductance are achieved through coordinated control of chip layout, bonding wire routing, common drain-source bus location, and drain-source power terminal structure. In terms of drive circuit design, consistency and synchronization of drive are ensured by integrating internal gate / Kelvin source resistors and symmetrically arranging gate-source signal terminals. Ultimately, the dynamic and static current sharing performance of the parallel SiC chips is significantly improved.

[0034] 5. Excellent heat dissipation performance: By adopting a PinFin direct liquid cooling base plate with integrated pin fins, the junction current thermal resistance of the parallel SiC chip is significantly reduced. Compared with the indirect cooling solution of printed thermal grease used in commercial kiloampere-level single-tube Si IGBT power modules, the heat dissipation performance of the chip is greatly improved, enhancing the reliability of the power semiconductor module.

[0035] 6. Low Package Parasitic Inductance and Baseboard Parasitic Capacitance: By adopting a stacked drain-source power terminal design, the package parasitic inductance is effectively reduced. Simultaneously, by reducing the size of the DBC substrate, the baseboard parasitic capacitance is also reduced, thereby mitigating electromagnetic interference issues such as overshoot oscillation and common-mode current caused by parasitic parameters during SiC high-speed switching, and improving the reliability of module operation.

[0036] Second, the main technical problem solved by this invention is how to reduce the package size of a kiloampere-level single-tube SiC power semiconductor module, increase current capacity and power density, and at the same time improve the multi-chip and linked static current sharing performance and heat dissipation performance.

[0037] The significant technological advancements achieved by this invention include:

[0038] 1. Improved power density: By leveraging the small size of SiC chips and combining a compact chip layout design with optimized copper areas on the DBC substrate, the module size is reduced, effectively improving the module's power density.

[0039] 2. Improved Current Handling Capacity: By connecting multiple SiC chips (≥36) in parallel within a single module, the module's current handling capacity is significantly improved, reaching the kiloampere level (≥1000A), thus meeting the demands of high-power applications. Furthermore, optimized electrical connection design ensures uniform current distribution among the parallel chips, enhancing the module's electrical performance reliability and stability.

[0040] 3. Optimized thermal management: The adoption of PinFin direct liquid cooling base plate technology effectively reduces the operating junction temperature of SiC chips, improves the thermal stability and service life of power semiconductor modules, and achieves efficient thermal management.

[0041] Third, as supplementary evidence of the inventive step of the claims of this invention, it is also reflected in the following important aspects:

[0042] (1) The expected benefits and commercial value of the technical solution of this invention after transformation are as follows:

[0043] The packaging structure proposed in this invention is particularly suitable for 1.7kV to 6.5kV kiloampere-level single-tube SiC power semiconductor modules used in high-power applications such as rail transit traction and flexible DC power transmission. It can improve the power density and efficiency of power electronic equipment such as traction inverters and flexible DC converter valves, save equipment construction, installation and operation and maintenance costs as well as power energy consumption, and has important economic, social and ecological benefits.

[0044] (2) The technical solution of this invention fills a technical gap in the industry both domestically and internationally:

[0045] This invention proposes for the first time a novel packaging structure for a 1.7kV to 6.5kV kiloampere-level single-tube SiC power semiconductor module, filling a technological gap in this field.

[0046] (3) The technical solution of the present invention solves a technical problem that people have long wanted to solve but have never been able to solve successfully:

[0047] The packaging structure proposed in this invention improves the electrothermal performance of multi-chip parallel connection, reduces the size of power module, breaks through the limitation of the number of parallel SiC chips, and greatly improves the current capacity and power density of existing SiC power semiconductor modules.

[0048] Fourth, the existing technical problems solved by the packaging structure of the kiloampere-level single-tube SiC power semiconductor module proposed in this invention and the significant technical advancements it brings mainly include the following points:

[0049] First, the proposed packaging structure effectively improves the current capacity of existing power semiconductor modules. Currently, commercial SiC power modules are limited by the number of parallel SiC chips, resulting in typically low current capacity (less than 1000A), which is insufficient for high-power applications. The proposed packaging structure utilizes advanced packaging technology to overcome the limitation on the number of parallel SiC chips (≥36), thereby increasing the current capacity of SiC power modules. This helps reduce power loss in the entire electronic system, improves the system's energy conversion efficiency, and saves energy.

[0050] Secondly, the proposed packaging structure effectively improves the power density of existing power semiconductor modules. Currently, commercially available kiloampere-level single-tube Si IGBT power modules suffer from drawbacks such as large size and low power density. The proposed packaging structure utilizes the small size of SiC chips, combined with advanced packaging technologies such as compact layout and optimized wiring, to effectively reduce the package size of power semiconductor modules. This helps to reduce the size and weight of the entire electronic system, improve system integration, and reduce equipment installation / maintenance costs.

[0051] Finally, the proposed packaging structure effectively enhances the reliability of existing power semiconductor modules. Optimized substrate layout and wiring improve the dynamic and static current sharing performance of parallel SiC chips, mitigating uneven losses and improving thermal uniformity. Direct liquid cooling via a PinFin baseplate effectively reduces chip junction thermal resistance, improving the overall heat dissipation performance of the SiC power module and ensuring its reliability under harsh environments such as high temperature and high pressure. Furthermore, the proposed packaging structure provides mechanical support and protection against external contamination, further enhancing the reliability of power electronic systems.

[0052] This kiloampere-level single-tube SiC power semiconductor module effectively solves existing technical problems through the adoption of advanced SiC chips, packaging structures, and design optimizations, achieving significant technological advancements in current capacity, efficiency, power density, and reliability. These advancements are of great significance for promoting the development of high-power applications such as flexible DC transmission and electric locomotive traction. Attached Figure Description

[0053] Figure 1 This is a circuit topology diagram of a single-tube SiC power semiconductor module provided in an embodiment of the present invention.

[0054] Figure 2 This is an overall packaging structure diagram of the 3.3kV / 2000A SiC power semiconductor module provided in an embodiment of the present invention.

[0055] Figure 3 This is a packaging structure diagram of the first power DBC substrate of the 3.3kV / 2000A SiC power semiconductor module provided in an embodiment of the present invention.

[0056] Figure 4 Here are structural diagrams of the drain and source power terminals provided in this embodiment of the invention: (a) Drain power terminal; (b) Source power terminal diagram.

[0057] Figure 5 This is a packaging structure diagram of one "sub-single tube" of a 3.3kV / 2000A SiC power semiconductor module provided in an embodiment of the present invention.

[0058] Figure 6 This is a structural diagram (bottom surface) of the PinFin direct liquid cooling base plate provided in an embodiment of the present invention.

[0059] Figure 7 This is a structural diagram of the finished 3.3kV / 2000A SiC power semiconductor module provided in an embodiment of the present invention.

[0060] Figure 8 This is a current waveform diagram of 36 parallel SiC MOSFET chips provided in an embodiment of the present invention.

[0061] The serial numbers of each encapsulated component in the diagram are as follows:

[0062] 1. Kelvin source signal terminal; 2. Gate signal terminal; 3. Kelvin drain signal terminal; 4. Source power terminal; 5. Drain power terminal; 6. Source power terminal; 7. Drain power terminal; 8. Source power terminal; 9. Drain power terminal; 10. First power DBC substrate; 11. Second power DBC substrate; 12. Signal DBC substrate; 13. PinFin direct liquid cooling base plate; 14. Drain copper area; 15. Power source copper area; 16. Kelvin source copper Regions; 17. Gate copper region; 18. SiC chip; 19. Integrated gate resistor; 20. Power source bond line; 21. Kelvin source bond line; 22. Gate bond line; 23. First interconnect gate bond line; 24. First interconnect Kelvin source bond line; 25. Second interconnect gate bond line; 26. Second interconnect Kelvin source bond line; 27. Third interconnect gate bond line; 28. Third interconnect Kelvin source bond line; 29. ​​Interconnect Kelvin drain bond line; 30. Housing. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0064] Regarding the packaging structure of kiloampere-level single-tube SiC power semiconductor modules, two specific embodiments are provided here to demonstrate the application of this technology in different application scenarios:

[0065] Example 1: MMC Flexible DC Transmission Converter Valve

[0066] High-voltage, high-capacity (kiloampere-level) power semiconductor modules are key components of the modular multilevel converter (MMC) flexible DC transmission converter valve in power systems, playing a crucial role in power conversion and control. Kiloampere-level single-tube SiC power semiconductor modules feature low on-state voltage drop and high switching frequency, effectively reducing the size and weight of MMC flexible DC converter valve equipment and improving efficiency, demonstrating significant advantages in applications such as offshore wind power flexible DC transmission.

[0067] 1. Power Conversion: In the MMC flexible DC converter valve, SiC power modules are used to achieve power conversion from AC to DC (rectification mode) or DC to AC (inverter mode). Furthermore, the low switching and conduction losses of SiC power modules can further improve power conversion efficiency.

[0068] 2. Module integration: Integrating SiC power modules into the MMC flexible DC converter valve can reduce DC bus voltage ripple, reduce the capacitance requirement of the bus capacitor, thereby reducing the size and weight of the converter valve and increasing the power density of the equipment.

[0069] 3. Thermal Management: Through optimized direct liquid cooling design, the module's thermal resistance is reduced, and its service life is improved.

[0070] Advantages and results:

[0071] Improved conversion efficiency: Compared with traditional Si IGBT power modules, SiC power modules have higher switching speeds and lower on-state voltage drops, thus achieving higher power conversion efficiency.

[0072] Increased power density: The high switching frequency characteristics of SiC power modules can reduce the size and weight of bus capacitors, thereby reducing the size and weight of the entire MMC flexible DC converter valve and increasing power density.

[0073] Extended lifespan: The optimized direct liquid cooling design can reduce the operating temperature of SiC chips and even the entire SiC power module, extending the lifespan of the MMC flexible DC converter valve.

[0074] Reduced operation and maintenance costs: The improved efficiency and power density of MMC flexible DC converter valves can effectively reduce the installation, operation and maintenance costs of the equipment, especially for offshore converter stations of offshore wind power flexible DC transmission systems.

[0075] Example 2: High-power locomotive traction inverter

[0076] High-power locomotive traction inverters are widely used in rail transit systems such as high-speed rail, light rail, and subway. Their main function is to convert direct current (DC) into three-phase alternating current (AC) to drive the three-phase asynchronous motors on the locomotive. Kiloampere-level single-tube SiC power semiconductor modules perform exceptionally well in these applications.

[0077] 1. Power Conversion: SiC power semiconductor modules are used in high-power locomotive traction inverters to convert DC power into three-phase AC power, thus realizing power conversion.

[0078] 2. Module integration: Integrating SiC power semiconductor modules into the locomotive traction inverter can reduce the weight of the inverter, increase power density, and reduce the operating noise of the locomotive.

[0079] 3. Thermal Management: Optimized direct liquid cooling is used to reduce the operating junction temperature of the traction inverter and extend its lifespan.

[0080] Advantages and results:

[0081] Improve conversion efficiency: SiC power modules can reduce power loss and improve the efficiency of traction inverters.

[0082] Increased power density: The high switching frequency characteristics of SiC power modules can reduce the weight of traction inverters.

[0083] Extended lifespan: The optimized direct liquid cooling design can extend the lifespan of the traction inverter.

[0084] Reduced operation and maintenance costs: Improved efficiency and power density of traction inverters can effectively reduce the operation and maintenance costs of the equipment and save on electricity consumption.

[0085] These two examples demonstrate that the kiloampere-level single-tube SiC power semiconductor module not only provides high-efficiency power conversion but also improves the power density and service life of power electronic equipment.

[0086] This invention provides a packaging structure for a kiloampere-level single-tube SiC power semiconductor module, characterized in that the connection or positional relationship of its components is as follows:

[0087] 1. Kelvin source signal terminal, gate signal terminal, and Kelvin drain signal terminal are disposed on the signal DBC substrate and are used to transmit corresponding control signals.

[0088] 2. The source power terminal and the drain power terminal are disposed on the first power DBC substrate and the second power DBC substrate, and are used to provide power output and input.

[0089] 3. SiC chips are arranged on the first and second power DBC substrates, and are connected to the source power terminals via power source bonding lines / copper regions, to the drain power terminals via drain copper regions, to the gate signal terminals via gate bonding lines / copper regions, and to the Kelvin source signal terminals via Kelvin source bonding lines / copper regions. In addition, an integrated gate resistor is placed on the split gate copper region and connected to the gate pad of the SiC chip via a gate bonding line.

[0090] 4. The signal DBC substrate, the first power DBC substrate, and the second power DBC substrate are all fixed on the PinFin direct liquid cooling base plate.

[0091] 5. Electrical interconnection of drive circuits is achieved between SiC chips on different DBC substrates through interconnect bonding lines (first, second, and third interconnect gate bonding lines and Kelvin source bonding lines).

[0092] 6. The entire encapsulation structure is housed in a housing, which, together with the potting silicone gel, provides electrical insulation and mechanical protection, and also prevents external contamination.

[0093] Specifically, the overall packaging structure of the 3.3kV / 2000A single-tube SiC power semiconductor module is as follows: Figure 2 As shown, the module mainly comprises SiC chips, DBC ceramic substrates, PinFin direct liquid-cooled base plates, power and signal terminals, integrated gate resistors, and a housing. The first power DBC substrate 10 and the second power DBC substrate 11 are two basic power units, connected in parallel via drain power terminals 5 / 7 / 9 and source power terminals 4 / 6 / 8 to form a "sub-transistor." The entire SiC power semiconductor module contains three "sub-transistors." Furthermore, gate signal terminal 2, Kelvin source signal terminal 1, and Kelvin drain signal terminal 3 are placed on three identical signal DBC substrates 12, and all DBC substrates are connected to the same PinFin direct liquid-cooled base plate 13. Even further, each power DBC substrate has six parallel SiC MOSFET chips (without SBD), rated at 3.3kV / 66A@Tc=100℃, sourced from Microchip Technology. Furthermore, the entire SiC power semiconductor module contains 36 parallel SiC MOSFET chips, achieving a current rating of 2376A@Tc=100℃. Considering a certain margin, its current capacity can be described as 2000A@Tc=100℃.

[0094] The following is a detailed description of the packaging structure design of the "first power DBC substrate", one "sub-single tube" and the "entire SiC power semiconductor module" provided in the embodiments of the present invention.

[0095] First, the packaging structure of the first power DBC substrate 10 is as follows: Figure 3As shown, the substrate includes a drain copper region 14, a power source copper region 15, a Kelvin source copper region 16, and a gate copper region 17. The drain copper region 14 is U-shaped, enclosing the rectangular power source copper region 15. The Kelvin source copper region 16 and the gate copper region 17 are arranged sequentially on the outer layer, also in a U-shape. Furthermore, six parallel SiC MOSFET chips 18 are compactly arranged on the drain copper region (three on each side), symmetrical about its centerline. To alleviate the asymmetry of parasitic parameters in the drive circuit and suppress dynamic current imbalance and gate parasitic oscillations, each SiC MOSFET chip's gate pad is connected in series with an integrated gate resistor 19 via a gate bonding line 22, with a resistance range of 5–15 Ω. Simultaneously, to reduce the length of the power DBC substrate, all split gate copper regions connected to the integrated gate resistor 19 are arranged on the same straight line and electrically connected via a first interconnect gate bonding line 23. Furthermore, due to the small Kelvin circulating current, the Kelvin source bonding wire 21 is not connected in series with a Kelvin source resistor. Further, the power source bonding wire 20 is bonded inwards to the power source copper region 15, while the gate bonding wire 22 and the Kelvin source bonding wire 21 are bonded outwards, with opposite bonding directions, thus decoupling the drive circuit from the power circuit. Even further, the common drain bus point of each parallel branch is located at the center line of the drain copper region 14, and the common source bus point is located slightly to the left of the center of the power source copper region 15. Simultaneously, the power source bonding wires 20 of each chip are also bonded towards the common source bus point, thereby effectively improving the dynamic and static current sharing performance of the six parallel SiC MOSFET chips within a single power DBC substrate.

[0096] Secondly, the packaging structure of a single "sub-tube" is as follows: Figure 5 As shown, a first power DBC substrate 10 and a second power DBC substrate 11 are connected in parallel via drain-source power terminals. It should be noted that the package structure of the second power DBC substrate 11 is almost identical to that of the first power DBC substrate 10; the only difference is that the gate-source copper region of the second power DBC substrate 11 does not include a U-shaped bottom edge, primarily to prevent circulating current in the drive circuit. Further, as... Figure 4As shown, the main body of the drain and source power terminals both adopt a flat structure (facilitating stacked arrangement and reducing package parasitic inductance), and include two support solder feet, placed at the common drain and common source busbars respectively. Due to the limitations of the package casing, the overall structure of the drain power terminals 5 / 7 / 9 cannot be completely symmetrical, but their busbars are symmetrical about the two support solder feet. Unlike the drain power terminals, when the busbars of the source power terminals 4 / 6 / 8 are located at the center of their two support solder feet, the overall dynamic current sharing performance of the 12 parallel SiC chips on the two power DBC substrates is very poor (due to partial mutual inductance between the drain and source terminals and self-inductance of the source terminal), even though the dynamic current sharing of each of the 6 chips on each power DBC substrate is good. Therefore, by comprehensively considering the dynamic and static current sharing performance, the busbar of the source power terminals is moved to the left to coincide with the busbar of the drain terminal, thereby optimizing the overall dynamic and static current sharing performance of the 12 parallel chips. Furthermore, the drive circuit electrical interconnection between the 12 parallel SiC chips is achieved through the first interconnect gate bonding line 23 and the first interconnect Kelvin source bonding line 24.

[0097] Furthermore, the entire SiC power semiconductor module's packaging structure is as follows: Figure 2 As shown, three "sub-transistors" are formed by arranging one "sub-transistor" at equal intervals (e.g., 2 mm). The gate signal terminal 2, Kelvin source signal terminal 1, and Kelvin drain signal terminal 3 are placed on three identical signal DBC substrates 12. All DBC substrates are soldered to... Figure 6 The PinFin direct liquid cooling base plate 13 is shown. Furthermore, since the SiC power module designed in this embodiment has a rated power of 3.3kV / 2000A@Tc=100℃, the copper layer thickness of the DBC substrate is selected as 0.4mm, and the ceramic layer is selected as 1mm AlN to ensure sufficient current carrying capacity and electrical insulation. Further, the gate signal terminal 2 and the Kelvin source signal terminal 1 are symmetrically arranged at the center of the module to ensure the symmetrical drive circuit of the three "sub-transistors". The Kelvin drain signal terminal 3 is arranged on one side of the module and connected to the drain copper area through interconnecting Kelvin drain bonding lines 29. This terminal can be used for functions such as chip desaturation protection, overvoltage monitoring, and junction temperature monitoring. Even further, the gate and source terminals of the 36 SiC MOSFET chips in the three "sub-transistors" are connected to the gate and source signal terminals 2 / 1 through the first, second, and third interconnecting gates and interconnecting Kelvin source bonding lines 23-28, realizing the electrical interconnection of the drive circuit.

[0098] Finally, the finished 3.3kV / 2000A SiC power semiconductor module, after assembling the casing, is as follows: Figure 7 As shown, its size is approximately 170*110mm, which is nearly 30% smaller than the 190*140mm size of existing commercial kiloampere-level single-tube Si IGBT power semiconductor modules, resulting in a significant increase in power density.

[0099] Based on the packaging structure of the kiloampere-level single-tube SiC power semiconductor module proposed in this invention, this embodiment provides a 3.3kV / 2000A SiC power semiconductor module, which has many advantages such as large capacity, small size, high power density, good dynamic and static current sharing performance and heat dissipation performance. It is the world's largest current capacity and highest power level SiC power semiconductor module to date, providing solid technical support for high-power applications such as rail transit traction and flexible DC power transmission.

[0100] This invention provides a packaging structure for a kiloampere-level single-tube SiC power semiconductor module, which mainly solves the problems of large size, low power density, small current capacity, and poor heat dissipation performance in existing power semiconductor packaging technologies. The specific working principle is as follows:

[0101] 1. Layout Design: This packaging structure includes multiple power DBC substrates, each equipped with multiple SiC chips, which are connected in parallel using power terminals to form multiple "sub-single-transistor" structures, improving the module's current handling capability. Furthermore, by optimizing the chip layout and the copper area of ​​the DBC substrate, the package size of the power semiconductor module is reduced, increasing the module's power density.

[0102] 2. Wiring Design: Optimized electrical connection design, such as the configuration of bonding wires, bus points, and terminals, ensures a balanced current distribution among parallel chips. Furthermore, reverse bonding technology decouples the drive circuit and power circuit, improving the module's switching speed while reducing electromagnetic interference.

[0103] 3. Heat dissipation design: Direct liquid cooling is achieved using a PinFin base plate, which improves heat dissipation efficiency, reduces the operating junction temperature of the SiC chip, and effectively improves the reliability and lifespan of the module.

[0104] Through the above design, the packaging structure proposed in this invention improves the electrothermal performance of multi-chip parallel connections, reduces the size of power modules, and overcomes the limitation on the number of parallel SiC chips. This significantly enhances the current capacity and power density of existing SiC power semiconductor modules, making it particularly suitable for 1.7kV to 6.5kV single-tube power semiconductor modules used in high-power applications such as rail transit traction and flexible DC transmission. Furthermore, the packaging structure proposed in this invention is compatible with traditional soldering, bonding, and potting processes, and the fabrication method is mature and suitable for large-scale application in practical engineering.

[0105] like Figure 7As shown, the 3.3kV / 2000A SiC power semiconductor module provided in this embodiment of the invention has a size of approximately 170*110mm, which is nearly 30% smaller than the 190*140mm size of existing commercial kiloampere-level single-tube Si IGBT power semiconductor modules, effectively improving power density. Furthermore, as... Figure 8 As shown, the electromagnetic co-simulation results of Ansys Q3D and Simplier verify the good dynamic and static current sharing performance of the 36 parallel SiC MOSFET chips. Specifically, the dual-pulse test bus voltage was 1700V, the total load current was 1800A, the maximum static current difference among the 36 parallel SiC MOSFET chips was 1.2A (imbalance <2.5%), and the maximum dynamic current difference was 28A (imbalance <40%).

[0106] The package structure of this kiloampere-level single-transistor SiC power semiconductor module is a high-performance structure designed for high-voltage, high-current applications. The specific package structure and the working principle of each component are as follows:

[0107] Power Input and Output: Source power terminals 4, 6, and 8, and drain power terminals 5, 7, and 9 are distributed on the first power DBC substrate 10 and the second power DBC substrate 11. These terminals are responsible for providing power input and output to the SiC chip.

[0108] SiC chip connection: Six parallel SiC chips are arranged on each power DBC substrate. These chips are connected to the source power terminal through the power source bonding line / copper region and to the drain power terminal through the drain copper region.

[0109] Signal Transmission and Control: Gate signal terminal 2, Kelvin source signal terminal 1, and Kelvin drain signal terminal 3 are mounted on the signal DBC substrate 12, responsible for transmitting control signals to the SiC chip. These signal terminals are connected to the gate pad of the SiC chip via gate bonding lines / copper regions, enabling precise control of the SiC chip. Furthermore, an integrated gate resistor 19 is placed on the gate copper region and connected to the SiC chip via gate bonding lines, thereby suppressing parasitic gate oscillations in parallel chips, improving dynamic current sharing, and enhancing reliability.

[0110] Thermal Solution: All signal DBC substrates and power DBC substrates are connected to the PinFin direct liquid cooling base plate 13. This base plate design utilizes PinFin technology to achieve direct liquid cooling, reducing the junction thermal resistance of the SiC chip and improving the overall heat dissipation performance of the SiC power module.

[0111] Housing and Protection: The entire encapsulation structure is housed within a housing 30. The housing and the potting silicone gel together provide electrical insulation and mechanical protection, while preventing the intrusion of external environments such as dust and moisture, ensuring stable operation of the device even in harsh environments.

[0112] This packaging design philosophy enhances the current capacity, power density, and reliability of high-voltage, high-current power semiconductor modules by optimizing electrical connections and physical layout. Simultaneously, the design also considers fault diagnosis needs in practical applications, enabling online status monitoring through integrated signal terminals.

[0113] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A packaging structure for a kiloampere-level single-transistor SiC power semiconductor module, characterized in that, include: Multiple source power terminals and drain power terminals are distributed on multiple power DBC substrates to provide power output and input for the module; Multiple parallel SiC chips are located on DBC substrates with the same or different power. Each SiC chip is connected to the corresponding source power terminal through its own power source bonding line and to the corresponding drain power terminal through the drain copper region. The signal DBC substrate has Kelvin source signal terminals, gate signal terminals and Kelvin drain signal terminals, which are used to receive and transmit control signals of the module. The base plate is fixedly connected to the power DBC substrate and the signal DBC substrate mentioned above, and is used to effectively conduct the heat generated by the SiC chip to ensure the high reliability of the module. The housing, along with the potting silicone gel, encapsulates and protects all the above components, ensuring electrical insulation and providing mechanical support.

2. The packaging structure of the kiloampere-level single-tube SiC power semiconductor module as described in claim 1, characterized in that, The kiloampere-level single-tube SiC power semiconductor module contains a total of 6 power DBC substrates, and each power DBC substrate has n parallel SiC chips arranged in it, where n≥6. Therefore, the kiloampere-level single-tube SiC power semiconductor module contains a total of 6*n parallel SiC chips.

3. The packaging structure of the kiloampere-level single-tube SiC power semiconductor module as described in claim 2, characterized in that, The power DBC substrate includes a drain, a power source, a Kelvin source, and a gate copper region. The drain copper region is U-shaped, and its opening surrounds the rectangular power source copper region. Parallel SiC chips are arranged at equal intervals on the drain copper region, symmetrical about the vertical center line of the U. The gate and Kelvin source copper regions are also U-shaped, with their openings facing the opposite direction to the opening of the drain copper region, and they surround the entire drain-source copper region.

4. The packaging structure of the kiloampere-level single-tube SiC power semiconductor module as described in claim 3, characterized in that, Each SiC chip's gate pad is connected in series with an integrated gate resistor via a bonding wire. Multiple sets of split gate copper regions connected to the integrated gate resistor are arranged on two straight lines or on the same straight line, and are electrically interconnected by long bonding wires with continuous landing points. In addition, when the Kelvin circulating current exceeds the maximum allowable current carrying capacity of the Kelvin source bonding wire, a Kelvin source resistor needs to be connected in series with the Kelvin source bonding wire of each SiC chip, and its layout is consistent with that of the integrated gate resistor.

5. The packaging structure of the kiloampere-level single-tube SiC power semiconductor module as described in claim 4, characterized in that, The power source bonding wires of each parallel SiC chip are bonded in opposite directions to the gate and Kelvin source bonding wires, thereby decoupling the drive circuit and the power circuit, minimizing the influence of common source parasitic inductance, and fully leveraging the high switching speed advantage of SiC chips.

6. The packaging structure of the kiloampere-level single-tube SiC power semiconductor module as described in claim 3, characterized in that, The common drain busbar of each parallel SiC chip current branch on the power DBC substrate is located at the vertical center line of the drain copper region, and the common source busbar is located near the center of the power source copper region. At the same time, the length and angle of the power source bonding line of each parallel SiC chip are precisely adjusted to improve the static current sharing performance of multi-chip linkage.

7. The packaging structure of the kiloampere-level single-tube SiC power semiconductor module as described in claim 6, characterized in that, The drain and source power terminals are symmetrically arranged and placed at the common drain and common source junctions of the two power DBC substrates, thus forming a "sub-single tube" structure.

8. The packaging structure of the kiloampere-level single-tube SiC power semiconductor module as described in claim 7, characterized in that, The "sub-transistor" is arranged at predetermined intervals to form three "sub-transistors"; the gate, Kelvin source, and Kelvin drain signal terminals are respectively placed on three identical signal DBC substrates; both the signal DBC substrate and the power DBC substrate have a three-layer structure, with an upper copper layer, a ceramic layer, and a lower copper layer, and are all connected to the base plate; the drive circuits of all parallel SiC chips are connected to the gate and Kelvin source signal terminals through copper leads or bonding wires to form an electrical interconnection of the drive circuits; at the same time, the Kelvin drain signal terminal and its DBC substrate are also connected to the drain copper area of ​​the power DBC substrate through bonding wires.

9. The packaging structure of the kiloampere-level single-tube SiC power semiconductor module as described in claim 1, characterized in that, The packaging structure of the kiloampere-level single-tube SiC power semiconductor module contains only SiC MOSFET chips, or a combination of SiC MOSFET chips and SiC SBD chips.

10. A packaging method for a kiloampere-level single-tube SiC power semiconductor module, characterized in that, Includes the following steps: S101, the SiC chip is welded or sintered to the power DBC substrate with the integrated gate / Kelvin source resistor; S102, performs wire bonding on the gate, Kelvin source, and power source bonding wires of the SiC chip; S103, respectively weld the drain and source power terminals and the gate, Kelvin source and Kelvin drain signal terminals to the power DBC substrate and the signal DBC substrate, and at the same time weld or sinter the power DBC substrate and the signal DBC substrate to the base plate. S104, perform wire bonding on the interconnect bonding lines between DBC substrates; S105 is used to assemble the SiC power semiconductor module housing and perform potting encapsulation.

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