Isolation capacitor device and preparation method thereof, multi-channel isolation chip and wafer

Abstract

The present application provides an isolated capacitor device and a preparation method thereof, a multi-channel isolation chip and a wafer, which belong to the field of semiconductor integrated circuit technology. The device includes a substrate, and a first metal layer, which is arranged on the substrate; a dielectric layer, which is arranged on the side of the first metal layer away from the substrate; a second metal layer, which is arranged on the side of the dielectric layer away from the first metal layer; and the orthographic projection of the center of the second metal layer on the substrate coincides with the orthographic projection of the center of the first metal layer on the substrate, and the potential of the second metal layer is higher than the potential of the first metal layer; at least two device metal ring groups, the spacing between the orthographic projection of the at least two device metal ring groups on the substrate and the first metal layer increases from the first metal layer to the second metal layer, and the device metal ring groups are connected through metal through holes and then grounded to form a Faraday cage to isolate and shield the isolated capacitor device from external interference.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to an isolation capacitor device, a method for preparing an isolation capacitor device, a multi-channel isolation chip and a wafer. Background Art

[0002] Isolation circuits are widely used in industrial automation systems, medical electronic equipment, and hybrid vehicles to protect systems and users from potentially dangerous voltages. In actual electronic industrial applications, equipment needs to work stably in strong magnetic fields, high surges, and more stringent temperature environments, which poses a greater challenge to the innovation and upgrading of isolation circuit technology.

[0003] There are currently four main digital isolator models: optocoupler, giant magnetoresistance (GMR) coupling, magnetic coupling, and capacitive coupling. Optocoupler isolation technology has low electro-optical conversion efficiency and is subject to certain limitations in service life, speed, and power consumption. Digital isolators based on giant magnetoresistance do not have absolute advantages in technical indicators for the time being. Capacitive isolation is achieved by adding a capacitive isolation barrier on the top of each chip to connect in series. Compared with several other isolation technologies, the main advantages of high-performance capacitive isolation chips are smaller area structures, higher transmission efficiency, high resistance to magnetic field interference, better overvoltage and overheating parameter stability, lower power consumption, wider operating temperature range, and longer service life. In terms of process, it has good compatibility with complementary metal oxide semiconductor (CMOS) processes, and can be integrated into a single chip with various functional unit circuits such as analog-to-digital converters (ADCs), serial peripheral devices (SPI) interfaces, and comparators. It is easy to realize serialized isolation products through multi-functional integration and improve product cost performance; currently, capacitive isolation chip technology has gradually expanded its market share.

[0004] Since complex application scenarios such as power, industrial control, and rail transit will pose greater challenges in terms of anti-electromagnetic interference capabilities, transmission rates, voltage resistance, and especially isolation safety performance, their core isolation capacitor components need further in-depth research. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide an isolation capacitor device and a preparation method thereof, a multi-channel isolation chip and a wafer. The isolation capacitor device is provided with at least two device metal ring groups to form a Faraday cage to isolate and shield the isolation capacitor device from external interference, so as to enhance the isolation capacitor device's ability to resist magnetic field interference.

[0006] In order to achieve the above-mentioned object, the present application provides, in a first aspect, an isolated capacitor device, including a substrate, wherein the isolated capacitor device further includes:

[0007] A first metal layer is disposed on the substrate;

[0008] A dielectric layer, disposed on a side of the first metal layer away from the substrate;

[0009] A second metal layer is disposed on a side of the dielectric layer away from the first metal layer; an orthographic projection of the center of the second metal layer on the substrate coincides with an orthographic projection of the center of the first metal layer on the substrate, and a potential of the second metal layer is higher than a potential of the first metal layer;

[0010] At least two device metal ring groups, the spacing between the orthographic projections of the at least two device metal ring groups on the substrate and the first metal layer increases from the first metal layer to the second metal layer, and the device metal ring groups are connected through metal through holes and then grounded to form a Faraday cage to isolate and shield the isolated capacitor device from external interference.

[0011] According to the above technical means, the isolation capacitor device is provided with at least two device metal ring groups, each device metal ring group is connected to the ground through a metal through hole, and each metal ring group is at zero potential, which can form a Faraday cage to isolate and shield the isolation capacitor device from external interference, so as to enhance the isolation capacitor device's ability to resist magnetic field interference.

[0012] In the embodiment of the present application, the device metal ring group includes a device metal ring group arranged at the periphery of the second metal layer and at least one device metal ring group arranged in the dielectric layer.

[0013] According to the above technical means, there is a device metal ring group flush with the second metal layer. The device metal ring group can be made in the same layer as the second metal layer, saving the process flow. The formed Faraday cage can isolate and shield the second metal layer from external interference.

[0014] In the embodiment of the present application, the device metal ring group includes a device metal ring group arranged at the periphery of the second metal layer and a device metal ring group arranged at the periphery of the first metal layer.

[0015] According to the above-mentioned technical means, device metal ring groups are respectively arranged on the periphery of the second metal layer and the periphery of the first metal layer. The device metal ring group on the periphery of the first metal layer is made in the same layer as the first metal layer, and the device metal ring group on the periphery of the second metal layer is made in the same layer as the second metal, which saves the process flow and can better shield the first metal layer and the second metal layer from external interference.

[0016] In an embodiment of the present application, the device metal ring group further includes at least one device metal ring group disposed in a dielectric layer.

[0017] According to the above technical means, adding a device metal ring group in the dielectric layer can further improve the shielding effect.

[0018] In an embodiment of the present application, the device metal ring group includes at least one metal ring, and the metal rings in the same metal ring group are concentric rings and are connected by metal wires.

[0019] According to the above technical means, at least one metal ring is arranged in the same metal ring group, and when the number of metal rings is greater than one, they are connected by metal wires, which can enhance the shielding effect.

[0020] In the embodiment of the present application, the number of metal rings in the device metal ring group increases from the first metal layer to the second metal layer, device metal ring group by device metal ring group.

[0021] According to the above technical means, the potential of the second metal layer is higher than that of the first metal layer, and the external interference to the second metal layer is also relatively high. The number of metal rings is set to increase from the first metal layer to the second metal layer, and the metal ring group of each device is increased gradually, so as to gradually enhance the shielding effect and protect the second metal layer from external interference.

[0022] In an embodiment of the present application, the device metal ring group includes at least one metal ring, the metal rings in the same metal ring group are concentric rings, and the metal rings located in the same circle layer in different metal ring groups are connected through metal through holes and then grounded to form a multi-layer Faraday cage isolation shielding the isolated capacitor device from external interference.

[0023] According to the above technical means, a multi-layer Faraday cage can be formed to shield the isolated capacitor device, further improving the shielding effect.

[0024] In an embodiment of the present application, there is a first distance between the first metal layer and the second metal layer; there is a second distance between the device metal ring group arranged at the periphery of the second metal layer and the second metal layer, and the second distance is greater than or equal to the first distance.

[0025] According to the above technical means, setting the second spacing to be greater than or equal to the first spacing can prevent the capacitor between the second metal layer and the device metal ring group arranged outside the second metal layer from being broken down in advance.

[0026] In the embodiment of the present application, the orthographic projections of the first metal layer and the second metal layer on the substrate are circular.

[0027] According to the above technical means, the first metal layer and the second metal layer are set to be circular, the outer circumference of the circle is smooth and there is no tip, which can effectively suppress tip discharge.

[0028] In the embodiment of the present application, the orthographic projections of the first metal layer and the second metal layer on the substrate are rounded rectangles.

[0029] According to the above technical means, the first metal layer and the second metal layer are set to be a rounded rectangle, which can effectively reduce tip discharge.

[0030] In the embodiment of the present application, the isolation capacitor device further includes: a buffer layer disposed between the dielectric layer and the second metal layer.

[0031] In an embodiment of the present application, the material of the buffer layer is silicon nitride or silicon nitride oxide.

[0032] According to the above technical means, a silicon nitride buffer layer is used to keep the polarity difference of the dielectric layer's surge resistance to a minimum, while increasing the barrier height, limiting charge injection and reducing the formation of space charge; the use of a silicon oxynitride buffer layer can make the distribution of the breakdown voltage of the entire wafer very compact, eliminating the differences between regions, and performing well in resisting warpage.

[0033] In the embodiment of the present application, the material of the dielectric layer is silicon dioxide, polyimide, silicon nitride, silicon oxynitride or high-K material.

[0034] According to the above technical means, the dielectric layer prepared using the above material can enable the isolated capacitor device to achieve a wider operating temperature range and a longer service life.

[0035] In an embodiment of the present application, the dielectric layer is formed by alternately stacking silicon dioxide, polyimide, silicon nitride, silicon oxynitride or high-K material.

[0036] A second aspect of the present application provides a multi-channel isolation chip, the multi-channel isolation chip comprising:

[0037] A plurality of said isolation capacitor devices;

[0038] At least two chip metal ring groups are provided, and the chip metal ring groups are connected through through holes and then grounded to form a Faraday cage to isolate and shield the plurality of isolated capacitor devices from external interference.

[0039] According to the above technical means, the multi-channel isolation chip has multiple isolation channels. The isolation capacitor device of each channel is separately provided with a device metal ring group for interference isolation. The channels do not interfere with each other. The entire chip is provided with a chip metal ring group to protect the entire chip from external interference.

[0040] In an embodiment of the present application, the multi-channel isolation chip further includes:

[0041] a plurality of first capacitive devices, wherein the first capacitive devices and the isolation capacitive devices are arranged at intervals, and any two first capacitive devices are not adjacent to each other;

[0042] The first capacitive device includes a first metal layer, a dielectric layer and a second metal layer.

[0043] According to the above technical means, a first capacitor device that does not include a device metal ring group is set in a multi-channel isolation chip, the first capacitor device and the isolation capacitor device are isolated and set, the device metal ring group of the isolation capacitor device is used to achieve interference isolation between each channel, and then the chip metal ring group set in the entire chip is used to achieve interference isolation between the first capacitor device and the isolation chip, which can further reduce the size of the isolation chip.

[0044] A third aspect of the present application provides a method for preparing an isolated capacitor device, the method being used to prepare the isolated capacitor device, the method comprising:

[0045] forming a first metal layer on a substrate;

[0046] forming a dielectric layer on the first metal layer; wherein at least one metal ring is provided in the dielectric layer;

[0047] forming a second metal layer on the dielectric layer; wherein the potential of the second metal layer is higher than the potential of the first metal layer; and the orthographic projection of the center of the second metal layer on the substrate coincides with the orthographic projection of the center of the first metal layer on the substrate;

[0048] A metal through hole and at least two device metal ring groups are formed, wherein the spacing between the orthographic projections of the at least two device metal ring groups on the substrate and the first metal layer increases from the first metal layer to the second metal layer, and the device metal ring groups are connected through the metal through hole and then grounded to form a Faraday cage to isolate and shield the first metal layer and the second metal layer from external interference.

[0049] According to the above technical means, the prepared isolation capacitor device is provided with at least two device metal ring groups, each device metal ring group is connected to the ground through a metal through hole, and each device metal ring group is at zero potential, which can form a Faraday cage to isolate and shield the first metal layer and the second metal layer from external interference, so as to enhance the isolation capacitor device's ability to resist magnetic field interference.

[0050] In the embodiment of the present application, the dielectric layer is composed of multiple layers of dielectrics;

[0051] Metal through holes and device metal ring groups are alternately formed in different layers of dielectrics to ensure that at least one device metal ring group is disposed in the dielectric layer;

[0052] A device metal ring group is formed on the dielectric layer to ensure that a device metal ring group is arranged on the periphery of the second metal layer.

[0053] According to the above technical means, there is a device metal ring group flush with the second metal layer. The device metal ring group can be made in the same layer as the second metal layer, saving the process flow. The formed Faraday cage can isolate and shield the second metal layer from external interference.

[0054] A fourth aspect of the present application provides a wafer, which includes the isolation capacitor device described above, or includes the multi-channel isolation chip described above.

[0055] Through the above technical solution, the present application provides an isolated capacitor device, which is provided with at least two device metal ring groups, each device metal ring group is connected to the ground through a metal through hole, each metal ring group is at zero potential, and can form a Faraday cage to isolate and shield the first metal layer and the second metal layer from external interference, so as to enhance the isolation capacitor device's ability to resist magnetic field interference.

[0056] The present application also provides a multi-channel isolation chip, which has multiple isolation channels. The isolation capacitor device of each channel is individually provided with a device metal ring group for interference isolation. The channels do not interfere with each other. The entire chip is provided with a chip metal ring group to protect the entire chip from external interference.

[0057] Other features and advantages of the embodiments of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The accompanying drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the embodiments of the present application, but do not constitute a limitation on the embodiments of the present application. In the accompanying drawings:

[0059] Figure 1 is a schematic top view of the isolated capacitor device structure provided in the first embodiment of the present application;

[0060] Figure 2 is a cross-sectional schematic diagram of an isolation capacitor device provided in Example 1 of the present application;

[0061] Figure 3 is a three-dimensional schematic diagram of an isolated capacitor device provided in Example 1 of the present application;

[0062] Figure 4 is a schematic top view of the isolated capacitor device structure provided in the second embodiment of the present application;

[0063] Figure 5 is a schematic top view of the isolated capacitor device structure provided in the third embodiment of the present application;

[0064] Figure 6 is a cross-sectional schematic diagram of an isolation capacitor device provided in Embodiment 3 of the present application;

[0065] Figure 7 is a three-dimensional schematic diagram of an isolated capacitor device provided in Embodiment 3 of the present application;

[0066] Figure 8 is a cross-sectional schematic diagram of an isolation capacitor device provided in Embodiment 4 of the present application;

[0067] Fig. 9 is a cross-sectional schematic diagram of an isolation capacitor device provided in Embodiment 5 of the present application;

[0068] Fig.10 is a cross-sectional schematic diagram of an isolation capacitor device provided in Example 6 of the present application;

[0069] Fig.11 This is a top view schematic diagram of a multi-channel isolation chip provided by an embodiment of the present application;

[0070] Fig.12 It is a top view schematic diagram of a multi-channel isolation chip provided in another embodiment of the present application.

[0071] Description of Reference Numerals

[0072] 100-isolation capacitor device, 200-chip metal ring group, 300-first capacitor device, 11-second metal layer, 12-device metal ring group, 13-dielectric layer, 14-substrate, 15-first metal layer, 16-metal through hole, 17-buffer layer, 121-first device metal ring group, 122-second device metal ring group, 123-third device metal ring group, 124-fourth device metal ring group, 125-fifth device metal ring group, 1211-metal ring, 1212-metal wire. DETAILED DESCRIPTION

[0073] The specific implementation of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the present invention, and is not used to limit the present invention.

[0074] The present application provides an isolated capacitor device, the isolated capacitor device comprising a substrate, and the isolated capacitor device further comprising:

[0075] A first metal layer is disposed on the substrate;

[0076] A dielectric layer, disposed on a side of the first metal layer away from the substrate;

[0077] A second metal layer is disposed on a side of the dielectric layer away from the first metal layer; an orthographic projection of the center of the second metal layer on the substrate coincides with an orthographic projection of the center of the first metal layer on the substrate, and a potential of the second metal layer is higher than a potential of the first metal layer;

[0078] At least two device metal ring groups, the spacing between the orthographic projections of the at least two device metal ring groups on the substrate and the first metal layer increases from the first metal layer to the second metal layer, and the device metal ring groups are connected through metal through holes and then grounded to form a Faraday cage to isolate and shield the isolated capacitor device from external interference. The orthographic projections of two adjacent device metal ring groups on the substrate overlap, and the overlapping parts of the two adjacent device metal ring groups are connected through vertically arranged metal through holes.

[0079] In the above-mentioned isolated capacitor device, the first metal layer is the lower plate of the isolated capacitor device, and the second metal layer is the upper plate of the isolated capacitor device. In the isolated capacitor device, the lower plate is grounded and is at zero potential. According to the above-mentioned technical means, the isolated capacitor device is provided with at least two device metal ring groups, each of which is connected to the ground through a metal through hole, and each metal ring group is at zero potential, which can form a Faraday cage to isolate and shield the isolated capacitor device from external interference, so as to improve the isolation capacitor device's ability to resist magnetic field interference.

[0080] In the embodiment of the present application, the device metal ring group includes a device metal ring group arranged at the periphery of the second metal layer and at least one device metal ring group arranged in the dielectric layer.

[0081] According to the above technical means, there is a device metal ring group flush with the second metal layer. The device metal ring group can be made in the same layer as the second metal layer, saving the process flow. The formed Faraday cage can isolate and shield the second metal layer from external interference.

[0082] In the embodiment of the present application, the device metal ring group includes a device metal ring group arranged at the periphery of the second metal layer and a device metal ring group arranged at the periphery of the first metal layer.

[0083] According to the above-mentioned technical means, device metal ring groups are respectively arranged on the periphery of the second metal layer and the periphery of the first metal layer. The device metal ring group on the periphery of the first metal layer is made in the same layer as the first metal layer, and the device metal ring group on the periphery of the second metal layer is made in the same layer as the second metal, which saves the process flow and can better shield the first metal layer and the second metal layer from external interference.

[0084] In an embodiment of the present application, the device metal ring group further includes at least one device metal ring group disposed in a dielectric layer.

[0085] According to the above technical means, adding a device metal ring group in the dielectric layer can further improve the shielding effect.

[0086] In the embodiment of the present application, there is a first spacing between the first metal layer and the second metal layer; there is a second spacing between the device metal ring group arranged at the periphery of the second metal layer and the second metal layer, and the second spacing is greater than or equal to the first spacing. If a device metal ring group is arranged at the periphery of the first metal layer, there is a third spacing between the device metal ring group at the periphery of the first metal layer and the first metal layer. On the basis of ensuring that the second spacing is greater than or equal to the first spacing, the second spacing and the third spacing are determined through simulation, while taking into account the size of the isolation capacitor device.

[0087] According to the above technical means, setting the second spacing to be greater than or equal to the first spacing can prevent the capacitor between the second metal layer and the device metal ring group arranged outside the second metal layer from being broken down in advance.

[0088] Embodiment 1

[0089] like Figure 1-Figure 3 As shown, this embodiment provides an isolated capacitor device 100, the isolated capacitor device 100 includes a substrate 14, a first metal layer 15, a dielectric layer 13 and a second metal layer 11, a first device metal ring group 121 is arranged on the periphery of the second metal layer 11, a second device metal ring group 122 is arranged in the dielectric layer 13, the first device metal ring group 121 and the second device metal ring group 122 are connected to each other through a metal through hole 16 and then grounded, in this embodiment, each device metal ring group includes a metal ring. The orthographic projections of the metal rings in two adjacent device metal ring groups on the substrate overlap, and the overlapping parts of the two adjacent device metal ring groups are connected through a vertically arranged metal through hole.

[0090] In the embodiment of the present application, there is a first distance between the first metal layer 15 and the second metal layer 11; there is a second distance between the device metal ring group 121 arranged at the periphery of the second metal layer 11 and the second metal layer 11, and the second distance is greater than or equal to the first distance.

[0091] According to the above technical means, setting the second spacing to be greater than or equal to the first spacing can prevent the capacitor between the second metal layer and the device metal ring group arranged outside the second metal layer from being broken down in advance.

[0092] In the embodiment of the present application, the orthographic projections of the first metal layer 15 and the second metal layer 11 on the substrate 14 are circular. The first metal layer 15 and the second metal layer 14 are set to be circular, and the outer periphery of the circle is smooth without a sharp point, which can effectively suppress the discharge of the sharp point.

[0093] In the embodiment of the present application, the material of the dielectric layer 13 is silicon dioxide SiO 2 , polyimide Polyimid, silicon nitride SiN, silicon oxynitride SiON or a high-K material.

[0094] According to the above technical means, the dielectric layer prepared using the above material can enable the isolated capacitor device to achieve a wider operating temperature range and a longer service life.

[0095] Embodiment 2

[0096] like Figure 4 As shown, an embodiment of the present application provides an isolated capacitor device 100, the isolated capacitor device 100 includes a substrate 14, a first metal layer 15, a dielectric layer 13 and a second metal layer 11, a first device metal ring group 121 is arranged on the periphery of the second metal layer 11, a fifth device metal ring group 125 is arranged on the periphery of the first metal layer 15, the first device metal ring group 121 and the fifth device metal ring group 125 are connected to ground through a metal through hole 16, in this embodiment, each device metal ring group includes a metal ring. The orthographic projections of two adjacent device metal ring groups on the substrate overlap, and the overlapping parts of the two adjacent device metal ring groups are connected through a vertically arranged metal through hole. The orthographic projections of the metal rings in the two adjacent device metal ring groups on the substrate overlap, and the overlapping parts of the two adjacent device metal ring groups are connected through a vertically arranged metal through hole.

[0097] In the embodiment of the present application, there is a first distance between the first metal layer 15 and the second metal layer 11; there is a second distance between the device metal ring group 121 arranged at the periphery of the second metal layer 11 and the second metal layer 11, and the second distance is greater than or equal to the first distance.

[0098] According to the above technical means, setting the second spacing to be greater than or equal to the first spacing can prevent the capacitor between the second metal layer and the device metal ring group arranged outside the second metal layer from being broken down in advance.

[0099] In the embodiment of the present application, the orthographic projections of the first metal layer 15 and the second metal layer 11 on the substrate 14 are circular. The first metal layer 15 and the second metal layer 14 are set to be circular, and the outer periphery of the circle is smooth without a sharp point, which can effectively suppress the discharge of the sharp point.

[0100] In the embodiment of the present application, the material of the dielectric layer 13 is silicon dioxide SiO 2 , polyimide Polyimid, silicon nitride SiN, silicon oxynitride SiON or a high-K material.

[0101] According to the above technical means, the dielectric layer prepared using the above material can enable the isolated capacitor device to achieve a wider operating temperature range and a longer service life.

[0102] Embodiment 3

[0103] like Figure 5-Figure 7As shown, this embodiment provides an isolated capacitor device 100, the isolated capacitor device 100 includes a substrate 14, a first metal layer 15, a dielectric layer 13 and a second metal layer 11, a first device metal ring group 121 is arranged on the periphery of the second metal layer 11, a second device metal ring group 122, a third device metal ring group 123 and a fourth device metal ring group 124 are arranged in the dielectric layer 13, a fifth device metal ring group 125 is arranged on the periphery of the first metal layer 15, the first device metal ring group 121, the second device metal ring group 122, the third device metal ring group 123, the fourth device metal ring group 124 and the fifth device metal ring group 125 are connected to ground through a metal through hole 16, in this embodiment, each device metal ring group includes a metal ring. The orthographic projections of the metal rings in two adjacent device metal ring groups on the substrate overlap, and the overlapping parts of the two adjacent device metal ring groups are connected through a vertically arranged metal through hole.

[0104] In the embodiment of the present application, there is a first distance between the first metal layer 15 and the second metal layer 11; there is a second distance between the device metal ring group 121 arranged at the periphery of the second metal layer 11 and the second metal layer 11, and the second distance is greater than or equal to the first distance.

[0105] According to the above technical means, setting the second spacing to be greater than or equal to the first spacing can prevent the capacitor between the second metal layer and the device metal ring group arranged outside the second metal layer from being broken down in advance.

[0106] In the embodiment of the present application, the orthographic projections of the first metal layer 15 and the second metal layer 11 on the substrate 14 are rounded rectangles. The first metal layer and the second metal layer are set to be rounded rectangles, which can effectively reduce tip discharge.

[0107] In the embodiment of the present application, the material of the dielectric layer 23 is silicon dioxide, polyimide, silicon nitride, silicon oxynitride or a high-K material.

[0108] According to the above technical means, the dielectric layer prepared using the above material can enable the isolated capacitor device to achieve a wider operating temperature range and a longer service life.

[0109] Embodiment 4

[0110] like Figure 8As shown, this embodiment provides an isolated capacitor device 100, which includes a substrate 14, a first metal layer 15, a dielectric layer 13, a buffer layer 17 and a second metal layer 11. The buffer layer 17 is arranged between the dielectric layer 13 and the second metal layer 11. A first device metal ring group 121 is arranged on the periphery of the second metal layer 11, and a second device metal ring group 122 and a third device metal ring group 123 are arranged in the dielectric layer 13. A fourth device metal ring group 124 is arranged on the periphery of the first metal layer 15. The first device metal ring group 121, the second device metal ring group 122, the third device metal ring group 123 and the fourth device metal ring group 124 are connected to the ground through a metal through hole 16. In this embodiment, each device metal ring group includes two metal rings, and the metal rings in the same metal ring group are concentric rings and connected by metal wires, so that the shielding effect can be enhanced. Take the first device metal ring group 121 as an example for explanation. Figure 8 As shown, the first device metal ring group 121 includes two metal rings 1211, and the two metal rings 1211 are connected by a metal wire 1212. The orthographic projection of the metal ring closest to the second metal layer 11 in the first device metal ring group 121 overlaps with the orthographic projection of the metal ring farthest from the second metal layer in the second device metal ring group 122 on the substrate, and the overlapping part is connected by a vertically arranged metal through hole. By analogy, the second device metal ring group 122 and the third metal ring group 123, and the third metal ring group 123 and the fourth metal ring group 124 are connected by vertically arranged metal through holes.

[0111] In the embodiment of the present application, there is a first distance between the first metal layer 15 and the second metal layer 11; there is a second distance between the device metal ring group arranged on the periphery of the second metal layer 15 and the second metal layer, and the second distance is greater than or equal to the first distance.

[0112] According to the above technical means, setting the second spacing to be greater than or equal to the first spacing can prevent the capacitor between the second metal layer and the device metal ring group arranged outside the second metal layer from being broken down in advance.

[0113] In the embodiment of the present application, the orthographic projections of the first metal layer 15 and the second metal layer 11 on the substrate 14 are circular. The first metal layer and the second metal layer are set to be circular, and the outer periphery of the circle is smooth without a tip, which can effectively suppress tip discharge.

[0114] In the embodiment of the present application, the material of the buffer layer 17 is silicon nitride or silicon oxynitride. The silicon nitride buffer layer is used to minimize the polarity difference of the surge resistance of the dielectric layer, while increasing the barrier height, limiting charge injection and reducing the formation of space charge; the silicon oxynitride buffer layer can make the distribution of the breakdown voltage of the entire wafer very compact, eliminate the difference between regions, and perform well in resisting warpage.

[0115] In the embodiment of the present application, the material of the dielectric layer 14 is silicon dioxide, polyimide, silicon nitride, silicon oxynitride or a high-K material.

[0116] According to the above technical means, the dielectric layer prepared using the above material can enable the isolated capacitor device to achieve a wider operating temperature range and a longer service life.

[0117] Embodiment 5

[0118] like Fig. 9 As shown, the present embodiment provides an isolated capacitor device 100, which includes a substrate 14, a first metal layer 15, a dielectric layer 13, a buffer layer 17 and a second metal layer 11. The buffer layer 17 is arranged between the dielectric layer 13 and the second metal layer 11. A first device metal ring group 121 is arranged on the periphery of the second metal layer 11, and a second device metal ring group 122 and a third device metal ring group 123 are arranged in the dielectric layer. A fourth device metal ring group 124 is arranged on the periphery of the first metal layer 15. The first device metal ring group 121, the second device metal ring group 122, the third device metal ring group 123 and the fourth device metal ring group 124 are connected to ground through a metal through hole 16. In the present embodiment, the fourth device metal ring group 124 includes one metal ring, the third device metal ring group 123 includes two metal rings, the second device metal ring group 122 includes three metal rings, and the fourth device metal ring group 124 includes four metal rings. The number of metal rings in the device metal ring group increases from the first metal layer to the second metal layer. Fig. 9 As shown, the first device metal ring group 121 includes four metal rings 1211, and the four metal rings 1211 are connected by three metal wires 1212. The orthographic projection of the metal ring closest to the second metal layer 11 in the first device metal ring group 121 overlaps with the orthographic projection of the metal ring farthest from the second metal layer in the second device metal ring group 122 on the substrate, and the overlapping parts are connected by vertically arranged metal vias. By analogy, the second device metal ring group 122 and the third metal ring group 123, and the third metal ring group 123 and the fourth metal ring group 124 are connected by vertically arranged metal vias.

[0119] The metal rings in the same metal ring group are concentric rings and connected by metal wires. The number of metal rings is increased from the first metal layer to the second metal layer, and the shielding effect can be gradually enhanced to protect the second metal layer from external interference.

[0120] In the embodiment of the present application, there is a first distance between the first metal layer 15 and the second metal layer 11; there is a second distance between the device metal ring group 12 arranged on the periphery of the second metal layer 11 and the second metal layer 11, and the second distance is greater than or equal to the first distance.

[0121] According to the above technical means, setting the second spacing to be greater than or equal to the first spacing can prevent the capacitor between the second metal layer and the device metal ring group arranged outside the second metal layer from being broken down in advance.

[0122] In the embodiment of the present application, the orthographic projections of the first metal layer 15 and the second metal layer 11 on the substrate 14 are circular. The first metal layer and the second metal layer are set to be circular, and the outer periphery of the circle is smooth without a tip, which can effectively suppress tip discharge.

[0123] In the embodiment of the present application, the material of the buffer layer 17 is silicon nitride or silicon oxynitride. The silicon nitride buffer layer is used to minimize the polarity difference of the surge resistance of the dielectric layer, while increasing the barrier height, limiting charge injection and reducing the formation of space charge; the silicon oxynitride buffer layer can make the distribution of the breakdown voltage of the entire wafer very compact, eliminate the difference between regions, and perform well in resisting warpage.

[0124] In the embodiment of the present application, the material of the dielectric layer 14 is silicon dioxide, polyimide, silicon nitride, silicon oxynitride or a high-K material.

[0125] According to the above technical means, the dielectric layer prepared using the above material can enable the isolated capacitor device to achieve a wider operating temperature range and a longer service life.

[0126] In some other embodiments, the dielectric layer is formed by alternately stacking silicon dioxide, polyimide, silicon nitride, silicon oxynitride or high-K materials.

[0127] Embodiment 6

[0128] like Fig.10As shown, the present embodiment provides an isolated capacitor device 100, the isolated capacitor device 100 includes a substrate 14, a first metal layer 15, a dielectric layer 13, a buffer layer 17 and a second metal layer 11, the buffer layer 17 is arranged between the dielectric layer 13 and the second metal layer 11, a first device metal ring group 121 is arranged on the periphery of the second metal layer 11, a second device metal ring group 122 and a third device metal ring group 123 are arranged in the dielectric layer, a fourth device metal ring group 124 is arranged on the periphery of the first metal layer 15, the first device metal ring group 121, the second device metal ring group 122, the third device metal ring group 123 and the fourth device metal ring group 124 are connected to ground through metal through holes 16. In the present embodiment, each device metal ring group includes two metal rings, the metal rings in the same metal ring group are concentric rings, and the metal rings in the same circle layer in different metal ring groups are connected to ground through metal through holes to form a multi-layer Faraday cage to isolate and shield the isolated capacitor device from external interference. In an embodiment of the present application, the metal ring with the smallest distance from the first metal layer in different metal ring groups belongs to the same circle layer, the metal ring with the second smallest distance from the first metal layer in different metal ring groups belongs to the same circle layer, and so on. Therefore, in an embodiment of the present application, the device metal ring group including two metal rings has two circle layers, and the metal rings in each circle layer are connected through metal through holes and then grounded, and finally form two layers of Faraday cages to isolate and shield the isolated capacitor device from external interference. The multi-layer Faraday cage shields the isolated capacitor device to further improve the shielding effect.

[0129] In the embodiment of the present application, there is a first distance between the first metal layer 15 and the second metal layer 11; there is a second distance between the device metal ring group 12 arranged on the periphery of the second metal layer 11 and the second metal layer 11, and the second distance is greater than or equal to the first distance.

[0130] According to the above technical means, setting the second spacing to be greater than or equal to the first spacing can prevent the capacitor between the second metal layer and the device metal ring group arranged outside the second metal layer from being broken down in advance.

[0131] In the embodiment of the present application, the orthographic projections of the first metal layer 15 and the second metal layer 11 on the substrate 14 are circular. The first metal layer and the second metal layer are set to be circular, and the outer periphery of the circle is smooth without a tip, which can effectively suppress tip discharge.

[0132] In the embodiment of the present application, the material of the buffer layer 17 is silicon nitride or silicon oxynitride. The silicon nitride buffer layer is used to minimize the polarity difference of the surge resistance of the dielectric layer, while increasing the barrier height, limiting charge injection and reducing the formation of space charge; the silicon oxynitride buffer layer can make the distribution of the breakdown voltage of the entire wafer very compact, eliminate the difference between regions, and perform well in resisting warpage.

[0133] In the embodiment of the present application, the material of the dielectric layer 14 is silicon dioxide, polyimide, silicon nitride, silicon oxynitride or a high-K material.

[0134] According to the above technical means, the dielectric layer prepared using the above material can enable the isolated capacitor device to achieve a wider operating temperature range and a longer service life.

[0135] In some other embodiments, the dielectric layer is formed by alternately stacking silicon dioxide, polyimide, silicon nitride, silicon oxynitride or high-K materials.

[0136] The second aspect of the present application provides a multi-channel isolation chip, such as Fig.11 As shown, the multi-channel isolation chip includes:

[0137] A plurality of said isolation capacitor devices;

[0138] At least two chip metal ring groups are provided, and the chip metal ring groups are connected through through holes and then grounded to form a Faraday cage to isolate and shield the plurality of isolated capacitor devices from external interference.

[0139] According to the above technical means, the isolation chip has multiple isolation channels, and the isolation capacitor device of each channel is separately provided with a device metal ring group for interference isolation. The channels do not interfere with each other. The entire chip is provided with a chip metal ring group to protect the entire chip from external interference.

[0140] like Fig.12 As shown, in another embodiment, the multi-channel isolation chip further includes:

[0141] a plurality of first capacitive devices, wherein the first capacitive devices and the isolation capacitive devices are arranged at intervals, and any two first capacitive devices are not adjacent to each other;

[0142] The first capacitive device includes a first metal layer, a dielectric layer and a second metal layer.

[0143] According to the above technical means, a first capacitor device that does not include a device metal ring group is set in a multi-channel isolation chip, the first capacitor device and the isolation capacitor device are isolated and set, the device metal ring group of the isolation capacitor device is used to achieve interference isolation between each channel, and then the chip metal ring group set in the entire chip is used to achieve interference isolation between the first capacitor device and the isolation chip, which can further reduce the size of the isolation chip.

[0144] A third aspect of the present application provides a method for preparing an isolated capacitor device, the method being used to prepare the isolated capacitor device, the method comprising:

[0145] The first metal layer is formed on the substrate, which specifically includes: growing a medium on the substrate by using a PECVD process, and then growing a metal by using a sputtering process to form the first metal layer as the lower electrode. In some embodiments, the first metal layer is made of metal aluminum AL.

[0146] A dielectric layer is formed on the first metal layer; wherein at least one metal ring is provided in the dielectric layer. In some embodiments, a deposition process is first used to form a first dielectric layer SIO2, or Polyimide, SiN, SiON, high K, or alternate deposition between the first metal layer and the second metal, and then an etching process is used to etch through holes, and the through holes are filled with tungsten to form metal through holes; then, metal rings are grown, and the metal rings are interconnected with the metal through holes, and the metal rings in the same device metal ring group are prepared simultaneously. For an isolated capacitor device with multiple device metal ring groups, the above steps are repeated to form a device metal ring group that is interconnected by metal.

[0147] A second metal layer and a device metal ring group on the same layer are formed on the dielectric layer; wherein the potential of the second metal layer is higher than the potential of the first metal layer; and the orthographic projection of the center of the second metal layer on the substrate coincides with the orthographic projection of the center of the first metal layer on the substrate;

[0148] A metal through hole and at least two device metal ring groups are formed, wherein the spacing between the orthographic projections of the at least two device metal ring groups on the substrate and the first metal layer increases from the first metal layer to the second metal layer, and the device metal ring groups are connected through the metal through hole and then grounded to form a Faraday cage to isolate and shield the first metal layer and the second metal layer from external interference.

[0149] According to the above technical means, the prepared isolation capacitor device is provided with at least two device metal ring groups, each device metal ring group is connected to the ground through a metal through hole, each metal ring group is at zero potential, and can form a Faraday cage to isolate and shield the first metal layer and the second metal layer from external interference, so as to enhance the isolation capacitor device's ability to resist magnetic field interference.

[0150] In the embodiment of the present application, the dielectric layer is composed of multiple layers of dielectrics;

[0151] Metal through holes and device metal ring groups are alternately formed in different layers of dielectrics to ensure that at least one device metal ring group is disposed in the dielectric layer;

[0152] A device metal ring group is formed on the dielectric layer to ensure that a device metal ring group is arranged on the periphery of the second metal layer.

[0153] According to the above technical means, there is a device metal ring group flush with the second metal layer. The device metal ring group can be made in the same layer as the second metal layer, saving the process flow. The formed Faraday cage can isolate and shield the second metal layer from external interference.

[0154] In other embodiments, after forming the dielectric layer, a buffer layer is formed on the dielectric layer, and an etching process is used to etch through holes in the buffer layer, and the through holes are filled with tungsten to connect the device metal ring group arranged on the periphery of the second metal layer and the device metal ring group arranged in the dielectric layer.

[0155] A fourth aspect of the present application provides a wafer, which includes the isolation capacitor device described above, or includes the multi-channel isolation chip described above.

[0156] Those skilled in the art will understand that all or part of the steps in the method for implementing the above-mentioned embodiments can be completed by instructing the relevant hardware through a program, and the program is stored in a storage medium, including several instructions for making a single-chip microcomputer, a chip or a processor execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0157] The optional embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the technical concept of the embodiments of the present invention, the technical scheme of the embodiments of the present invention can be subjected to a variety of simple modifications, and these simple modifications all belong to the protection scope of the embodiments of the present invention. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the embodiments of the present invention will not further describe various possible combinations.

[0158] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the embodiments of the present invention, they should also be regarded as the contents disclosed in the embodiments of the present invention.

Claims

1. An isolated capacitor device, comprising a substrate, characterized in that: The isolation capacitor device also includes: A first metal layer is disposed on the substrate; A dielectric layer, disposed on a side of the first metal layer away from the substrate; A second metal layer is disposed on a side of the dielectric layer away from the first metal layer; an orthographic projection of the center of the second metal layer on the substrate coincides with an orthographic projection of the center of the first metal layer on the substrate, and a potential of the second metal layer is higher than a potential of the first metal layer; At least two device metal ring groups, the spacing between the orthographic projections of the at least two device metal ring groups on the substrate and the first metal layer increases from the first metal layer to the second metal layer, and the device metal ring groups are connected through metal through holes and then grounded to form a Faraday cage to isolate and shield the isolated capacitor device from external interference; The device metal ring group includes at least one metal ring, and the metal rings in the same metal ring group are concentric rings and connected by metal wires; The number of metal rings in the device metal ring group increases from the first metal layer to the second metal layer, one device metal ring group at a time; The orthographic projections of the first metal layer and the second metal layer on the substrate are circular or rounded rectangles; The isolation capacitor device further includes: a buffer layer disposed between the dielectric layer and the second metal layer; The material of the buffer layer is silicon nitride or silicon oxynitride; There is a first distance between the first metal layer and the second metal layer; there is a second distance between the device metal ring group arranged at the periphery of the second metal layer and the second metal layer, and the second distance is greater than or equal to the first distance.

2. The isolation capacitor device according to claim 1, characterized in that: The device metal ring group includes a device metal ring group arranged at the periphery of the second metal layer and at least one device metal ring group arranged in the dielectric layer.

3. The isolated capacitor device according to claim 1, characterized in that: The device metal ring group includes a device metal ring group arranged at the periphery of the second metal layer and a device metal ring group arranged at the periphery of the first metal layer.

4. The isolated capacitor device according to claim 3, characterized in that: The device metal ring group also includes at least one device metal ring group arranged in the dielectric layer.

5. The isolated capacitor device according to claim 1, characterized in that: The metal rings in the same circle layer in different metal ring groups are connected through metal through holes and then grounded to form a multi-layer Faraday cage to isolate and shield the isolated capacitor device from external interference.

6. The isolated capacitor device according to claim 1, characterized in that: The material of the dielectric layer is silicon dioxide, polyimide or high-K material.

7. The isolated capacitor device according to claim 1, characterized in that: The dielectric layer is formed by alternately stacking silicon dioxide, polyimide or high-K material.

8. A multi-channel isolation chip, characterized in that: The multi-channel isolation chip comprises: A plurality of isolated capacitor devices as claimed in any one of claims 1 to 7; At least two chip metal ring groups are provided, and the chip metal ring groups are connected through through holes and then grounded to form a Faraday cage to isolate and shield the plurality of isolated capacitor devices from external interference.

9. The multi-channel isolation chip according to claim 8, characterized in that: The multi-channel isolation chip also includes: a plurality of first capacitive devices, wherein the first capacitive devices and the isolation capacitive devices are arranged at intervals, and any two first capacitive devices are not adjacent to each other; The first capacitive device includes a first metal layer, a dielectric layer and a second metal layer.

10. A method for preparing an isolated capacitor device, characterized in that: The method is used to prepare the isolated capacitor device according to claim 2, and the method comprises: forming a first metal layer on a substrate; forming a dielectric layer on the first metal layer; wherein at least one metal ring is provided in the dielectric layer; forming a second metal layer on the dielectric layer; wherein the potential of the second metal layer is higher than the potential of the first metal layer; and the orthographic projection of the center of the second metal layer on the substrate coincides with the orthographic projection of the center of the first metal layer on the substrate; A metal through hole and at least two device metal ring groups are formed, wherein the spacing between the orthographic projections of the at least two device metal ring groups on the substrate and the first metal layer increases from the first metal layer to the second metal layer, and the device metal ring groups are connected through the metal through hole and then grounded to form a Faraday cage to isolate and shield the first metal layer and the second metal layer from external interference.

11. The method for preparing an isolated capacitor device according to claim 10, characterized in that: The dielectric layer is composed of multiple layers of dielectrics; Metal through holes and device metal ring groups are alternately formed in different layers of dielectrics to ensure that at least one device metal ring group is disposed in the dielectric layer; A device metal ring group is formed on the dielectric layer to ensure that a device metal ring group is arranged on the periphery of the second metal layer.

12. A wafer, characterized in that: The wafer includes the isolation capacitor device according to any one of claims 1 to 7, or includes the multi-channel isolation chip according to any one of claims 8 to 9.

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