Analog domain signal normalization method and device for sensing, storage and computing fusion processing scenarios

Abstract

This application relates to the field of sensor signal processing, and specifically to a method for normalizing analog domain signals in a sensing, storage, and computing fusion processing scenario, comprising: sampling and acquiring an analog domain signal; acquiring the mean and standard deviation of the analog domain signal; calculating a first difference between the analog domain signal and the mean of the analog domain signal; and dividing the first difference by the standard deviation of the analog domain signal to obtain a normalized value of the analog domain signal. This application provides hardware for implementing simple analog domain signal normalization, providing a normalization operator for implementing sensor-side data compression in the analog domain, thereby reducing the computational pressure of the analog-to-digital converter (ADC).

Description

Technical Field

[0001] The present application relates to the field of sensor signal processing, and in particular to an analog domain signal normalization method and an analog domain signal normalization device for a sensing-storage-computing fusion processing scenario. Background Art

[0002] Currently, in sensors, analog sensor signals are typically converted to digital signals via an analog-to-digital converter (ADC) before being normalized. This requires a large number of ADCs and digital processing units. Due to the fundamental separation of computation and storage in the traditional von Neumann architecture, storage and power consumption become key bottlenecks in computer architecture, particularly in neural network computing. The integrated sensing, storage, and computing architecture offers an effective solution to this dilemma. Its deep integration of sensing, computing, and storage significantly reduces data transfer overhead, making it a hot topic of research in academia and industry. A typical integrated sensing, storage, and computing architecture processes and compresses analog signals at the sensor end in the analog domain before converting them to digital signals for further processing. This approach reduces the overhead of analog-to-digital conversion (including power consumption and area). However, analog domain compression typically requires normalization of the analog signal to improve neural network performance. However, existing technologies lack feasible methods for normalizing analog signals. Summary of the Invention

[0003] In order to solve the lack of a method for normalizing analog domain signals, the present application provides an analog domain signal normalization method for a sensing-storage-computing fusion processing scenario and an analog domain signal normalization device for a sensing-storage-computing fusion processing scenario.

[0004] This application provides a method for normalizing analog domain signals in a sensing, storage, and computing fusion processing scenario, which adopts the following technical solutions:

[0005] In the first aspect, a method for normalizing analog domain signals in a sensing-storage-computing fusion processing scenario is provided, which is applied to sensor signal processing and includes:

[0006] Sampling to obtain analog domain signals;

[0007] Sampling to obtain the mean and standard deviation of the analog domain signal;

[0008] Obtaining a first difference value by using a difference between the analog domain signal and a mean value of the analog domain signal;

[0009] The first difference is divided by the standard deviation of the analog domain signal to obtain a normalized value of the analog domain signal.

[0010] Optionally, the analog domain signal is a voltage signal.

[0011] Optionally, the sampling to obtain the analog domain signal includes: sampling the voltage signal once or twice.

[0012] Optionally, after sampling the voltage signal twice, the method further includes:

[0013] Calculating the difference between the first sampling voltage and the second sampling voltage obtained by the two samplings to obtain a second difference;

[0014] A normalized value of the voltage signal is obtained by subtracting the mean value of the voltage signal from the second difference and dividing the result by the standard deviation of the voltage signal.

[0015] Secondly, an analog domain signal normalization device for a sensing, storage, and computing fusion processing scenario is also provided, which is applied to sensor signal processing and includes:

[0016] A first sampling unit is configured to sample and obtain an analog domain signal, and to sample and obtain a mean value and a standard deviation of the analog domain signal; the analog domain signal is a voltage signal;

[0017] The calculation unit is configured to obtain a first difference value by using the difference between the analog domain signal and the mean value of the analog domain signal; and to obtain a normalized value of the analog domain signal by dividing the first difference value by the standard deviation of the analog domain signal.

[0018] Optionally, the first sampling unit includes:

[0019] The first switch SW1 is used to sample the voltage signal and send it to the calculation unit;

[0020] The second switch SW2 is used to sample the dark current information of the voltage signal and send it to the calculation unit;

[0021] The third switch SW3 is used to sample the mean value of the voltage signal and send it to the calculation unit;

[0022] The second reference voltage switch SWN2 is used to send the reference voltage VREF to the calculation unit when the second switch SW2 is disconnected;

[0023] The third reference voltage switch SWN3 is used to send the reference voltage VREF to the calculation unit when the third switch SW3 is disconnected.

[0024] Optionally, the computing unit includes:

[0025] The fourth switch SW4 is used to send the reference voltage VREF to the right plate of the fourth capacitor C4;

[0026] The fifth switch SW5 is used to connect the inverting input terminal of the operational amplifier unit AMP and the output terminal of the operational amplifier unit AMP, and its closed and closed states are consistent with those of the fourth switch SW4;

[0027] The sixth switch SW6 is used to connect the fourth capacitor C4 between the inverting input terminal and the output terminal of the operational amplifier unit AMP when the fourth switch SW4 is disconnected, thereby forming a feedback loop.

[0028] First capacitor C1: used to receive the sampling voltage signal sent by the first switch SW1;

[0029] The second capacitor C2 is used to receive the dark current information of the sampling voltage signal sent by the second switch SW2, or receive the reference voltage VREF sent by the second reference voltage switch SWN2;

[0030] The third capacitor C3 is used to receive the average value of the sampled voltage signal sent by the third switch SW3, or receive the reference voltage VREF sent by the third reference voltage switch SWN3;

[0031] Fourth capacitor C4: used to receive the reference voltage VREF input by the fourth switch SW4, or connected to the output terminal of the operational amplifier unit AMP to form a feedback loop between the inverting input terminal and the output terminal of the operational amplifier AMP;

[0032] Operational amplifier unit AMP: used to input reference voltage VREF at the non-inverting input terminal, and connect the first capacitor C1, the second capacitor C2, the right plate of the third capacitor C3, and the left plate of the fourth capacitor C4 at the inverting input terminal.

[0033] In summary, this application includes at least one of the following beneficial technical effects:

[0034] 1. Implemented hardware for simple analog domain signal normalization;

[0035] 2. Provide a normalization operator for sensor-side data compression in the analog domain, thereby reducing the computational pressure (including power consumption, speed, and area) of the analog-to-digital converter (ADC). BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 The present invention is a first embodiment of a method for normalizing analog domain signals in a sensing, storage and computing fusion processing scenario;

[0037] Figure 2 The present invention is a second embodiment of a method for normalizing analog domain signals in a sensing, storage and computing fusion processing scenario;

[0038] Figure 3 The present invention is a first embodiment of an analog domain signal normalization device for a sensing, storage and computing fusion processing scenario;

[0039] Figure 4 The present invention is a second embodiment of an analog domain signal normalization device for a sensing, storage, and computing fusion processing scenario.

[0040] Explanation of the accompanying symbols: 1. An analog domain signal normalization device for a sensing, storage, and computing fusion processing scenario; 101. Sampling unit; 102. Computing unit. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of this application more clear, the following Figure 1 -Attached Figure 4 It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0042] Explanation of terms:

[0043] Standard Deviation: (Standard Deviation), standard deviation can reflect the degree of dispersion of a data set. Two sets of data with the same mean may not have the same standard deviation. Standard deviation plays an important role in Batch Normalization. The standard deviation is the square root of the arithmetic mean of the squared deviations from the mean, and is used to reflect the degree of dispersion of the data set. In Batch Normalization, the standard deviation is used to calculate the distribution of each batch of data for normalization. Specifically, BatchNorm estimates the mean and standard deviation of each batch of data, and then normalizes the data so that it obeys the standard normal distribution (mean is 0, standard deviation is 1). Standard deviation plays a key role in Batch Normalization. It helps BatchNorm understand the distribution of the data, thereby performing effective normalization and improving the training efficiency and performance of the neural network.

[0044] Dark current refers to the phenomenon in physical devices whereby a pixel generates an electric charge even when no light is shining on it. This charge forms the so-called dark current, a type of noise that affects CMOS sensor image quality. The generation of dark current is related to various factors, such as impurities and heat.

[0045] This application provides a method for normalizing analog domain signals in a sensing, storage, and computing fusion processing scenario, which adopts the following technical solutions:

[0046] First, as Figure 1 As shown, a method for normalizing analog domain signals in a sensing-storage-computing fusion processing scenario is provided, including:

[0047] S101: Sampling to obtain an analog domain signal; generally, the analog domain signal is a time-continuous signal;

[0048] S201: Sampling and obtaining the mean and standard deviation of the analog domain signal. The mean and standard deviation of the analog domain signal are known in advance. For example, in the field of CMOS image sensors, the mean and standard deviation of the image signal are obtained in advance based on an existing data set during the neural network algorithm training process. The mean and standard deviation are sampled.

[0049] S301: Obtain a first difference value by using a difference between the analog domain signal and a mean value of the analog domain signal;

[0050] S401: Divide the first difference by the standard deviation of the analog domain signal to obtain a normalized value of the analog domain signal. In this technical solution, the normalized value of the analog domain signal is obtained by dividing the difference between the sampled analog domain signal and the mean of the stored analog domain signal by the standard deviation of the stored analog domain signal. This technical solution normalizes the analog domain signal at the analog domain signal stage; in the prior art, the analog domain signal is first converted to a digital signal via an analog-to-digital converter (ADC), and then the digital signal is processed to obtain the normalized value of the digital signal. This technical solution achieves normalization of the analog domain signal at the analog domain signal stage, significantly reducing the processing overhead after converting the analog domain signal to a digital signal and reducing the computational pressure (including power consumption, speed, and area) of the analog-to-digital converter (ADC); this overhead includes the power consumption and area of ​​the digital signal processor. In particular, the basic characteristic of the traditional von Neumann architecture, that is, the separation of computation and storage, creates a storage barrier and a power consumption barrier, which become key bottlenecks in computer architecture, especially in neural network computing. The implementation of this technical solution significantly reduces the overhead required for data transfer, facilitating the deployment of neural networks on integrated "sensing, storage, and computing" chips. The so-called "sensing, storage, and computing" refers to sensing, storing, and computing signals.

[0051] Optionally, the analog domain signal is a voltage signal. Analog domain signals include various types of signals that can be processed by electronic devices, including voltage signals and current signals. In this technical solution, the voltage signal can be processed.

[0052] Optionally, sampling to obtain an analog domain signal includes sampling the voltage signal once or twice. In this technical solution, the voltage signal can be sampled once or twice. In the field of image sensors, sampling once can also be used to process the perceived image signal and normalize it.

[0053] Optional, such as Figure 2 As shown, when the voltage signal is sampled twice, it also includes:

[0054] S202: Calculating the difference between the first sampled voltage and the second sampled voltage obtained from the two samplings to obtain a second difference. In this technical solution, particularly in CMOS image sensors, excessive noise, such as dark current noise, may occur due to the single sampling. Using the twice-sampled voltage signals and performing subsequent processing can completely eliminate the dark current noise.

[0055] S203: Subtracting the mean value of the voltage signal from the second difference value and dividing the result by the standard deviation of the voltage signal to obtain a normalized value of the voltage signal.

[0056] Second, as Figure 3 As shown, an analog domain signal normalization device 1 for a sensing, storage, and computing fusion processing scenario is also provided, comprising:

[0057] Sampling unit 101: used for sampling and acquiring an analog domain signal, and sampling and acquiring a mean value and a standard deviation of the analog domain signal; the analog domain signal is a voltage signal;

[0058] The calculation unit 102 is configured to obtain a first difference value by using the difference between the analog domain signal and the mean value of the analog domain signal; and divide the first difference value by the standard deviation of the analog domain signal to obtain a normalized value of the analog domain signal.

[0059] Optional, such as Figure 4 As shown, the first sampling unit 101 includes:

[0060] The first switch SW1 is used to sample the voltage signal and send it to the calculation unit;

[0061] The second switch SW2 is used to sample the dark current information of the voltage signal and send it to the calculation unit;

[0062] The third switch SW3 is used to sample the mean value of the voltage signal and send it to the calculation unit;

[0063] The second reference voltage switch SWN2 is used to send the reference voltage VREF to the calculation unit when the second switch SW2 is disconnected;

[0064] The third reference voltage switch SWN3 is used to send the reference voltage VREF to the calculation unit when the third switch SW3 is disconnected.

[0065] Optional, such as Figure 4 As shown, the calculation unit 102 includes:

[0066] The fourth switch SW4 is used to send the reference voltage VREF to the right plate of the fourth capacitor C4;

[0067] The fifth switch SW5 is used to connect the inverting input terminal of the operational amplifier unit AMP and the output terminal of the operational amplifier unit AMP, and its closed and closed states are consistent with those of the fourth switch SW4;

[0068] The sixth switch SW6 is used to connect the fourth capacitor C4 between the inverting input terminal and the output terminal of the operational amplifier unit AMP to form a feedback loop when the fourth switch SW4 is disconnected; and is also used to connect the variable capacitor C4 into the feedback loop.

[0069] First capacitor C1: used to receive the sampling voltage signal sent by the first switch SW1;

[0070] The second capacitor C2 is used to receive the dark current information of the sampling voltage signal sent by the second switch SW2, or receive the reference voltage VREF sent by the second reference voltage switch SWN2;

[0071] The third capacitor C3 is used to receive the average value of the sampled voltage signal sent by the third switch SW3, or receive the reference voltage VREF sent by the third reference voltage switch SWN3;

[0072] Fourth capacitor C4: used to receive the reference voltage VREF input by the fourth switch SW4, or connected to the output terminal of the operational amplifier unit AMP to form a feedback loop between the inverting input terminal and the output terminal of the operational amplifier AMP;

[0073] Operational amplifier unit AMP: used to input reference voltage VREF at the non-inverting input terminal, and connect the first capacitor C1, the second capacitor C2, the right plate of the third capacitor C3, and the left plate of the fourth capacitor C4 at the inverting input terminal.

[0074] In summary, this application includes at least one of the following beneficial technical effects:

[0075] 1. Implemented hardware for simple analog domain signal normalization;

[0076] 2. Provide a normalization operator for achieving sensor-side data compression in the analog domain, thereby reducing the computational pressure (including power consumption, speed, and area) of the analog-to-digital converter (ADC). The implementation principle of the analog domain signal normalization method and device of the embodiment of the present application is as follows:

[0077] like Figure 4As shown, when sampling once, a normalized voltage value can be obtained. The working process is as follows: First, the fourth switch SW4 and the fifth switch SW5 are closed, and the sixth switch SW6 is opened. Then, the voltage connected to the right plate of the fourth capacitor C4 is the reference voltage VREF. Since the ideal model of the operational amplifier unit AMP is a virtual short state, that is, the voltages of the inverting input terminal and the non-inverting input terminal are equal, the potential of the inverting input terminal of the operational amplifier unit AMP and the right plate of the fourth capacitor C4 is the reference voltage VREF.

[0078] When the first switch SW1 is closed, the sampling terminal VPIXEL_IN is connected to the left plate of the first capacitor C1 to obtain the first sampling signal VPIXEL_IN; the first reference voltage switch SWN1, which is complementary to the first switch SW1, is disconnected; the second switch SW2 and the third switch SW3 are disconnected, and the second reference voltage switch SWN2 and the third reference voltage switch SWN3, which are complementary to the second switch SW2 and the third switch SW3, respectively, are closed, so that the left plates of the second capacitor C2 and the third capacitor C3 are connected to the reference voltage VREF.

[0079] At this point, the charge accumulated on the first capacitor C1 is C1*(VPIXEL_IN-VREF), and the charge accumulated on the second and third capacitors C2 and C3 is zero. Therefore, the total charge on the right plates of the first, second, and third capacitors C1, C2, and C3, and the left plate of the fourth capacitor C4 is C1*(VPIXEL_IN-VREF).

[0080] Next, the first switch SW1 is opened, while the first reference voltage switch SWN1 is closed, the second switch SW2 and the third switch SW3 are closed, and the second reference voltage switches SWN2 and SWN3, which are complementary to the second and third switches SW2 and SW3, are opened. The dark current information DARK_IN is input to the left plate of the second capacitor C2, and the mean voltage signal NORM_IN is input to the left plate of the third capacitor C3. At this point, the charge accumulated on C1 becomes zero, and the charge accumulated on C2 is C2*(VDARK_IN-VREF), where VDARK_IN = VDARK, i.e., the input voltage at the VDARK_IN pin is VDARK. The charge accumulated on C3 is C3*(VNORM_IN-VREF), where VNORM_IN = VNORM+VREF, i.e., the input voltage at the VNORM_IN pin is VNORRM+VREF. At this point, the total charge on the right plates of capacitors C1, C2, and C3 is C2*(VDARK-VREF)+C3*(VNORM+VREF-VREF), and the charge on the left plate of capacitor C4 is C4*(V_OUT-VREF). Therefore, the total charge is C2*(VDARK-VREF)+C3*VNORM+C4*(V_OUT-VREF).

[0081] Since the right plate of the first capacitor C1, the right plate of the second capacitor C2, the right plate of the third capacitor C3, and the left plate of the fourth capacitor C4 constitute a closed system, the closed system follows the principle of conservation of charge. Therefore, the following charge conservation formula exists:

[0082] C1*(VPIXEL_IN-VREF)=C2*(VDARK-VREF)+C3*VNORM+C4*(V_OUT-VREF)

[0083] The above formula follows the principle of Q=CU, where Q is the charge, C is the capacitance of the capacitor, and U is the voltage between the two plates of the capacitor. The left side of the above charge conservation formula represents the total charge in the above closed system when the first switch SW1 is closed, the fourth switch SW4 and the fifth switch SW5 are closed, the sixth switch SW6 is open, and the right plate of the fourth capacitor C4 is connected to the reference voltage VREF. The right side of the above charge conservation formula represents the total charge in the above closed system after the second switch SW2 and the third switch SW3 are closed. Obviously, since it is a closed system, the charge on both sides is equal. VREF can be zero or a reference value.

[0084] Furthermore, the capacitance values ​​of the first capacitor C1, the second capacitor C2, and the third capacitor C3 can be set to be equal, and the normalized value of the analog voltage signal can be calculated as:

[0085] V_OUT=Cunit / C4*(VPIXEL_IN-VDARK-VNORM)+VREF

[0086] Where C1 = C2 = C3 = Cunit, VDARK is the dark current information, and VNORM is the mean value of the voltage signal. The fourth capacitor C4 can be a variable capacitor array. Changing the value of the variable capacitor can adjust the value of Cunit / C4. That is, the capacitance ratio of the first capacitor C1, the second capacitor C2, or the third capacitor C3 to the variable capacitor array represents the normalized standard deviation. V_OUT is the normalized voltage value.

[0087] Because this application is primarily used in the field of CMOS image sensors, the sampled voltage signal is typically sampled twice. This double sampling is done to eliminate noise in the CMOS image sensor, such as dark current noise. To achieve this, after the first sampling, the first switch SW1 is closed again, and the first reference voltage switch SWN1, which is complementary to the first switch SW1, is opened. The fourth and fifth switches SW4 and SW5 are opened, and the sixth switch SW6 is closed. The sampling terminal VPIXEL_IN receives the second sampling signal VPIXEL_IN2, which is then connected to the left plate of the first capacitor C1.

[0088] According to the principle of charge conservation, the following charge conservation formula can be obtained:

[0089] C1*(VPIXEL_IN1-VREF)=C1*(VPIXEL_IN2-VREF)+C2*(VDARK_IN-VREF)+C3*(VNORM_IN-VREF)+C4*(V_OUT-VREF)

[0090] Among them, C1=C2=C3=Cunit, VDARK_IN=VDARK+VREF, VNORM_IN=VNORM+VREF, VDARK is the dark current information, and VNORM is the mean value of the voltage signal. The fourth capacitor C4 can be a variable capacitor. If the value of the variable capacitor changes, the value of Cunit / C4 can be adjusted, that is, the capacitance ratio of the first capacitor C1, the second capacitor C2 or the third capacitor C3 and the variable capacitor array represents the normalized standard deviation. VPIXEL_IN1 is the sampled voltage obtained by the first sampling, and VPIXEL_IN2 is the sampled voltage obtained by the second sampling. V_OUT is the normalized voltage value.

[0091] Furthermore, the capacitance values ​​of the first capacitor C1, the second capacitor C2, and the third capacitor C3 can be set to be equal, and the normalized value of the analog voltage signal can be calculated as:

[0092] V_OUT=Cunit / C4*(VPIXEL_IN1-VPIXEL_IN2-VDARK-VNORM)+VREF

[0093] VREF can be 0 or some other reference value that is convenient for the calculation of the lower-level circuit (such as parameters near the threshold voltage Vth). CL is the load capacitance, which is the equivalent load capacitance of the next-level circuit.

[0094] The above are all preferred embodiments of the present application and are not intended to limit the scope of protection of this application. Unless otherwise stated, any feature disclosed in this specification (including the abstract and drawings) may be replaced by other equivalent or similar features. In other words, unless otherwise stated, each feature is merely an example of a series of equivalent or similar features.

Claims

1. An analog domain signal normalization device for sensor-storage-computing fusion processing scenarios, applied to sensor signal processing, characterized in that: include: A first sampling unit is configured to sample and obtain an analog domain signal, and sample and obtain a mean value and a standard deviation of the analog domain signal; The analog domain signal is a voltage signal; A calculation unit: configured to obtain a first difference value by using a difference between the analog domain signal and a mean value of the analog domain signal; Dividing the first difference by the standard deviation of the analog domain signal to obtain a normalized value of the analog domain signal; The computing unit comprises: The fourth switch SW4 is used to send the reference voltage VREF to the right plate of the fourth capacitor C4; The fifth switch SW5 is used to connect the inverting input terminal of the operational amplifier unit AMP and the output terminal of the operational amplifier unit AMP, and its closed and closed states are consistent with those of the fourth switch SW4; The sixth switch SW6 is used to connect the fourth capacitor C4 between the inverting input terminal and the output terminal of the operational amplifier unit AMP when the fourth switch SW4 is disconnected, thereby forming a feedback loop. First capacitor C1: used to receive the sampling voltage signal sent by the first switch SW1; The second capacitor C2 is used to receive the dark current information of the sampling voltage signal sent by the second switch SW2, or receive the reference voltage VREF sent by the second reference voltage switch SWN2; The third capacitor C3 is used to receive the average value of the sampled voltage signal sent by the third switch SW3, or receive the reference voltage VREF sent by the third reference voltage switch SWN3; Fourth capacitor C4: used to receive the reference voltage VREF input by the fourth switch SW4, or connected to the output terminal of the operational amplifier unit AMP to form a feedback loop between the inverting input terminal and the output terminal of the operational amplifier AMP; Operational amplifier unit AMP: used to input reference voltage VREF at the non-inverting input terminal, and connect the first capacitor C1, the second capacitor C2, the right plate of the third capacitor C3, and the left plate of the fourth capacitor C4 at the inverting input terminal.

2. The normalization device according to claim 1, characterized in that The first sampling unit includes: The first switch SW1 is used to sample the voltage signal and send it to the calculation unit; The second switch SW2 is used to sample the dark current information of the voltage signal and send it to the calculation unit; The third switch SW3 is used to sample the mean value of the voltage signal and send it to the calculation unit; The second reference voltage switch SWN2 is used to send the reference voltage VREF to the calculation unit when the second switch SW2 is disconnected; The third reference voltage switch SWN3 is used to send the reference voltage VREF to the calculation unit when the third switch SW3 is disconnected.

3. A method for analog domain signal normalization in a sensor-storage-computing fusion processing scenario, applied to sensor signal processing, characterized in that: Based on the normalization device of claim 1, the analog domain signal normalization method includes: Sampling to obtain analog domain signals; Sampling to obtain the mean and standard deviation of the analog domain signal; Obtaining a first difference value by using a difference between the analog domain signal and a mean value of the analog domain signal; The first difference is divided by the standard deviation of the analog domain signal to obtain a normalized value of the analog domain signal.

4. The normalization method according to claim 3, wherein: The analog domain signal is a voltage signal.

5. The normalization method according to claim 4, characterized in that: The sampling and acquiring of the analog domain signal includes: sampling the voltage signal once or twice.

6. The normalization method according to claim 5, characterized in that After sampling the voltage signal twice, the following steps are also included: Calculating the difference between the first sampling voltage and the second sampling voltage obtained by the two samplings to obtain a second difference; A normalized value of the voltage signal is obtained by subtracting the mean value of the voltage signal from the second difference and dividing the result by the standard deviation of the voltage signal.

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