A method, device and system for sending data in Ethernet

Abstract

Provided are a method, device and system for sending data, wherein a PMA sublayer of an Ethernet device obtains a data stream encoded by FEC, performs a first data processing process on the data stream to obtain an interleaved data stream, wherein the first data processing process includes interleaving through a first interleaving mode, and the interleaving type of the first interleaving mode is specifically symbol interleaving or convolution interleaving. Through the present application, the function of the PMA sublayer can be expanded to meet the technical problem of reducing the BER requirement in a high-speed Ethernet data transmission scenario.

Description

[0001] This application is a divisional application. The application number of the original application is 202310247349.4, and the original application date is March 3, 2023. The entire contents of the original application are incorporated into this application by reference.

[0002] This application claims priority to Chinese patent application No. 202310149106.7, filed on February 14, 2023, and entitled “A Method for Processing Ethernet Physical Layer Data”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of communications, and in particular to a method, device and system for sending data in an Ethernet. Background Art

[0004] In the process of Ethernet data transmission, due to various factors such as environmental interference and system errors, there will be inconsistencies between the data received by the data receiving end and the data sent by the data sending end, that is, bit errors are inevitable. Current methods such as forward error correction (FEC) and interleaver can reduce the bit error rate (BER).

[0005] However, when the data transmission rate is further increased, the existing physical coding sublayer (PCS) interleaving method will not be able to meet the demand. Summary of the invention

[0006] Provided are a method, device and system for sending data, which are used to solve the problem that technical means for reducing BER due to an increase in data transmission rate cannot meet the demand.

[0007] In the first aspect, a method for sending data is provided, which is performed by an Ethernet device. The Ethernet device can be an Ethernet chip, an Ethernet forwarding device such as a switch or a router, and a pluggable optical module or electrical module in an Ethernet, etc. When the Ethernet device is used as a data sending side, the physical medium attachment (PMA) sublayer of the Ethernet device obtains a data stream encoded by FEC, and performs a first data processing process on the data stream to obtain an interleaved data stream (interleaved data stream), wherein the first data processing process includes interleaving through a first interleaving method, and the interleaving type of the first interleaving method is specifically symbol interleaving (symbol interleave) or convolutional interleaving (convolutional interleave). Among them, the data stream obtained by the PMA sublayer can be one data stream or multiple data streams, and the number of the data streams is related to the number of data channels between the PMA sublayer and the upper sublayer, and further, interleaving can refer to interleaving within a data stream, or interleaving between multiple data streams. In addition, the interleaved data stream can also be one data stream or multiple data streams.

[0008] In the present application, the PMA sublayer on the data transmission side performs symbol interleaving or convolution interleaving on the data stream, and the specific method of performing interleaving by the PMA sublayer can be flexibly designed to ensure that the actual demand for reducing BER in the network is met. In addition, since the expansion of the PMA sublayer is relatively simple, the design of the PMA sublayer does not require changes to the existing PCS, and even when the PMA sublayer is located in a pluggable module, the design of the PMA sublayer does not require changes to the main chip of the existing Ethernet physical PHY layer, thereby meeting the demand for reducing BER in high-speed data transmission scenarios while minimizing research and development costs.

[0009] In a possible implementation, the PMA sublayer performs symbol interleaving at a granularity of 10 bits, or in other words, the PMA sublayer performs 10-bit symbol interleaving. The 10-bit symbol interleaving is consistent with the granularity of the existing PCS interleaving, and the symbol interleaving at this granularity can effectively reduce the BER.

[0010] In a possible implementation, the first data processing performed by the PMA sublayer on the data stream also includes bit multiplexing (bit mux) or symbol group multiplexing (symbol-group mux), wherein the granularity of bit multiplexing is 1 bit, and the granularity of symbol group multiplexing can be 20 bits or 40 bits. Through the bit multiplexing or symbol group multiplexing, the number of data streams output by the PMA sublayer can adapt to the number of data channels between the PMA and the next sublayer in the data transmission direction. Optionally, the bit multiplexing or symbol group multiplexing process can be performed after the above-mentioned interleaving process by the first interleaving method, or the bit multiplexing or symbol group multiplexing process can also be included in the above-mentioned interleaving process by the first interleaving method.

[0011] In a possible implementation, the first data processing process performed by the PMA sublayer on the data stream further includes bit demultiplexing (bit demux) or symbol group demultiplexing (symbol-group demux), wherein the granularity of the bit demultiplexing is 1 bit, and the granularity of the symbol group demultiplexing can be 20 bits or 40 bits.

[0012] In a possible implementation, the first data processing performed by the PMA sublayer on the data stream further includes alignment marker (AM) locking and deskew.

[0013] The data stream acquired by the PMA sublayer comes from the upper sublayer in the data transmission direction, and the upper sublayer may be, for example, PCS, data terminal equipment extender sublayer (DTE_XS) or another PMA sublayer. The data stream from the upper sublayer may be recovered through the above-mentioned bit demultiplexing or symbol group demultiplexing, as well as alignment mark locking and de-skew. Optionally, the above-mentioned bit demultiplexing or symbol group demultiplexing, as well as alignment mark locking and de-skew processing may be performed before the above-mentioned interleaving processing by the first interleaving mode, that is, after the data stream from the upper sublayer is recovered, subsequent interleaving is performed.

[0014] In a possible implementation, the data stream obtained by the PMA sublayer is a data stream obtained after executing a second data processing process, and the second data processing process includes interleaving through a second interleaving method. That is, the data stream obtained by the PMA sublayer may be a data stream that has been interleaved. The second data processing process may be executed by other sublayers before the PMA sublayer, for example, it may be executed by PCS or DTE_XS. Moreover, the sublayer executing the second data processing process may be directly adjacent to the PMA sublayer, or may be indirect adjacent, that is, there may be other sublayers in between. In other words, the interleaving performed by the PMA sublayer does not conflict with the interleaving performed by other previous sublayers, and therefore, there is no need to change the data processing methods of other existing sublayers, and it is compatible with existing Ethernet devices.

[0015] In one possible implementation, the interleaving depth of the first interleaving mode is different from that of the second interleaving mode, that is, the interleaving change is performed through the interleaving of the PMA sublayer. To some extent, it can be considered that the interleaving of the PMA sublayer covers the interleaving of other previous sublayers. Through this interleaving change, the new error correction design can be flexibly implemented in the PMA sublayer to better meet the demand for reducing BER brought about by the ever-increasing Ethernet data transmission rate, without the need to change other previous sublayers, and may not even be necessary to change the main chip of the entire Ethernet PHY layer. Specifically, the interleaving of the PMA sublayer can be different from the interleaving depth of the interleaving performed by other previous sublayers, and the interleaving of the PMA sublayer can be flexibly designed according to actual network requirements to meet the demand for reducing BER brought about by the ever-increasing Ethernet data transmission rate.

[0016] In a possible implementation, the interleaving depth of the second interleaving mode is 2 FEC codewords. For example, when Reed-Solomon (RS) codewords are used, the interleaving depth of the second interleaving mode is 2 RS codewords, that is, 2×RS.

[0017] In a possible implementation, the first data processing process may include deinterleaving for the second interleaving mode, or the first data processing process may not include deinterleaving for the second interleaving mode. Optionally, deinterleaving for the second interleaving mode may be performed before interleaving by the first interleaving mode, that is, the PMA sublayer first deinterleaves the interleaving performed by other previous sublayers, and then performs interleaving within the PMA sublayer. In addition, the PMA sublayer may not deinterleave the interleaving performed by other previous sublayers, but directly perform interleaving within the PMA sublayer.

[0018] In a possible implementation, the interleaving depth of the first interleaving mode is 4×RS. When the interleaving depth is increased to 4×RS, it can ensure that the requirements for reducing BER in various high-speed Ethernet data transmission scenarios are met, and the BER of the data interleaved by FEC after error correction can meet the network requirements. For example, the depth of 4×RS can at least meet the requirements for reducing BER in a scenario where the rate of a single physical lane is 200 gigabits per second Gbps.

[0019] In a possible implementation, the Ethernet device may include at least one of the following: a PHY chip, a forwarding device, or a pluggable module.

[0020] In a possible implementation, the single physical channel rate of the data stream obtained after the PMA sublayer performs interleaving is 200 Gbps. It is easy to understand that the 200 Gbps is a floating value within the conventional range in the art, rather than the exact value of the channel rate at any time.

[0021] In a possible implementation manner, a rate of an interface of the PMA sublayer for receiving the data stream is at least one of the following: 200 Gbps or 400 Gbps.

[0022] In a possible implementation, the PMA sublayer obtains the data stream from any of the following interfaces: an attachment unit interface (AUI) or a common electrical interface (CEI). For example, the PMA sublayer may be separated from the upper sublayer in circuitry and obtain the data stream from the upper sublayer through an interface, wherein the interface may be AUI or CEI, etc.

[0023] In a possible implementation, the PMA sublayer sends the interleaved data stream to a physical medium dependent (PMD) sublayer. In a transmitting Ethernet device, the PMD sublayer is the next sublayer of the PMD sublayer in the data transmission direction.

[0024] In the second aspect, a method for receiving data is provided, which is performed by an Ethernet device. The Ethernet device can be an Ethernet chip, an Ethernet forwarding device such as a switch or a router, and a pluggable optical module or electrical module in an Ethernet, etc. After the PMA sublayer in the Ethernet device on the data sending side performs interleaving, the PMA sublayer in the Ethernet device on the data receiving side needs to perform a deinterleaving process corresponding thereto. The PMA sublayer of the Ethernet device on the data receiving side obtains a data stream, and performs a third data processing process on the data stream to obtain a deinterleaved data stream (de-interleaved data stream), wherein the third data processing process includes deinterleaving by a first deinterleaving method, and the deinterleaving type of the first deinterleaving method is specifically symbol deinterleaving (symbol de-interleave) or convolutional deinterleaving (convolutional de-interleave). Among them, the data stream obtained by the PMA sublayer can be one data stream or multiple data streams, and the number of the data streams is related to the number of data channels between the PMA sublayer and the upper sublayer, and further, deinterleaving can refer to deinterleaving within a data stream, or deinterleaving between multiple data streams.

[0025] In the present application, the PMA sublayer on the data sending side performs symbol interleaving or convolution interleaving on the data stream, and correspondingly, the PMA sublayer on the data receiving side performs symbol deinterleaving or convolution deinterleaving on the data stream. The specific way in which the PMA sublayer performs deinterleaving can be flexibly designed to ensure that the actual needs for reducing BER in the network are met. In addition, since the expansion of the PMA sublayer is relatively simple, the design of the PMA sublayer does not require changes to the existing PCS, and even when the PMA sublayer is located in a pluggable module, the design of the PMA sublayer does not require changes to the main chip of the existing Ethernet physical PHY layer, thereby meeting the needs of reducing BER in high-speed data transmission scenarios while minimizing research and development costs.

[0026] In a possible implementation, the PMA sublayer performs symbol deinterleaving with a granularity of 10 bits, or in other words, the PMA sublayer performs 10-bit symbol deinterleaving.

[0027] In a possible implementation, the third data processing performed by the PMA sublayer on the data stream also includes bit multiplexing (bit mux) or symbol group multiplexing (symbol-group mux), wherein the granularity of bit multiplexing is 1 bit, and the granularity of symbol group multiplexing can be 20 bits or 40 bits. Through the bit multiplexing or symbol group multiplexing, the number of data streams output by the PMA sublayer can adapt to the number of data channels between the PMA and the next sublayer in the data transmission direction. Optionally, the bit multiplexing or symbol group multiplexing process can be performed after the above-mentioned deinterleaving process by the third interleaving method, or the bit multiplexing or symbol group multiplexing process can also be included in the above-mentioned deinterleaving process by the third interleaving method.

[0028] In a possible implementation, the third data processing process performed by the PMA sublayer on the data stream includes bit demultiplexing (bit demux) or symbol group demultiplexing (symbol-group demux), wherein the granularity of the bit demultiplexing is 1 bit, and the granularity of the symbol group demultiplexing can be 20 bits or 40 bits.

[0029] In a possible implementation, the third data processing performed by the PMA sublayer on the data stream includes alignment marker (AM) locking and deskew.

[0030] The data stream acquired by the PMA sublayer comes from the upper sublayer in the data transmission direction, and the upper sublayer may be, for example, a PMD sublayer. Through the above-mentioned bit demultiplexing or symbol group demultiplexing, as well as alignment mark locking and de-skew, the data stream from the upper sublayer may be recovered. Optionally, in the above-mentioned bit demultiplexing or symbol group demultiplexing, as well as alignment mark locking and de-skew processing, the processing of the first deinterleaving mode may also be implemented, that is, the data stream from the upper sublayer may be recovered and deinterleaving may be implemented through the bit demultiplexing or symbol group demultiplexing, as well as alignment mark locking and de-skew processing.

[0031] In a possible implementation, after the PMA sublayer performs deinterleaving in the third data processing process on the data stream, it can also re-interleave the deinterleaved data stream through the second interleaving method to obtain a re-interleaved data stream. This is to cooperate with the deinterleaving processing of the PCS or DTE_XS in the existing receiving-side Ethernet device, so that there is no need to improve the existing PCS or DTE_XS to adapt to the existing PHY chip as much as possible.

[0032] In a possible implementation manner, the deinterleaving depth of the first deinterleaving manner is 4×RS.

[0033] In a possible implementation, the Ethernet device may include at least one of the following: a PHY chip, a forwarding device, or a pluggable module.

[0034] In a third aspect, a method for receiving data is provided, which is performed by an Ethernet device. The Ethernet device may be an Ethernet chip, an Ethernet forwarding device such as a switch or a router, and a pluggable optical module or electrical module in an Ethernet, etc. After the PMA sublayer in the Ethernet device on the data sending side performs an interleaving transformation, the PMA sublayer in the Ethernet device on the data receiving side needs to perform a corresponding interleaving transformation to transform the interleaving mode of the data stream into an interleaving mode that is compatible with the deinterleaving process performed in other sublayers, so as to avoid changes to the PHY chip. For example, if 2×RS deinterleaving is performed on the data stream in the Ethernet PHY chip, the interleaving mode of the acquired data stream may be transformed into 2×RS interleaving in the PMA sublayer, so that the 2×RS deinterleaving performed on the data stream in the PHY chip can obtain the correct data stream. Specifically, the PMA sublayer of the Ethernet device on the data receiving side obtains the data stream, and performs a third data processing process on the data stream to obtain the interleaved data stream, wherein the third data processing process includes interleaving the data stream, and the interleaving type of the interleaving is symbol interleaving or convolution interleaving. The data stream obtained by the PMA sublayer may be one data stream or multiple data streams. The number of data streams is related to the number of data channels between the PMA sublayer and the upper sublayer. Furthermore, interleaving may refer to interleaving within one data stream or between multiple data streams.

[0035] In a possible implementation, the symbol interleaving is performed with a granularity of 10 bits.

[0036] In a possible implementation manner, the interleaved data stream is deinterleaved by a physical coding sublayer PCS or a data terminal equipment extension sublayer DTE_XS.

[0037] In a possible implementation, the interleaving depth of the interleaving is 2×RS. When the Ethernet PHY chip performs 2×RS deinterleaving on the data stream, the PMA sublayer can transform the interleaving mode of the acquired data stream into 2×RS interleaving, so that the correct data stream can be obtained after the PHY chip performs 2×RS deinterleaving on the data stream.

[0038] In a possible implementation, the third data processing process includes: performing deinterleaving through a first deinterleaving method, where the deinterleaving type of the first deinterleaving method is specifically symbol deinterleaving or convolutional deinterleaving, to obtain a deinterleaved data stream.

[0039] In a possible implementation, the third data processing process includes: bit demultiplexing or symbol group demultiplexing, wherein the granularity of the bit demultiplexing is 1 bit, and the granularity of the symbol group demultiplexing may be 20 bits or 40 bits.

[0040] In a possible implementation, the third data processing process includes: locking the alignment mark AM and de-skew.

[0041] The data stream acquired by the PMA sublayer comes from the upper sublayer in the data transmission direction, and the upper sublayer may be, for example, a PMD sublayer. Through the above-mentioned bit demultiplexing or symbol group demultiplexing, as well as alignment mark locking and de-skew, the data stream from the upper sublayer may be recovered. Optionally, in the above-mentioned bit demultiplexing or symbol group demultiplexing, as well as alignment mark locking and de-skew processing, the processing of the first deinterleaving mode may also be implemented, that is, the data stream from the upper sublayer may be recovered and deinterleaving may be implemented through the bit demultiplexing or symbol group demultiplexing, as well as alignment mark locking and de-skew processing.

[0042] In a possible implementation, the third data processing process includes: bit multiplexing or symbol group multiplexing. The granularity of bit multiplexing is 1 bit, and the granularity of symbol group multiplexing can be 20 bits or 40 bits. Through the bit multiplexing or symbol group multiplexing, the number of data streams output by the PMA sublayer can adapt to the number of data channels between the PMA and the next sublayer in the data transmission direction. Optionally, the bit multiplexing or symbol group multiplexing process can be performed after the above-mentioned deinterleaving process through the third interleaving method, or the bit multiplexing or symbol group multiplexing process can also be included in the above-mentioned deinterleaving process through the third interleaving method.

[0043] In a possible implementation, the Ethernet device includes at least one of the following: a physical layer PHY chip, a forwarding device, or a pluggable module.

[0044] In a fourth aspect, an Ethernet device is provided, comprising at least one module; the at least one module is used to execute the method provided in the first aspect or any optional manner of the first aspect; or the at least one module is used to execute the method provided in the second aspect or any optional manner of the second aspect; or the at least one module is used to execute the method provided in the third aspect or any optional manner of the third aspect. The at least one module can be implemented based on software, hardware, or a combination of software and hardware, and the module can be arbitrarily combined or divided based on specific implementation.

[0045] In a fifth aspect, an Ethernet device is provided, comprising a memory and a processor; the memory is used to store a computer program; the processor is used to execute the computer program stored in the memory so that the Ethernet device performs the method provided in the first aspect or any optional manner of the first aspect, or performs the method provided in the second aspect or any optional manner of the second aspect; or the at least one module is used to perform the method provided in the third aspect or any optional manner of the third aspect.

[0046] In a sixth aspect, an Ethernet device is provided, comprising a main control board and an interface board, wherein the main control board or the interface board is used to implement the method provided in the first aspect or any optional manner of the first aspect, or the main control board or the interface board is used to implement the method provided in the second aspect or any optional manner of the second aspect; or the at least one module is used to execute the method provided in the third aspect or any optional manner of the third aspect.

[0047] In a seventh aspect, a communication system is provided, which includes an Ethernet device, wherein the Ethernet device is used to execute the method provided in the first aspect or any optional manner of the first aspect, or to execute the method provided in the second aspect or any optional manner of the second aspect; or, the at least one module is used to execute the method provided in the third aspect or any optional manner of the third aspect.

[0048] In an eighth aspect, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed, it implements the method provided in the first aspect or any optional aspect of the first aspect; or, it implements the method provided in the second aspect or any optional aspect of the second aspect; or, it implements the method provided in the third aspect or any optional aspect of the third aspect; or, the at least one module is used to execute the method provided in the third aspect or any optional aspect of the third aspect.

[0049] In the ninth aspect, a computer program product is provided, which includes a program or code, and when the program or code is executed, it implements the method provided by the first aspect or any optional method of the first aspect; or, it implements the method provided by the second aspect or any optional method of the second aspect; or, it implements the method provided by the third aspect or any optional method of the third aspect; or, the at least one module is used to execute the method provided by the third aspect or any optional method of the third aspect.

[0050] In the tenth aspect, a chip is provided, which, when running, implements the method provided in the first aspect or any optional manner of the first aspect; or, implements the method provided in the second aspect or any optional manner of the second aspect; or, implements the method provided in the third aspect or any optional manner of the third aspect. The chip may be a control chip or a forwarding chip, and the chip includes a programmable logic circuit and / or a program instruction; or, the at least one module is used to execute the method provided in the third aspect or any optional manner of the third aspect.

[0051] The technical effects of the second to tenth aspects mentioned above can refer to the technical effects of the first aspect and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings used in the embodiments. Obviously, the following drawings are only drawings of some embodiments of the present application. For ordinary technicians in this field, other technical solutions and drawings that can also implement the present application can be obtained based on these drawings without creative labor.

[0053] FIG1( a ) is a schematic diagram of a random bit error provided by an embodiment of the present invention;

[0054] FIG1( b ) is a schematic diagram of a random bit error provided by an embodiment of the present invention;

[0055] Figure 2 A schematic diagram of an interleaver processing process provided by an embodiment of the present invention;

[0056] Figure 3 A schematic diagram of a data transmission method provided by an embodiment of the present invention;

[0057] FIG4( a) is a schematic diagram of an implementation method of a physical layer of an Ethernet device provided in an embodiment of the present invention;

[0058] FIG4( b) is a schematic diagram of an implementation method of the physical layer of an Ethernet device provided in an embodiment of the present invention;

[0059] FIG4( c) is a schematic diagram of an implementation method of the physical layer of an Ethernet device provided in an embodiment of the present invention;

[0060] Figure 5 A schematic diagram of an interleaved data processing process provided by an embodiment of the present invention;

[0061] Figure 6 A schematic diagram of an interleaved data processing process provided by an embodiment of the present invention;

[0062] FIG. 7( a) is a schematic diagram of a multiplexed data processing process provided by an embodiment of the present invention;

[0063] FIG7( b) is a schematic diagram of a multiplexed data processing process provided by an embodiment of the present invention;

[0064] FIG7( c ) is a schematic diagram of a multiplexed data processing process provided by an embodiment of the present invention;

[0065] FIG8( a) is a schematic flow chart of a method for receiving data provided by an embodiment of the present invention;

[0066] FIG8( b) is a schematic flow chart of a method for receiving data provided by an embodiment of the present invention;

[0067] FIG9( a) is a schematic flow chart of a method for sending and receiving PMA sublayer data provided by an embodiment of the present invention;

[0068] FIG9( b ) is a schematic flow chart of a method for sending and receiving PMA sublayer data provided by an embodiment of the present invention;

[0069] FIG9( c ) is a schematic flow chart of a method for sending and receiving PMA sublayer data provided by an embodiment of the present invention;

[0070] FIG9( d ) is a schematic flow chart of a method for sending and receiving PMA sublayer data provided by an embodiment of the present invention;

[0071] Fig.10 A schematic diagram of the structure of an Ethernet device provided by an embodiment of the present invention;

[0072] Fig.11 A schematic diagram of the structure of an Ethernet device provided by an embodiment of the present invention;

[0073] Fig.12 A schematic diagram of the structure of an Ethernet device provided by an embodiment of the present invention;

[0074] Fig.13 A schematic diagram of a communication system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0075] During the communication transmission process, due to various reasons such as environmental interference and system errors, there is a high probability that there will be inconsistencies between the data received by the data receiving end and the data sent by the data sending end. This inconsistency is also called a bit error. It can be seen that the problem of bit errors in the communication transmission process is inevitable. Bit errors can cause many problems. For example, when there are bit errors in the key control signals for the interaction between various devices in the network, it may cause serious problems such as system crashes and data loss. In addition, the existence of bit errors will greatly affect the network communication delay, and thus affect consumers' experience of watching videos, online games, and making calls. Therefore, the bit error rate BER has always been an important performance indicator of the communication system. The smaller the BER value at the data receiving end, the higher the network transmission reliability.

[0076] In order to ensure the high reliability of the communication system, the industry usually puts forward clear requirements for the BER of the communication system. For example, the Institute of Electrical and Electronics Engineers (IEEE) standard 802.3bs requires that the BER of the data received by the data receiving end when entering the media access control (MAC) sublayer should be less than 1×10 -13 However, when the data in the network completes the transmission in the network link and enters the data receiving end, its BER can usually reach 2.4×10 -4 At this point, the data receiving end can use FEC to correct the bit errors in the data stream to restore it to the transmitted data. FEC can eliminate most of the bit errors, greatly reducing the BER of the processed data.

[0077] The effect of FEC is related to the error distribution. When the error distribution of two data streams is different, even if their BER before correction is the same, their BER after correction will be different. Among them, the BER before correction refers to the BER before FEC, and the BER after correction refers to the BER after FEC. The distribution of errors can be mainly divided into two categories: random error and non-random error. For the sake of illustration, Figure 1 (a) and Figure 1 (b) illustrate random errors and non-random errors, where b represents the correct bit of the data and x represents the bit where the error occurs. Random errors are manifested as random error distribution, as shown in Figure 1 (a), and non-random errors are manifested as multiple errors appearing in a shorter data sequence, as shown in Figure 1 (b). Therefore, non-random errors can also be called burst errors. Burst errors are common in actual communication networks, such as continuous errors caused by decision feedback equalization (DFE) and continuous errors caused by fast fading caused by the multipath effect of wireless information. As shown above, the current BER of the data in Figure 1(a) and Figure 1(b) is the same, but different error distributions will cause differences in the BER of these data after FEC. Under most communication transmission conditions, based on the same pre-correction FEC, burst errors will result in a better post-correction BER than random errors.

[0078] In order to further reduce the post-correction FEC in the case of burst errors, an interleaver is usually introduced. Figure 2 shown. Figure 2 In the figure, Tx is the data to be input into the FEC encoder at the data transmitting end. After being encoded by the FEC encoder at the data transmitting end, these data are input into the interleaver for interleaving. The data output by the interleaver is transmitted to the data receiving end through the communication channel. The data is input into the deinterleaver at the data receiving end for deinterleaving, and then enters the FEC decoder for decoding. Rx is the data output by the FEC decoder at the data receiving end. After FEC and interleaving processing, the BER in Rx will be greatly reduced. The above interleaver can be set in the PCS of the Ethernet device, for example, the PCS in the Ethernet PHY chip, that is, the PCS performs interleaving on the data.

[0079] As mentioned above, with the development of Internet technology, the Ethernet data transmission rate continues to increase, resulting in a further increase in the BER of the data receiving end. At this time, the interleaving performed by the PCS often cannot meet the demand for reducing the BER. At this time, if the PCS circuit is redesigned, it means redesigning the Ethernet PHY chip, which will result in high costs.

[0080] The present application proposes a method for sending data, which is performed by an Ethernet device on the data sending side. In this method, the function of the PMA sublayer of the Ethernet device is extended, and the data is interleaved in the PMA sublayer. Specifically, the PMA sublayer obtains a data stream encoded by FEC, and performs a data processing process 1 on the data stream to obtain an interleaved data stream, wherein the data processing process 1 includes interleaving through a first interleaving method, and the interleaving type of the first interleaving method is specifically symbol interleaving or convolution interleaving. Through this method, the PMA sublayer performs symbol interleaving or convolution interleaving on the data stream, and the specific method of performing interleaving by the PMA sublayer can be flexibly designed to ensure that the actual demand for reducing BER in the network is met. In addition, since the expansion of the PMA sublayer is relatively simple, the design of the PMA sublayer does not need to change the existing PCS, and even when the PMA sublayer is located in a pluggable module, the design of the PMA sublayer does not need to change the main chip of the existing Ethernet physical PHY layer, thereby meeting the demand for reducing BER in high-speed data transmission scenarios while saving research and development costs as much as possible.

[0081] Figure 3 3 is a flow chart of a data transmission method 300 in an embodiment of the present application. The method may include, for example:

[0082] Step 301: The physical medium of the Ethernet device connects to the PMA sublayer to obtain a data stream, which is a data stream encoded by forward error correction (FEC).

[0083] The Ethernet device may be an Ethernet chip, an Ethernet forwarding device such as a switch or a router, and a pluggable optical module or electrical module in the Ethernet. At this time, the Ethernet device is an Ethernet device on the data sending side. It is easy to understand that at some point, the Ethernet device may also be an Ethernet device on the data receiving side to execute the method on the data receiving side.

[0084] In an embodiment of the present application, the Ethernet physical layer can be further divided into multiple sublayers according to the main functions, and these sublayers include but are not limited to: PCS, PMA sublayer, physical medium dependent (physical medium dependent, PMD) sublayer, etc. The specific implementation of these sublayers can be an electronic circuit. Among them, the PCS is responsible for encoding, scrambling and other processing of the data, and FEC encoding is also performed in the PCS. There are three ways to implement the Ethernet physical layer in the embodiment of the present application. The first way is shown in Figure 4 (a), where the Ethernet physical layer includes PCS, PMA sublayer and PMD sublayer, and the three sublayers are all included in the PHY chip. This method is generally suitable for copper cable transmission, backplane transmission and co-packaging optics (CPO) transmission scenarios. The second method is shown in FIG4(b), where the Ethernet physical layer includes PCS, PMA sublayer and PMD sublayer, PCS and one PMA sublayer are included in the PHY chip, and the other PMA sublayer and PMD sublayer are included in a pluggable optical module or a pluggable electrical module, which is independent of the PHY chip in circuit implementation and connected to the PHY chip through an interface. The interface type shown in FIG4(b) is AUI. It can be understood that the interface type can also include other types, such as CEI. This method is generally applicable to optical fiber transmission or electrical transmission scenarios, and is also applicable to scenarios using cascaded codes. The third method is shown in Figure 4(c), where the Ethernet physical layer includes PCS, PMA sublayer, PMD sublayer, DTE_XS and physical layer device extender sublayer (physical layer device extender sublayer, PHY_XS), DTE_XS and the first PMA sublayer are included in the PHY chip, the second PMA sublayer, PHY_XS, PCS, the third PMA sublayer and the PMD sublayer are included in a pluggable optical module or a pluggable electrical module, and the pluggable optical module or the pluggable electrical module is also independent of the PHY chip in circuit implementation, and is connected to the PHY chip through an interface. The interface type shown in Figure 4(c) is AUI. It can be understood that the interface type can also include other types, such as CEI.

[0085] In an embodiment of the present application, the PMA sublayer interleaved by the first interleaving method may be the PMA sublayer in FIG. 4(a) above, the PMA sublayer located in the pluggable optical module or the pluggable electrical module in FIG. 4(b) above, the PMA sublayer located in the PHY chip in FIG. 4(c), or the second PMA sublayer located in the pluggable optical module or the pluggable electrical module in FIG. 4(c), that is, the PMA sublayer adjacent to the PCS and the PMD.

[0086] When the PMA sublayer interleaved by the first interleaving method is a PMA sublayer located in a pluggable optical module or a pluggable electrical module, in order to implement the method in the embodiment of the present application, it is only necessary to design in the PMA sublayer in the pluggable module without changing the PHY chip, and it is compatible with the existing PHY chip. And the same PHY chip can match a variety of different pluggable optical modules or pluggable electrical modules to achieve the expansion of a variety of different interleaving methods. When the Ethernet data transmission rate is further improved in the future, the error correction performance can be upgraded by directly replacing the pluggable module.

[0087] When the PMA sublayer interleaved by the first interleaving mode is a PMA sublayer located in a PHY chip, in order to implement the method in the embodiment of the present application, only the PMA sublayer in the chip needs to be redesigned, and the existing PCS can still be reused. As mentioned above, the PCS has complex functions, while the PMA sublayer is relatively simple and easier to expand. Therefore, the method in the embodiment of the present application can minimize the modification of the PHY chip.

[0088] In an optional manner, the PMA sublayer interleaved by the first interleaving mode obtains the data stream, which may refer to the PMA sublayer obtaining the data stream from the upper sublayer in the data stream transmission direction. In combination with the above three physical layer implementations, the upper sublayer may be PCS, PMA or DTE_XS. When the PMA sublayer and the upper sublayer are separated from each other in circuit implementation, the PMA sublayer obtains the data stream from the upper sublayer through an interface, wherein the interface may be AUI or CEI, etc.

[0089] In an optional manner, the rate of the interface through which the PMA sublayer obtains the data stream is at least one of the following: 200 Gbps or 400 Gbps, or other rate values, which are not limited here.

[0090] In an optional manner, the data stream acquired by the PMA sublayer may be one data stream or multiple data streams.

[0091] In an optional manner, after obtaining the data stream, the PMA sublayer may first split the single data stream. For example, when the rate of the interface of the PMA sublayer receiving the data stream is 400 Gbps, it may first split it into two groups of data streams, and then the PMA sublayer interleaves them respectively. This facilitates the subsequent breakout processing in the pluggable module.

[0092] Step 302: The PMA sublayer performs data processing process 1 on the data stream to obtain an interleaved data stream, where the data processing process 1 includes interleaving in a first interleaving manner.

[0093] As mentioned above, the data stream acquired by the PMA sublayer may be one data stream or multiple data streams. Accordingly, the interleaving in the first interleaving manner may be interleaving within a data stream or between data streams.

[0094] In an embodiment of the present application, the interleaving method may have multiple attributes. The interleaving type is an attribute of the interleaving method, and the interleaving type of the first interleaving method is symbol interleaving or convolution interleaving. Among them, symbol interleaving may also be called block interleaving. Symbol interleaving and convolution interleaving are basically the same in terms of error correction performance, but when the same error correction performance is achieved, the delay and power consumption of the two methods may be different.

[0095] The interleaving depth is also a property of the interleaving mode. The interleaving depth indicates the number of FEC codewords involved in the interleaving, and the number of FEC codewords involved in the interleaving affects the error correction performance.

[0096] Figure 5 A schematic diagram of a data processing method for symbol interleaving is given as an example.

[0097] like Figure 5 As shown, multiple FEC-encoded codewords are obtained from the data stream to be interleaved as codewords participating in the interleaving, such as codewordA, codewordB, codewordC, codewordD, etc. in the figure. When the codewords participating in the interleaving come from the same data stream, it is the interleaving within the data stream. When the codewords participating in the interleaving come from different data streams, it is the interleaving between data streams. Each codeword includes p FEC-encoded symbols, each symbol includes q bits, that is, each codeword includes p×q bits. For example, the length of each symbol can be 10 bits, that is, the symbol is interleaved with a granularity of 10 bits. As shown in the figure, 4 codewords are selected from the data stream to be interleaved to participate in the interleaving, that is, the interleaving depth is 4 codewords. When the codeword is an RS codeword, it can be called an interleaving depth of 4×RS. The four codewords are alternately distributed as n data streams on n lanes at a symbol granularity, so that adjacent symbols of each data stream come from different codewords, that is, the symbols from the above four codewords appear alternately, thus forming an interleaved data sequence, namely interleaved lane 1 to interleaved lane n shown in the figure.

[0098] Figure 6 A schematic diagram of a data processing method of convolution interleaving is given as an example. Convolution interleaving involves a variety of design parameters, including the number of delay lines, the length of delay blocks, the number of delay blocks, etc. Figure 6 As shown, multiple FEC-encoded codewords are obtained from the data stream to be interleaved to participate in interleaving, including cwA, cwB, cwC, cwD, etc. The interleaving depth is 4 codewords, that is, 4 codewords are selected from the data stream to be interleaved, namely the above-mentioned cwA, cwB, cwC, cwD, and the number of delayed lines is 4, namely 4 lines of data line 0, 1, 2, 3 from top to bottom. Figure 6 D stands for delay block. Each delay block consists of a shift register (LFSR) that can temporarily store certain data, and the number of delay blocks on each delay line is different. There is a switch that can be switched on the input and output sides of the interleaver to connect a certain delay line. The data of the FEC codeword enters the convolutional interleaver column by column with the delay block length as the granularity, such as Figure 6 As shown in a, b, c, and d. Among them, when the FEC codeword length is the same as the delay block length, the granularity entering the convolution interleaver is also the length of the FEC codeword. When the FEC codeword length is different from the delay block length, when entering the convolution interleaver, the FEC codeword data needs to be adjusted to enter the convolution interleaver with the delay block length as the granularity. When the input side inputs data of a delay block length each time, the output side will output data of a delay block length at the same time. After that, the switchable connection switches on both sides will switch to the next delay line, and poll in the order of {line 0, line 1, line 2, line 3, line 0, line 1, line 2, line 3, line 0, line 1,…}. In addition, Figure 6 The output side x in the delay block represents the data before 4 codewords. Figure 6 In this paper, the convolution interleaving of a data stream is taken as an example, but the convolution interleaving between multiple data streams is similar to Figure 6 The process shown in is similar to that shown in , except that the codewords involved in the interleaving come from multiple data streams, which will not be described in detail here.

[0099] In an embodiment of the present application, the first interleaving mode performed by the PMA sublayer can be implemented by the above-mentioned symbol interleaving or convolution interleaving. Optionally, the PMA sublayer needs to retain the availability of an alignment marker (AM) during the interleaving process so that data synchronization can still be performed according to AM at the data receiving side.

[0100] In an optional manner, the data stream obtained by the PMA sublayer from the previous sublayer may be a data stream that has been interleaved, that is, other sublayers before the PMA sublayer may have interleaved the data stream. Specifically, the data stream obtained by the PMA sublayer is a data stream obtained after executing data processing process 2, and the data processing process 2 includes interleaving through the second interleaving method. The data processing process 2 can be executed by other sublayers before the PMA sublayer. As mentioned above, the sublayer that executes the data processing process 2 can be directly adjacent to the PMA sublayer, or it can be indirectly adjacent, that is, there are other sublayers in between. Optionally, the second interleaving method can be executed by PCS or DTE_XS. The second interleaving method can also be implemented by the above-mentioned symbol interleaving or convolution interleaving. In other words, the interleaving performed by the PMA sublayer does not conflict with the interleaving performed by other previous sublayers. In particular, when the PMA sublayer is located in a pluggable optical module or a pluggable electrical module, there is no need to modify the PCS or DTE_XS in the PHY chip, and it is compatible with the existing PHY chip. It only needs to be designed in the PMA sublayer in the pluggable module to meet the requirements of reducing BER in the network. When the PMA sublayer is located in the PHY chip, it is also possible to reuse the existing PCS or DTE_XS, and only the PMA sublayer in the chip needs to be redesigned, and the requirements of reducing BER in the network can be met through relatively simple expansion.

[0101] In an optional manner, the first interleaving mode and the second interleaving mode may be different, that is, an interleaving change is performed through the interleaving of the PMA sublayer. To some extent, it can be considered that the interleaving of the PMA sublayer covers the interleaving of other previous sublayers. Through this interleaving change, the new error correction design can be flexibly implemented in the PMA sublayer, better meeting the demand for reducing BER brought about by the ever-increasing Ethernet data transmission rate, without changing other previous sublayers, and even without changing the main chip of the entire Ethernet PHY layer.

[0102] In an optional manner, the above interleaving transformation is specifically: the interleaving depth of the first interleaving mode is different from that of the second interleaving mode. Taking the PCS performing 2×RS interleaving as an example, the interleaving depth performed by the PMA sublayer can be 4×RS, that is, the PMA sublayer achieves deeper interleaving, which can meet the error correction requirements in the scenario where the speed of a single physical channel reaches 200Gbps.

[0103] In an optional manner, the interleaving types of the first interleaving mode and the second interleaving mode may be the same or different. For example, the PMA sublayer and the PCS both perform symbol interleaving with a 10-bit granularity. For another example, the PCS sublayer performs symbol interleaving, while the PMA sublayer performs convolutional interleaving.

[0104] In an optional manner, before interleaving by the first interleaving mode, the second interleaving mode may be deinterleaved in the PMA sublayer, or the second interleaving mode may not be deinterleaved in the PMA sublayer. That is, the PMA sublayer may first deinterleave the interleaving performed by other previous sublayers, and then perform the interleaving within the PMA sublayer. Alternatively, the PMA sublayer may not deinterleave the interleaving performed by other previous sublayers, but directly perform the interleaving within the PMA sublayer. Taking the PCS performing 2×RS interleaving as an example, the PMA sublayer first waits for the data of 2 codewords to be obtained, and then starts to interleave with the data of the 2 codewords that arrive subsequently. The total number of codewords involved in the interleaving is 4, that is, the interleaving depth is 4×RS.

[0105] In an optional manner, the data processing process 1 performed by the PMA sublayer on the data stream also includes bit multiplexing or symbol group multiplexing. As mentioned above, the PMA sublayer outputs the data to the next sublayer, such as the PMD sublayer, after data processing. Therefore, the PMA sublayer needs to ensure that the output data is adapted to the number of channels connected to the next sublayer. Specifically, the data to be output can be processed to adapt to the number of channels connected to the next sublayer through bit multiplexing or symbol group multiplexing. The bit multiplexing or symbol group multiplexing can be included in the data processing process corresponding to the above-mentioned first interleaving mode, that is, the PMA sublayer performs the interleaving process, and at the same time, the data is bit multiplexed or symbol group multiplexed, taking into account the number of channels connected to the next sublayer. The bit multiplexing or symbol group multiplexing can also be after the data processing process corresponding to the above-mentioned first interleaving mode, that is, the PMA sublayer first performs the interleaving process, and then performs bit multiplexing or symbol group multiplexing on the data, so that the data stream is adapted to the number of channels connected to the next sublayer.

[0106] Figure 7(a) to Figure 7(c)A schematic diagram of a data processing method for symbol group multiplexing is given as an example. For example, there are two initial data streams participating in the multiplexing, namely data stream 1 and data stream 2, wherein the number of initial data streams participating in the multiplexing can be any number and is not limited here. In symbol group multiplexing, each data stream is divided into symbols as the granularity, and the length of the symbol can be, for example, 20 bits or 40 bits. At least 2 symbols in each data stream can form a symbol group (symbol-group), and then the data from the two data streams are polled and alternately multiplexed to one channel with the granularity of the symbol group, such as the muxed lane in Figure 7 (a), which corresponds to a channel in the interface between sublayers. It is easy to understand that when the interface between two sublayers includes 4 channels, when multiplexing is performed in the manner shown in Figure 7 (a), 8 data streams will be multiplexed to 4 muxed lanes. In the embodiment of the present application, in the symbol group multiplexing performed by the PMA sublayer, the number of input data streams and the number of channels after multiplexing can be determined according to actual conditions and are not limited here. Moreover, in symbol group multiplexing, when data from two data streams are multiplexed alternately to one channel in symbol group polling, it can also include exchanging the data position in one of the data streams, for example, swapping the positions of two symbols front and back, as shown in FIG7(b), or delaying the data position in one of the data streams by one symbol to form a misalignment and other operations, as shown in FIG7(c), where x is the previous or next symbol that appears due to the delay. In bit multiplexing, the data streams participating in the multiplexing are divided into 1 bit granularity, and other operations are similar to those of symbol group multiplexing, which will not be repeated here.

[0107] In an optional manner, before the PMA sublayer performs convolution interleaving, a step of bit multiplexing or symbol group multiplexing of the data stream may be added to adjust the number of data streams during convolution interleaving. The specific operation may refer to the above Figure 7(a) to Figure 7(c) As shown, no further description is given here.

[0108] In an optional manner, the data processing process 1 performed by the PMA sublayer on the data stream may also include one or more other processes, such as bit demultiplexing (bit demux) or symbol group demultiplexing (symbol-group demux), AM locking and deskew, etc. As mentioned above, the data stream obtained by the PMA sublayer comes from the upper sublayer, and the upper sublayer may be, for example, PCS, DTE_XS or another PMA sublayer, etc. The PMA sublayer and the upper sublayer may be separated or not separated in circuit. When the PMA sublayer and the upper sublayer are separated in circuit, the two may be connected through an interface, and the interface type includes but is not limited to AUI or CEI, etc. Before being sent from the upper sublayer to the PMA sublayer, these data streams may be bit multiplexed or symbol group multiplexed to adapt the number of channels between sublayers, and when transmitted through the interface, the data in these data streams may also be unlocked or skewed. Therefore, it is necessary to recover the received data stream in the PMA sublayer. For example, in the implementation of the Ethernet physical layer shown in FIG4(b), the PMA sublayer in the pluggable module receives a data stream through AUI, and the data stream is bit-multiplexed or symbol-group-multiplexed in the PMA sublayer in the PHY chip. The PMA sublayer in the pluggable module first needs to perform corresponding bit demultiplexing or symbol-group demultiplexing in a targeted manner, and perform AM locking and de-skew on the data that is lost or skewed when transmitted through the AUI interface, so as to restore the data stream sent to the channel by the previous sublayer, for example, when the previous sublayer is the PCS layer, the PCS lane data stream is restored. Optionally, the above-mentioned bit demultiplexing or symbol-group demultiplexing, as well as the alignment mark locking and de-skew processing, can be performed before the above-mentioned interleaving processing through the first interleaving method, that is, the PMA sublayer first restores the data stream from the previous sublayer, and then performs subsequent interleaving. Optionally, the granularity of the bit demultiplexing is 1 bit, and the granularity of the symbol group demultiplexing can be 20 bits or 40 bits. Optionally, in the above de-skew processing, the data can be aligned to AM, or the data can be aligned to the symbol boundary, for example, the data can be aligned to the symbol boundary with a granularity of 10 bits, or the data can be aligned to the symbol boundary with a granularity of 20 bits, or the data can be aligned to the symbol boundary with a granularity of 40 bits.

[0109] In an optional manner, the PMA sublayer may further perform FEC encoding to improve data error correction performance.

[0110] In an optional manner, the single physical channel rate of the data stream obtained after the PMA sublayer performs interleaving is 200 Gbps. It is easy to understand that the 200 Gbps is a floating value within the conventional range in the art, rather than the exact value of the channel rate at any time.

[0111] The above is a description of the method executed by the Ethernet device on the data sending side. The Ethernet device on the data receiving side needs to execute a method that cooperates with the data sending side. Figure 8(a) shows a method for receiving data. After the PMA sublayer in the Ethernet device on the data sending side performs interleaving, the PMA sublayer in the Ethernet device on the data receiving side needs to perform a deinterleaving process corresponding thereto. The method is executed by an Ethernet device, which can be an Ethernet chip, an Ethernet forwarding device such as a switch or a router, and a pluggable optical module or electrical module in an Ethernet, etc. The PMA sublayer of the Ethernet device on the data receiving side obtains a data stream, and performs a data processing process 31 on the data stream to obtain a deinterleaved data stream, wherein the data processing process 31 includes deinterleaving by a first deinterleaving method, and the deinterleaving type of the first deinterleaving method is specifically symbol deinterleaving or convolutional deinterleaving. In this method, since the expansion of the PMA sublayer is relatively simple, the design of the PMA sublayer does not require changes to the existing PCS. Even when the PMA sublayer is located in a pluggable module, the design of the PMA sublayer does not require changes to the main chip of the existing Ethernet physical PHY layer. This can meet the need to reduce BER in high-speed data transmission scenarios while minimizing research and development costs.

[0112] FIG8(a) is a flow chart of a data transmission method in an embodiment of the present application. The method may include:

[0113] Step 8011: The PMA sublayer of the Ethernet device obtains a data stream, which is a data stream encoded by forward error correction (FEC).

[0114] The Ethernet device may be an Ethernet chip, an Ethernet forwarding device such as a switch or a router, and a pluggable optical module or electrical module in the Ethernet. At this time, the Ethernet device is an Ethernet device on the data receiving side. It is easy to understand that at some point, the Ethernet device may also be an Ethernet device on the data sending side to execute the method on the data sending side.

[0115] The implementation of the Ethernet physical layer in the Ethernet device on the data receiving side can also refer to the implementation shown in Figures 4(a), 4(b), and 4(c), which will not be described in detail here.

[0116] In an embodiment of the present application, the PMA sublayer that is deinterleaved by the first deinterleaving method may be the PMA sublayer in FIG. 4(a) above, the PMA sublayer located in the pluggable optical module or the pluggable electrical module in FIG. 4(b) above, the PMA sublayer located in the PHY chip in FIG. 4(c), or the second PMA sublayer located in the pluggable optical module or the pluggable electrical module in FIG. 4(c), that is, the PMA sublayer adjacent to the PCS and the PMD.

[0117] In an optional manner, the PMA sublayer obtains the data stream, which may mean that the PMA sublayer obtains the data stream from the upper sublayer in the data stream transmission direction. In combination with the above three physical layer implementations, the upper sublayer may be PMD. When the PMA sublayer and the upper sublayer are separated from each other in circuit implementation, the PMA sublayer obtains the data stream from the upper sublayer through an interface, wherein the interface may be AUI or CEI, etc.

[0118] In an optional manner, the data stream acquired by the PMA sublayer may be one data stream or multiple data streams.

[0119] Step 8012: The PMA sublayer performs data processing process 31 on the data stream to obtain a deinterleaved data stream. The data processing process 31 includes deinterleaving in a first deinterleaving manner.

[0120] As mentioned above, the data stream acquired by the PMA sublayer may be one data stream or multiple data streams. Accordingly, the interleaving in the first deinterleaving manner may be deinterleaving within a data stream or deinterleaving between data streams.

[0121] In the embodiment of the present application, the deinterleaving type of the first deinterleaving mode is symbol deinterleaving or convolutional deinterleaving. The data processing process of symbol deinterleaving or convolutional deinterleaving is as described above. Figure 5 and Figure 6 The specific details of the de-interleaving process corresponding to the data processing process shown are not repeated here.

[0122] In an optional manner, corresponding to the first interleaving manner, the deinterleaving of the first deinterleaving manner is based on a granularity of 10 bits, or in other words, the PMA sublayer performs 10-bit symbol deinterleaving.

[0123] In an optional manner, the data processing process 31 performed by the PMA sublayer on the receiving side also includes bit multiplexing or symbol group multiplexing, so that the number of output data streams can adapt to the number of data channels between the PMA sublayer and the next sublayer in the data transmission direction. Its specific implementation method is similar to the bit multiplexing or symbol group multiplexing in the PMA sublayer on the sending side, and will not be repeated here. Among them, the granularity of bit multiplexing is 1 bit, and the granularity of symbol group multiplexing can be 20 bits or 40 bits. Optionally, the processing of bit multiplexing or symbol group multiplexing can be performed after the above-mentioned deinterleaving processing through the third interleaving method, or the processing of bit multiplexing or symbol group multiplexing can also be included in the above-mentioned deinterleaving processing through the third interleaving method.

[0124] In an optional manner, the data processing process 31 performed by the PMA sublayer on the data stream further includes bit demultiplexing or symbol group demultiplexing, wherein the granularity of the bit demultiplexing is 1 bit, and the granularity of the symbol group demultiplexing can be 20 bits or 40 bits.

[0125] In an optional manner, the data processing process 31 performed by the PMA sublayer on the data stream also includes AM locking and de-skew.

[0126] Through the above-mentioned bit demultiplexing or symbol group demultiplexing, as well as alignment mark locking and de-skew, the data stream from the upper sublayer can be recovered. For example, the upper sublayer is PMD. Optionally, in the above-mentioned bit demultiplexing or symbol group demultiplexing, as well as alignment mark locking and de-skew processing, the first deinterleaving mode is implemented before the deinterleaving processing, that is, the data stream from the upper sublayer is recovered and deinterleaved through the above-mentioned bit demultiplexing or symbol group demultiplexing, as well as alignment mark locking and de-skew processing.

[0127] In an optional manner, after the PMA sublayer performs deinterleaving in the data processing process 31 on the data stream, it can also reinterleave the deinterleaved data stream through a second interleaving mode to obtain a reinterleaved data stream. This is to cooperate with the deinterleaving processing of the PCS or DTE_XS in the existing Ethernet device on the receiving side, so that there is no need to improve the existing PCS or DTE_XS to adapt to the existing PHY chip as much as possible.

[0128] In an optional manner, the deinterleaving depth of the first deinterleaving manner is 4×RS.

[0129] In an optional manner, the PMA sublayer may also perform FEC decoding to improve data error correction performance.

[0130] In addition, more implementation details in the receiving-side Ethernet device can be coordinated with the above-mentioned sending-side Ethernet device, which will not be repeated here.

[0131] FIG8(b) shows another method for receiving data, which is performed by an Ethernet device, which may be an Ethernet chip, an Ethernet forwarding device such as a switch or a router, and a pluggable optical module or electrical module in an Ethernet. After the PMA sublayer in the Ethernet device on the data sending side performs interleaving, the interleaving mode of the data stream changes. The PMA sublayer in the Ethernet device on the data receiving side needs to perform a corresponding interleaving transformation to transform the interleaving mode of the data stream into an interleaving mode that is compatible with the deinterleaving process performed in other sublayers, thereby avoiding changes to the PHY chip. For example, if 2×RS deinterleaving is performed on the data stream in the Ethernet PHY chip, the PMA sublayer may transform the interleaving mode of the acquired data stream into 2×RS interleaving, so that the 2×RS deinterleaving performed on the data stream in the PHY chip can obtain the correct data stream. The PMA sublayer of the Ethernet device on the data receiving side obtains the data stream, and performs a data processing process 32 on the data stream to obtain the interleaved data stream, wherein the data processing process 32 includes interleaving the data stream, and the interleaving type of the interleaving is symbol interleaving or convolution interleaving. In this method, the PMA sublayer in the Ethernet device on the data receiving side performs interleaving to transform the interleaving mode of the data stream into an interleaving mode that is compatible with the deinterleaving process performed in other sublayers, that is, to achieve interleaving transformation, which can improve the error correction performance and meet the BER reduction requirements in the network while avoiding changes to the PHY chip.

[0132] FIG8( b) is a flow chart of a data transmission method in an embodiment of the present application. The method may include:

[0133] Step 8021: The PMA sublayer of the Ethernet device obtains a data stream, where the data stream is a data stream encoded by forward error correction (FEC).

[0134] The Ethernet device may be an Ethernet chip, an Ethernet forwarding device such as a switch or a router, and a pluggable optical module or electrical module in the Ethernet. At this time, the Ethernet device is an Ethernet device on the data receiving side. It is easy to understand that at some point, the Ethernet device may also be an Ethernet device on the data sending side to execute the method on the data sending side.

[0135] The implementation of the Ethernet physical layer in the Ethernet device on the data receiving side can also refer to the implementation shown in Figures 4(a), 4(b), and 4(c), which will not be described in detail here.

[0136] In an embodiment of the present application, the PMA sublayer that is deinterleaved by the first deinterleaving method may be the PMA sublayer in FIG. 4(a) above, the PMA sublayer located in the pluggable optical module or the pluggable electrical module in FIG. 4(b) above, the PMA sublayer located in the PHY chip in FIG. 4(c), or the second PMA sublayer located in the pluggable optical module or the pluggable electrical module in FIG. 4(c), that is, the PMA sublayer adjacent to the PCS and the PMD.

[0137] In an optional manner, the PMA sublayer obtains the data stream, which may mean that the PMA sublayer obtains the data stream from the upper sublayer in the data stream transmission direction. In combination with the above three physical layer implementations, the upper sublayer may be PMD. When the PMA sublayer and the upper sublayer are separated from each other in circuit implementation, the PMA sublayer obtains the data stream from the upper sublayer through an interface, wherein the interface may be AUI or CEI, etc.

[0138] In an optional manner, the data stream acquired by the PMA sublayer may be one data stream or multiple data streams.

[0139] Step 8022: The PMA sublayer performs a data processing process 32 on the data stream to obtain an interleaved data stream, where the data processing process 32 includes interleaving the data stream.

[0140] As mentioned above, the data stream acquired by the PMA sublayer may be one data stream or multiple data streams. Accordingly, the above interleaving may be interleaving within a data stream or interleaving between data streams.

[0141] In the embodiment of the present application, the interleaving type of the interleaving is symbol interleaving or convolution interleaving. The data processing process of symbol interleaving or convolution interleaving is referred to above. Figure 5 and Figure 6 The specific details of the data processing process shown are not repeated here.

[0142] In an optional embodiment, the symbol interleaving is performed with a granularity of 10 bits.

[0143] In an optional manner, the interleaved data stream is deinterleaved by the PCS or DTE_XS.

[0144] In an optional manner, the interleaving depth is 2×RS. When the PCS or DTE_XS in the Ethernet PHY chip performs 2×RS deinterleaving on the data stream, the PMA sublayer may transform the interleaving mode of the acquired data stream into 2×RS interleaving, so that the PHY chip can obtain the correct data stream after performing 2×RS deinterleaving on the data stream.

[0145] In an optional manner, the data processing process 32 includes: performing deinterleaving by a first deinterleaving mode, wherein the deinterleaving type of the first deinterleaving mode is specifically symbol deinterleaving or convolution deinterleaving, to obtain a deinterleaved data stream. The deinterleaving of the first deinterleaving mode may be 4×RS. For more details about the process of performing deinterleaving by the first deinterleaving mode, reference may be made to the relevant description in the data transmission method shown in FIG. 8(a), which will not be repeated here.

[0146] In an optional manner, the data processing process 32 includes: bit demultiplexing or symbol group demultiplexing, wherein the granularity of the bit demultiplexing is 1 bit, and the granularity of the symbol group demultiplexing may be 20 bits or 40 bits.

[0147] In an optional manner, the data processing process 32 includes: alignment mark AM locking and de-skew.

[0148] The data stream acquired by the PMA sublayer comes from the upper sublayer in the data transmission direction, and the upper sublayer may be, for example, a PMD sublayer. Through the above-mentioned bit demultiplexing or symbol group demultiplexing, as well as alignment mark locking and de-skew, the data stream from the upper sublayer may be recovered. Optionally, in the above-mentioned bit demultiplexing or symbol group demultiplexing, as well as alignment mark locking and de-skew processing, the processing of the first deinterleaving mode may also be implemented, that is, the data stream from the upper sublayer may be recovered and deinterleaving may be implemented through the bit demultiplexing or symbol group demultiplexing, as well as alignment mark locking and de-skew processing.

[0149] In an optional manner, the data processing process 32 includes: bit multiplexing or symbol group multiplexing. The granularity of bit multiplexing is 1 bit, and the granularity of symbol group multiplexing can be 20 bits or 40 bits. Through the bit multiplexing or symbol group multiplexing, the number of data streams output by the PMA sublayer can adapt to the number of data channels between the PMA and the next sublayer in the data transmission direction. Optionally, the bit multiplexing or symbol group multiplexing process can be performed after the above-mentioned deinterleaving process by the third interleaving method, or the bit multiplexing or symbol group multiplexing process can also be included in the above-mentioned deinterleaving process by the third interleaving method.

[0150] In an optional manner, the PMA sublayer may also perform FEC decoding to improve data error correction performance.

[0151] In addition, more implementation details in the receiving-side Ethernet device can be coordinated with the above-mentioned sending-side Ethernet device, which will not be repeated here.

[0152] Furthermore, in the method shown in FIG. 8( a ) or FIG. 8( b ), in the receiving-side Ethernet device, after the interleaving transformation in the PMA sublayer, the data stream may be directly AUI lane data or PCS lane data.

[0153] The main steps performed by the receiving side and the transmitting side PMA sublayer in the embodiment of the present application can be Figure 9(a) to Figure 9(d) An example is given in .

[0154] When applicable to the implementation of the physical layer as shown in Figure 4(b), the PMA sublayer is located in a pluggable optical module or a pluggable electrical module and is connected to the upper sublayer through an interface. The main steps performed by the PMA sublayer on the data sending side are shown on the left side of Figure 9(a), and the main steps performed by the PMA sublayer on the data receiving side are shown on the right side of Figure 9(a). The arrows in the figure indicate the direction of data transmission.

[0155] On the data transmission side, PMA recovers PCS Lane data through the first two steps, namely bit demultiplexing or symbol group demultiplexing, AMlock and Deskew. The subsequent interleaving step, namely Distribution and interleave, re-performs new symbol interleaving or convolution interleaving through PCS Lane data. The interleaving step can be implemented in different ways: the interleaving performed in PCS can be deinterleaved first to restore it to a complete RS codeword, and then the 4 codewords are collected for symbol interleaving or convolution interleaving and distributed to the required number of lanes; or the PCS Lane data can be directly arranged in a specific order to obtain the required number of lanes for output without deinterleaving or restoring it to a complete RS codeword. The above interleaving steps can be referred to. Figure 5 and Figure 6 The description of the method shown in FIG9(a) is omitted here. In addition, FIG9(a) also includes a step of symbol group multiplexing or bit multiplexing, which is used to combine data into the number of data channels required by the next sublayer. For other details in FIG9(a), please refer to the above Figure 3 The relevant description of the data sending method shown in FIG. 8( a ) or FIG. 8( b ) is not repeated here. In addition, each step on the data receiving side corresponds to the data sending side, and the relevant description of the data receiving method shown in FIG. 8( a ) or FIG. 8( b ) can be referred to, which is not repeated here.

[0156] When applicable to the implementation of the physical layer as shown in Figure 4(b), the PMA sublayer is located in a pluggable optical module or a pluggable electrical module, and is connected to the previous sublayer through an interface. The main steps performed by the PMA sublayer on the data sending side can also be shown on the left side of Figure 9(b), and the main steps performed by the PMA sublayer on the data receiving side can also be shown on the right side of Figure 9(b), where the arrow indicates the direction of data transmission. Compared with Figure 9(a), the main difference between the steps shown in Figure 9(b) is that the process of symbol group multiplexing or bit multiplexing is included in the interleaving step, and the number of lanes distributed after interleaving is equal to the number of lanes required by the next sublayer. The number of lanes may be the number of physical channels, or it may be equal to the number of PCS lanes. Therefore, a separate mux step is no longer required. The various steps on the data receiving side correspond to the data sending side and will not be repeated here.

[0157] When applicable to the implementation of the physical layer as shown in Figure 4(b), the PMA sublayer is located in a pluggable optical module or a pluggable electrical module, and is connected to the previous sublayer through an interface. The main steps performed by the PMA sublayer on the data sending side can also be as shown on the left side of Figure 9(c), and the main steps performed by the PMA sublayer on the data receiving side can also be as shown on the right side of Figure 9(c), where the arrow indicates the direction of data transmission. Compared with Figure 9(a), the main difference between the steps shown in Figure 9(c) is that the PMA layer performs the FEC encoding step. The various steps on the data receiving side correspond to the data sending side and will not be repeated here.

[0158] When applicable to the implementation of the physical layer as shown in Figure 4(b), the PMA sublayer is located in a pluggable optical module or a pluggable electrical module, and is connected to the previous sublayer through an interface. The main steps performed by the PMA sublayer on the data sending side can also be as shown on the left side of Figure 9(d), and the main steps performed by the PMA sublayer on the data receiving side can also be as shown on the right side of Figure 9(d), where the arrow indicates the direction of data transmission. Compared with Figure 9(b), the main difference between the steps shown in Figure 9(d) is that the PMA layer performs the FEC encoding step. The various steps on the data receiving side correspond to the data sending side and will not be repeated here.

[0159] When applicable to the implementation of the physical layer as shown in Figure 4(a) or Figure 4(c), the PMA sublayer is not connected to the previous sublayer through an interface, and the PMA sublayer can directly obtain lane data. Therefore, compared with Figures 9(a) to (d), when applicable to the implementation of the physical layer as shown in Figure 4(a) or Figure 4(c), the main steps performed by the PMA sublayer on the data receiving side will not include the two steps of bit demultiplexing or symbol group demultiplexing, AM lock and Deskew. Similarly, the main steps performed by the PMA sublayer on the data sending side will not include the two steps of bit demultiplexing or symbol group demultiplexing, AM lock and Deskew. Other steps are similar to Figure 9(a) to Figure 9(d) Similar, no further elaboration is required here.

[0160] The above describes the method for sending and receiving data according to the embodiment of the present application. Corresponding to the above method, the embodiment of the present application also provides an Ethernet device for sending and receiving data.

[0161] Fig.10 is a schematic diagram of the structure of an Ethernet device provided in an embodiment of the present application. The Ethernet device can be used to send or receive data. The Ethernet device can be Figure 3 The Ethernet device in the method of sending data shown. Fig.10 The structure shown in the figure can be implemented by the Ethernet device. Figure 3 It should be understood that the Ethernet device may include more additional structures than the structure shown or omit a part of the structure shown therein, and the embodiment of the present application is not limited to this. Fig.10 As shown, the Ethernet device 1000 includes:

[0162] The PMA circuit 1001 is used to obtain a data stream, which is a data stream encoded by forward error correction (FEC); perform a first data processing process on the data stream to obtain an interleaved data stream, wherein the first data processing process includes interleaving through a first interleaving method; wherein the interleaving type of the first interleaving method is symbol interleaving or convolution interleaving.

[0163] In some possible implementations, the symbol interleaving is performed with a granularity of 10 bits.

[0164] In some possible implementations, the first data processing process further includes: bit multiplexing or symbol group multiplexing.

[0165] In some possible implementations, before interleaving in the first interleaving manner, the first data processing process further includes: bit demultiplexing or symbol group demultiplexing.

[0166] In some possible implementations, before interleaving in the first interleaving manner, the first data processing process further includes: locking an alignment mark AM and de-skewing.

[0167] In some possible implementations, the data stream is a data stream obtained after executing a second data processing process, and the second data processing process includes interleaving through a second interleaving method.

[0168] In some possible implementations, the first interleaving mode and the second interleaving mode have different interleaving depths.

[0169] In some possible implementations, the interleaving depth of the second interleaving mode is 2×RS.

[0170] In some possible implementations, the first data processing process further includes: deinterleaving the second interleaving method.

[0171] In some possible implementations, the second data processing process is performed by a physical coding sublayer PCS or a data terminal equipment extension sublayer DTE_XS.

[0172] In some possible implementations, the interleaving depth of the first interleaving mode is 4×RS.

[0173] In some possible implementations, the channel rate of the interleaved data stream is 200 Gbps.

[0174] In some possible implementations, a rate of an interface through which the PMA circuit receives the data stream is at least one of the following: 200 Gbps or 400 Gbps.

[0175] In some possible implementations, the PMA circuit obtains the data stream from an connection unit interface AUI or a common electrical interface CEI.

[0176] In some possible implementations, the PMA circuit sends the interleaved data stream to a physical medium dependent PMD sublayer.

[0177] The detailed description of the operation performed by the Ethernet device 1000 can be referred to above. Figure 3 The detailed description of the illustrated method embodiment will not be repeated here.

[0178] The Ethernet device 1000 may be an Ethernet chip, an Ethernet forwarding device such as a switch or a router, or a pluggable optical module or electrical module in the Ethernet.

[0179] When the Ethernet device 1000 is an Ethernet chip, the Ethernet chip can be implemented by the structure shown in Figure 4 (a). The PMA circuit 1001 in the Ethernet device 1000 corresponds to the PMA sublayer shown in Figure 4 (a). Optionally, the Ethernet device 1000 also includes PCS and PMD sublayers.

[0180] When the Ethernet device 1000 is a pluggable optical module or electrical module, the pluggable optical module or electrical module can be implemented by the structure shown in FIG. 4(b) or FIG. 4(c). The PMA circuit 1001 in the Ethernet device 1000 corresponds to the PMA sublayer shown in FIG. 4(b) or the PMA sublayer adjacent to the PMD layer shown in FIG. 4(c). Optionally, the Ethernet device 1000 also includes a PMD sublayer.

[0181] When the Ethernet device 1000 is an Ethernet forwarding device such as a switch or a router, the Ethernet device 1000 may include an Ethernet chip, or a pluggable optical module or an electrical module, wherein the Ethernet chip, or the pluggable optical module or the electrical module can perform Figure 3 All or part of the operations in the method.

[0182] Fig.10 8(a) is a schematic diagram of the structure of an Ethernet device provided in an embodiment of the present application. The Ethernet device can be used to send or receive data. The Ethernet device can be the Ethernet device in the method for receiving data shown in FIG. 8(a). Fig.10 The structure shown in FIG8 (a) can be used to perform all or part of the operations in the method shown in FIG8 (a). It should be understood that the Ethernet device may include more additional structures than the structure shown or omit a part of the structure shown therein, and the present application embodiment does not limit this. Fig.10 As shown, the Ethernet device 1000 includes:

[0183] The PMA circuit 1001 is used to obtain a data stream, which is a data stream encoded by forward error correction (FEC); perform a third data processing process on the data stream to obtain a deinterleaved data stream, and the third data processing process includes deinterleaving through a first deinterleaving method; wherein the deinterleaving type of the first deinterleaving method is symbol deinterleaving or convolutional deinterleaving.

[0184] In some possible implementations, the symbol deinterleaving is performed with a granularity of 10 bits.

[0185] In some possible implementations, the third data processing process includes: bit multiplexing or symbol group multiplexing.

[0186] In some possible implementations, the third data processing process includes: bit demultiplexing or symbol group demultiplexing.

[0187] In some possible implementations, the third data processing process includes: alignment mark AM locking and de-skew.

[0188] In some possible implementations, after the PMA circuit performs a third data processing process on the data stream, the method further includes: the PMA circuit interleaving the deinterleaved data stream in a second interleaving manner to obtain a re-interleaved data stream.

[0189] In some possible implementations, the re-interleaved data stream is deinterleaved by a physical coding sublayer PCS or a data terminal equipment extension sublayer DTE_XS.

[0190] In some possible implementations, the interleaving depth of the first deinterleaving mode is 4×RS.

[0191] In some possible implementations, the PMA circuit acquires the data stream, including: the PMA circuit acquires the data stream after sending the interleaved data from a physical medium dependent PMD sublayer.

[0192] For a detailed description of the operations performed by the Ethernet device 1000, reference may be made to the detailed description of the method embodiment shown in FIG. 8(a) above, which will not be repeated here.

[0193] The Ethernet device 1000 may be an Ethernet chip, an Ethernet forwarding device such as a switch or a router, or a pluggable optical module or electrical module in the Ethernet.

[0194] When the Ethernet device 1000 is an Ethernet chip, the Ethernet chip 1000 can be implemented by the structure shown in Figure 4 (a). The PMA circuit 1001 in the Ethernet device 1000 corresponds to the PMA sublayer shown in Figure 4 (a). Optionally, the Ethernet device 1000 also includes PCS and PMD sublayers.

[0195] When the Ethernet device 1000 is a pluggable optical module or electrical module, the pluggable optical module or electrical module can be implemented by the structure shown in FIG. 4(b) or FIG. 4(c). The PMA circuit 1001 in the Ethernet device 1000 corresponds to the PMA sublayer shown in FIG. 4(b) or the PMA sublayer adjacent to the PMD layer shown in FIG. 4(c). Optionally, the Ethernet device 1000 also includes a PMD sublayer.

[0196] When the Ethernet device 1000 is an Ethernet forwarding device such as a switch or a router, the Ethernet device 1000 may include an Ethernet chip, or a pluggable optical module or an electrical module, wherein the Ethernet chip, or the pluggable optical module or the electrical module can perform all or part of the operations in the method shown in FIG. 8( a).

[0197] Fig.11 8(b) is a schematic diagram of the structure of an Ethernet device provided in an embodiment of the present application. The Ethernet device can be used to send data or receive data. The Ethernet device can be the Ethernet device in the method for receiving data shown in FIG. 8(b). Fig.11 The structure shown in FIG8 (b) can be used to perform all or part of the operations in the method shown in FIG8 (b). It should be understood that the Ethernet device may include more additional structures than the structure shown or omit a part of the structure shown therein, and the present application embodiment does not limit this. Fig.11 As shown, the Ethernet device 1000 includes:

[0198] The PMA circuit 1001 is used to obtain a data stream, which is a data stream encoded by forward error correction (FEC); the PMA sublayer performs a third data processing process on the data stream to obtain an interleaved data stream, and the third data processing process includes interleaving the data stream; wherein the interleaving type of the interleaving is symbol interleaving or convolution interleaving.

[0199] In some possible implementations, the symbol interleaving is performed with a granularity of 10 bits.

[0200] In some possible implementations, the interleaved data stream is deinterleaved by a physical coding sublayer PCS or a data terminal equipment extension sublayer DTE_XS.

[0201] In some possible implementations, the interleaving depth of the interleaving is 2×RS.

[0202] In some possible implementations, the third data processing process further includes: bit demultiplexing or symbol group demultiplexing.

[0203] In some possible implementations, the third data processing process further includes: alignment mark AM locking and de-skew.

[0204] In some possible implementations, the third data processing process further includes: bit multiplexing or symbol group multiplexing.

[0205] For the detailed description of the operations performed by the Ethernet device 1000, reference may be made to the detailed description of the method embodiment shown in FIG. 8(b) above, which will not be repeated here.

[0206] The Ethernet device 1000 may be an Ethernet chip, an Ethernet forwarding device such as a switch or a router, or a pluggable optical module or electrical module in the Ethernet.

[0207] When the Ethernet device 1000 is an Ethernet chip, the Ethernet chip can be implemented by the structure shown in Figure 4 (a). The PMA circuit 1001 in the Ethernet device 1000 corresponds to the PMA sublayer shown in Figure 4 (a). Optionally, the Ethernet device 1000 also includes PCS and PMD sublayers.

[0208] When the Ethernet device 1000 is a pluggable optical module or electrical module, the pluggable optical module or electrical module can be implemented by the structure shown in FIG. 4(b) or FIG. 4(c). The PMA circuit 1001 in the Ethernet device 1000 corresponds to the PMA sublayer shown in FIG. 4(b) or the PMA sublayer adjacent to the PMD layer shown in FIG. 4(c). Optionally, the Ethernet device 1000 also includes a PMD sublayer.

[0209] When the Ethernet device 1000 is an Ethernet forwarding device such as a switch or a router, the Ethernet device 1000 may include an Ethernet chip, or a pluggable optical module or an electrical module, wherein the Ethernet chip, or the pluggable optical module or the electrical module can perform all or part of the operations in the method shown in FIG. 8( b).

[0210] See also Fig.12 , Fig.12 FIG. 2 shows a schematic diagram of the structure of an Ethernet device 2100 provided by another exemplary embodiment of the present application. Fig.12 The Ethernet device 2100 shown is used to perform the above Figure 3 The network device 2100 is, for example, an Ethernet forwarding device such as a switch or a router, and the Ethernet device 2100 can be implemented by a general bus architecture.

[0211] like Fig.12 As shown, the Ethernet device 2100 includes: a main control board 2110 and an interface board 2130 .

[0212] The main control board is also called a main processing unit (MPU) or a route processor card. The main control board 2110 is used to control and manage various components in the Ethernet device 2100, including routing calculation, device management, device maintenance, and protocol processing functions. The main control board 2110 includes: a central processing unit 2111 and a memory 2112.

[0213] The interface board 2130 is also called a line processing unit (LPU), a line card (linecard) or a service board. The interface board 2130 is used to provide various service interfaces and realize the forwarding of data packets. The service interface includes but is not limited to an Ethernet interface, a POS (Packet over SONET / SDH) interface, etc., and the Ethernet interface is, for example, a Flexible Ethernet Service Interface (Flexible Ethernet Clients, FlexE Clients). The interface board 2130 includes: a central processing unit 2131, a network processor 2132, a forwarding table entry memory 2134 and a physical interface card (physical interface card, PIC) 2133.

[0214] The central processor 2131 on the interface board 2130 is used to control and manage the interface board 2130 and communicate with the central processor 2111 on the main control board 2110 .

[0215] The network processor 2132 is used to implement the forwarding processing of the message. The network processor 2132 can be in the form of a forwarding chip. The forwarding chip can be a network processor (NP). In some embodiments, the forwarding chip can be implemented by an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA). Specifically, the network processor 2132 is used to forward the received message based on the forwarding table stored in the forwarding table entry memory 2134. If the destination address of the message is the address of the Ethernet device 2100, the message is sent to the CPU (such as the central processor 2131) for processing; if the destination address of the message is not the address of the Ethernet device 2100, the next hop and the output interface corresponding to the destination address are found from the forwarding table according to the destination address, and the message is forwarded to the output interface corresponding to the destination address. Among them, the processing of the uplink message may include: processing of the message input interface, forwarding table search; the processing of the downlink message may include: forwarding table search, etc. In some embodiments, the central processor can also perform the function of the forwarding chip, such as implementing software forwarding based on a general-purpose CPU, so that the forwarding chip is not required in the interface board.

[0216] The physical interface card 2133 is used to implement the physical layer docking function, whereby the original traffic enters the interface board 2130, and the processed message is sent out from the physical interface card 2133. The physical interface card 2133, also called a daughter card, can be installed on the interface board 2130, and is responsible for converting the photoelectric signal into a message and forwarding the message to the network processor 2132 for processing after checking the legitimacy of the message. In some embodiments, the central processor 2131 can also perform the functions of the network processor 2132, such as implementing software forwarding based on a general-purpose CPU, so that the network processor 2132 is not required in the physical interface card 2133.

[0217] Optionally, the Ethernet device 2100 includes a plurality of interface boards, for example, the Ethernet device 2100 further includes an interface board 2140, and the interface board 2140 includes: a central processor 2141, a network processor 2142, a forwarding table entry memory 2144, and a physical interface card 2143. The functions and implementation methods of the components in the interface board 2140 are the same or similar to those of the interface board 2130, and are not described in detail herein.

[0218] Optionally, the Ethernet device 2100 further includes a switching fabric board 2120. The switching fabric board 2120 may also be referred to as a switch fabric unit (SFU). When the network device 2100 has multiple interface boards, the switching fabric board 2120 is used to complete data exchange between the interface boards. For example, the interface board 2130 and the interface board 2140 may communicate via the switching fabric board 2120.

[0219] The main control board 2110 is coupled to the interface board. For example, the main control board 2110, the interface board 2130, the interface board 2140, and the switching network board 2120 are connected to the system backplane through the system bus to achieve intercommunication. In a possible implementation, an inter-process communication (IPC) channel is established between the main control board 2110 and the interface board 2130 and the interface board 2140, and the main control board 2110 and the interface board 2130 and the interface board 2140 communicate through the IPC channel.

[0220] Logically, the Ethernet device 2100 includes a control plane and a forwarding plane. The control plane includes a main control board 2110 and a central processor 2111. The forwarding plane includes various components for performing forwarding, such as a forwarding table entry memory 2134, a physical interface card 2133, and a network processor 2132. The control plane performs functions such as a router, generating a forwarding table, processing signaling and protocol messages, and configuring and maintaining the status of network devices. The control plane sends the generated forwarding table to the forwarding plane. On the forwarding plane, the network processor 2132 forwards the message received by the physical interface card 2133 based on the forwarding table sent by the control plane. The forwarding table sent by the control plane can be stored in the forwarding table entry memory 2134. In some embodiments, the control plane and the forwarding plane can be completely separated and not on the same network device.

[0221] It is worth noting that there may be one or more main control boards, and when there are multiple boards, they may include a primary main control board and a backup main control board. There may be one or more interface boards. The stronger the data processing capability of the network device, the more interface boards are provided. There may also be one or more physical interface cards on the interface board. There may be no switching network board, or there may be one or more switching network boards. When there are multiple switching network boards, they can jointly realize load sharing and redundant backup. In a centralized forwarding architecture, the network device may not need a switching network board, and the interface board is responsible for the processing function of the service data of the entire system. In a distributed forwarding architecture, the network device may have at least one switching network board, and the switching network board is used to realize data exchange between multiple interface boards, providing large-capacity data exchange and processing capabilities. Therefore, the data access and processing capabilities of the network device with a distributed architecture are greater than those of the network device with a centralized architecture. Optionally, the network device may have only one board, that is, no switching board, and the functions of the interface board and the main control board are integrated on the board. In this case, the central processor on the interface board and the central processor on the main control board can be combined into one central processor on the board to perform the functions of the two. This type of network device has low data exchange and processing capabilities (for example, low-end switches or routers and other network devices). The specific architecture to be adopted depends on the specific networking deployment scenario, and no limitation is made here.

[0222] In a specific embodiment, the Ethernet device 2100 corresponds to the above Fig.10 or Fig.11 Ethernet devices shown.

[0223] For example, the Ethernet device 2100 may be Fig.10 or Fig.11 The Ethernet devices shown are switches, routers and other Ethernet forwarding devices. Figure 3The Ethernet chip of the method shown in Figure 8(a) or Figure 8(b) can be located in the main control board 2110, or can also be located in the interface board 2130 or the interface board 2140, and the Ethernet chip can specifically be located in the physical interface card 2133 or 2143.

[0224] See also Fig.13 The embodiment of the present application further provides a communication system 3000, the message processing system comprising: a first Ethernet device 3001 and a second Ethernet device 3002. Optionally, the first Ethernet device 3001 may be a sending-side Ethernet device, executing Figure 3 In the data sending method shown in FIG. 8 , the second Ethernet device 3002 may be a receiving-side Ethernet device, executing the method for receiving data shown in FIG. 8 (a) or FIG. 8 (b).

[0225] An embodiment of the present application also provides a computer-readable storage medium, in which at least one instruction is stored. The instruction is loaded and executed by a processor so that a computer implements any of the above data sending methods or data receiving methods.

[0226] The embodiments of the present application also provide a computer program (product), which, when executed by a computer, can enable a processor or a computer to execute the corresponding steps and / or processes in the above method embodiments.

[0227] An embodiment of the present application also provides a chip, including a processor, for calling and executing instructions stored in a memory, so that a communication device equipped with the chip executes any of the above data sending methods or data receiving methods.

[0228] An embodiment of the present application also provides another chip, including: an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected via an internal connection path, and the processor is used to execute the code in the memory. When the code is executed, the processor is used to execute any of the above data sending methods or data receiving methods.

[0229] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the process or function according to the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, a computer, a server or a data center to another website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integration. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state drive (solid state disk)), etc.

[0230] Those of ordinary skill in the art will appreciate that, in conjunction with the various method steps and modules described in the embodiments disclosed herein, they can be implemented in software, hardware, firmware, or any combination thereof. In order to clearly illustrate the interchangeability of hardware and software, the steps and components of each embodiment have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those of ordinary skill in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0231] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0232] When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer program instructions. As an example, the method of the embodiment of the present application can be described in the context of a machine executable instruction, and the machine executable instruction is such as included in the program module executed in the device on the real or virtual processor of the target. Generally speaking, a program module includes a routine, a program, a library, an object, a class, a component, a data structure, etc., which performs a specific task or realizes a specific abstract data structure. In various embodiments, the function of the program module can be merged or divided between the described program modules. The machine executable instruction for the program module can be executed in a local or distributed device. In a distributed device, the program module can be located in both a local and a remote storage medium.

[0233] The computer program code for realizing the method for the embodiment of the present application can be written in one or more programming languages. These computer program codes can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device, so that the program code, when executed by a computer or other programmable data processing device, causes the function / operation specified in the flow chart and / or block diagram to be implemented. The program code can be executed completely on a computer, partially on a computer, as an independent software package, partially on a computer and partially on a remote computer or completely on a remote computer or server.

[0234] In the context of the embodiments of the present application, computer program codes or related data may be carried by any appropriate carrier to enable a device, apparatus or processor to perform the various processes and operations described above. Examples of carriers include signals, computer readable media, and the like.

[0235] Examples of signals may include electrical, optical, radio, acoustic or other forms of propagated signals, such as carrier waves, infrared signals, etc.

[0236] A machine-readable medium may be any tangible medium that contains or stores a program for or related to an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More detailed examples of machine-readable storage media include an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0237] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0238] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the module is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, or it can be an electrical, mechanical or other form of connection.

[0239] The modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0240] In addition, each functional module in each embodiment of the present application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.

[0241] If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0242] In the present application, the terms "first", "second", etc. are used to distinguish between identical or similar items having substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there a limitation on quantity and execution order. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various examples, a first image may be referred to as a second image, and similarly, a second image may be referred to as a first image. Both the first image and the second image may be images, and in some cases, may be separate and different images.

[0243] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0244] The term "at least one" in this application means one or more, and the term "multiple" in this application means two or more, for example, multiple second messages means two or more second messages. The terms "system" and "network" are often used interchangeably herein.

[0245] It should be understood that the terms used in the description of the various examples herein are only for describing specific examples and are not intended to be limiting. As used in the description of the various examples and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0246] It should also be understood that the term "and / or" used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The term "and / or" is a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this application generally indicates that the associated objects before and after are in an "or" relationship.

[0247] It should also be understood that the term “comprise” (also known as “includes,” “including,” “comprises” and / or “comprising”) when used in this specification specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0248] It should also be understood that the terms "if" and "if" may be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting." Similarly, the phrases "if it is determined that ..." or "if [a stated condition or event] is detected" may be interpreted to mean "upon determining that ..." or "in response to determining that ..." or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0249] It should be understood that determining B based on A does not mean determining B only based on A. B can also be determined based on A and / or other information.

[0250] It should also be understood that the references to "one embodiment", "an embodiment", or "a possible implementation" throughout the specification mean that specific features, structures, or characteristics related to the embodiment or implementation are included in at least one embodiment of the present application. Therefore, the references to "in one embodiment" or "in an embodiment", or "a possible implementation" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0251] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application should be included in the protection scope of the present application.

Claims

1. A method for sending data, characterized in that: The method comprises: The physical medium connection PMA sublayer of the Ethernet device obtains multiple data streams, where the data in the multiple data streams are data streams that are forward error correction FEC encoded in the physical coding sublayer PCS, and the data in the multiple data streams are interleaved in the PCS using a second interleaving mode, where the interleaving depth of the second interleaving mode is 2×RS; The PMA sublayer performs a first data processing process on the multiple data streams to obtain interleaved data streams, wherein the first data processing process includes interleaving the multiple data streams in a first interleaving manner; The PMA sublayer sends the interleaved data stream to the physical medium dependent PMD sublayer; The interleaving type of the first interleaving mode is symbol interleaving or convolution interleaving, and the interleaving depth of the first interleaving mode is 4×RS; The step of interleaving the multiple data streams in a first interleaving manner includes: The PMA sublayer first waits to obtain data of two code words, and then interleaves the data of the two code words with data of two code words that arrive subsequently.

2. The method according to claim 1, characterized in that: The symbol interleaving is performed with a granularity of 10 bits.

3. The method according to claim 1 or 2, characterized in that: The granularity of the symbol interleaving is 1 symbol.

4. The method according to claim 1 or 2, characterized in that: Before interleaving in the first interleaving mode, the first data processing process further includes: locking the alignment mark AM and de-skewing.

5. The method according to claim 1 or 2, characterized in that: The Ethernet device includes at least one of the following: a server, a physical layer PHY chip, a forwarding device, or a pluggable module.

6. The method according to claim 1 or 2, characterized in that: The channel rate of the interleaved data stream is 200 Gbps.

7. The method according to claim 1 or 2, characterized in that: The rate of the interface of the PMA sublayer for receiving the data stream is at least one of the following: 200 Gbps or 400 Gbps.

8. The method according to claim 1 or 2, characterized in that: The PMA sublayer obtains the data stream from the connection unit interface AUI or the common electrical interface CEI.

9. A method for receiving data, characterized in that: The physical medium connection PMA sublayer of the Ethernet device obtains a data stream from the physical medium related PMD sublayer, wherein the data stream is a data stream encoded by forward error correction FEC; The PMA sublayer performs a third data processing process on the data stream to obtain a plurality of deinterleaved data streams, wherein the third data processing process includes deinterleaving the data streams by a first deinterleaving mode, and interleaving the data in the plurality of deinterleaved data streams by a second interleaving mode in a physical coding sublayer PCS, wherein the interleaving depth of the second interleaving mode is 2×RS; The deinterleaving type of the first deinterleaving mode is symbol deinterleaving or convolutional deinterleaving, and the deinterleaving depth of the first deinterleaving mode is 4×RS; The deinterleaving between data streams by using a first deinterleaving mode includes: After the PMA sublayer deinterleaves the data stream, it first waits to obtain data of two code words, and then processes the data of the two code words and the data of two code words that arrive subsequently.

10. The method according to claim 9, characterized in that The symbol deinterleaving is performed with a granularity of 10 bits.

11. The method according to claim 9 or 10, characterized in that: The granularity of the symbol deinterleaving is 1 symbol.

12. The method according to claim 9 or 10, characterized in that The third data processing process also includes: alignment mark AM locking and de-skew.

13. The method according to claim 9 or 10, characterized in that: The Ethernet device includes at least one of the following: a physical layer PHY chip, a forwarding device, or a pluggable module.

14. An Ethernet device, characterized in that: The Ethernet device is used to execute the method according to any one of claims 1-13.

15. A chip, characterized in that: The chip is used to execute the method according to any one of claims 1 to 13.

16. A communication system, characterized in that: The communication system comprises a first Ethernet device and a second Ethernet device, The first Ethernet device is used to execute the method according to any one of claims 1 to 8, and the second Ethernet device is used to execute the method according to any one of claims 9 to 13.

Images