Driving system and display of carbon-based active matrix micro-led

Abstract

The application discloses a carbon-based active matrix Micro-LED driving system and display, and belongs to the field of display control. The system comprises an FPGA controller, a power supply and communication interface module, a power management circuit, a voltage regulation circuit and a control level operational amplifier circuit. The power supply and communication interface module is used for connecting an external power supply and an upper computer. The FPGA controller is connected to the upper computer through the power supply and communication interface module and is used for performing display control on the carbon-based P-type active matrix Micro-LED. The power management circuit is connected to the power supply and communication interface module and is used for converting the external power supply into +5V power supply and -5V power supply and supplying power to each module. The voltage regulation circuit is used for regulating and controlling the +5V power supply and the -5V power supply, can supply power to the VDD end and output linear voltage of 0.5V to +5V and -1.2V to -5V. The control level operational amplifier circuit supplies power to the DATA end and the SCAN end. The driving system can drive and control the carbon-based P-type active matrix Micro-LED, realizes brightness regulation and display of characters and pictures.

Description

Technical Field

[0001] This application belongs to the field of display drivers, and specifically relates to a driving system and display for a carbon-based active matrix Micro-LED. Background Technology

[0002] Carbon-based chips exhibit significant technological advantages over traditional silicon-based chips in several key properties, such as electrical and thermal conductivity, and are expected to become the market mainstream. Carbon-based Micro-LED active-matrix display chips differ from traditional silicon-based Micro-LED active-matrix display chips; the main differences are as follows:

[0003] Traditional silicon-based active-matrix Micro-LED display chips use silicon-based field-effect transistors (FETs), while carbon-based active-matrix Micro-LED display chips use carbon-based FETs, a new type of FET fabricated from a novel material. The semiconductor conductivity characteristics of the two differ significantly. The on / off control and brightness control characteristics of carbon-based FETs differ from those of traditional silicon-based FETs, primarily in that they do not adhere to market-standard high / low level control and are less affected by current.

[0004] The mainstream driving control circuits currently used in the LED display field are completely unsuitable for driving and measuring carbon-based active matrix Micro-LED display chips in terms of control levels and signal refresh frequencies. For example, LED display driver digital chips such as MAX7219, MAX7221, and CD74HC595NSR are only suitable for driving passive matrix LEDs. Although they can forcibly drive some traditional silicon N-type field-effect transistor active matrix Micro-LEDs, they are not suitable for carbon-based active matrix Micro-LED driving circuits. The main reasons are as follows:

[0005] The output level amplitude has only a few selectable levels, which are fixed values, and the output range is discontinuous. The generated control voltage only has high and low levels, such as (0V or 5V), and there is no continuously adjustable range such as (0~5V). However, the testing and display control of carbon-based active matrix Micro-LED display chips require a continuously adjustable range of (-1.2V to -5V, +1.2V to +5V) to meet the requirements.

[0006] The output level refresh frequency is relatively low and the range is narrow, typically 10Hz-1kHz. However, Micro-LEDs have higher requirements for the refresh frequency of the control signal. The testing and display control of carbon-based active matrix Micro-LED display chips require an output level refresh frequency of 60Hz to 6kHz or higher.

[0007] Brightness adjustment in traditional passive matrix LED display control is based on current, not voltage, which differs from the display control of active matrix Micro-LEDs. Furthermore, the control methods and mechanisms of traditional silicon N-type field-effect transistor active matrix Micro-LED displays also differ from those of carbon-based active matrix Micro-LEDs.

[0008] Therefore, a driving system for carbon-based active matrix Micro-LEDs is needed to solve the above problems. Summary of the Invention

[0009] To address the shortcomings of the prior art, this application provides a driving system for a carbon-based active matrix Micro-LED, which can provide power supply and continuous control levels to the carbon-based P-type active matrix Micro-LED via four terminals: VDD, DATA, SCAN, and GND, thereby achieving on / off display control and brightness adjustment, and can also display graphics and text through an FPGA controller.

[0010] The technical effect to be achieved in this application is accomplished through the following solution:

[0011] According to a first aspect of this application, a driving system for a carbon-based active matrix Micro-LED is provided, comprising an FPGA controller, a power supply and communication interface module, a power management circuit, a voltage regulation circuit, and a control level operational amplifier circuit, wherein:

[0012] The power supply and communication interface module is used to connect to an external power supply and a host computer;

[0013] The FPGA controller is connected to the host computer through the power supply and communication interface module and is used for display control of carbon-based P-type active matrix Micro-LED;

[0014] The power management circuit is connected to the power supply and communication interface module and is used to convert external power into +5V power, -5V power and power each module.

[0015] The voltage regulation circuit is used to regulate and control the +5V power supply and the -5V power supply, and output linear voltages of 0.5V to +5V and -1.2V to -5V, wherein the 0.5V to +5V power supply supplies power to the VDD terminal of the carbon-based active matrix Micro-LED.

[0016] The control level operational amplifier circuit is connected to a linear voltage, with an input range of +1.2V to +5V and -1.2V to -5V, to power the DATA and SCAN terminals of the carbon-based active matrix Micro-LED.

[0017] Preferably, the FPGA controller is connected to the power supply and communication interface module via an RS422 digital signal conversion module, and communicates with the host computer.

[0018] Preferably, the +5V power supply of the power management circuit is connected to a voltage reference conversion module, and the voltage reference conversion module outputs 3.3V, 2.5V and 1.8V power supplies for use by the FPGA controller.

[0019] Preferably, the voltage regulation circuit includes a VDD regulated power generation circuit for supplying power to the VDD terminal. The VDD regulated power generation circuit includes a voltage regulator and a digital adjustment potentiometer. The voltage regulator uses a TPS7A7001 chip, and the digital adjustment potentiometer uses an AD5282 chip. The digital adjustment potentiometer is connected to the FPGA controller and converts the digital input from the FPGA controller into an analog resistance value. The voltage regulator is connected to a +5V power supply and the digital adjustment potentiometer, thereby outputting a 0V to +5V regulated power supply to power the VDD terminal.

[0020] Preferably, the voltage regulation circuit further includes a positive level regulation circuit and a negative level regulation circuit. The positive level regulation circuit uses a digital adjustment potentiometer and two linear regulators to output a linear voltage of 0V to +5V. The digital adjustment potentiometer uses an AD5282 chip, and the linear regulator uses a TPS7A7001 chip. The negative level regulation circuit includes an adjustment potentiometer and two analog regulators. The adjustment potentiometer uses an AD8402 chip, and the analog regulator uses an LM337 chip to output a linear voltage of 0V to -5V.

[0021] Preferably, the FPGA controller controls the negative level adjustment circuit via the SPI bus and the positive level adjustment circuit via the IIC bus.

[0022] Preferably, the control level operational amplifier circuit corresponds to the rows and columns of the carbon-based active matrix Micro-LED, and the rows and columns are connected to the I / O terminals of the FPGA controller.

[0023] Preferably, the voltage output of the control level operational amplifier circuit at the DATA terminal is -1.2V to -5V and 1.2V to +5V; the voltage output of the control level operational amplifier circuit at the SCAN terminal is -1.2V to -5V and +1.2V to +5V.

[0024] Preferably, the control level operational amplifier circuit includes an operational amplifier, the input terminal of which is connected to the FPGA controller, the power input terminal of which is connected to the voltage regulation circuit, and the output terminal of which is connected to the DATA terminal and the SCAN terminal.

[0025] According to a second aspect of this application, a display is provided that employs the above-described driving system for carbon-based active matrix Micro-LEDs and the carbon-based active matrix Micro-LEDs.

[0026] According to one embodiment of this application, the beneficial effects of using this application are as follows:

[0027] It provides the necessary power supply and continuous control level for four terminals: VDD, DATA, SCAN, and GND. The driving voltage range is: VDD (0.5V~+5V), DATA (-1.2V~-5V, +1.2V~+5V), and SCAN (-1.2V~-5V, +1.2V~+5V) to achieve on / off display control;

[0028] The output level refresh frequency can be output in the range of 1Hz to 100kHz; it meets the requirements of 60Hz to 6kHz or higher for the testing and display control of carbon-based P-type active matrix Micro-LED display chips.

[0029] Adjustable display brightness is achieved by controlling the driving voltage. Brightness adjustment is achieved through voltage combinations at the VDD terminal (0.5V~+5V), DATA terminal (-1.2V~-5V, +1.2V~+5V), and SCAN terminal (-1.2V~-5V, +1.2V~+5V).

[0030] Using an FPGA controller, it can control carbon-based P-type active matrix Micro-LED displays of English and Chinese characters, black and white images, and dynamic images. Attached Figure Description

[0031] To more clearly illustrate the embodiments of this application or the existing technical solutions, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a circuit structure block diagram of a driving system for a carbon-based active matrix Micro-LED according to an embodiment of this application;

[0033] Figure 2 This is a schematic diagram of the structure of a carbon-based active matrix Micro-LED in one embodiment of this application;

[0034] Figure 3 for Figure 1 Circuit diagram of medium voltage regulation circuit;

[0035] Figure 4 for Figure 1 Circuit diagram of the neutral level adjustment circuit;

[0036] Figure 5 for Figure 1 Circuit diagram of the negative level adjustment circuit;

[0037] Figure 6 for Figure 1 The circuit diagram of the control level operational amplifier circuit. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0039] like Figure 1 As shown, a driving system for a micro-LED active matrix according to an embodiment of this application includes an FPGA controller, a power supply and communication interface module, a power management circuit, a voltage regulation circuit, and a control level operational amplifier circuit, wherein:

[0040] The power supply and communication interface module is used to connect to an external power supply and a host computer.

[0041] The FPGA controller, connected to the host computer via a power supply and communication interface module, is used for display control of carbon-based P-type active matrix Micro-LEDs.

[0042] The power management circuit connects to the power supply and communication interface module and is used to convert external power into +5V and -5V power to power various modules.

[0043] The voltage regulation circuit is used to regulate and control the +5V and -5V power supplies, and output linear voltages of 0.5V to +5V and -1.2V to -5V. The 0.5V to +5V power supply powers the VDD terminal of the carbon-based active matrix Micro-LED.

[0044] The control level operational amplifier circuit is connected to linear voltages of +1.2V to +5V and -1.2V to -5V to power the DATA and SCAN terminals of the carbon-based active matrix Micro-LED.

[0045] In this embodiment, to improve versatility, the drive system adopts a four-wire power supply method, such as... Figure 2The schematic diagram of the 2T1C structure of the carbon-based Micro-LED is shown. This driving system provides the necessary VDD, DATA, SCAN, and GND terminal levels, and is compatible with both 2T1C and 1T1D structures to realize the display control of carbon-based P-type active matrix Micro-LEDs.

[0046] In one embodiment of this application, the FPGA controller connects to the power supply and communication interface module via an RS422 digital signal conversion module, and communicates with the host computer. RS422 is a differential signal transmission, supports full-duplex communication, and can perform simultaneous sending and receiving operations, effectively reducing noise interference and improving signal stability and reliability.

[0047] In one embodiment of this application, the power management circuit converts the externally input +24V voltage into +5V and -5V power supplies to power the circuit module. The +5V power supply can be output through the voltage reference conversion module to provide 3.3V, 2.5V and 1.8V power supplies for use by the FPGA controller.

[0048] like Figure 3 As shown, in one embodiment of this application, the voltage regulation circuit includes a VDD regulating power generation circuit for supplying power to the VDD terminal. The VDD regulating power generation circuit includes a voltage regulator and a digital adjustment potentiometer. The voltage regulator uses a TPS7A7001 chip, and the digital adjustment potentiometer uses an AD5282 chip, used to output +5V and -5V power supplies. Wherein:

[0049] The AD5282 potentiometer generates two 8-bit resolution resistance values. W1 and W2 are sliding adjustment latches, and A and B are full-scale resistance values. Both A and W, and W and B, can generate adjustable resistance values, and these are non-polarized and can be connected in series. Pins 7 and 8 receive the IIC control bus timing, converting the input digital value into a high-precision analog resistance value. The adjustable resistance value R' is output from B1 to B2 after W1 and W2 are shorted and connected in series.

[0050] The TPS7A7001 voltage regulator features a high power supply rejection ratio, helping to reduce the impact of power line noise on the output voltage. Pin 3 of the TPS7A7001 regulator connects to the +5V input power supply, pin 2 connects to the enable control, pins 6 and 7 connect to the adjustment resistor R' generated by the AD5282, and pin 7 is connected to the reference resistor R3 between pin 7 and GND. The output adjustment voltage VDD at pin 6 is 0.5*(1+R' / R3), with an output range of 0.5≤VDD≤+5V.

[0051] like Figure 4 and Figure 5As shown, the voltage regulation circuit in one embodiment of this application further includes a positive level regulation circuit and a negative level regulation circuit. The positive level regulation circuit uses a TPS7A7001 linear regulator to output a linear voltage of 0.5V to +5V. The negative level regulation circuit uses an AD8402 digital potentiometer and an LM337 analog regulator to output a linear voltage of -1.2V to -5V.

[0052] The positive level adjustment circuit is based on the same principle as the VDD power supply generation circuit. The difference is that W1 and W2 of the AD5282 are not shorted. W1 to B1 and W2 to B2 each provide an adjustment potentiometer R' for a TPS7A7001. Pin 3 of the TPS7A7001 regulator is connected to the input power supply +5V, and pin 7 is connected to GND via a reference resistor R6. Pin 6 outputs an adjustable voltage V0+ / V1+ = 0.5*(1+R' / R6), with an output range of 0.5V ≤ V0+ / V1+ ≤ +5V. The two TPS7A7001 regulators provide the adjustable positive level for the DATA and SCAN terminals, respectively.

[0053] In the negative level adjustment circuit, the AD8402 adjustment potentiometer is connected to two LM337 analog voltage regulators, which output V0- and V1- respectively.

[0054] The AD8402 potentiometer generates two 8-bit resolution resistance values. W1 and W2 are sliding adjustment latches, and A and B are full-scale resistance values. Both A-to-W and W-to-B can generate adjustable resistance values, and these are non-polarized and can be connected in series. Pins 7, 8, and 9 receive the SPI control bus timing, converting the input digital value into a high-precision analog resistance value. The adjustable resistance value R' is output by W1-to-B1 and W2-to-B2 respectively.

[0055] Pin 1 of the LM337 analog voltage regulator is the input power supply -5V. Pins 2 and 3 are connected to a reference resistor R. Pin 2 is connected to GND via an adjustment resistor R'. Pin 3 is connected to GND as the output voltage V0- / V1- = -1.2*(1+R' / R), with an output range of -1.2V ≤ V0- / V1- ≤ -5V. Two LM337 analog voltage regulators provide the regulated negative level to the DATA and SCAN terminals, respectively.

[0056] like Figure 6The control level operational amplifier circuit in one embodiment of this application includes an AD8052 operational amplifier. Pin 3 of the operational amplifier is connected to the FPGA controller, pin 2 is connected to a 1.2V power supply, and the power input terminal of the operational amplifier is connected to a positive and negative voltage adjustment circuit (which can control the input V+ and V- power supply ranges: -1.2V to -5V and +1.2V to +5V). The output terminal of pin 1 of the operational amplifier is connected to the DATA terminal and the SCAN terminal. This circuit is an open-loop comparator circuit. When the FPGA input level at pin 3 is high (approximately 3.3V), exceeding the 1.2V level at pin 2, the output voltages Vscan = V0+ and Vdata = V1+. Similarly, when the FPGA input level at pin 3 is low (approximately 0V), lower than the 1.2V level at pin 2, the output voltages Vscan = V0- and Vdata = V1-.

[0057] In one embodiment of this application, since the AD8402 requires SPI bus connection control and the AD5282 requires IIC bus connection control, the FPGA controller controls the negative level adjustment circuit through the SPI bus and the positive level adjustment circuit through the IIC bus to generate adjusted positive voltage amplitudes V0+ and V1+ and adjusted negative voltage amplitudes V0- and V1-. The FPGA controller's I / O terminals control the operational amplifier circuits corresponding to the rows and columns of the carbon-based active matrix Micro-LED. The voltage specifications of the SCAN and DATA terminals are ±1.2V to ±5V, and the amplitude is determined by the positive and negative voltage adjustment modules; their high and low timing and change frequency are jointly controlled by the FPGA and the AD8052 amplifier. The official datasheet of the AD8052 specifies a conversion rate of 100MHz, while the configurable rate of the FPGA's clock module is much greater than 100MHz. To ensure the stability of the working waveform, considering that the design margin is much greater than the actual application requirements (60Hz to 6kHz), the circuit output level refresh frequency range is set to 1Hz to 100kHz.

[0058] According to a second aspect of this application, a display is provided that employs the above-described driving system for carbon-based active matrix Micro-LEDs and the carbon-based active matrix Micro-LEDs.

[0059] According to one embodiment of this application, the beneficial effects of using this application are as follows:

[0060] It provides the necessary power supply and continuous control level for four terminals: VDD, DATA, SCAN, and GND. The driving voltage range is: VDD (0.5V~+5V), DATA (-1.2V~-5V, +1.2V~+5V), and SCAN (-1.2V~-5V, +1.2V~+5V) to achieve on / off display control;

[0061] The output level refresh frequency can be in the range of 1Hz to 100KHz; it meets the requirements of 60Hz to 6kHz or higher for the testing and display control of carbon-based P-type active matrix Micro-LED display chips.

[0062] Adjustable display brightness is achieved through controllable driving voltage. Brightness adjustment is achieved by varying the voltage combinations at the VDD terminal (0.5V~+5V), DATA terminal (-1.2V~-5V, +1.2V~+5V), and SCAN terminal (-1.2V~-5V, +1.2V~+5V); the specific principle is as follows... Figure 2 As shown:

[0063] Each cell contains two TFTs and one capacitor. TFTs are off when high and on when low. The display uses a progressive scan mode. A low-level signal to the SCAN terminal turns on all T1s in that row. T1s write the DATA voltage to the capacitor. Different DATA voltages control the switching of T2s, converting the DATA voltage into a current signal, which in turn controls the brightness of that pixel. For example, a low-level signal to the DATA terminal turns on the T1 of that pixel, charging the capacitor. When the SCAN and DATA signals are removed, the capacitor maintains the voltage of the gate electrode of T2, allowing the pixel to maintain its brightness for a period of time until the next scan signal voltage arrives. The TFT is off when high level (+3V typical value) and on when low level (-3V typical value). When a +3V voltage is applied to VDD, a -3V typical value voltage is applied to the SCAN terminal row by row to turn on T1 row by row. When the DATA terminal is fully input with a +3V typical value, all LEDs are dark; when the DATA terminal is fully input with a -3V typical value, all LEDs are bright. The brightness of the LED is affected by the voltage (-1.2V to -5V, +1.2V to +5V) between the DATA terminal and GND.

[0064] Using an FPGA controller, it can control carbon-based P-type active matrix Micro-LED displays of English and Chinese characters, black and white images, and dynamic images.

[0065] It should be noted that the above detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0066] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0067] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0068] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or apparatus.

[0069] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways, such as rotated 90 degrees or in other orientations, and the spatial relative descriptions used herein will be interpreted accordingly.

[0070] In the detailed description above, reference has been made to the accompanying drawings, which form part of this document. In the drawings, similar symbols typically identify similar parts unless the context otherwise indicates otherwise. The illustrated embodiments described in the detailed specification, drawings, and claims are not intended to be limiting. Other embodiments may be used and other changes may be made without departing from the spirit or scope of the subject matter presented herein.

[0071] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A driving system of carbon-based active matrix Micro-LED, characterized in that, The FPGA controller, the power supply and communication interface module, the power management circuit, the voltage regulation circuit and the control level operational amplifier circuit are included. The power supply and communication interface module is used for connecting an external power supply and a host computer. The FPGA controller is connected to the host computer through the power supply and communication interface module and is used for performing display control of the carbon-based P-type active matrix Micro-LED. The power management circuit is connected to the power supply and communication interface module and is used for converting the external power supply into +5V power supply and -5V power supply and supplying power to each module. The voltage regulation circuit is used for adjusting and controlling the +5V power supply and the -5V power supply and outputting linear voltages of 0.5V~+5V and -1.2V~-5V, wherein the 0.5V~+5V power supply is used for supplying power to the VDD end of the carbon-based active matrix Micro-LED; the voltage regulation circuit includes a VDD adjustment power supply generation circuit used for supplying power to the VDD end, the VDD adjustment power supply generation circuit includes a voltage stabilizer and a digital adjustment potentiometer, the voltage stabilizer adopts a TPS7A7001 chip, the digital adjustment potentiometer adopts an AD5282 chip, the digital adjustment potentiometer is connected to the FPGA controller, converts digital quantities input by the FPGA controller into analog resistance values, and the voltage stabilizer is connected to the +5V power supply and the digital adjustment potentiometer, so as to output the 0.5V~+5V adjustment power supply for supplying power to the VDD end. The voltage regulation circuit further includes a positive level adjustment circuit and a negative level adjustment circuit, the positive level adjustment circuit adopts a digital adjustment potentiometer and two linear voltage stabilizers, outputs linear voltages of 0.5V~+5V, wherein the digital adjustment potentiometer adopts an AD5282 chip, and the linear voltage stabilizers adopt TPS7A7001 chips; the negative level adjustment circuit includes an adjustment potentiometer and two analog voltage stabilizers, the adjustment potentiometer adopts an AD8402 chip, the analog voltage stabilizers adopt LM337 chips, and linear voltages of -1.2V~-5V are output. The control level operational amplifier circuit is connected to linear voltages, the input range is selected from +1.2V~+5V and -1.2V~-5V, and the control level operational amplifier circuit supplies power to the DATA end and the SCAN end of the carbon-based active matrix Micro-LED. 2.The carbon-based active-matrix Micro-LED driving system of claim 1, wherein, The FPGA controller is connected to the power supply and communication interface module through an RS422 digital signal conversion module and is connected to the host computer for communication. 3.The carbon-based active-matrix Micro-LED driving system of claim 1, wherein, The +5V power supply of the power management circuit is connected to a voltage reference conversion module, the voltage reference conversion module outputs 3.3V, 2.5V and 1.8V power supplies for the FPGA controller. 4.The carbon-based active matrix Micro-LED driving system of claim 1, wherein, The FPGA controller controls the negative level adjustment circuit through an SPI bus and controls the positive level adjustment circuit through an IIC bus. 5.The carbon-based active matrix Micro-LED driving system of claim 1, wherein, The control level operational amplifier circuit corresponds to rows and columns of the carbon-based active matrix Micro-LED, and the rows and columns are connected to IO ends of the FPGA controller.

6. The carbon-based active matrix Micro-LED driving system according to claim 5, wherein, The voltage specification of the control level operational amplifier circuit output at the DATA end is -1.2V~ -5V and 1.2V~ +5V; the voltage specification of the control level operational amplifier circuit output at the SCAN end is -1.2V~ -5V and +1.2V~ +5V.

7. The carbon-based active matrix Micro-LED driving system according to claim 5, wherein, The control level operational amplifier circuit comprises an operational amplifier, an input end of the operational amplifier is connected to the FPGA controller, a power supply input end of the operational amplifier is connected to the voltage regulating circuit, and an output end of the operational amplifier is connected to the DATA end and the SCAN end.

8. A display, characterized by The carbon-based active matrix Micro-LED driving system and the carbon-based active matrix Micro-LED of any one of claims 1 to 7.

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