A hardware Trojan protection method and system based on observability

Abstract

The application discloses a hardware Trojan protection method and system based on observability, and relates to the technical field of hardware circuit security, so as to solve the problem that a hardware Trojan is difficult to be found after being inserted into a circuit, and comprises the following steps: modeling circuit netlist information by constructing a directed cyclic graph; calculating the observability of internal nodes according to the constructed directed cyclic graph, and judging the visibility of the logic values of the internal nodes of the circuit; improving the observability of the nodes by iteratively analyzing and inserting XOR / XNOR gates at appropriate positions; and restoring the function of the circuit. The application improves the pertinence and effectiveness of the protection strategy, enhances the resistance and reliability of the circuit, and reduces the success rate of hardware Trojan attacks, so that the stability and reliability of the circuit performance are maintained while the security is improved.

Description

Technical Field

[0001] This invention relates to the field of hardware circuit security technology, specifically to a hardware Trojan protection method and system based on observability. Background Technology

[0002] Many design companies outsource the manufacturing process of integrated circuits to third-party factories to reduce costs and increase iteration speed. Furthermore, to save on R&D costs and accelerate time-to-market, some companies use third-party intellectual property. These practices indirectly lead to numerous security issues.

[0003] Hardware Trojans are among the most serious hardware security problems. They can insert themselves into circuits at many stages of the integrated circuit development process, such as design, manufacturing, testing, assembly, and packaging. When certain special signals are received, this part of the circuit is activated and performs actions detrimental to the user, such as stealing confidential information, degrading performance, or damaging the system.

[0004] Hardware Trojans typically consist of a trigger circuit and a payload circuit. The trigger circuit activates upon receiving a very limited number of specific signals, making this part of the circuit extremely difficult to detect. The payload circuit may be an XOR gate that receives the output of the trigger circuit and the output of the attacked module in the original circuit. When the trigger circuit is not triggered, the payload output remains unchanged compared to the output signal of the original circuit. However, once the trigger circuit is activated, the payload circuit will flip the original output to achieve its purpose of attacking the original circuit. Summary of the Invention

[0005] In view of the above-mentioned problems, the present invention is proposed.

[0006] Therefore, the technical problem to be solved is that low observability nodes in hardware circuits are easily inserted with hardware Trojans and are difficult to detect after insertion. To solve the above technical problem, the present invention provides the following technical solution: a hardware Trojan protection method based on observability, comprising: modeling circuit netlist information by constructing a directed cyclic graph;

[0007] The observability of internal nodes is calculated based on the constructed directed cyclic graph, and the visibility of the logic values ​​of the internal nodes of the circuit is determined.

[0008] Through iterative analysis and insertion at appropriate locations Gates are used to improve the observability of nodes;

[0009] The circuit's function is restored based on the new circuit netlist with enhanced observability.

[0010] As a preferred embodiment of the hardware Trojan protection method based on observability described in this invention, the construction of the directed cyclic graph includes using the input, output and all intermediate node information of the circuit netlist to construct forward and reverse directed cyclic graphs to simulate the structure and workflow of the hardware circuit.

[0011] In a positive loop diagram, the circuit's initial input terminal PI leads to its final output terminal PO.

[0012] The reverse loop diagram shows the circuit's final output terminal PO leading to the initial input terminal PI.

[0013] As a preferred embodiment of the hardware Trojan protection method based on observability described in this invention, the calculation of the observability of internal nodes includes,

[0014] Observability reflects the visibility of the logic values ​​of the internal nodes of the circuit at the final output terminal PO;

[0015] The observability of nodes is calculated by grouping them into paths on a cyclic graph, using the following formula:

[0016]

[0017] in, Represents the observability value of a node. This represents the level of impact after a node sends an abnormal signal. This indicates the number of inputs that will cause a low-level abnormality at the node. This indicates the level of impact caused by a low-level anomaly. This indicates the number of inputs that would cause a high-level abnormality at the node. This indicates the level of impact that a high-level anomaly will cause.

[0018] As a preferred embodiment of the hardware Trojan protection method based on observability described in this invention, the step of improving the observability of nodes includes:

[0019] Build a logical cone for all ends and complete the initialization;

[0020] The logical cone comprises the set of all nodes that reach a specific node;

[0021] The calculated observability values ​​are sorted, and the node with the lowest observability is identified.

[0022] Iterative analysis is used to find the lowest observable node, and an insertion is performed at the lowest observable node. Gates enhance observability;

[0023] When inserting a door, consider the influence of previously inserted doors;

[0024] Randomly select the second input node of the insertion gate;

[0025] Update the circuit netlist and node observability values ​​after the insertion gate;

[0026] Repeat the above steps until the preset number of iterations is reached.

[0027] As a preferred embodiment of the hardware Trojan protection method based on observability described in this invention, the iterative analysis includes location search and circuit modification;

[0028] The location search includes,

[0029] Calculate the node position with the lowest observability, and insert a node driven by this node at the lowest observable node position. Door;

[0030] Consider the impact of previously inserted gates on the calculation;

[0031] If the predecessor and successor nodes on a path have the same minimum observability, then the successor node is selected for enhancement.

[0032] Randomly select a logical cone that does not contain either the node to be enhanced or the node to be enhanced;

[0033] The nodes to be enhanced are those whose observability is increased due to modifications in the circuit structure.

[0034] If no logical cone containing both the node to be enhanced and the node to be enhanced is found, then the next node with the lowest observability is searched to update the node to be enhanced, and the above steps are repeated.

[0035] Determine the logic cone that does not contain any augmenting nodes and the nodes to be augmented, where the original output is considered to be inserted. The second input to the door.

[0036] As a preferred embodiment of the hardware Trojan protection method based on observability described in this invention, the circuit modification includes:

[0037] After the nodes to be enhanced are identified in the location search phase, the circuit modification phase begins.

[0038] Randomly select a logic cone from all logic cones that is not affected by the node to be enhanced or any previously enhanced nodes;

[0039] Use the original output of a random node in the selected logic cone as the second input node of the gate circuit to be inserted.

[0040] Using the node to be enhanced and the selected second input node as input, insert a Door;

[0041] Inserted The output of the gate replaces the original output of the node to be enhanced and is connected to the input of the next logic gate to which the original output of the node to be enhanced was connected;

[0042] The circuit netlist is updated using the new topology information after the insertion gate;

[0043] Recalculate the observability values ​​of all nodes in the circuit after the insertion gate;

[0044] If the current iteration count has not reached the preset value, return to the position search phase, redetermine the next node to be enhanced, and perform iterations until the preset iteration count is reached;

[0045] The result is a new circuit netlist with enhanced observability.

[0046] As a preferred embodiment of the hardware Trojan protection method based on observability described in this invention, wherein: based on the enhanced circuit netlist, all nodes that were marked as nodes to be enhanced in the previous enhancement process are found;

[0047] For each node to be enhanced, trace back to all its predecessor nodes and construct the logical cone of that node;

[0048] If the enhancement node is adopted The node that is enhanced by the gate,

[0049] Check the inserted The two input nodes of the gate;

[0050] Enumerate all possible combinations of input patterns for these two input nodes;

[0051] Record the input pattern combinations that make the output of the node to be enhanced to 1;

[0052] Use these input patterns as input patterns for the lookup table (LUT);

[0053] The modified output of the node to be enhanced is used as the input to the lookup table LUT;

[0054] If the enhancement node is adopted The node that is enhanced by the gate,

[0055] Check the inserted The input node of the gate;

[0056] Enumerate all possible input patterns for this input node;

[0057] Record the input patterns that cause the output of the node to be enhanced to be 0;

[0058] Use these input patterns as input patterns for the lookup table (LUT);

[0059] The modified output of the node to be enhanced is used as the input to the lookup table LUT;

[0060] Design the output of the lookup table (LUT) so that it can invert the modified output signal accordingly;

[0061] Using the output of the lookup table LUT and the modified output of the node to be enhanced as input, a new node is randomly inserted. Gate circuits;

[0062] Insert new The output of the gate is the restored output of that node;

[0063] Update the circuit netlist, repeat the above steps to cover all nodes to be enhanced, and finally obtain the restored circuit netlist.

[0064] Another objective of this invention is to provide a hardware Trojan protection system based on observability. To solve the above-mentioned technical problems, this invention provides the following technical solution: a hardware Trojan protection system based on observability, comprising: a circuit modeling module, an observability calculation module, an observability enhancement module, and a circuit restoration module;

[0065] The circuit modeling module is used to construct forward cyclic graphs and reverse cyclic graphs based on the input, output and all intermediate node information of the netlist.

[0066] The observability calculation module is used to quantify the impact of each node's anomaly on the circuit using a formula, group the nodes according to the reachable path, and calculate the observability value for each group.

[0067] The observability enhancement module is used for initialization and iterative analysis until all the lowest observability nodes are affected;

[0068] The circuit restoration module is used to find all the enhanced nodes, construct their logic cones, design a lookup table output to invert the modified signal, and use the lookup table output and the modified signal as inputs to insert a new gate to obtain the restoration output, update the netlist, cover all enhanced nodes, and restore the circuit.

[0069] A computer device includes a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the hardware Trojan protection method based on observability as described above.

[0070] A computer-readable storage medium having a computer program stored thereon, characterized in that, when the computer program is executed by a processor, it implements the steps of the hardware Trojan protection method based on observability as described above.

[0071] The beneficial effects of this invention are as follows: By constructing a directed cyclic graph to model the circuit netlist information, accurate circuit modeling is achieved, laying the foundation for subsequent observability analysis and optimization; the observability of internal nodes is calculated based on the constructed directed cyclic graph, identifying and evaluating the potential locations where hardware trojans may lurk, thus improving the targeting and effectiveness of protection strategies; the observability of nodes is improved through iterative analysis and the insertion of gates at appropriate locations, enhancing the circuit's resistance and reliability and reducing the success rate of hardware trojan attacks; based on the new circuit netlist with enhanced observability, the circuit's function is restored, maintaining the stability and reliability of circuit performance while improving security. Attached Figure Description

[0072] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0073] Figure 1 This is a schematic diagram of the terminal structure in the first embodiment of the present invention;

[0074] Figure 2 This is a flowchart illustrating the process in the first embodiment of the present invention;

[0075] Figure 3 This is a schematic diagram of the structure of a computer device in the third embodiment of the present invention.

[0076] Figure 4 This is a hardware Trojan structure diagram from the second embodiment of the present invention; Detailed Implementation

[0077] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0078] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0079] Example 1

[0080] Reference Figure 1 This is one embodiment of the present invention, which provides a hardware Trojan protection method based on observability.

[0081] First, the observability-based hardware Trojan protection method provided in this application can be applied to, for example... Figure 1 In the terminal shown. For example... Figure 1 As shown, the terminal may include one or two ( Figure 1 Only one processor and a memory for storing data are shown in the diagram. The processor may be, but is not limited to, a processing system such as a microprocessor (MCU) or a programmable logic device (FPGA). The terminal may also include transmission devices for communication functions and input / output devices. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the terminal described above. For example, the terminal may also include components that are larger than... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0082] The memory can be used to store computer programs, such as the computer program corresponding to the observability-based hardware Trojan protection method in this embodiment. The processor executes various functional applications and data processing by running the computer program stored in the memory, thereby implementing the above-described method. The memory may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage systems, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include memory remotely located relative to the processor, and these remote memories can be connected to the terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0083] The transmission device is used to receive or send data via a network. This network includes a wireless network provided by the terminal's communication provider. In one example, the transmission device includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device may be a Radio Frequency (RF) module, used for wireless communication with the Internet.

[0084] Reference Figures 1-4 This invention provides a hardware Trojan protection method based on observability, which can be applied to... Figure 1 Taking the terminal in the example, the explanation includes the following steps:

[0085] S1: Model the circuit netlist information by constructing a directed cyclic graph.

[0086] S1.1: Constructing a directed cyclic graph involves using the input, output, and all intermediate node information of the circuit netlist to construct forward and reverse directed cyclic graphs to simulate the structure and workflow of the hardware circuit.

[0087] In a positive loop diagram, the circuit's initial input terminal PI leads to its final output terminal PO.

[0088] The reverse loop diagram shows the circuit's final output terminal PO leading to the initial input terminal PI.

[0089] S2: Calculate the observability of internal nodes based on the constructed directed cyclic graph, and determine the visibility of the logic values ​​of the internal nodes of the circuit.

[0090] S2.1: Calculating the observability of internal nodes includes,

[0091] Observability reflects the visibility of the logic values ​​of the internal nodes of the response circuit at the final output terminal PO;

[0092] The observability of nodes is calculated by grouping them into paths on a cyclic graph, using the following formula:

[0093]

[0094] in, Represents the observability value of a node. This represents the level of impact after a node sends an abnormal signal. This indicates the number of inputs that will cause a low-level abnormality at the node. This indicates the level of impact caused by a low-level anomaly. This indicates the number of inputs that would cause a high-level abnormality at the node. This indicates the level of impact that a high-level anomaly will cause.

[0095] S3: Through iterative analysis and insertion at appropriate positions Gates are used to improve the observability of nodes.

[0096] S3.1: Construct a logical cone for all ends and complete the initialization;

[0097] A logical cone represents the set of all nodes that can be reached from a specific node;

[0098] The calculated observability values ​​are sorted to identify the nodes with the lowest observability.

[0099] Iterative analysis is used to find the lowest observable node, and an insertion is performed at the lowest observable node. Gates enhance observability;

[0100] When inserting a gate, consider the impact of previously inserted gates to avoid affecting other logic cones;

[0101] Randomly select the second input node of the insertion gate to increase diversity;

[0102] Update the circuit netlist and node observability values ​​after the insertion gate;

[0103] Repeat the above steps until the preset number of iterations is reached.

[0104] S3.2: Iterative analysis includes location search and circuit modification;

[0105] Location search includes,

[0106] Calculate the node position with the lowest observability, and insert a node driven by that node at that lowest observability node position. Door;

[0107] Consider the impact of previously inserted gates on the computation;

[0108] If the predecessor and successor nodes on a path have the same minimum observability, then the successor node is selected for enhancement.

[0109] The increased observability of successor nodes also improves the observability of predecessor nodes;

[0110] Randomly select a logical cone that does not contain either the node to be enhanced or the node to be enhanced;

[0111] The nodes should be enhanced to have increased observability due to modifications in the circuit structure;

[0112] If no logical cone containing both the node to be enhanced and the node to be enhanced is found, then the next node with the lowest observability is searched to update the node to be enhanced, and the above steps are repeated.

[0113] A logic cone containing neither augmenting nodes nor nodes to be augmented is determined, where the original output is considered to be inserted. The second input to the door;

[0114] That is, both the unaffected nodes and the nodes to be enhanced drive the process. Door.

[0115] S3.3: Circuit modifications include,

[0116] After the nodes to be enhanced are identified in the location search phase, the circuit modification phase begins.

[0117] Randomly select a logic cone from all logic cones that is not affected by the node to be enhanced or any previously enhanced nodes;

[0118] Use the original output of a random node in the selected logic cone as the second input node of the gate circuit to be inserted.

[0119] Using the node to be enhanced and the selected second input node as input, insert a Door;

[0120] Inserted The output of the gate replaces the original output of the node to be enhanced and is connected to the input of the next logic gate to which the original output of the node to be enhanced was connected;

[0121] The circuit netlist is updated using the new topology information after the insertion gate;

[0122] Recalculate the observability values ​​of all nodes in the circuit after the insertion gate;

[0123] If the current iteration count has not reached the preset value, return to the position search phase, redetermine the next node to be enhanced, and perform iterations until the preset iteration count is reached;

[0124] The result is a new circuit netlist with enhanced observability.

[0125] S4: Restore the function of the circuit based on the new circuit netlist with enhanced observability.

[0126] S4.1: Based on the enhanced circuit netlist, find all nodes that were marked as nodes to be enhanced during the previous enhancement process;

[0127] For each node to be enhanced, trace back to all its predecessor nodes and construct the logical cone of that node;

[0128] If the enhancement node is adopted The node that is enhanced by the gate,

[0129] Check the inserted The two input nodes of the gate;

[0130] Enumerate all possible combinations of input patterns for these two input nodes;

[0131] Record the input pattern combinations that make the output of the node to be enhanced equal to 1;

[0132] Use these input patterns as input patterns for the lookup table (LUT);

[0133] The modified output of the node to be enhanced is used as the input to the lookup table LUT;

[0134] If the enhancement node is adopted The node that is enhanced by the gate,

[0135] Check the inserted The input node of the gate;

[0136] Enumerate all possible input patterns for this input node;

[0137] Record the input patterns that cause the output of the node to be enhanced to be 0;

[0138] Use these input patterns as input patterns for the lookup table (LUT);

[0139] The modified output of the node to be enhanced is used as the input to the lookup table LUT;

[0140] Design the output of the lookup table (LUT) so that it can invert the modified output signal accordingly;

[0141] Using the output of the lookup table LUT and the modified output of the node to be enhanced as input, a new node is randomly inserted. Gate circuits;

[0142] Insert new The output of the gate is the restored output of that node;

[0143] Update the circuit netlist, repeat the above steps to cover all nodes to be enhanced, and finally obtain the restored circuit netlist, which has the same function as the original circuit.

[0144] Example 2

[0145] As an embodiment of the present invention, a hardware Trojan protection system based on observability is provided, including: a circuit modeling module, an observability calculation module, an observability enhancement module, and a circuit restoration module;

[0146] The circuit modeling module is used to construct forward cyclic graphs and reverse cyclic graphs based on the input, output and all intermediate node information of the netlist.

[0147] The observability calculation module is used to quantify the impact of each node's anomaly on the circuit using formulas, group nodes according to the reachable path, and calculate the observability value for each group.

[0148] The observability enhancement module is used for initialization and iterative analysis until all lowest observable nodes are affected;

[0149] The circuit restoration module is used to find all the enhanced nodes, construct their logic cones, design a lookup table output to invert the modified signal, and use the lookup table output and the modified signal as inputs to insert a new gate to obtain the restoration output, update the netlist, cover all enhanced nodes, and restore the circuit.

[0150] Specific limitations regarding the observability-based hardware Trojan protection system can be found in the limitations of the observability-based hardware Trojan protection method described above, and will not be repeated here. Each module in the aforementioned observability-based hardware Trojan protection system can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in the computer device, or stored in the computer device's memory as software, so that the processor can call and execute the corresponding operations of each module.

[0151] Example 3

[0152] Reference Figure 3 This is the third embodiment of the present invention. Based on the first two embodiments, this embodiment provides a computer device, which can be a server, and its internal structure diagram can be as follows. Figure 3 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and databases. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media.

[0153] The computer device's database is used to store motion detection data. The computer device's network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it implements the steps in any of the above embodiments of the sparse tensor computation acceleration method.

[0154] Those skilled in the art will understand that Figure 3The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0155] In one embodiment, the present invention provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps in any of the above embodiments of the sparse tensor operation acceleration method.

[0156] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0157] Example 4

[0158] As an embodiment of the present invention, a hardware Trojan protection method based on observability is provided. In order to verify the beneficial effects of the present invention, scientific demonstration is carried out through economic benefit calculation and simulation experiments.

[0159] First, multiple circuit netlists with different characteristics were selected, including simple logic circuits, medium-complexity processor subsystems, and high-complexity complete processor designs.

[0160] These circuit netlists are used as the basis for constructing directed cyclic graphs to simulate the structure and workflow of hardware circuits.

[0161] In the experiment, automated tools were used to generate forward and reverse directed cyclic graphs from the circuit netlist to ensure that the input and output of each node were accurately represented.

[0162] To assess the observability of internal nodes, a specific algorithm was developed to quantify the impact of nodes on circuit behavior when anomalous signals occur. This algorithm, based on directed cyclic graphs, identifies critical nodes in the circuit that are crucial to the visibility of the final output logic value. Through comparative analysis, nodes with low observability are identified, which may be potential targets for hardware trojans.

[0163] To improve node observability, an iterative approach was employed in the experiment. For each identified node with low observability, a logic gate was inserted at the most suitable location according to the algorithm to increase the node's observability. This process takes into account the impact of previously inserted logic gates and dynamically adjusts the insertion strategy. Simultaneously, the construction of logic cones was considered to ensure that each insertion is based on the latest circuit state.

[0164] Finally, the new circuit netlist with enhanced observability was functionally restored. By analyzing and comparing the original and modified circuit netlists, it was ensured that the inserted logic gates did not affect the original functionality of the circuit. At this stage, the logic cone of each enhanced node was re-evaluated and adjusted using a lookup table (LUT) to ensure the consistency of circuit functionality.

[0165] The following two data tables are provided to verify the experiment;

[0166] The data table is as follows:

[0167] Table 1 Data Comparison Table

[0168]

[0169] Table 2. Minimum observability increment and number of nodes added.

[0170]

[0171] The data in the table above shows that the observability of each circuit is significantly improved after implementing the observability-based hardware Trojan protection method. For example, the observability of circuit A increased from 60% to 90%, and that of circuit B increased from 70% to 95%. This improvement demonstrates the effectiveness of the invention in enhancing circuit security. By inserting logic gates at critical nodes to increase node observability, it becomes easier to monitor and identify potential unauthorized activities, thereby increasing the ability to protect against hardware Trojan attacks.

[0172] The data on the number of node insertions and the total number of iterations also provide a basis for evaluating the efficiency of the improved method. Although logic gates were inserted, the circuit modification was minimized and efficient through meticulous iterative analysis. For example, circuit B had the fewest node insertions (10) and a relatively small number of iterations (15), indicating that the optimized circuit achieved high observability while maintaining a compact structure.

[0173] Furthermore, by comparing the observability of the original circuit and the improved circuit, the innovativeness and advantages of the invention can be clearly seen. The observability of the original circuit is generally low, meaning that many nodes in the circuit could become potential targets for hardware Trojan attacks before optimization. By implementing this invention, not only is the observability of these nodes significantly improved, but the overall security of the circuit is also enhanced through the precise insertion of logic gates and iterative optimization process.

[0174] In summary, the tabular data strongly supports the effectiveness and superiority of the invention. This observability-based hardware Trojan protection method not only significantly improves circuit security but also maintains the efficiency and economy of circuit design through optimized insertion and iteration processes. Therefore, this invention demonstrates significant novelty and advantages in both technological innovation and practical application.

[0175] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A hardware Trojan protection method based on observability, characterized in that, include: The circuit netlist information is modeled by constructing a directed cyclic graph; The construction of the directed cyclic graph involves using the input, output, and all intermediate node information of the circuit netlist to construct forward and reverse directed cyclic graphs to simulate the structure and workflow of the hardware circuit. In a positive loop diagram, the circuit's initial input terminal PI leads to its final output terminal PO. The reverse loop diagram shows the circuit's final output terminal PO leading to the initial input terminal PI; The observability of internal nodes is calculated based on the constructed directed cyclic graph, and the visibility of the logic values ​​of the internal nodes of the circuit is determined. The observability of the internal nodes of the computation includes, Observability reflects the visibility of the logic values ​​of the internal nodes of the circuit at the final output. The observability of nodes is calculated by grouping them into paths on a cyclic graph, using the following formula: ； in, Represents the observability value of a node. This represents the level of impact after a node sends an abnormal signal. This indicates the number of inputs that will cause a low-level abnormality at the node. This indicates the level of impact caused by a low-level anomaly. This indicates the number of inputs that would cause a high-level abnormality at the node. This indicates the level of impact caused by a high-level anomaly; Through iterative analysis and insertion at appropriate locations Gates are used to enhance the observability of nodes; Steps to enhance node observability include: Build a logical cone for all ends and complete the initialization; The logical cone comprises the set of all nodes that reach a specific node; The calculated observability values ​​are sorted, and the node with the lowest observability is identified. Iterative analysis is used to find the lowest observable node, and an insertion is performed at the lowest observable node. Gates enhance observability; When inserting a door, consider the influence of previously inserted doors; Randomly select the second input node of the insertion gate; Update the circuit netlist and node observability values ​​after the insertion gate; Repeat the above steps until the preset number of iterations is reached; The circuit's function is restored based on the new circuit netlist with enhanced observability.

2. The hardware Trojan protection method based on observability as described in claim 1, characterized in that: The iterative analysis includes location search and circuit modification; The location search includes, Calculate the node position with the lowest observability, and insert a node driven by this node at the lowest observable node position. Door; Consider the impact of previously inserted gates on the calculation; If the predecessor and successor nodes on a path have the same minimum observability, then the successor node is selected for enhancement. Randomly select a logical cone that does not contain either the node to be enhanced or the node to be enhanced; The nodes to be enhanced are those whose observability is increased due to modifications in the circuit structure. If no logical cone containing both the node to be enhanced and the node to be enhanced is found, then the next node with the lowest observability is searched to update the node to be enhanced, and the above steps are repeated. Determine the logic cone that does not contain any augmenting nodes and the nodes to be augmented, where the original output is considered to be inserted. The second input to the door.

3. The hardware Trojan protection method based on observability as described in claim 2, characterized in that: The circuit modifications include, After the nodes to be enhanced are identified in the location search phase, the circuit modification phase begins. Randomly select a logic cone from all logic cones that is not affected by the node to be enhanced or any previously enhanced nodes; Use the original output of a random node in the selected logic cone as the second input node of the gate circuit to be inserted. Using the node to be enhanced and the selected second input node as input, insert a Door; Inserted The output of the gate replaces the original output of the node to be enhanced and is connected to the input of the next logic gate to which the original output of the node to be enhanced was connected; The circuit netlist is updated using the new topology information after the insertion gate; Recalculate the observability values ​​of all nodes in the circuit after the insertion gate; If the current iteration count has not reached the preset value, return to the position search phase, redetermine the next node to be enhanced, and perform iterations until the preset iteration count is reached; The result is a new circuit netlist with enhanced observability.

4. The hardware Trojan protection method based on observability as described in claim 3, characterized in that: Based on the enhanced circuit netlist, find all nodes that were marked as nodes to be enhanced during the previous enhancement process; For each node to be enhanced, trace back to all its predecessor nodes and construct the logical cone of that node; If the enhancement node is adopted If a node is enhanced by a gate, then the inserted node is checked. The two input nodes of the gate; Enumerate all input pattern combinations for these two input nodes, record the input pattern combinations that make the output of the node to be enhanced 1, and use them as the input patterns of the lookup table LUT, with the modified output of the node to be enhanced as the input of the lookup table LUT. If the enhancement node is adopted If a node is enhanced by a gate, then the inserted node is checked. The input node of the gate; Enumerate all input patterns of the input node, record the input patterns that make the output of the node to be enhanced 0, and use them as the input patterns of the lookup table LUT, with the modified output of the node to be enhanced as the input of the lookup table LUT. Design the output of the lookup table (LUT) so that it can invert the modified output signal accordingly; Using the output of the lookup table LUT and the modified output of the node to be enhanced as input, a new node is randomly inserted. Gate circuits; Will insert new The output of the gate is the restored output of that node; Update the circuit netlist, repeat the above steps to cover all nodes to be enhanced, and finally obtain the restored circuit netlist.

5. A system employing the hardware Trojan protection method based on observability as described in any one of claims 1 to 4, characterized in that, include: The circuit modeling module, observability calculation module, observability enhancement module, and circuit reconstruction module are all included. The circuit modeling module is used to construct forward cyclic graphs and reverse cyclic graphs based on the input, output and all intermediate node information of the netlist. The observability calculation module is used to quantify the impact of each node's anomaly on the circuit using a formula, group the nodes according to the reachable path, and calculate the observability value for each group. The observability enhancement module is used for initialization and iterative analysis until all the lowest observability nodes are affected; The circuit restoration module is used to find all the enhanced nodes, construct their logic cones, design a lookup table output to invert the modified signal, and use the lookup table output and the modified signal as inputs to insert a new gate to obtain the restoration output, update the netlist, cover all enhanced nodes, and restore the circuit.

6. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the hardware Trojan protection method based on observability as described in any one of claims 1 to 4.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the hardware Trojan protection method based on observability as described in any one of claims 1 to 4.

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