Software-defined wake-up receiver implementation method and system

Abstract

The application provides a software-defined wake-up receiver implementation method and system, which comprises the following steps: a transmitter generates a wake-up sequence according to an agreed code rate and a wake-up sequence, and transmits the wake-up sequence at a frequency point at which a wake-up receiver works, so as to form a wake-up signal; a radio frequency front end of the wake-up receiver performs low-power down-conversion on the received wake-up signal, so as to obtain a baseband signal, and then moves the baseband signal from a carrier frequency to a base frequency; a comparator in the wake-up receiver compares the baseband signal after down-conversion with a threshold, so as to generate a bit stream; a correlator and a masker in a digital circuit of the wake-up receiver compare the bit stream under the clock driving of a digital control oscillator, detect a moment at which the wake-up signal ends, and pull up a wake-up flag, so as to enable a high-power circuit part. According to different steps and purposes of software definition, the wake-up receiver technology can be used for implementing network address allocation, changing signal properties of the wake-up sequence, improving security and the like.

Description

Technical Field

[0001] This invention relates to the fields of low-power communication, time-domain synchronization, and wireless communication technologies, and specifically to a software-defined wake-up receiver implementation method and system. Background Technology

[0002] The Internet of Things (IoT) technology has significant application prospects in smart homes, smart transportation, smart cities, smart manufacturing, and smart healthcare. To maintain low power consumption in mobile scenarios, IoT terminals are typically designed for standby operation, but can be woken up by events. Wake-up receivers are key low-power standby devices that utilize wireless event-driven mechanisms. To conserve power, they typically only demodulate on-off keying (OOK) signals. They are usually composed of an antenna, envelope detector circuit, correlator, and other components. Existing wake-up receivers can only detect fixed sequences with fixed code lengths and can only operate within a relatively small OOK code rate range. With the increasing number of IoT devices and the application of new low-power communication technologies such as backscatter, wake-up receivers not only perform wake-up functions but also synchronization functions in communication. Their specific synchronization performance requirements are closely related to the parameters of the wake-up receiver.

[0003] Patent document CN106604377A discloses a data communication method and apparatus. The data communication method includes: when the communication module is in a sleep state, a wake-up receiver receives a wake-up frame sent by a wireless access device; the wake-up receiver wakes up the communication module according to the wake-up frame to trigger data communication between the communication module and the wireless access device; wherein the power consumption of the wake-up receiver is less than the power consumption of the communication module. However, this patent cannot completely solve the existing technical problems, nor can it meet the needs of this invention. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the purpose of this invention is to provide a software-defined wake-up receiver implementation method and system.

[0005] The software-defined wake-up receiver implementation method provided by the present invention includes:

[0006] Step S1: The transmitter generates a wake-up sequence according to the code rate and wake-up sequence agreed upon with the wake-up receiver, and sends it at the frequency point where the wake-up receiver is working to form a wake-up signal;

[0007] Step S2: The RF front-end of the wake-up receiver performs low-power down-conversion on the received wake-up signal to obtain the baseband signal, and then shifts it from the carrier frequency to the baseband frequency;

[0008] Step S3: Wake up the comparator in the receiver to compare the down-converted baseband signal with the threshold and generate a bit stream;

[0009] Step S4: The correlator and mask in the digital circuit of the wake-up receiver compare the bit stream under the clock drive of the numerically controlled oscillator, detect the end of the wake-up signal and pull up the wake-up flag to enable the high-power circuit section.

[0010] Preferably, the numerically controlled oscillator is driven by a master clock with a constant frequency and includes a register that adds its stored value to a frequency control constant in each cycle and stores the new value in the register; the numerically controlled oscillator also provides clocks for the comparator, correlator, and mask.

[0011] Preferably, the correlator and the mask have the same bit depth; the correlator adopts a shift register structure, and in each clock cycle, the least significant bit of the correlator is input as a new bit by the comparator, while the most significant bit of the correlator is discarded;

[0012] The comparison sequence of the correlator is stored in a register, is software-defined, and adapts to different wake-up sequences;

[0013] The masker includes a mask sequence and OR logic. Each bit of the mask sequence is ORed with each bit of the correlator, and the output of all the OR logic is accumulated by an adder and compared with the wake-up threshold to obtain the wake-up flag bit. When a part of the mask sequence is bit 1, the output of the OR logic is always bit 1, so that bit information is ignored.

[0014] Preferably, the shift register in the wake-up receiver is controlled by a mask, so that when the signal sequence stored in the shift register is correlated with the wake-up sequence, the result of the XOR operation is not directly accumulated, but is first subjected to a bitwise OR logical operation with the mask. This process ensures that the register corresponding to the mask bit value of 1 in the shift register does not affect the result of the correlation operation, thereby shortening the wake-up sequence code length.

[0015] Preferably, in the wake-up receiver, the comparator, shift register, and correlator are all driven by a numerically controlled oscillator to realize the software definition of the wake-up receiver code rate; when the system clock is f, if the bit width of the numerically controlled oscillator is N, then the frequency configuration step size of up to f / 2^N can be realized.

[0016] The software-defined wake-up receiver implementation system provided by the present invention includes:

[0017] Module M1: The transmitter generates a wake-up sequence based on the code rate and wake-up sequence agreed upon with the wake-up receiver, and sends it at the frequency point where the wake-up receiver is operating, forming a wake-up signal;

[0018] Module M2: The RF front-end of the wake-up receiver performs low-power down-conversion on the received wake-up signal to obtain the baseband signal, and then shifts it from the carrier frequency to the baseband frequency;

[0019] Module M3: Wakes up the comparator in the receiver to compare the down-converted baseband signal with a threshold and generate a bit stream;

[0020] Module M4: The correlator and mask in the digital circuit of the wake-up receiver compare the bit stream under the clock drive of the numerically controlled oscillator, detect the end of the wake-up signal and pull up the wake-up flag to enable the high-power circuit section.

[0021] Preferably, the numerically controlled oscillator is driven by a master clock with a constant frequency and includes a register that adds its stored value to a frequency control constant in each cycle and stores the new value in the register; the numerically controlled oscillator also provides clocks for the comparator, correlator, and mask.

[0022] Preferably, the correlator and the mask have the same bit depth; the correlator adopts a shift register structure, and in each clock cycle, the least significant bit of the correlator is input as a new bit by the comparator, while the most significant bit of the correlator is discarded;

[0023] The comparison sequence of the correlator is stored in a register, is software-defined, and adapts to different wake-up sequences;

[0024] The masker includes a mask sequence and OR logic. Each bit of the mask sequence is ORed with each bit of the correlator, and the output of all the OR logic is accumulated by an adder and compared with the wake-up threshold to obtain the wake-up flag bit. When a part of the mask sequence is bit 1, the output of the OR logic is always bit 1, so that bit information is ignored.

[0025] Preferably, the shift register in the wake-up receiver is controlled by a mask, so that when the signal sequence stored in the shift register is correlated with the wake-up sequence, the result of the XOR operation is not directly accumulated, but is first subjected to a bitwise OR logical operation with the mask. This process ensures that the register corresponding to the mask bit value of 1 in the shift register does not affect the result of the correlation operation, thereby shortening the wake-up sequence code length.

[0026] Preferably, in the wake-up receiver, the comparator, shift register, and correlator are all driven by a numerically controlled oscillator to realize the software definition of the wake-up receiver code rate; when the system clock is f, if the bit width of the numerically controlled oscillator is N, then the frequency configuration step size of up to f / 2^N can be realized.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] (1) The wake-up sequence, code length and detection clock frequency of the wake-up receiver proposed in this invention can all be changed by software. Depending on the steps and purposes defined by the software, this wake-up receiver technology can be used to realize network address allocation, change the signal attributes of the wake-up sequence to improve security, etc.

[0029] (2) The method proposed in this invention can realize the software definition of the sequence content, code rate and code length of the wake-up receiver. It is helpful to realize the flexible deployment of network system for a large number of IoT devices and backscatter communication terminals, and can be applied to the time synchronization of backscatter communication system. Attached Figure Description

[0030] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0031] Figure 1 The logical connection diagram between the shift register, correlator, and masker of the software-defined wake-up receiver is shown below.

[0032] Figure 2 This is a system framework diagram for a software-defined wake-up receiver implementation. Detailed Implementation

[0033] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0034] Example 1

[0035] This invention provides a method for configuring a wake-up sequence content, length, and code rate to wake up a receiver, the implementation of which includes the following steps:

[0036] Step S1: Based on the target code rate R of the wake-up system, calculate the frequency control word of the numerically controlled oscillator and generate a clock signal with a frequency closest to R;

[0037] Step S2: Based on the target wake-up sequence, compare its length M with the bit depth N of the correlator and masker, and set the mask sequence at the end of the NM length to bit 1 to achieve the wake-up sequence length configuration of length M;

[0038] Step S3: Write the target wake-up sequence of length M into the high M bits of the correlator register, and ignore the NM bits at the end;

[0039] Step S4: When it is necessary to wake up the wake-up receiver, send the wake-up sequence through the wireless channel to realize the wake-up operation;

[0040] Step S5: If it is necessary to change the sequence content, length or bitrate, repeat steps S1-S3 to configure, and send the changed wake-up signal through step S4 to realize the wake-up operation.

[0041] Example 2

[0042] This invention provides a software-defined wake-up receiver implementation method, comprising:

[0043] Step S1: The transmitter generates a wake-up sequence according to the code rate and wake-up sequence agreed upon with the wake-up receiver, and sends it at the frequency point where the wake-up receiver is working to form a wake-up signal;

[0044] Step S2: The RF front-end of the wake-up receiver performs low-power down-conversion on the received wake-up signal to obtain the baseband signal, and then shifts it from the carrier frequency to the baseband frequency;

[0045] Step S3: Wake up the comparator in the receiver to compare the down-converted baseband signal with the threshold and generate a bit stream;

[0046] Step S4: The correlator and mask in the digital circuit of the wake-up receiver compare the bit stream under the clock drive of the numerically controlled oscillator, detect the end of the wake-up signal and pull up the wake-up flag to enable the high-power circuit section.

[0047] The numerically controlled oscillator is driven by a master clock with a constant frequency and includes a register that adds its stored value to a frequency control constant in each cycle and stores the new value in the register. The numerically controlled oscillator also provides clocks for the comparator, correlator, and mask.

[0048] The correlator and the mask have the same bit depth; the correlator adopts a shift register structure, and in each clock cycle, the least significant bit of the correlator is input as a new bit by the comparator, while the most significant bit of the correlator is discarded.

[0049] The comparison sequence of the correlator is stored in a register, is software-defined, and adapts to different wake-up sequences;

[0050] The masker includes a mask sequence and OR logic. Each bit of the mask sequence is ORed with each bit of the correlator, and the output of all the OR logic is accumulated by an adder and compared with the wake-up threshold to obtain the wake-up flag bit. When a part of the mask sequence is bit 1, the output of the OR logic is always bit 1, so that bit information is ignored.

[0051] In the wake-up receiver, the shift register is controlled by a mask, so that when the signal sequence stored in the shift register is correlated with the wake-up sequence, the result of the XOR operation is not directly accumulated, but is first ORed with the mask. This process ensures that the registers corresponding to the mask bits in the shift register have no effect on the result of the correlation operation, thereby shortening the wake-up sequence code length.

[0052] In the wake-up receiver, the comparator, shift register, and correlator are all driven by a numerically controlled oscillator, enabling the software definition of the wake-up receiver's code rate. With the system clock being f, if the bit width of the numerically controlled oscillator is N, then a frequency configuration step size of up to f / 2^N can be achieved.

[0053] Example 3

[0054] like Figure 2 This invention provides a software-defined wake-up receiver implementation system, comprising:

[0055] Module M1: The transmitter generates a wake-up sequence based on the code rate and wake-up sequence agreed upon with the wake-up receiver, and sends it at the frequency point where the wake-up receiver is operating, forming a wake-up signal;

[0056] Module M2: The RF front-end of the wake-up receiver performs low-power down-conversion on the received wake-up signal to obtain the baseband signal, and then shifts it from the carrier frequency to the baseband frequency;

[0057] Module M3: Wakes up the comparator in the receiver to compare the down-converted baseband signal with a threshold and generate a bit stream;

[0058] Module M4: The correlator and mask in the digital circuit of the wake-up receiver compare the bit stream under the clock drive of the numerically controlled oscillator, detect the end of the wake-up signal and pull up the wake-up flag to enable the high-power circuit section.

[0059] The numerically controlled oscillator is driven by a master clock with a constant frequency and includes a register that adds its stored value to a frequency control constant in each cycle and stores the new value in the register. The numerically controlled oscillator also provides clocks for the comparator, correlator, and mask.

[0060] The correlator and the mask have the same bit depth; the correlator adopts a shift register structure, and in each clock cycle, the least significant bit of the correlator is input as a new bit by the comparator, while the most significant bit of the correlator is discarded.

[0061] The comparison sequence of the correlator is stored in a register, is software-defined, and adapts to different wake-up sequences;

[0062] The masker includes a mask sequence and OR logic. Each bit of the mask sequence is ORed with each bit of the correlator, and the output of all the OR logic is accumulated by an adder and compared with the wake-up threshold to obtain the wake-up flag bit. When a part of the mask sequence is bit 1, the output of the OR logic is always bit 1, so that bit information is ignored.

[0063] In the wake-up receiver, the shift register is controlled by a mask, so that when the signal sequence stored in the shift register is correlated with the wake-up sequence, the result of the XOR operation is not directly accumulated, but is first ORed with the mask. This process ensures that the registers corresponding to the mask bits in the shift register have no effect on the result of the correlation operation, thereby shortening the wake-up sequence code length.

[0064] In the wake-up receiver, the comparator, shift register, and correlator are all driven by a numerically controlled oscillator, enabling the software definition of the wake-up receiver's code rate. With the system clock being f, if the bit width of the numerically controlled oscillator is N, then a frequency configuration step size of up to f / 2^N can be achieved.

[0065] Those skilled in the art will understand that, in addition to implementing the system, apparatus, and their modules provided by this invention in purely computer-readable program code, the same program can be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system, apparatus, and their modules provided by this invention can be considered a hardware component, and the modules included therein for implementing various programs can also be considered structures within the hardware component; alternatively, modules for implementing various functions can be considered both software programs implementing the method and structures within the hardware component.

[0066] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A method for implementing a software-defined wake-up receiver, the method comprising: Comprising: Step S1: the transmitter generates a wake-up sequence according to the code rate and the wake-up sequence agreed with the wake-up receiver, and sends at the frequency point where the wake-up receiver works to form a wake-up signal; Step S2: the radio frequency front end of the wake-up receiver performs low-power down-conversion on the received wake-up signal to obtain a baseband signal, and then moves from the carrier frequency to the base frequency; Step S3: the comparator in the wake-up receiver compares the baseband signal after down-conversion with a threshold to generate a bit stream; Step S4: the correlator and the masker in the digital circuit of the wake-up receiver detect the moment when the wake-up signal ends under the clock driving of the numerically controlled oscillator and pull up the wake-up flag bit to enable the high-power circuit part; The correlator and the masker have the same bit depth; the correlator adopts a shift register structure, and in each clock cycle, the correlator inputs a new bit from the comparator at the lowest bit, and the highest bit of the correlator discards the bit; The comparison sequence of the correlator is stored in a register and is defined by software, which is suitable for different wake-up sequences; The masker includes a mask sequence and an or logic, each bit of the mask sequence is subjected to or operation with each bit of the correlator, and the output result of all or logics is accumulated through an adder and compared with a wake-up threshold to obtain a wake-up flag bit; when a part of the mask sequence takes a bit 1, the output of the or logic is constant as a bit 1, so that the bit information is ignored.

2. The software defined wake-up receiver implementation method of claim 1, wherein, The numerically controlled oscillator is driven by a frequency constant master clock and includes a register, which adds the value stored in the register to a frequency control constant in each cycle and stores the new value obtained in the register; the numerically controlled oscillator simultaneously provides a clock for the comparator, the correlator and the masker.

3. The software defined wake-up receiver implementation method of claim 1, wherein, In the wake-up receiver, the shift register is controlled by the masker to make the result of the exclusive or operation not directly accumulated when the signal sequence stored in the shift register is subjected to correlation operation with the wake-up sequence, but first subjected to bit-by-bit or logic operation with the masker; this process makes the register corresponding to the mask bit taking a value 1 not have any influence on the result of the correlation operation, thereby shortening the code length of the wake-up sequence.

4. The software defined wake-up receiver implementation method of claim 1, wherein, In the wake-up receiver, the comparator, the shift register and the correlator are driven by the numerically controlled oscillator to realize software definition of the code rate of the wake-up receiver; in the case that the system clock is f, if the bit width of the numerically controlled oscillator is N, a frequency configuration step of f / 2^N can be realized.

5. A software defined wake-up receiver implementation system, comprising: Comprising: Module M1: the transmitter generates a wake-up sequence according to the code rate and the wake-up sequence agreed with the wake-up receiver, and sends at the frequency point where the wake-up receiver works to form a wake-up signal; Module M2: the radio frequency front end of the wake-up receiver performs low-power down-conversion on the received wake-up signal to obtain a baseband signal, and then moves from the carrier frequency to the base frequency; Module M3: the comparator in the wake-up receiver compares the baseband signal after down-conversion with a threshold to generate a bit stream; Module M4: the correlator and the masker in the digital circuit of the wake-up receiver compare the bit stream under the clock driving of the numerically controlled oscillator, detect the moment when the wake-up signal ends, and pull up the wake-up flag bit to enable the high-power consumption circuit part; The correlator and the masker have the same bit depth; the correlator adopts a shift register structure, and every clock cycle, the correlator lowest bit is input with a new bit by the comparator, and the correlator highest bit discards the bit; The comparison sequence of the correlator is stored in a register and is defined by software, and is adapted to different wake-up sequences; The masker contains a mask sequence and or logic, each bit of the mask sequence is operated with each bit of the correlator by or logic, and the output result of all or logic is accumulated by an adder, and is compared with a wake-up threshold to obtain a wake-up flag bit; when a part of the mask sequence takes a bit 1, the output of or logic is constant as bit 1, so that the bit information is ignored.

6. The software defined wake-up receiver implementation system of claim 5, wherein, The numerically controlled oscillator is driven by a frequency constant main clock, and contains a register, which adds the value stored in itself with a frequency control constant every cycle, and stores the new value obtained in the register; the numerically controlled oscillator simultaneously provides a clock for the comparator, the correlator and the masker.

7. The software defined wake-up receiver implementation system of claim 5, wherein, In the wake-up receiver, the shift register is combined and controlled by the masker, so that when the signal sequence stored in the shift register is correlated with the wake-up sequence, the result of the exclusive or operation is not directly accumulated, but is first operated by or logic with the masker bit by bit; this process makes the register corresponding to the mask bit taking 1 in the shift register not have any influence on the result of the correlation operation, thereby shortening the code length of the wake-up sequence.

8. The software defined wake-up receiver implementation system of claim 5, wherein, In the wake-up receiver, the comparator, the shift register and the correlator are all driven by the numerically controlled oscillator, and the code rate of the wake-up receiver is defined by software; in the case that the system clock is f, if the bit width of the numerically controlled oscillator is N, then the highest frequency configuration step of f / 2^N can be realized.

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