Fully through deep trench isolation structure and manufacturing method thereof

Abstract

The present invention provides a fully through deep trench isolation structure and a manufacturing method thereof, the method comprising: providing a first substrate having a relative front and back surface, a shallow trench isolation structure formed in the front surface of the first substrate; forming a deep trench, penetrating the shallow trench isolation structure and extending into the first substrate, the deep trench comprising a first trench penetrating the shallow trench isolation structure and a second trench below the first trench; filling amorphous silicon in the second trench, filling a first isolation material in the first trench; bonding the front surface of the first substrate to the second substrate; removing a portion of the back surface of the first substrate to expose the second trench, removing amorphous silicon in the second trench; filling a high-k dielectric layer on the sidewall and bottom of the second trench, and filling a second isolation material in the second trench. The present invention effectively integrates the advantages of FDTI and BDTI processes, can effectively reduce optical and electrical crosstalk, reduce pixel dark current, and increase pixel quantum efficiency, so as to achieve the purpose of improving pixel performance.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a fully through deep trench isolation structure and a manufacturing method thereof. Background Art

[0002] As people pursue high performance of high-end mobile devices with ultra-high resolution imaging, CMOS image sensors (CIS) with deep sub-micron pixels have received extensive attention. Compared with large-size pixel sensors, how to maintain a large full well capacity (FWC) and effectively reduce the impact of crosstalk as well as maintain a large dynamic range (DR) and high signal-to-noise ratio (SNR) has become the biggest challenge for small-size high-resolution pixels.

[0003] Front-Side Deep Trench Isolation (FDTI) and Backside Deep Trench Isolation (BDTI) isolation processes are used to isolate pixels in back-illuminated stacked sensors, and have become an effective way to continuously reduce pixel size while maintaining a large dynamic range and full well capacity while reducing optical and electrical crosstalk.

[0004] However, the current FDTI process has the following main problems: 1) Due to the presence of multiple heat treatment processes in the front side (FSI) process, the ability of high-k materials (HK) to store charge above 600°C is greatly reduced, so HK cannot be used in the FDTI process. The HK process is very critical for suppressing pixel dark current (DC), so how to introduce HK into FDTI while maintaining its ability to store charge becomes particularly important. 2) In the FSI process, in order to prevent the different expansion coefficients of different materials from causing wafer cracking, FDTI is filled with amorphous silicon (A-Si), but amorphous silicon absorbs incident light and reduces the pixel quantum efficiency (QE), thereby affecting pixel performance.

[0005] For the BDTI process, the BDTI backside (BSI) process is a partial deep trench isolation pixel area, which is not as good as the full-through deep trench isolation and cannot achieve good optical and electrical crosstalk isolation. In addition, the alignment accuracy is limited by the bonding wafer distortion and the front layer overlay accuracy of the machine, and it is impossible to achieve a full-through isolation structure, and it may even cause over-etching, resulting in metal contamination. Summary of the invention

[0006] The object of the present invention is to provide a fully through deep trench isolation structure and a manufacturing method thereof, which has a high-k dielectric layer and high alignment accuracy, combines the advantages of FDTI and BDTI processes, and improves pixel performance.

[0007] To solve the above technical problems, according to a first aspect of the present invention, a method for manufacturing a fully through deep trench isolation structure is provided, comprising the following steps:

[0008] Providing a first substrate, wherein the first substrate has a front side and a back side opposite to each other, and a shallow trench isolation structure is formed in the front side of the first substrate;

[0009] forming a deep trench, the deep trench penetrating the shallow trench isolation structure and extending into the first substrate, the deep trench comprising a first trench penetrating the shallow trench isolation structure and a second trench located below the first trench;

[0010] Filling amorphous silicon in the second trench and filling a first isolation material in the first trench;

[0011] Providing a second substrate, and bonding the front side of the first substrate to the second substrate;

[0012] removing a portion of the back surface of the first substrate until the second trench is exposed, and removing the amorphous silicon in the second trench; and

[0013] A high-k dielectric layer is filled on the sidewall and the bottom of the second trench, and a second isolation material is filled in the second trench.

[0014] Optionally, the method of forming the deep trench includes:

[0015] Forming a patterned hard mask layer on the front surface of the first substrate, wherein the patterned hard mask layer exposes the top surface of the shallow trench isolation structure;

[0016] Using the patterned hard mask layer as a mask, etching the shallow trench isolation structure and the first substrate below the shallow trench structure; and

[0017] The patterned hard mask layer is removed.

[0018] Optionally, the method of filling amorphous silicon in the second trench and filling the first isolation material in the first trench includes:

[0019] Filling amorphous silicon in the deep trench, wherein the amorphous silicon fills up the deep trench;

[0020] removing the amorphous silicon in the first trench; and

[0021] A first isolation material is filled in the first trench.

[0022] Optionally, the amorphous silicon is P-type or N-type doped; when the amorphous silicon is P-type doped, the doping concentration of the amorphous silicon is greater than the doping concentration of the first substrate.

[0023] Optionally, a wet etching process is used to remove the amorphous silicon in the first trench.

[0024] Optionally, the method of forming a shallow trench isolation structure in the front surface of the first substrate includes:

[0025] forming an oxide layer and a nitride layer on the front surface of the first substrate;

[0026] forming a shallow trench, wherein the shallow trench penetrates the nitride layer and the oxide layer and extends into the first substrate; and

[0027] A third isolation material is filled in the shallow trench, and a surface of the third isolation material is flush with a surface of the nitride layer.

[0028] Optionally, after filling the first isolation material in the first trench and before bonding, the method further includes: removing the nitride layer.

[0029] Optionally, the first isolation material, the second isolation material and the third isolation material are all silicon oxide.

[0030] In order to solve the above technical problems, according to a second aspect of the present invention, a full-through deep trench isolation structure is also provided, comprising:

[0031] a second substrate, the first substrate being located on the second substrate;

[0032] A deep trench, penetrating the first substrate, the deep trench comprising a first trench close to the second substrate and a second trench far away from the second substrate;

[0033] A first isolation material filling the first trench;

[0034] a high-k dielectric layer covering the sidewalls and the bottom of the second trench; and

[0035] The second isolation material fills the two trenches.

[0036] Optionally, the first material layer and the second material layer are both silicon oxide.

[0037] Compared with the prior art, the present invention has the following beneficial effects:

[0038] Compared with BDTI, it solves the problem that the alignment accuracy of BDTI is limited by the distortion of the bonded wafer and the overlay accuracy of the front layer of the machine. It has high alignment accuracy, realizes a fully through deep trench isolation structure and effectively reduces optical and electrical crosstalk, while also avoiding over-etching and metal contamination.

[0039] Compared with FDTI, the introduction of a high-k dielectric layer in the fully through deep trench isolation structure and maintaining its original charge storage capacity can effectively reduce the pixel dark current. In addition, the amorphous silicon filled in the deep trench is replaced with silicon oxide, which effectively reduces the absorption of light and increases the pixel quantum efficiency.

[0040] The fully through deep trench isolation structure and its manufacturing method provided by the present invention have a high-k dielectric layer and high alignment accuracy, effectively integrate the advantages of FDTI and BDTI processes, can effectively reduce optical and electrical crosstalk, reduce pixel dark current, and increase pixel quantum efficiency, thereby achieving the purpose of improving pixel performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a structural schematic diagram of the front deep trench structure in the prior art.

[0042] Figure 2 It is a structural schematic diagram of a rear deep trench structure in the prior art.

[0043] Figure 3 It is a schematic flow chart of a method for manufacturing a fully through deep trench isolation structure provided by an embodiment of the present invention.

[0044] Figures 4 to 14 It is a schematic structural diagram of each step of a method for manufacturing a fully through deep trench isolation structure provided by an embodiment of the present invention.

[0045] Description of reference numerals:

[0046] Figure 1 and Figure 2 In the figure, 10 is a first substrate; 11 is a shallow trench isolation structure; 12 is a deep trench isolation structure; 13 is an oxide layer; 14 is an interlayer dielectric layer; 15 is a metal layer; and 20 is a second substrate.

[0047] Figures 4 to 14 In the figure, 100 is a first substrate; 101 is an oxide layer; 102 is a nitride layer; 103 is a shallow trench isolation structure; 104 is a patterned hard mask layer; 105 is a deep trench; 105a is a first trench; 105b is a second trench; 106 is an amorphous silicon; 107 is a first isolation material; 108 is an interlayer dielectric layer; 109 is a metal layer; 110 is a high-k dielectric layer; 111 is a second isolation material; 200 is a second substrate. DETAILED DESCRIPTION

[0048] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0049] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense that includes "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense that includes "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense that includes "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0050] Figure 1 This is a schematic diagram of the structure of the front deep trench structure in the prior art. Please refer to Figure 1 As shown, a relatively aligned shallow trench isolation structure 11 and a deep trench isolation structure 12 are formed on the first substrate 10, and the surface of the shallow trench isolation structure 11 protrudes from the surface of the substrate 10 and extends into the interlayer dielectric layer 14, a metal layer 15 is formed in the interlayer dielectric layer 14, and a second substrate 20 is arranged on the other side of the interlayer dielectric layer 14.

[0051] The deep trench isolation structure 12 is filled with amorphous silicon (A-Si) and cannot be filled with a high-k dielectric layer, which affects the suppression of dark current. At the same time, amorphous silicon absorbs incident light, which reduces pixel quantum efficiency and affects pixel performance.

[0052] Figure 2 This is a schematic diagram of the structure of the rear deep trench structure in the prior art. Figure 2 As shown, the deep trench isolation structure 12 is not aligned with the shallow trench isolation structure 11, and a fully through isolation structure cannot be realized, and good optical and electrical crosstalk isolation cannot be achieved. In addition, over-etching occurs when forming the deep trench isolation structure 12, which easily causes metal contamination.

[0053] In view of the problems existing in the above-mentioned FDTI and BDTI, the present invention provides a full-through deep trench isolation structure and a manufacturing method thereof, which can combine the advantages of FDTI and BDTI to improve pixel performance.

[0054] Figure 3 FIG. 1 is a flow chart of a method for manufacturing a fully through deep trench isolation structure provided by an embodiment of the present invention. Figure 3 As shown, the method for manufacturing a fully through deep trench isolation structure includes the following steps:

[0055] S1: providing a first substrate, wherein the first substrate has a front side and a back side opposite to each other, and a shallow trench isolation structure is formed in the front side of the first substrate;

[0056] S2: forming a deep trench, wherein the deep trench penetrates the shallow trench isolation structure and extends into the first substrate, wherein the deep trench includes a first trench penetrating the shallow trench isolation structure and a second trench located below the first trench;

[0057] S3: filling amorphous silicon in the second trench and filling the first isolation material in the first trench;

[0058] S4: providing a second substrate, and bonding the front surface of the first substrate to the second substrate;

[0059] S5: removing a portion of the back surface of the first substrate until the second trench is exposed, and removing the amorphous silicon in the second trench; and

[0060] S6: filling a high-k dielectric layer on the sidewall and bottom of the second trench, and filling a second isolation material in the second trench.

[0061] Figures 4 to 14 FIG. 1 is a schematic diagram of the steps of a method for manufacturing a fully through deep trench isolation structure according to an embodiment of the present invention. Figure 3 and Figures 4 to 14 The method for manufacturing the fully-through deep trench isolation structure provided by the embodiment of the present invention is described in detail.

[0062] In step S1, refer to Figure 4 As shown, a first substrate 100 is provided. The first substrate 100 has a front side and a back side opposite to each other. A shallow trench isolation structure 103 is formed in the front side of the first substrate 100 .

[0063] The material of the first substrate 100 may be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, etc., or silicon on insulator, germanium on insulator; or other materials, such as III-V compounds such as gallium arsenide. Optionally, the first substrate 100 may be a substrate doped with a P-type dopant such as boron (i.e., a P-type substrate). The first substrate 100 may also be a substrate doped with an N-type dopant such as phosphorus or arsenic (i.e., an N-type substrate).

[0064] In one embodiment of the present invention, the first substrate 100 is a P-type silicon substrate doped with boron, wherein the first substrate 100 includes an upper and a lower part, the first part is doped with a low concentration, and the second part is doped with a high concentration, that is, the doping concentration of the second part is higher than the doping concentration of the first part. The first part is close to the front side of the first substrate 100, the second part is close to the back side of the first substrate 100, and the thickness of the first part is greater than the thickness of the second part. Exemplarily, the thickness of the first part is, for example, 5 μm.

[0065] In one embodiment of the present invention, an oxide layer 101 and a nitride layer 102 are further formed on the front surface of the first substrate 100 , and the shallow trench isolation structure 103 penetrates the silicon nitride 102 and the oxide layer 101 and extends into the first substrate 100 .

[0066] Exemplarily, the method for forming the shallow trench isolation structure 103 includes: first, forming an oxide layer 101 and a nitride layer 102 on the front surface of the first substrate 100, wherein the material of the oxide layer 101 is, for example, silicon oxide, and the material of the nitride layer 102 is, for example, silicon nitride; then, etching the nitride layer 102, the oxide layer 101, and a portion of the thickness of the first substrate 100 in sequence to form a shallow trench; then filling the shallow trench with a third isolation material, wherein the third isolation material fills the shallow trench and covers the nitride layer 102; then, planarizing the third isolation material until the nitride layer 102 is exposed, and the surface of the remaining third isolation material is flush with the surface of the nitride layer 102. In this embodiment, the third isolation material is silicon oxide.

[0067] In step S2, please refer to Figure 7 As shown, a deep trench 105 is formed, the deep trench 105 penetrates the shallow trench isolation structure 103 and extends into the first substrate 100, and the deep trench 105 includes a first trench 105a penetrating the shallow trench isolation structure 103 and a second trench 105b located below the first trench 105a.

[0068] For example, first, Figure 5As shown, a patterned hard mask layer 104 is formed on the front of the first substrate 100, and the patterned hard mask layer 104 exposes the top surface of the shallow trench isolation structure 103. In this embodiment, the material of the patterned hard mask layer 104 is silicon oxide. Then, the shallow trench isolation structure 103 and the first substrate 100 below the shallow trench isolation structure 103 are etched using the patterned hard mask layer 104 as a mask to form the deep trench 105. Next, the patterned hard mask layer 104 is removed to form the deep trench 105. Figure 6 The structure shown.

[0069] In one embodiment of the present invention, the cross-sectional size exposed by the patterned hard mask layer 104 is smaller than the top surface of the shallow trench isolation structure 103, that is, the patterned hard mask layer 104 exposes part of the top surface of the shallow trench isolation structure 103, and then the shallow trench isolation structure 103 and the first substrate 100 are etched using the patterned hard mask layer 104 as a mask to form a deep trench 105. Please refer to Figure 6 As shown, the deep trench 105 includes a first trench 105a that passes through the shallow trench isolation structure 103 and a second trench 105b below the first trench 105a. The first trench 105a and the second trench 105b together constitute the deep trench 105, and the cross-sectional dimension of the first trench 105a close to the front side of the first substrate 100 is equal to the cross-sectional dimension of the second trench 105b close to the front side of the first substrate 100.

[0070] In another embodiment of the present invention, the cross-sectional size exposed by the patterned hard mask layer 104 is smaller than the top surface of the shallow trench isolation structure 103, that is, the patterned hard mask layer 104 exposes a portion of the top surface of the shallow trench isolation structure 103, and then the shallow trench isolation structure 103 and the first substrate 100 are etched using the patterned hard mask layer 104 as a mask to form a Figure 6 The deep trench shown in FIG. 1 is then formed by removing the shallow trench isolation structure 103 remaining on the upper sidewall of the deep trench to form a Figure 7 The deep trench 105 is shown.

[0071] Figure 7In the embodiment, the deep trench 105 includes a first trench 105a that penetrates the shallow trench isolation structure 103 and a second trench 105b below the first trench 105a, that is, the first trench 105a is formed at the location of the shallow trench isolation structure 103, and the second trench 105b is located below the first trench 105a. The first trench 105a and the second trench 105b together constitute the deep trench 105, and the cross-sectional size of the first trench 105a close to the front side of the first substrate 100 is larger than the cross-sectional size of the second trench 105b close to the front side of the first substrate 100. The following embodiments are based on Figure 7 The deep groove shown is used as an example for explanation.

[0072] In one embodiment of the present invention, the deep trench 105 extends to the junction between the first portion and the second portion in the first substrate 100 .

[0073] In step S3, please refer to Fig.10 As shown, amorphous silicon 106 is filled in the second trench 105 b , and a first isolation material 107 is filled in the first trench 105 a .

[0074] First, please refer to Figure 8 As shown, amorphous silicon 106 is filled in the deep trench 105 , and the amorphous silicon 106 fills up the deep trench 105 and covers the nitride layer 102 .

[0075] Then, please refer to Fig. 9 As shown, the amorphous silicon 106 in the first trench 105 a is removed.

[0076] In one embodiment of the present invention, the first substrate 100 is a P-type silicon substrate doped with boron, the amorphous silicon 106 is also P-type doped, for example, boron doped, and the doping concentration of the amorphous silicon 106 is greater than the doping concentration of the first substrate 100 (specifically, greater than the doping concentration of the first portion of the first substrate 100), so that the amorphous silicon 106 can be selectively removed without damaging the first substrate 100.

[0077] Exemplarily, the amorphous silicon 106 in the first trench 105a is removed by a wet etching process, for example, a HNO3 solution may be used.

[0078] In one embodiment of the present invention, the doping type in the amorphous silicon 106 may also be opposite to the doping type of the first substrate 100, for example, the first substrate 100 is a P-type doped substrate, and the amorphous silicon 106 is an N-type doped substrate. The present invention is not limited to this, and the doping types of the first substrate 100 and the amorphous silicon 106 are freely selected for the purpose of conveniently removing the amorphous silicon 106 without damaging the first substrate 100.

[0079] Next, a first material layer 107 is filled in the first trench 105a. The first material layer 107 fills the first trench 105a and covers the nitride layer 102. The first material layer 107 is then planarized until the nitride layer 102 is exposed, forming a structure as shown in FIG. Fig.10 In this embodiment, the first material layer 107 is silicon oxide.

[0080] At this time, the deep trench 105 is filled with amorphous silicon 106 and the first material layer 107 .

[0081] Then, please refer to Fig.11 As shown, the method further includes: removing the nitride layer 102 to expose the oxide layer 101 , and the surface of the first isolation material 107 is higher than the surface of the oxide layer 101 .

[0082] Next, an interlayer dielectric layer 108 may be formed on the oxide layer 101, and a metal layer 109 may be formed in the interlayer dielectric layer 108. For details, see Fig.12 The interlayer dielectric layer 108 covers the first isolation material 107 .

[0083] In step S4, please continue to refer to Fig.12 As shown, a second substrate 200 is provided, and the front side of the first substrate 100 is bonded to the second substrate 200 .

[0084] In this embodiment, specifically, the first substrate 100 is bonded to the second substrate 200 on one side where the interlayer dielectric layer 108 is formed. The material of the second substrate 200 may be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium, etc., or may be silicon on insulator, germanium on insulator; or may be other materials, such as III-V compounds such as gallium arsenide.

[0085] In step S5, please refer to Fig.13 As shown, a portion of the back side of the first substrate 100 is removed until the second trench 105 b is exposed, and the amorphous silicon 106 in the second trench 105 b is removed.

[0086] Exemplarily, a grinding method is used to remove a portion of the back surface of the first substrate 100, and a wet etching process is used to remove the amorphous silicon 106 in the second trench 105b. For example, HNO3 solution may be used.

[0087] In step S6, please refer to Fig.14 As shown, a high-k dielectric layer 110 is filled on the sidewall and bottom of the second trench 105 b , and a second isolation material 111 is filled in the second trench 105 b .

[0088] The high-k dielectric layer 110 covers the sidewalls and bottom of the second trench 105b (ie, the surface exposed by the first isolation material 107), and can also cover the back side of the first substrate 100. The second isolation material 111 fills the second trench 105b.

[0089] The material of the high-k dielectric layer 110 may include tantalum oxide (Ta2O5), strontium titanium oxide (SrTiO3), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO) or zirconium oxide (ZrO2), etc. The second isolation material 111 is silicon oxide.

[0090] At this time, the through-deep trench isolation structure has been formed, the first trench 105a is filled with the first isolation material 107, and the second trench 105b is filled with the high-k dielectric layer 110 and the second isolation material 111. The first isolation material 107, the high-k dielectric layer 110 and the second isolation material 111 together constitute the through-deep trench isolation structure.

[0091] Compared with the existing FDTI, since the process of manufacturing the fully through deep trench isolation structure does not involve an annealing process, a high-k dielectric layer 110 can be introduced into the isolation structure and its original charge storage capacity can be maintained, which can effectively reduce the pixel dark current. In addition, replacing the amorphous silicon filled in the deep trench with silicon oxide effectively reduces the absorption of light and increases the pixel quantum efficiency.

[0092] Compared with the existing BDTI, a deep trench 105 penetrating the shallow trench isolation structure 103 is formed before the first substrate 100 and the second substrate 200 are bonded, and then two materials are filled in the deep trench 105 to form a fully-through deep trench isolation structure. Since the deep trench 105 is directly formed and there is no need to align the isolation structure filled with the two materials, the problem that the alignment accuracy of BDTI is limited by the distortion of the bonded wafer and the overlay accuracy of the front layer of the machine is solved. It has high alignment accuracy, realizes a fully-through deep trench isolation structure process method and effectively reduces optical and electrical crosstalk, while also avoiding over-etching and metal contamination.

[0093] The fully through deep trench isolation structure and its manufacturing method provided by the present invention have a high-k dielectric layer and high alignment accuracy, effectively integrate the advantages of FDTI and BDTI processes, can effectively reduce optical and electrical crosstalk, reduce pixel dark current, and increase pixel quantum efficiency, thereby achieving the purpose of improving pixel performance.

[0094] Correspondingly, the present invention also provides a fully through deep trench isolation structure, which is manufactured using the manufacturing method of the fully through deep trench isolation structure as described above.

[0095] Please refer to Fig.14 As shown, the fully through deep trench isolation structure includes:

[0096] A second substrate 200, and a first substrate 100 located on the second substrate 200;

[0097] A deep trench 105 penetrating the first substrate 100 , wherein the deep trench 105 includes a first trench 105 a close to the second substrate 200 and a second trench 105 b away from the second substrate 200 ;

[0098] A first isolation material 107 filling the first trench 105a;

[0099] A high-k dielectric layer 110 covering the sidewalls and bottom of the second trench 105b;

[0100] The second isolation material 111 fills the second trenches 105b.

[0101] In one embodiment of the present invention, both the first isolation material 107 and the second isolation material 111 are silicon oxide.

[0102] In summary, in the fully-through deep trench isolation structure and its manufacturing method provided by the present invention, compared with BDTI, the problem that the alignment accuracy of BDTI is limited by the distortion of the bonded wafer and the overlay accuracy of the front layer of the machine is solved, and it has high alignment accuracy, realizes the fully-through deep trench isolation structure process method and effectively reduces the optical and electrical crosstalk, while also avoiding over-etching and metal contamination. Compared with FDTI, a high-k dielectric layer is introduced into the fully-through deep trench isolation structure and its original charge storage capacity is maintained, which can effectively reduce the pixel dark current. In addition, the amorphous silicon filled in the deep trench is replaced with silicon oxide, which effectively reduces the absorption of light and increases the pixel quantum efficiency. The fully-through deep trench isolation structure and its manufacturing method provided by the present invention have a high-k dielectric layer and high alignment accuracy, effectively integrate the advantages of FDTI and BDTI processes, can effectively reduce optical and electrical crosstalk, reduce pixel dark current, and increase pixel quantum efficiency, so as to achieve the purpose of improving pixel performance.

[0103] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a fully through deep trench isolation structure, characterized in that: The following steps are involved: Providing a first substrate, wherein the first substrate has a front side and a back side opposite to each other, and a shallow trench isolation structure is formed in the front side of the first substrate; forming a deep trench, the deep trench penetrating the shallow trench isolation structure and extending into the first substrate, the deep trench comprising a first trench penetrating the shallow trench isolation structure and a second trench located below the first trench; Filling amorphous silicon in the second trench and filling a first isolation material in the first trench; Providing a second substrate, and bonding the front side of the first substrate to the second substrate; removing a portion of the back surface of the first substrate until the second trench is exposed, and removing the amorphous silicon in the second trench; as well as A high-k dielectric layer is filled on the sidewall and the bottom of the second trench, and a second isolation material is filled in the second trench.

2. The method for manufacturing a fully through deep trench isolation structure according to claim 1, characterized in that: Methods for forming deep trenches include: Forming a patterned hard mask layer on the front surface of the first substrate, wherein the patterned hard mask layer exposes the top surface of the shallow trench isolation structure; Using the patterned hard mask layer as a mask, etching the shallow trench isolation structure and the first substrate below the shallow trench structure; and The patterned hard mask layer is removed.

3. The method for manufacturing a fully through deep trench isolation structure according to claim 1, characterized in that: The method of filling amorphous silicon in the second trench and filling the first isolation material in the first trench comprises: Filling amorphous silicon in the deep trench, wherein the amorphous silicon fills up the deep trench; removing the amorphous silicon in the first trench; and A first isolation material is filled in the first trench.

4. The method for manufacturing a fully through deep trench isolation structure according to claim 3, characterized in that: The amorphous silicon is P-type or N-type doped; when the amorphous silicon is P-type doped, the doping concentration of the amorphous silicon is greater than the doping concentration of the first substrate.

5. The method for manufacturing a fully through deep trench isolation structure according to claim 4, characterized in that: The amorphous silicon in the first trench is removed by a wet etching process.

6. The method for manufacturing a fully through deep trench isolation structure according to claim 1, characterized in that: The method of forming a shallow trench isolation structure in the front surface of the first substrate comprises: forming an oxide layer and a nitride layer on the front surface of the first substrate; forming a shallow trench, wherein the shallow trench penetrates the nitride layer and the oxide layer and extends into the first substrate; and A third isolation material is filled in the shallow trench, and a surface of the third isolation material is flush with a surface of the nitride layer.

7. The method for manufacturing a fully through deep trench isolation structure according to claim 6, characterized in that: After filling the first isolation material in the first trench and before bonding, the method further includes: removing the nitride layer.

8. The method for manufacturing a fully through deep trench isolation structure according to claim 6, characterized in that: The first isolation material, the second isolation material and the third isolation material are all silicon oxide.

9. A fully through deep trench isolation structure, characterized in that: The method for manufacturing a fully through deep trench isolation structure according to any one of claims 1 to 8 is used to manufacture the fully through deep trench isolation structure, wherein the fully through deep trench isolation structure comprises: a second substrate, the first substrate being located on the second substrate; A deep trench, penetrating the first substrate, the deep trench comprising a first trench close to the second substrate and a second trench far away from the second substrate; A first isolation material filling the first trench; a high-k dielectric layer covering the sidewalls and the bottom of the second trench; and The second isolation material fills the two trenches.

10. The fully through deep trench isolation structure according to claim 9, characterized in that: The first isolation material and the second isolation material are both silicon oxide.

Images