VHF Data Link Simulator Based on Software Radio

Abstract

The present invention discloses a VHF data link simulation device based on software radio, which includes a controller; a vector signal transceiver connected to the controller; a VHF data link component connected to the vector signal transceiver; wherein the vector signal transceiver is used to receive the pulse signal sent by the VHF data link component and decode it to obtain a message according to the control of the controller, and to perform VDL encoding and up-conversion according to the configuration operation of the user to output the corresponding VHF data link signal; the pulse signal or the VHF data link signal is a VHF data link mode A signal or a VHF data link mode 2 signal. It can be seen that the present invention can realize the simulation of pulse signal sending and receiving of two VDL modes, and overcome the problems of low efficiency and incomplete functions of existing similar VHF data link simulation devices.

Description

Technical Field

[0001] The invention relates to the technical field of radio signal processing, and in particular to a very high frequency data link simulation device based on software radio. Background Art

[0002] The VHF data link on civil aircraft is used to achieve two-way communication between the aircraft and the ground. The VHF data link signals that need to be simulated for maintenance and testing of airborne VHF data link components mainly include Mode A and Mode 2. At present, this type of simulation device technology can simulate relatively few functions and monitor relatively few indicators, and can support only a few modes. Therefore, the existing technology has defects and needs to be improved urgently. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a very high frequency data link simulation device based on software radio, which overcomes the problems of low efficiency and incomplete functions of the existing similar very high frequency data link simulation devices.

[0004] In order to solve the above technical problems, the first aspect of the present invention discloses a very high frequency data link simulation device based on software radio, the device comprising: a controller; a vector signal transceiver connected to the controller; a very high frequency data link component connected to the vector signal transceiver; wherein the vector signal transceiver is used to receive the pulse signal emitted by the very high frequency data link component and decode it to obtain a message according to the control of the controller, and to perform VDL encoding and up-conversion to output the corresponding very high frequency data link signal according to the user's configuration operation; the pulse signal or the very high frequency data link signal is a very high frequency data link mode A signal or a very high frequency data link mode 2 signal.

[0005] Furthermore, when the pulse signal is a VHF data link mode A signal, the specific manner in which the vector signal transceiver receives the pulse signal sent by the VHF data link component and decodes the message includes:

[0006] Down-converting the pulse signal to obtain a first signal;

[0007] Performing rising edge capture pulse on the first signal to obtain a second signal;

[0008] The second signal is decoded to obtain a message.

[0009] Furthermore, before decoding the second signal to obtain a message, the vector signal transceiver further performs the following steps:

[0010] Determining the message power of the entire message according to the power of the leading header of the pulse signal;

[0011] Automatically power amplify the second signal according to the message power.

[0012] Furthermore, the specific manner in which the vector signal transceiver automatically amplifies the power of the second signal according to the message power includes:

[0013] Determine a reference power according to the message power;

[0014] The leading header in the second signal is discarded, and all remaining information bits are automatically gain amplified according to the reference power.

[0015] Furthermore, the specific manner in which the vector signal transceiver decodes the second signal to obtain a message includes:

[0016] Performing AM demodulation on the second signal to obtain a third signal;

[0017] Performing FIR low-pass filtering on the third signal to obtain a filtered signal;

[0018] The filtered signal is subjected to MSK demodulation, synchronization judgment, CRC verification and ISO5 decoding to obtain a message.

[0019] Furthermore, the specific manner in which the vector signal transceiver performs rising edge capture pulse on the first signal to obtain the second signal includes:

[0020] Delaying the first signal to obtain a first channel signal;

[0021] Performing FIR filtering on the first signal and amplifying the level by a preset multiple to obtain a second channel signal;

[0022] The first channel signal and the second channel signal are both input into a waiting trigger judgement device, and a second signal is generated when triggered.

[0023] Furthermore, when the VHF data link signal is a VHF data link mode A signal, the specific manner in which the vector signal transceiver performs VDL encoding and up-conversion according to the configuration operation of the user to output the corresponding VHF data link signal includes:

[0024] Receive configuration messages generated by user configuration;

[0025] Performing VDL encoding and MSK modulation on the configuration message to obtain a fourth signal;

[0026] After performing a frequency deviation of 1800 Hz on the fourth signal, I-channel AM is intercepted and AM modulation is performed to obtain a fifth signal;

[0027] The fifth signal is subjected to FPGA clock control triggering and VDL signal up-conversion to output a corresponding very high frequency data link signal.

[0028] Furthermore, when the pulse signal is a VHF data link mode 2 signal, the specific manner in which the vector signal transceiver receives the pulse signal sent by the VHF data link component and decodes the message includes:

[0029] Performing VDL signal down-conversion, rising edge triggering capture pulse and D8PSK demodulation on the pulse signal to obtain a sixth signal;

[0030] Performing a 180-degree phase shift on the sixth signal to obtain a seventh signal;

[0031] Performing respective synchronization decisions on the sixth signal and the seventh signal, and taking the one with a lower modulation error as the eighth signal;

[0032] Perform VDL decoding on the eighth signal to obtain a message.

[0033] Furthermore, the vector signal transceiver is further configured to perform the following steps:

[0034] obtaining historical communication records of the VHF data link component;

[0035] Inputting the historical communication records into a trained mode prediction neural network model to obtain a predicted VDL mode for the next communication; the VDL mode is a very high frequency data link mode A signal or a very high frequency data link mode 2 signal; the mode prediction neural network model is trained by training data including a plurality of training VDL communication records and corresponding next VDL mode annotations;

[0036] According to the VDL mode, the corresponding codes and components are pre-called before the next communication to improve the data processing efficiency of the next communication.

[0037] Furthermore, the vector signal transceiver is further used to perform the following steps:

[0038] obtaining historical communication records of the VHF data link component;

[0039] Inputting the historical communication records into a trained time prediction neural network model to obtain a predicted processing time for the next communication; the time prediction neural network model is trained by training data including a plurality of training VDL communication records and corresponding next communication time annotations;

[0040] Determine whether the predicted processing time is greater than a preset time threshold, if not, no operation is required;

[0041] If so, according to the correspondence between the preset time and the performance requirement, the corresponding processing performance requirement is determined according to the predicted processing time;

[0042] Before the next communication, the component that meets the processing performance requirement is determined as the processing component to improve the data processing efficiency of the next communication.

[0043] Compared with the prior art, the present invention has the following beneficial effects:

[0044] The present invention can realize the simulation of pulse signal sending and receiving of two VDL modes, and overcomes the problems of low efficiency and incomplete functions of the existing similar VDL simulation devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 The invention discloses a structural diagram of a very high frequency data link simulation device based on software radio.

[0047] Figure 2 It is a structural schematic diagram of a specific implementation scheme of a very high frequency data link simulation device based on software radio disclosed in an embodiment of the present invention.

[0048] Figure 3 It is a flowchart of receiving software of a very high frequency data link mode A disclosed in an embodiment of the present invention.

[0049] Figure 4 It is a schematic diagram of the process and waveform results of an automatic power amplification technology of a very high frequency data link mode A disclosed in an embodiment of the present invention.

[0050] Figure 5 The invention is a flowchart of a VHF data link rising edge triggering method disclosed in an embodiment of the invention.

[0051] Figure 6 The present invention is a flowchart of a method for outputting a very high frequency data link signal disclosed in an embodiment of the present invention.

[0052] Figure 7 It is a flowchart of a decoding method of a very high frequency data link mode 2 signal disclosed in an embodiment of the present invention.

[0053] Figure 8 It is a flow chart of an output coding method of a very high frequency data link mode 2 signal disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0054] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] The terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, device, product or end including a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules that are not listed, or may optionally include other steps or modules that are inherent to these processes, methods, products or ends.

[0056] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0057] The present invention aims to provide an innovative VHF data link simulation device based on software radio, which can realize the simulation of pulse signal sending and receiving of two VDL modes, and overcome the problems of low efficiency and incomplete functions of existing similar VHF data link simulation devices.

[0058] For details, please refer to Figure 1 , Figure 1 1 is a schematic diagram of the structure of a VHF data link simulation device based on software radio disclosed in an embodiment of the present invention. Figure 1 As shown, the VHF data link simulation device based on software radio includes a controller, a vector signal transceiver connected to the controller, and a VHF data link component connected to the vector signal transceiver.

[0059] Specifically, the vector signal transceiver is used to receive the pulse signal sent by the very high frequency data link component and decode it to obtain a message according to the control of the controller, and to perform VDL encoding and up-conversion to output the corresponding very high frequency data link signal according to the user's configuration operation, wherein the pulse signal or very high frequency data link signal is a very high frequency data link mode A signal or a very high frequency data link mode 2 signal.

[0060] Specifically, the VHF data link, or VDL (VHF Air-Ground Digital Link) equipment is mainly used for data transmission between air and ground. Its data transmission capability makes it a mobile sub-network of the Aeronautical Telecommunications Network (ATN). Due to the use of the AVLC (Aviation VHF Link Control) message protocol format, the VHF data link has reporting and addressing capabilities.

[0061] In a specific implementation scheme, based on a PXIe chassis, modular hardware is used to design the simulation device in the present invention. A single device can realize the functional performance test, debugging, and signal simulation of the very high frequency data link of Collins VHF-2100 aviation materials or other similar equipment. It has the advantages of small size and easy expansion and upgrading. Specifically, this implementation scheme can refer to Figure 2 , including PXIe chassis (including controller, vector signal transceiver), display (touch screen), RF components and front panel interface; the transmission pulse of the VHF data link component passes through the RF input port and is down-converted by the vector signal transceiver to obtain the baseband signal; the user customizes the VHF data link signal generated by the display screen, the vector signal transceiver realizes the generation of pulse baseband signal, and the up-converter is used to output the RF signal.

[0062] In an optional embodiment, when the pulse signal is a VHF data link mode A signal, the specific manner in which the vector signal transceiver receives the pulse signal sent by the VHF data link component and decodes the message includes:

[0063] Down-converting the pulse signal to obtain a first signal;

[0064] Capturing the rising edge pulse of the first signal to obtain a second signal;

[0065] The second signal is decoded to obtain a message.

[0066] In an optional embodiment, the specific manner in which the vector signal transceiver decodes the second signal to obtain a message includes:

[0067] Performing AM demodulation on the second signal to obtain a third signal;

[0068] Performing FIR low-pass filtering on the third signal to obtain a filtered signal;

[0069] The filtered signal is subjected to MSK demodulation, synchronization judgment, CRC verification and ISO5 decoding to obtain the message.

[0070] In the above implementation scheme, a VHF data link mode A receiving software is implemented according to the above embodiment. The flow chart can be found in Figure 3, its demodulation mode is A3E, i.e., MSK-AM. Based on the traditional demodulation mode, between AM demodulation and MSK demodulation, the present invention introduces a FIR low-pass filter, which is based on the not smooth waveform obtained after the previous step of AM envelope demodulation. The sudden change of amplitude will lead to the increase of interference in the frequency domain, and the bit error rate can be reduced after filtering. After demodulation, the message of VHF data link mode A is obtained through synchronization and decoding. CRC verification is used to verify the correctness of the message and count the frame error rate.

[0071] In an optional embodiment, before decoding the second signal to obtain the message, the vector signal transceiver further performs the following steps:

[0072] Determine the message power of the entire message according to the power of the leading header of the pulse signal;

[0073] Automatically power amplify the second signal according to the message power.

[0074] In an optional embodiment, the specific manner in which the vector signal transceiver automatically amplifies the power of the second signal according to the message power includes:

[0075] Determine the reference power according to the message power;

[0076] The leading header in the second signal is discarded, and all remaining information bits are automatically gain amplified according to the reference power.

[0077] In the above implementation scheme, an automatic power amplification technology of VHF data link mode A is implemented according to the above embodiment, see Figure 4 The above process can determine the power of the entire message based on the message characteristics of mode A and the power of its pre-key, and automatically complete the power measurement and reference power adjustment within the transmission time of the pre-key, so that the optimal reference power state is achieved before the arrival of the subsequent message. Before adding this function, the dynamic receiving range of the vector signal transceiver was only 20dB; after adding this function, the dynamic receiving range of the vector signal transceiver reaches a maximum of 60dB, which greatly improves the sensitivity of the VHF data link mode A receiver. The effect can be seen in Figure 4 The waveform diagram below shows this.

[0078] In an optional embodiment, the specific manner in which the vector signal transceiver performs rising edge capture pulse on the first signal to obtain the second signal includes:

[0079] Delaying the first signal to obtain a first channel signal;

[0080] Performing FIR filtering on the first signal and amplifying the level by a preset multiple to obtain a second channel signal;

[0081] The first channel signal and the second channel signal are both input into the waiting trigger judgement device, and the second signal is generated when triggered.

[0082] In the above implementation scheme, a VHF data link rising edge triggering method is implemented according to the above embodiment, see Figure 5 Different from the traditional half-wave rising edge trigger, the VHF data link rising edge trigger mode does not use half of the pulse amplitude itself, but uses N times the noise level after FIR filtering as the trigger threshold. This change is based on the pulse characteristics of the VHF data link: unfixed pulse width, unfixed transmission period, and the internal power level of the transmitted pulse is not constant (mode 2). Therefore, a dedicated trigger mode is redesigned, which has the characteristics of no false triggering and no missed triggering. When waiting for triggering, channel 2 is N times larger than channel 1; at the moment of triggering, due to the delay effect, the VHF data link signal-to-noise ratio only needs to be greater than N to trigger; during the triggering period, channel 2 is N times larger than channel 1 again, and there is no false triggering.

[0083] In an optional embodiment, when the VHF data link signal is a VHF data link mode A signal, the specific manner in which the vector signal transceiver performs VDL encoding and up-conversion according to the user's configuration operation to output the corresponding VHF data link signal includes:

[0084] Receive configuration messages generated by user configuration;

[0085] Performing VDL encoding and MSK modulation on the configuration message to obtain a fourth signal;

[0086] After the fourth signal is frequency-shifted by 1800 Hz, I-channel AM is intercepted and AM modulation is performed to obtain a fifth signal;

[0087] The fifth signal is triggered by FPGA clock control and the VDL signal is up-converted to output a corresponding very high frequency data link signal.

[0088] In the above implementation scheme, a method of outputting a VHF data link signal is implemented according to the above embodiment, see Figure 6 After the user configures the VHF data link message through the software interface, VDL mode A encoding (including ISO5, CRC, parity check, etc.) is performed. The present invention intercepts I-channel AM by MSK frequency deviation 1800Hz for A3E modulation. 1800Hz is calculated by the code rate 2400Hz and the encoding characteristics of mode A; this modulation method is simple and easy to use, and does not require too much hardware computing resources. After the modulation is completed, the RF output is output.

[0089] In an optional embodiment, when the pulse signal is a VHF data link mode 2 signal, the specific manner in which the vector signal transceiver receives the pulse signal sent by the VHF data link component and decodes the message includes:

[0090] Performing VDL signal down-conversion, rising edge triggering capture pulse and D8PSK demodulation on the pulse signal to obtain a sixth signal;

[0091] Performing a 180-degree phase shift on the sixth signal to obtain a seventh signal;

[0092] Performing synchronization judgment on the sixth signal and the seventh signal respectively, and taking the group with lower modulation error as the eighth signal;

[0093] Perform VDL decoding on the eighth signal to obtain a message.

[0094] In the above implementation scheme, a decoding method of VHF data link mode 2 signal is implemented according to the above embodiment, see Figure 7 , after the VHF data link mode 2 is down-converted, the rising edge trigger judgment is used to obtain a pulse, and the waveform can be FFT to obtain the spectrum. The demodulation method is D8PSK, and the raised cosine coefficient is 0.6. Based on the traditional demodulation method, the present invention performs synchronization judgment on the two phase-symmetrical signals obtained by phase shifting 180°, and takes the group with lower modulation error for decoding to reduce the bit error rate. After synchronization, the VHF data link mode 2 message is obtained through mode 2 decoding; the decoding structure is shown in the figure, and the bits are de-interleaved and RS is de-interleaved at the same time. RS can count the bit error rate and make error correction. The present invention finds the start bit, end bit, interleaving number, and RS algorithm for de-interleaving. Then find the flag bit to identify the CRC position and verify that the message is correct and count the frame error rate, remove the inserted 0 bit and remove the padding bit. Finally, ISO5 decoding is performed to obtain the VDL message.

[0095] More specifically, the above implementation scheme also designs an output encoding method for VHF data link mode 2 signals, see Figure 8 After the user configures the VHF data link message through the software interface, VDL mode 2 encoding (including ISO5, CRC, FEC, RS, etc.) is performed. The software of the present invention realizes the signal generation process of the VHF data link mode 2 message, as shown in the figure. After encoding, D8PSK modulation and raised cosine 0.6 filtering are performed. The mode 2 header is made to meet the standard through the window function method. After modulation is completed, the RF output is performed.

[0096] In an optional embodiment, the vector signal transceiver is further configured to perform the following steps:

[0097] Obtain historical communication records of VHF data link components;

[0098] Inputting historical communication records into a trained mode prediction neural network model to obtain a predicted VDL mode of next communication; the VDL mode is a very high frequency data link mode A signal or a very high frequency data link mode 2 signal; the mode prediction neural network model is trained by training data including a plurality of training VDL communication records and corresponding next VDL mode annotations;

[0099] According to the VDL mode, the corresponding codes and components are pre-called before the next communication to improve the data processing efficiency of the next communication.

[0100] Specifically, the pattern prediction neural network model can be trained by collecting, cleaning and annotating historical communication data of multiple simulation devices to obtain training data.

[0101] Through the above embodiments, it is possible to predict the pre-set VDL mode to improve the data processing efficiency of the next communication.

[0102] In an optional embodiment, the vector signal transceiver is further configured to perform the following steps:

[0103] Obtain historical communication records of VHF data link components;

[0104] Inputting historical communication records into a trained time prediction neural network model to obtain a predicted processing time of the next communication; the time prediction neural network model is trained by training data including a plurality of training VDL communication records and corresponding next communication time annotations;

[0105] Determine whether the predicted processing time is greater than a preset time threshold, if not, no operation is required;

[0106] If so, according to the correspondence between the preset time and the performance requirement, the corresponding processing performance requirement is determined according to the predicted processing time;

[0107] Before the next communication, the component that meets the processing performance requirement is determined as the processing component to improve the data processing efficiency of the next communication.

[0108] Optionally, the processing component may be a controller or a vector signal transceiver or a signal processing component with different performances.

[0109] Specifically, the historical communication data of multiple simulation devices can be collected, cleaned and annotated to obtain training data, the time prediction neural network model can be trained, and the correspondence between the above-mentioned preset time and performance requirements can be simulated through a mathematical simulation algorithm, which can be a mathematical polynomial relationship model or a numerical correspondence.

[0110] Through the above embodiments, it is possible to predict the predicted processing time of the next communication to determine the corresponding processing performance requirements, so that before the next communication, the components that meet the processing performance requirements are determined as processing components, thereby improving the data processing efficiency of the next communication.

[0111] The above describes specific embodiments of the present specification, and other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily have to be performed in the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0112] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device, equipment, and non-volatile computer-readable storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0113] The apparatus, device, non-volatile computer-readable storage medium and method provided in the embodiments of this specification correspond to each other, and therefore, the apparatus, device, and non-volatile computer storage medium also have similar beneficial technical effects as the corresponding methods. Since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the corresponding apparatus, device, and non-volatile computer storage medium will not be repeated here.

[0114] In the 1990s, improvements to a technology could be clearly distinguished as hardware improvements (for example, improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the method flow). However, with the development of technology, many improvements to the method flow today can be regarded as direct improvements to the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that an improvement in a method flow cannot be implemented using a hardware entity module. For example, a programmable logic device (PLD) (such as a field programmable gate array (FPGA)) is such an integrated circuit whose logical function is determined by the user's programming of the device. Designers can "integrate" a digital system on a PLD by programming it themselves, without having to ask a chip manufacturer to design and produce a dedicated integrated circuit chip. Moreover, nowadays, instead of manually making integrated circuit chips, this kind of programming is mostly implemented by "logic compiler" software, which is similar to the software compiler used when developing and writing programs, and the original code before compilation must also be written in a specific programming language, which is called hardware description language (HDL). There is not only one HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. The most commonly used ones are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also know that it is only necessary to program the method flow slightly in the above-mentioned hardware description languages ​​and program it into the integrated circuit, and then it is easy to obtain the hardware circuit that implements the logic method flow.

[0115] The controller can be implemented in any appropriate manner, for example, the controller can take the form of a microprocessor or processor and a computer-readable medium storing a computer-readable program code (such as software or firmware) that can be executed by the (micro)processor, a logic gate, a switch, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320. The memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art also know that in addition to implementing the controller in a purely computer-readable program code manner, the controller can be implemented in the form of a logic gate, a switch, an application-specific integrated circuit, a programmable logic controller, and an embedded microcontroller by logically programming the method steps. Therefore, this controller can be considered as a hardware component, and the devices included therein for implementing various functions can also be regarded as structures within the hardware component. Or even, the devices for implementing various functions can be regarded as both software modules for implementing the method and structures within the hardware component.

[0116] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0117] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing this specification, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0118] Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems, or computer program products. Therefore, the embodiments of this specification may be in the form of complete hardware embodiments, complete software embodiments, or embodiments in combination with software and hardware. Moreover, the embodiments of this specification may be in the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0119] This specification is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of this specification. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0120] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0121] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0122] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0123] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0124] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0125] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0126] This specification may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. This specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0127] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0128] Finally, it should be noted that the VHF data link simulation device based on software radio disclosed in the embodiment of the present invention only discloses a preferred embodiment of the present invention, which is only used to illustrate the technical solution of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions recorded in the aforementioned embodiments can still be modified, or some of the technical features therein can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A very high frequency data link simulation device based on software radio, characterized in that: The device comprises: Controller; a vector signal transceiver connected to the controller; A very high frequency data link component connected to the vector signal transceiver; wherein the vector signal transceiver is used to receive the pulse signal sent by the very high frequency data link component and decode it to obtain a message according to the control of the controller, and to perform VDL encoding and up-conversion according to the configuration operation of the user to output the corresponding very high frequency data link signal; the pulse signal or the very high frequency data link signal is a very high frequency data link mode A signal or a very high frequency data link mode 2 signal; the vector signal transceiver is also used to perform the following steps: obtaining historical communication records of the VHF data link component; Inputting the historical communication records into the trained mode prediction neural network model to obtain the predicted VDL mode of the next communication; the VDL mode is a very high frequency data link mode A signal or a very high frequency data link mode 2 signal; the mode prediction neural network model is trained by training data including a plurality of training VDL communication records and corresponding next VDL mode annotations; the mode prediction neural network model is trained by collecting, cleaning and annotating the historical communication data of a plurality of simulation devices to obtain training data; According to the VDL mode, the corresponding codes and components are pre-called before the next communication to improve the data processing efficiency of the next communication; The historical communication records are input into a trained time prediction neural network model to obtain a predicted processing time for the next communication; the time prediction neural network model is trained by training data including a plurality of training VDL communication records and corresponding annotations of the next communication time; the training data is obtained by collecting, cleaning and annotating the historical communication data of a plurality of simulation devices, and the time prediction neural network model is trained; Determine whether the predicted processing time is greater than a preset time threshold, if not, no operation is required; If so, according to the correspondence between the preset time and the performance requirement, the corresponding processing performance requirement is determined according to the predicted processing time; the correspondence between the preset time and the performance requirement is simulated by a mathematical simulation algorithm, and the correspondence is a mathematical polynomial relationship model or a numerical correspondence; Before the next communication, the component that meets the processing performance requirement is determined as the processing component to improve the data processing efficiency of the next communication; the processing component is a controller or vector signal transceiver or signal processing component with different performance.

2. The VHF data link simulation device based on software radio according to claim 1, characterized in that: When the pulse signal is a VHF data link mode A signal, the specific manner in which the vector signal transceiver receives the pulse signal sent by the VHF data link component and decodes the message includes: Down-converting the pulse signal to obtain a first signal; Performing rising edge capture pulse on the first signal to obtain a second signal; The second signal is decoded to obtain a message.

3. The VHF data link simulation device based on software radio according to claim 2, characterized in that: Before decoding the second signal to obtain a message, the vector signal transceiver further performs the following steps: Determining the message power of the entire message according to the power of the leading header of the pulse signal; Automatically power amplify the second signal according to the message power.

4. The VHF data link simulation device based on software radio according to claim 3 is characterized in that: The specific manner in which the vector signal transceiver automatically amplifies the power of the second signal according to the message power includes: Determine a reference power according to the message power; The leading header in the second signal is discarded, and all remaining information bits are automatically gain amplified according to the reference power.

5. The VHF data link simulation device based on software radio according to claim 2 is characterized in that: The specific manner in which the vector signal transceiver decodes the second signal to obtain a message includes: Performing AM demodulation on the second signal to obtain a third signal; Performing FIR low-pass filtering on the third signal to obtain a filtered signal; The filtered signal is subjected to MSK demodulation, synchronization judgment, CRC verification and ISO5 decoding to obtain a message.

6. The VHF data link simulation device based on software radio according to claim 2 is characterized in that: The specific method in which the vector signal transceiver performs rising edge capture pulse on the first signal to obtain the second signal includes: Delaying the first signal to obtain a first channel signal; Performing FIR filtering on the first signal and amplifying the level by a preset multiple to obtain a second channel signal; The first channel signal and the second channel signal are both input into a waiting trigger judgement device, and a second signal is generated when triggered.

7. The VHF data link simulation device based on software radio according to claim 1 is characterized in that: When the VHF data link signal is a VHF data link mode A signal, the specific manner in which the vector signal transceiver performs VDL encoding and up-conversion according to the configuration operation of the user to output the corresponding VHF data link signal includes: Receive configuration messages generated by user configuration; Performing VDL encoding and MSK modulation on the configuration message to obtain a fourth signal; After performing a frequency deviation of 1800 Hz on the fourth signal, I-channel AM is intercepted and AM modulation is performed to obtain a fifth signal; The fifth signal is subjected to FPGA clock control triggering and VDL signal up-conversion to output a corresponding very high frequency data link signal.

8. The VHF data link simulation device based on software radio according to claim 1 is characterized in that: When the pulse signal is a VHF data link mode 2 signal, the specific manner in which the vector signal transceiver receives the pulse signal sent by the VHF data link component and decodes the message includes: Performing VDL signal down-conversion, rising edge triggering capture pulse and D8PSK demodulation on the pulse signal to obtain a sixth signal; Performing a 180-degree phase shift on the sixth signal to obtain a seventh signal; Performing respective synchronization decisions on the sixth signal and the seventh signal, and taking the one with a lower modulation error as the eighth signal; Perform VDL decoding on the eighth signal to obtain a message.

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