Occultation detector, debugging method and debugging system

Abstract

The present invention provides an occultation detector, a debugging method and a debugging system, which belong to the technical field of occultation detectors. The interface conversion circuit includes a serial bus interface, a power module and a signal conversion module; the power module is configured to output a startup voltage to the signal conversion module in response to an external electronic device accessing the serial bus interface; the signal conversion module is configured to receive a program to be burned transmitted by the external electronic device via the serial bus interface in response to the startup voltage, and transmit the program to be burned to the JTAG interface of the SOC chip to burn the program to the SOC chip; and the debugging result information output by the debugging serial port of the SOC chip is transmitted to the external electronic device through the serial bus interface. The interface conversion circuit provided by the present invention improves the convenience of external electronic devices burning programs and debugging the SOC chip in the occultation detector.

Description

Technical Field

[0001] The invention belongs to the technical field of occultation detectors, and in particular relates to an occultation detector, a debugging method and a debugging system. Background Art

[0002] With the widespread application of detection data from space-borne occultation detectors in the field of meteorology, in order to be able to receive all frequencies of all GNSS (Global Navigation Satellite System), multiple SOC (System on Chip) chips are set in the occultation detector as core processors to improve the effective observation volume of occultation detection.

[0003] However, when programming each SOC chip, an additional JTAG program downloader and a USB-to-serial converter are required, and each time the SOC chip is switched for program programming, the power needs to be turned off and the power needs to be re-plugged, which is inconvenient to operate. Summary of the invention

[0004] In view of the above problems, the embodiments of the present application provide an occultation detector, a debugging method and a debugging system to overcome the above problems or at least partially solve the above problems.

[0005] In a first aspect of an embodiment of the present application, an occultation detector is provided, the occultation detector comprising an interface conversion circuit and at least one SOC chip; wherein:

[0006] The interface conversion circuit includes a serial bus interface, and a power module and a signal conversion module connected to the serial bus interface; wherein the signal conversion module is also connected to the power module and the SOC chip, and the serial bus interface is used to connect to an external electronic device;

[0007] The power supply module is configured to output a startup voltage to the signal conversion module in response to the external electronic device being connected to the serial bus interface;

[0008] The signal conversion module is configured to receive the program to be burned transmitted by the external electronic device via the serial bus interface in response to the startup voltage, and transmit the program to be burned to the JTAG interface of the SOC chip, so as to burn the program to be burned into the SOC chip;

[0009] And, transmitting the debugging result information output by the debugging serial port of the SOC chip to the external electronic device through the serial bus interface;

[0010] The debugging result information is the result information of the SOC chip debugging the burned program.

[0011] Furthermore, the interface conversion circuit also includes an isolation chip; wherein,

[0012] The isolation chip is connected in series between the signal conversion module and the SOC chip, and is connected to the power module;

[0013] The isolation chip is configured to isolate the communication between the signal conversion module and the SOC chip in response to the external electronic device being unplugged from the serial bus interface.

[0014] Furthermore, the isolation chip includes a first isolation chip and a second isolation chip; wherein,

[0015] The first end of the first isolation chip and the first end of the second isolation chip are connected in parallel to one end of the signal conversion module, and the second end of the first isolation chip and the second end of the second isolation chip are connected to different SOC chips respectively.

[0016] Further, the SOC chip includes a first SOC chipset and a second SOC chipset; wherein the second SOC chipset is a backup SOC chip of the first SOC chipset;

[0017] The first SOC chipset is connected to the first isolation chip, and the second SOC chipset is connected to the second isolation chip.

[0018] Furthermore, the first SOC chipset includes a plurality of first SOC chips; wherein each first SOC chip is provided with a first interface and a second interface respectively;

[0019] The first interfaces and the second interfaces corresponding to the plurality of the first SOC chips are connected in series with each other, and among the plurality of the first SOC chips, there is a first interface corresponding to the first SOC chip connected in series with the first isolation chip, and there is another second interface corresponding to the first SOC chip connected in series with the isolation chip;

[0020] Among them, other interfaces except the first interface and the second interface on each first SOC chip are connected in parallel to the first isolation chip.

[0021] Furthermore, the SOC chip includes: a clock interface, a mode interface, a data input interface, a data output interface and a debugging serial port;

[0022] The signal conversion module includes: a JTAG signal output interface, a JTAG signal input interface and a debug input serial port; wherein,

[0023] The clock interface, the mode interface, and the data input interface are connected to the JTAG signal output interface, the data output interface is connected to the JTAG signal input interface, and the debugging serial port is connected to the debugging input serial port.

[0024] Further, it includes: a plurality of SOC chips; wherein,

[0025] The debugging serial ports corresponding to the plurality of SOC chips are connected to the debugging input serial port of the signal conversion module;

[0026] The clock interfaces and mode interfaces corresponding to the plurality of SOC chips are respectively connected to the JTAG signal output interface of the signal conversion module; wherein,

[0027] Among the multiple SOC chips, there is at least one data output interface of a first SOC chip, which is connected in series with the data input interface of at least one second SOC chip, and the data input interface of the first SOC chip is connected to the JTAG signal output interface, and the data output interface of the second SOC chip is connected to the JTAG signal input interface; wherein the number of the first SOC chips is equal to the number of the second SOC chips.

[0028] Furthermore, the interface conversion circuit also includes a memory; wherein the memory is connected in series between the power module and the signal conversion module;

[0029] The memory is configured to output a configuration code to the signal conversion module in response to the startup voltage; the configuration code is used to define a function of the signal conversion module.

[0030] Furthermore, the interface conversion circuit further comprises a crystal oscillator; wherein the crystal oscillator is connected in series between the power supply module and the signal conversion module;

[0031] The crystal oscillator is configured to output a clock signal to the signal conversion module in response to the start-up voltage.

[0032] Furthermore, the occultation detector further includes: a third isolation chip and a fourth isolation chip, wherein:

[0033] The first end of the third isolation chip and the first end of the fourth isolation chip are connected in parallel to one end of the isolation chip, and the second end of the third isolation chip and the second end of the fourth isolation chip are connected to different SOC chips respectively;

[0034] The third isolation chip is configured to present a low impedance state in response to a power-on signal output by a SOC chip connected to the third isolation chip;

[0035] The fourth isolation chip is configured to present a low impedance state in response to a power-on signal output by a SOC chip connected to the fourth isolation chip.

[0036] Furthermore, a first AND gate circuit is provided between the first isolation chip and the power module; wherein the first AND gate circuit is also connected to a first SOC chip connected to the first isolation chip, and is used to receive a first power-on signal output by the first SOC chip;

[0037] A second AND gate circuit is provided between the second isolation chip and the power module, wherein the second AND gate circuit is also connected to a second SOC chip connected to the second isolation chip, and is used to receive a second power-on signal output by the second SOC chip;

[0038] Wherein, the first AND gate circuit is configured to control the first isolation chip to be in a low-resistance state in response to the start-up voltage and the first power-on signal;

[0039] The second AND gate circuit is configured to control the second isolation chip to be in a low-resistance state in response to the start-up voltage and the second power-on signal.

[0040] Furthermore, the first isolation chip and the second isolation chip do not present a low-resistance state at the same time.

[0041] Furthermore, the serial bus interface is a universal serial bus interface.

[0042] In a second aspect of the embodiment of the present application, a debugging method is provided, which is applied to the interface conversion circuit in the occultation detector described in the first aspect of the embodiment of the present application, and the debugging method includes:

[0043] Acquiring power information of at least one SOC chip in the occultation detector; wherein the power information is used to indicate whether the SOC chip is powered on;

[0044] Based on the power information, receiving the program to be burned transmitted by the external electronic device via the serial bus interface through the serial bus interface of the interface conversion circuit;

[0045] And, transmitting the program to be burned to the JTAG interface of the SOC chip through the signal conversion module of the interface conversion circuit;

[0046] And receiving the debugging result information output by the debugging serial port of the SOC chip based on the serial bus interface; wherein the debugging result information is the result information of the debugging of the burned program by the SOC chip.

[0047] Furthermore, the at least one SOC chip includes a plurality of SOC chips connected in series in sequence; and the step of obtaining power supply information of at least one SOC chip in the occultation detector includes:

[0048] Acquiring power information of the plurality of SOC chips;

[0049] Based on the power information, determining the order of programs to be burned into the plurality of SOC chips;

[0050] The signal conversion module of the interface conversion circuit transmits the program to be burned to the JTAG interface of the SOC chip, including:

[0051] Based on the burning order of the programs to be burned, the communication connection between the external electronic device and the plurality of SOC chips is sequentially conducted, so as to sequentially transmit the programs to be burned to the JTAG interfaces of the plurality of SOC chips.

[0052] Furthermore, the occultation detector includes a first SOC chipset and a second SOC chipset connected in parallel, and the front ends of the first SOC chipset and the second SOC chipset are respectively provided with different isolation chips, and the first SOC chipset and the second SOC chipset are backup for each other; the step of obtaining power supply information of at least one SOC chip in the occultation detector includes:

[0053] Respectively obtaining power information of the first SOC chipset and the second SOC chipset;

[0054] Based on the power information, determining a target SOC chipset for the program to be burned;

[0055] Based on the target SOC chipset, maintaining the target isolation chip provided at the front end of the target SOC chipset in a low impedance state through the power module of the interface conversion circuit;

[0056] The signal conversion module of the interface conversion circuit transmits the program to be burned to the JTAG interface of the SOC chip, including:

[0057] Based on the conduction of the isolation chip, the program to be burned is transmitted to the JTAG interface of the target SOC chipset through the signal conversion module.

[0058] Furthermore, after transmitting the program to be burned to the JTAG interface of the target SOC chipset through the signal conversion module based on the conduction of the isolation chip, the method further includes:

[0059] Obtaining debugging result information output by the debugging serial port of the target SOC chipset;

[0060] Based on the debugging result information, determining whether the target SOC chipset is burned successfully;

[0061] If so, the target isolation chip is switched to a high-impedance state through the power module, and other target isolation chips except the target isolation chip are switched to a low-impedance state, and the program to be burned is transmitted to the JTAG interface of the SOC chipset corresponding to the other target isolation chips through the signal conversion module.

[0062] In a third aspect of the embodiment of the present application, a debugging system is provided, comprising an external electronic device and the occultation detector described in the first aspect of the embodiment of the present application; wherein:

[0063] The external electronic device transmits the program to be burned to the interface conversion circuit in response to the serial bus interface connected to the interface conversion circuit;

[0064] The interface conversion circuit, in response to the arrival of the program to be burned, transmits the program to be burned to the JTAG interface of the SOC chip in the occultation detector through the signal conversion module in the interface conversion circuit;

[0065] The occultation detector, in response to the arrival of the program to be burned, burns the program to be burned into the SOC chip.

[0066] Furthermore, the interface conversion circuit is also responsive to the debugging result information output by the debugging serial port of the SOC chip, and transmits the debugging result information to the external electronic device via the serial bus interface; wherein the debugging result information is the result information of the SOC chip debugging the burned program;

[0067] The external electronic device also determines whether to debug the SOC chip again in response to the debugging result information.

[0068] Furthermore, the external electronic device also performs fault detection on the SOC chip corresponding to the number of debugging times exceeding a threshold value in response to the number of debugging times of each SOC chip.

[0069] The interface conversion circuit provided in this embodiment is arranged in an occultation detector; the occultation detector includes at least one SOC chip.

[0070] The interface conversion circuit includes a serial bus interface, and a power module and a signal conversion module connected to the serial bus interface; wherein the signal conversion module is also connected to the power module and the SOC chip, and the serial bus interface is used to connect to external electronic devices.

[0071] Therefore, during the process of burning programs and debugging the SOC chip in the occultation detector, a communication connection can be established with external electronic devices through the serial bus interface in the interface conversion circuit, thereby reducing the interface resources of the occultation detector (the number of JTAG program downloaders and USB-to-serial converters).

[0072] In addition, the power module is configured to output a starting voltage to the signal conversion module in response to an external electronic device being connected to the serial bus interface; therefore, during the process of burning the program and debugging the SOC chip in the occultation detector, the signal conversion module can be powered by the power module without increasing the extra power consumption of the occultation detector as a whole, while also ensuring that the interface conversion circuit will not affect the reliability of the on-orbit operation of the occultation detector.

[0073] Secondly, the signal conversion module is configured to respond to the starting voltage, receive the program to be burned transmitted by the external electronic device via the serial bus interface, and transmit the program to be burned to the JTAG interface of the SOC chip, so as to burn the program to be burned into the SOC chip; and transmit the debugging result information output by the debugging serial port of the SOC chip to the external electronic device through the serial bus interface; wherein the debugging result information is the result information of the SOC chip debugging the burned program, so when multiple SOC chips in the occultation detector are burned and debugged, the communication connection between the occultation detector and the external electronic device is directly established through the signal conversion module and the serial bus interface, without re-plugging, and the data transmission of the program to be burned and the debugging result information between the external electronic device and the multiple SOC chips can be realized, thereby improving the convenience of the external electronic device burning the program and debugging the SOC chip in the occultation detector. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0075] Figure 1 It is a schematic diagram of connection between an occultation detector and external equipment provided by the related technology;

[0076] Figure 2 This is a schematic diagram of the connection between an occultation detector and external equipment provided in an embodiment of the present application;

[0077] Figure 3 It is a module detailed schematic diagram of an interface conversion circuit provided in an embodiment of the present application;

[0078] Figure 4It is for Figure 3 A schematic diagram of the connection between an interface conversion circuit and a SOC chip is provided;

[0079] Figure 5 It is for Figure 3 A schematic diagram of the connection between an interface conversion circuit and a SOC chipset is provided;

[0080] Figure 6 This is a connection diagram of a power module control isolation chip provided in an embodiment of the present application;

[0081] Figure 7 This is a connection diagram of another power module control isolation chip provided in an embodiment of the present application;

[0082] Figure 8 It is for Figure 5 A schematic diagram of the connection between an interface conversion circuit and multiple SOC chips in a SOC chipset is provided;

[0083] Fig. 9 This is a schematic diagram of the connection between an interface conversion circuit and a SOC chip provided in an embodiment of the present application;

[0084] Fig.10 This is a schematic diagram of the connection between an interface conversion circuit and multiple SOC chips provided by an embodiment of the present application;

[0085] Fig.11 This is a detailed schematic diagram of a module of another interface conversion circuit provided in an embodiment of the present application;

[0086] Fig.12 This is a schematic diagram of the connection between an occultation detector and an external electronic device provided in an embodiment of the present application;

[0087] Fig.13 It is for Fig.12 A schematic diagram of an interface conversion circuit is provided;

[0088] Fig.14 It is for Fig.12 A schematic diagram of the connection between an interface conversion circuit and a SOC chip is provided;

[0089] Fig.15 It is for Fig.12 A simplified schematic diagram of the connection between an occultation detector and external electronic equipment is provided;

[0090] Fig.16 It is a step flow chart of a debugging method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0091] The exemplary embodiments of the present application will be described in more detail below in conjunction with the accompanying drawings in the embodiments of the present application. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present application and to enable the scope of the present application to be fully conveyed to those skilled in the art.

[0092] With the widespread application of detection data from space-borne occultation detectors in the field of meteorology, new requirements have been put forward for occultation detectors. They need to be able to receive all frequency points of all GNSS systems to improve the effective observation of occultation detection, and at the same time, higher requirements have been put forward for the reliability of occultation detectors. The current occultation detector uses a SOC as the core processor. Due to limited resources, it cannot meet the signal processing of all frequency points of all GNSS systems, so two SOCs are needed for signal processing. At the same time, in order to improve the reliability of the occultation detector on orbit, a master-backup design is required. The master and backup circuits are exactly the same. By default, only the master is powered on and works. When the master is abnormal, it can switch to the backup to work, thereby improving the reliability of the occultation reflection detector on orbit. In this way, a total of 4 SOC chips are required for an occultation detector.

[0093] Reference Figure 1 , Figure 1 This is a schematic diagram of the connection between an occultation detector and external equipment provided by the relevant technology. Figure 1 It can be seen that Figure 1 The external device in the system is a computer. Since each SOC chip of the occultation detector requires a program burning interface and a debugging information output interface, the JTAG program downloader is connected to the computer to debug and burn the SOC program. The debugging information output by the occultation detector SOC is received through the computer through the USB to serial converter to view the system debugging information. The current method is used to burn the program and view the debugging information. Therefore, a total of 4 program download interfaces and 4 debugging information output interfaces are required for 4 SOC chips, and additional JTAG program downloaders and USB to serial converters are required. When burning the program for debugging, the program burner and the debugging USB to serial converter of the SOC chip that needs to be debugged need to be connected. When debugging another SOC chip, the program burning line and the debugging line need to be unplugged and plugged into the download port and debugging port of another SOC to burn and debug the program. Each switch requires power off and re-plugging, which is inconvenient to operate. In addition, since the 4-channel program burning interface and the 4-channel debugging interface need to be led out from the casing of the occultation detector, more space is occupied, and the size and weight of the occultation detector are further increased.

[0094] Therefore, in order to solve the above problems, an occultation detector provided in an embodiment of the present application can reduce the number of JTAG program downloaders and USB-to-serial converters to solve the above problems.

[0095] Reference Figure 2 , Figure 2 is a schematic diagram of the connection between an occultation detector and an external device provided in an embodiment of the present application, Figure 2 It can be seen that the occultation detector includes an interface conversion circuit and at least one SOC chip; wherein the interface conversion circuit includes: a serial bus interface, a power module and a signal conversion module.

[0096] The connection relationship between the serial bus interface, power module, signal conversion module, SOC chip and external electronic equipment is as follows:

[0097] The serial bus interface is connected to the power module and the signal conversion module respectively. The signal conversion module is also connected to the power module and the SOC chip. The serial bus interface is used to connect to external electronic devices.

[0098] The power module and the signal conversion module are configured with the following functions:

[0099] A power module configured to output a startup voltage to the signal conversion module in response to an external electronic device being connected to the serial bus interface;

[0100] The signal conversion module is configured to receive the program to be burned transmitted by the external electronic device via the serial bus interface in response to the start-up voltage, and transmit the program to be burned to the JTAG interface of the SOC chip to burn the program to be burned into the SOC chip;

[0101] And, the debugging result information output by the debugging serial port of the SOC chip is transmitted to the external electronic device through the serial bus interface; wherein the debugging result information is the result information of the SOC chip debugging the burned program.

[0102] In this embodiment, each SOC chip in the occultation detector requires a program burning interface and a debugging information output interface. First, the JTAG program downloader is connected through an external electronic device to perform program burning and debugging on each SOC chip. Then, the USB-to-serial port converter is connected through the external electronic device to receive the debugging result information output by the debugging serial port of the SOC chip that has been program burned and debugged in the occultation detector. This makes it convenient for the debugging personnel to directly operate the external electronic device, thereby realizing program burning and debugging of each SOC chip in the occultation detector.

[0103] The interface conversion circuit is a circuit used to replace the corresponding functions of the JTAG program downloader and the USB to serial converter.

[0104] The JTAG program downloader is used to convert the program to be burned output by external electronic equipment into JTAG information that can be recognized by the SOC chip, and then the SOC chip burns and debugs the recognizable program.

[0105] The USB to serial converter is used to convert the debugging result information output by the debugging serial port of the SOC chip into USB information that can be recognized by external electronic devices, so that the debugger can view the debugging result information of the SOC chip through the external electronic device and take the next step.

[0106] The serial bus interface is an interface for connecting the occultation detector to an external electronic device. The serial bus interface is used to transmit the program to be burned output by the external electronic device to the occultation detector, and to transmit the debugging result information output by the occultation detector to the external electronic device. The type of the serial bus interface is an interface adapted to the data interface of the external electronic device. In this embodiment, the external electronic device can be a computer or other electronic device that can be operated by a debugger.

[0107] The power module is a circuit used to provide a starting voltage to the signal conversion module, and can use the power provided by the external electronic device to perform power conversion. The power module is configured to respond to the external electronic device being connected to the serial bus interface, which indicates that the SOC chip in the occultation detector needs to be burned and debugged at this time, so the power module needs to start the signal conversion module to maintain normal communication between the external electronic device and the SOC chip in the occultation detector. In this embodiment, the power of the power module can come from the voltage output by the external electronic device, or it can be other external devices that can provide power to the power module. The power of the power module can be obtained without the power supply in the occultation detector, so the extra power consumption of the occultation detector can be avoided.

[0108] The signal conversion module is a circuit or electronic device used to convert the program to be burned output by the external electronic device and the debugging result information output by the SOC chip, so as to facilitate the external electronic device to identify the debugging result information output by the SOC chip, and the JTAG interface of the SOC chip to identify the program to be burned, and then burn the program to be burned into the SOC chip.

[0109] For example, taking the serial bus interface as a USB interface as an example, the program burning and debugging of the SOC chip in the occultation detector through an external electronic device, that is, a computer is described:

[0110] First, the computer is connected to the serial bus interface in the interface conversion circuit via a USB cable. The computer outputs electric energy to the power module in the interface conversion circuit via the USB cable, so that the power module converts electric energy in response to the electric energy and outputs a starting voltage to the signal conversion module.

[0111] Then the signal conversion module is started, and it can receive the program to be burned output by the computer through the serial bus interface. Since the serial bus interface is a USB interface, and the differential transmission mechanism helps to improve the reliability and anti-interference performance of signal transmission, the program to be burned can be transmitted to the signal conversion module through the differential signal mode. At this time, the signal conversion module has been started, so the program to be burned can be converted into a JTAG signal that can be recognized by the JTAG interface of the SOC chip for transmission, so that the SOC chip can burn the program.

[0112] After the SOC chip program is burned, the signal conversion module can also receive the debugging result information output by the debugging serial port of the SOC chip. The signal conversion module can convert the debugging result information into information that can be recognized by the computer, and transmit the information to the computer via the USB cable in the differential signal mode, so that the computer can display the debugging result information for easy viewing by the debugger.

[0113] Through the interface conversion circuit provided in this embodiment, during the process of burning programs and debugging the SOC chip in the occultation detector, the signal conversion module is powered by the power module, without increasing the extra power consumption of the occultation detector as a whole. At the same time, it also ensures that the interface conversion circuit will not affect the reliability of the on-orbit operation of the occultation detector, and directly establishes a communication connection between the occultation detector and the external electronic device through the signal conversion module and the serial bus interface. The data transmission of the program to be burned and the debugging result information between the external electronic device and multiple SOC chips can be achieved without re-plugging, thereby improving the convenience of external electronic devices in burning programs and debugging the SOC chip in the occultation detector.

[0114] Reference Figure 3 , Figure 3 is a detailed schematic diagram of a module of an interface conversion circuit provided in an embodiment of the present application, from Figure 3 It can be seen that the interface conversion circuit also includes an isolation chip; wherein the isolation chip is connected in series between the signal conversion module and the SOC chip, and is connected to the power module, and the isolation chip is configured to isolate the communication between the signal conversion module and the SOC chip in response to the external electronic device unplugging the serial bus interface.

[0115] In this embodiment, the interface conversion circuit in the occultation detector conducts the communication connection between the external electronic device and the SOC chip only when the SOC chip in the occultation detector is tested on the ground, so that the external electronic device can burn and debug the program to be tested on the SOC chip. However, when the occultation detector is working normally on orbit, in order to avoid other data information irrelevant to the on-orbit operation of the occultation detector being transmitted to the SOC chip through the interface conversion circuit during the on-orbit operation of the occultation detector, thereby affecting the on-orbit operation of the occultation detector, the interface conversion circuit needs to stop conducting the communication connection between the external electronic device and the SOC chip.

[0116] Therefore, the interface conversion circuit also includes an isolation chip, which is connected in series between the conversion module and the SOC chip and is connected to the power module. Since the isolation chip is configured to isolate the communication between the signal conversion module and the SOC chip in response to the external electronic device being unplugged from the serial bus interface, when the external electronic device is unplugged from the serial bus interface, the power module will stop outputting the starting voltage. At this time, the signal conversion module has no starting voltage and will stop converting the output signal. However, there is a power supply inside the occultation detector, and a voltage that replaces the starting voltage to start the signal conversion module can also be output to the signal conversion module through the SOC chip.

[0117] Therefore, by connecting the power module to the isolation chip, it can be known that when the external electronic device is unplugged from the serial bus interface, the power module will not output the starting voltage, and the isolation chip can respond to the disappearance of the starting voltage in time, isolate the communication between the signal conversion module and the SOC chip, and maintain the reliability of the on-orbit operation of the occultation detector.

[0118] In a specific embodiment, in order to meet the wide application of the detection data of the occultation detector in the meteorological field, the occultation detector is required to receive all frequency points of all GNSS systems. Therefore, in order to improve the effective observation amount detected by the occultation detector, multiple SOC chips are set in the occultation detector as the core processor to receive all frequency points of all GNSS systems.

[0119] In addition, in order to improve the reliability of the occultation detector on orbit, the multiple SOC chips in the occultation detector will be set up in a master-backup mode. Specifically, when the master SOC chip is abnormal, the backup SOC chip will be switched to replace the master SOC chip to improve the reliability of the occultation detector on orbit.

[0120] The following are the implementation methods 1 and 2 for improving the reliability and effective observation volume of the occultation detector on orbit:

[0121] Implementation 1:

[0122] Reference Figure 4 , Figure 4 It is for Figure 3 A schematic diagram of the connection between an interface conversion circuit and a SOC chip is provided. Figure 4 It can be seen that the isolation chip includes a first isolation chip and a second isolation chip; wherein, the first end of the first isolation chip and the first end of the second isolation chip are connected in parallel to one end of the signal conversion module, and the second end of the first isolation chip and the second end of the second isolation chip are respectively connected to different SOC chips.

[0123] In this embodiment, in order to ensure the improvement of the reliability and effective observation amount of the occultation detector on orbit, a plurality of SOC chips are arranged in the occultation detector. The plurality of SOC chips may be different SOC chips. The different SOC chips may be a main SOC chip and a backup SOC chip, or may be SOC chips that need to download different programs to be burned, in order to smoothly isolate the communication connection between the main SOC chip and the backup SOC chip and the external electronic device, or to prevent the external electronic device from transmitting different programs to be burned to non-corresponding SOC chips.

[0124] Therefore, the isolation chips include a first isolation chip and a second isolation chip, which are respectively connected to different SOC chips to achieve isolation of different SOC chips. Specifically, the first end of the first isolation chip and the first end of the second isolation chip are connected in parallel at one end of the signal conversion module, and the second end of the first isolation chip and the second end of the second isolation chip are respectively connected to different SOC chips. By controlling the conduction between the first isolation chip and the second isolation chip, a signal conversion module can be used to conduct the communication connection between different SOC chips and external electronic devices.

[0125] Implementation 2

[0126] Reference Figure 5 , Figure 5 It is for Figure 3 A schematic diagram of the connection between an interface conversion circuit and a SOC chipset is provided. Figure 5 It can be seen that the SOC chip includes a first SOC chipset and a second SOC chipset; wherein the second SOC chipset is a backup SOC chip of the first SOC chipset; wherein the first SOC chipset is connected to the first isolation chip, and the second SOC chipset is connected to the second isolation chip.

[0127] In this embodiment, in order to ensure the improvement of the reliability and effective observation amount of the occultation detector on orbit, a plurality of SOC chips are arranged in the occultation detector. Although there are main SOC chips and backup SOC chips among the plurality of SOC chips, in order to meet the requirement that the occultation detector receives all frequency points of all GNSS systems, a plurality of main SOC chips and a plurality of backup SOC chips are required. Therefore, the SOC chip includes a first SOC chipset and a second SOC chipset. Therefore, the first SOC chipset includes a plurality of main SOC chips, and the second SOC chipset includes a plurality of backup SOC chips.

[0128] Since the second SOC chipset is the backup SOC chip of the first SOC chipset, the first SOC chipset and the second SOC chipset play the same role in occultation detection. The external electronic device transmits the program to be burned for program burning and debugging, and isolates the communication between the signal conversion module when the occultation detector is in orbit. Therefore, the first SOC chipset is connected to the first isolation chip, and the second SOC chipset is connected to the second isolation chip.

[0129] In a specific embodiment, referring to Figure 6 , Figure 6 This is a connection diagram of a power module control isolation chip provided in an embodiment of the present application. Figure 6 It can be seen that the occultation detector also includes: a third isolation chip and a fourth isolation chip, the first end of the third isolation chip and the first end of the fourth isolation chip are connected in parallel to one end of the isolation chip, the second end of the third isolation chip and the second end of the fourth isolation chip are respectively connected to different SOC chips, the third isolation chip is configured to present a low-impedance state in response to a power-on signal output by the SOC chip connected to the third isolation chip; the fourth isolation chip is configured to present a low-impedance state in response to a power-on signal output by the SOC chip connected to the fourth isolation chip.

[0130] In this embodiment, the occultation detector also includes a third isolation chip and a fourth isolation chip. The third isolation chip and the fourth isolation chip are isolation chips located outside the interface conversion circuit. The function of the third isolation chip and the fourth isolation chip is to isolate the SOC chip connected to the third isolation chip and the SOC chip connected to the fourth isolation chip for simultaneous program burning and debugging. It is assumed that the SOC chip connected to the third isolation chip is the third SOC chip, and the SOC chip connected to the fourth isolation chip is the fourth SOC chip. Because the SOC chip will only be program burned and debugged after the power-on of the SOC chip is detected, the third isolation chip is configured to present a low-impedance state in response to the arrival of the power-on signal of the SOC chip connected to the third isolation chip. At this time, the third isolation chip will turn on the communication connection between the SOC chip connected to the third isolation chip and the interface conversion circuit, and can communicate with external electronic devices through the interface conversion circuit to complete program burning and debugging.

[0131] At this time, since the SOC chip connected to the fourth isolation module is not powered on, it is impossible to output a power-on signal to the fourth isolation module, so the fourth isolation module presents a high configuration, and the SOC chip connected to the third isolation module is isolated, and program burning and debugging interference are not performed on it. In this embodiment, the power-on signal can be a digital signal or a voltage signal similar to a start-up voltage, as long as it acts on the third isolation module or the fourth isolation module to make the third isolation module or the fourth isolation module present a low-impedance state.

[0132] In a specific embodiment, referring to Figure 7 , Figure 7 This is a connection diagram of another power module control isolation chip provided in an embodiment of the present application. Figure 7 It can be seen that a first AND gate circuit is arranged between the first isolation chip and the power module; wherein the first AND gate circuit is also connected to the first SOC chip connected to the first isolation chip, for receiving the first power-on signal output by the first SOC chip; a second AND gate circuit is arranged between the second isolation chip and the power module, wherein the second AND gate circuit is also connected to the second SOC chip connected to the second isolation chip, for receiving the second power-on signal output by the second SOC chip; wherein the first AND gate circuit is configured to control the first isolation chip to be in a low-resistance state in response to the arrival of the startup voltage and the first power-on signal; and the second AND gate circuit is configured to control the second isolation chip to be in a low-resistance state in response to the arrival of the startup voltage and the second power-on signal.

[0133] In the present embodiment, in order to allow different SOC chips in the occultation detector to be programmed and debugged separately, for example, when programming and debugging the first SOC chip, it is necessary to isolate the communication between the second SOC chip and the interface conversion circuit to avoid the data transmitted when programming and debugging the first SOC chip is transmitted to the second SOC chip, resulting in failure of programming the first SOC chip or erroneous modification of the internal program in the second SOC chip. However, as long as the power module is connected to the serial bus interface of an external electronic device, it will output a startup voltage, and the startup voltage will be transmitted to the first isolation chip and the second isolation chip, thereby making the first isolation chip and the second isolation chip present a low-resistance state at the same time. At this time, the first isolation chip and the second isolation chip will lose the function of isolating the first SOC chip from the second SOC chip.

[0134] In addition, when the first SOC chip is programmed and debugged, the internal power supply in the occultation detector will only power on the first SOC chip, and will not power on other SOC chips except the first SOC chip. Therefore, by providing a first AND gate circuit between the first isolation chip and the power module, and providing a second AND gate circuit between the second isolation chip and the power module, and the first AND gate circuit is also connected to the first SOC chip connected to the first isolation chip, for receiving the first power-on signal output by the first SOC chip, and the second AND gate circuit is also connected to the second SOC chip connected to the second isolation chip, for receiving the second power-on signal output by the second SOC chip, it can be realized that the first AND gate circuit and the second AND gate circuit will only output a signal to control the corresponding first isolation chip or the second isolation chip to present a low configuration when the start signal and the power-on signal are received at the same time. The first power-on signal and the second power-on signal in this embodiment can be data signals or voltage signals. As long as they are ANDed with the start voltage, the AND gate circuit is controlled to output a high level to the corresponding isolation chip to control it to present a low resistance state. In addition, the first and the second in the first power-on signal and the second power-on signal in this embodiment are only used to distinguish that the first power-on signal and the second power-on signal are output by different SOC chips.

[0135] Therefore, when it is necessary to burn and debug the program of the first SOC chip, the first power-on signal is output to the first AND gate circuit through the first SOC chip. In conjunction with the starting voltage received by the first AND gate circuit, the first AND gate circuit can be controlled to output a high-level signal to the first isolation module, and the first isolation chip is controlled to present a low configuration. At this time, since the second SOC chip is not powered on, the second SOC chip cannot output the second power-on signal to the second AND gate circuit. The second AND gate circuit only receives the starting voltage and cannot output a high-level signal to the second isolation module. At this time, the second isolation module presents a high configuration, isolating the communication between the second SOC chip and the interface conversion circuit. The program that needs to be burned to the first SOC chip cannot be transmitted to the second SOC chip.

[0136] In a specific embodiment, the first isolation chip and the second isolation chip do not present a low resistance state at the same time.

[0137] In this embodiment, if the first isolation chip and the second isolation chip are respectively connected to different SOC chips or different SOC chips groups, in order to avoid interference from other SOC chips when programming and debugging a SOC chip or a SOC chips group, the first isolation chip and the second isolation chip do not present a low resistance state at the same time, that is, they are not turned on at the same time.

[0138] The following will further explain the connection method of multiple SOC chips in one SOC chipset in implementation method 2:

[0139] Reference Figure 8 , Figure 8 It is for Figure 5 A schematic diagram of the connection between an interface conversion circuit and multiple SOC chips in a SOC chipset is provided. Figure 8 It can be seen that the first SOC chipset includes multiple first SOC chips; wherein each first SOC chip is respectively provided with a first interface and a second interface; the first interfaces and the second interfaces corresponding to the multiple first SOC chips are connected in series with each other, and among the multiple first SOC chips, there is a first interface corresponding to a first SOC chip connected in series with the first isolation chip, and there is another first SOC chip corresponding to the second interface connected in series with the isolation chip; wherein, the interfaces other than the first interface and the second interface on each first SOC chip are connected in parallel on the first isolation chip.

[0140] In this embodiment, the first SOC chipset includes a plurality of first SOC chips, that is, the main SOC chipset includes a plurality of main SOC chips. Since each first SOC chip is provided with a first interface and a second interface, the first interface is used to receive the program to be burned that can be recognized by the first SOC chip output by the signal conversion module, and the second interface is used to output the first SOC chip to the signal conversion module for program burning and then feedback the burning result data. The first interface can be a data input interface for receiving the data signal in the JTAG information, and the second interface can be a data output interface for outputting the data signal in the JTAG information.

[0141] In order to reduce the number of interfaces on the first isolation chip and simplify the path for transmitting the program to be burned, the first interfaces and the second interfaces corresponding to the multiple first SOC chips can be connected in series, that is, the multiple first SOC chips are connected end to end, for example, the first interface of the first SOC chip is connected to the first isolation chip, the second interface of the first SOC chip is connected to the first interface of the second SOC chip, the second interface of the second first SOC chip is connected to the first interface of the third SOC chip..., until the second interface of the last first SOC chip is connected to the first isolation chip.

[0142] Therefore, it is only necessary that among the multiple first SOC chips, there is only a first interface corresponding to a first SOC chip connected in series with the first isolation chip, and another first SOC chip corresponding to a second interface connected in series with the first isolation chip, so that the first first SOC chip connected in series and the last first SOC chip connected in series among the multiple first SOC chips can be connected to the isolation chip, which does not affect the data transmission between the signal conversion module and the multiple first SOC chips and can also save the number of interfaces on the first isolation chip.

[0143] In addition, in order to adapt the JTAG interface corresponding to the first SOC chip to burn the program and debug the first SOC chip, the first SOC chip has other interfaces in addition to the first interface and the second interface. The information of the other interfaces is unique to each first SOC chip, such as test mode, test time, etc. Therefore, the other interfaces can be connected in parallel to the first isolation chip. The other interfaces can specifically be a clock interface for receiving the clock signal in the JTAG information and a mode interface for the test mode signal, as well as a debugging serial port for outputting debugging information. Figure 8 Not shown.

[0144] In addition, the connection of multiple SOC chips in the second SOC chipset can refer to Figure 8 The method shown will not be repeated here.

[0145] Since the occultation detector has at least one SOC chip as a core processor, there is one SOC chip or multiple SOC chips in the occultation detector, and the SOC chip in the occultation detector has multiple interfaces to receive the program to be burned transmitted by the external electronic device, so there is a connection method of one SOC chip and the interface conversion circuit as implementation method 3, and a connection method of multiple SOC chips and the interface conversion circuit as implementation method 4. The following will be described with implementation methods 3 and 4:

[0146] Implementation 3:

[0147] Reference Fig. 9 , Fig. 9is a schematic diagram of a connection between an interface conversion circuit and a SOC chip provided in an embodiment of the present application, from Fig. 9 It can be seen that the occultation detector includes a SOC chip, which includes: a clock interface, a mode interface, a data input interface, a data output interface and a debugging serial port; the signal conversion module includes: a JTAG signal output interface, a JTAG signal input interface and a debugging input serial port; among them, the clock interface, the mode interface, the data input interface are connected to the JTAG signal output interface, the data output interface is connected to the JTAG signal input interface, and the debugging serial port is connected to the debugging input serial port.

[0148] In this embodiment, a SOC chip includes: a clock interface, a mode interface, a data input interface, a data output interface and a debugging serial port, and the clock interface, the mode interface, the data input interface are connected to the JTAG signal output interface, the data output interface is connected to the JTAG signal input interface, and the debugging serial port is connected to the debugging input serial port.

[0149] Therefore, the clock interface is used to receive the test clock information output from the JTAG signal output interface, and the test clock information is used to synchronize the transmission of data on the JTAG signal; the mode interface is used to receive the test mode selection information output from the JTAG signal output interface, and the test mode selection information is used to control the state of the JTAG signal, thereby selecting different test or operation modes; the data input interface is used to receive the test data information output from the JTAG signal output interface, and the test data information is the program to be burned; the data output interface is used to output the status information or output data of the SOC chip in response to the test data information to the JTAG signal input interface; the debug serial port is used to output the result information of debugging or testing after the SOC chip burns the program to the debug input serial port.

[0150] Implementation 4

[0151] Reference Fig.10 , Fig.10 This is a schematic diagram of the connection between an interface conversion circuit and multiple SOC chips provided by an embodiment of the present application. Fig.10 It can be seen that the occultation detector includes multiple SOC chips; wherein, the debugging serial ports corresponding to the multiple SOC chips are connected to the debugging input serial port of the signal conversion module; the clock interfaces and mode interfaces corresponding to the multiple SOC chips are respectively connected to the JTAG signal output interface of the signal conversion module; there is at least one data output interface of the first SOC chip among the multiple SOC chips, which is connected in series with the data input interface of at least one second SOC chip, and the data input interface of the first SOC chip is connected to the JTAG signal output interface, and the data output interface of the second SOC chip is connected to the JTAG signal input interface; wherein, the number of the first SOC chip and the second SOC chip is equal.

[0152] In this embodiment, each of the multiple SOC chips has a clock interface, a mode interface, a data input interface, a data output interface and a debug serial port, and the clock interface and mode interface of each SOC chip are connected to the JTAG signal output interface on the interface conversion circuit, and the debug serial port is connected to the debug input serial port.

[0153] Since there are multiple SOC chips, in order to reduce the complexity of connecting the multiple SOC chips with the interface conversion circuit, the data input interfaces and data output interfaces corresponding to the multiple SOC chips can be connected in series head to tail in sequence, and the data input interface of the SOC chip corresponding to the head can be connected to the JTAG signal output interface in the interface conversion circuit, and the data output interface of the SOC chip corresponding to the tail can be connected to the JTAG signal input interface in the interface conversion circuit.

[0154] For example, there are two SOC chips among multiple SOC chips, namely the first SOC chip and the second SOC chip. The data input interface of the first SOC chip is connected to the JTAG signal output interface, the data output interface of the second SOC chip is connected to the JTAG signal input interface, and the data output interface of the first SOC chip is connected in series with the data input interface of the second SOC chip.

[0155] In addition, if there are three SOC chips among the plurality of SOC chips, they are a first SOC chip, a second SOC chip and a third SOC chip.

[0156] The data input interface of the first SOC chip is connected to the JTAG signal output interface, the data output interface of the second SOC chip is connected to the JTAG signal input interface, the data output interface of the first SOC chip is connected in series with the data input interface of the third SOC chip, and the data output interface of the third SOC chip is connected in series with the data input interface of the second SOC chip.

[0157] In a specific embodiment, referring to Fig.11 , Fig.11 This is a detailed schematic diagram of a module of another interface conversion circuit provided in an embodiment of the present application, from Fig.11 It can be seen that the interface conversion circuit also includes a memory; wherein the memory is connected in series between the power module and the signal conversion module; the memory is configured to output a configuration code to the signal conversion module in response to a start-up voltage; the configuration code is used to define the function of the signal conversion module.

[0158] In this embodiment, the signal conversion module in the interface conversion circuit plays a role of signal conversion. For example, device A and device B transmit signals through the interface conversion circuit to realize two-line communication. The signal conversion module in the interface conversion circuit converts the signal sent by device A into a signal adapted for device B and sends it to device B, and converts the signal sent by device B into a signal adapted for device A and sends it to device A.

[0159] Then, during the signal transmission process, there may be more than one type of signal that needs to be transmitted, and the signal conversion function of the signal conversion module will also be required to be increased. In order to facilitate the signal conversion module to adapt to various types of signal conversion, the configuration code of the signal conversion module is stored in the memory. The conversion function of the signal conversion module can be defined in the configuration code, so the memory is connected in series between the power module and the signal conversion module. When the signal conversion module is started, the memory is also started accordingly, so the memory can also be configured to respond to the start-up voltage and output the configuration code to the signal conversion module. In this embodiment, the memory can be a powered erasable programmable read-only memory.

[0160] In a specific embodiment, continue to refer to Fig.11 ,from Fig.11 It can be seen that the interface conversion circuit also includes a crystal oscillator; wherein the crystal oscillator is connected in series between the power module and the signal conversion module; the crystal oscillator is configured to output a clock signal to the signal conversion module in response to a start-up voltage.

[0161] In this embodiment, the interface conversion circuit also includes a crystal oscillator, which is connected in series between the power module and the signal module. When the signal conversion module is started, in order to make the signal conversion module synchronously transmit the program to be burned, and in order for the crystal oscillator to synchronously respond to the start of the signal conversion module, the crystal oscillator can be configured to respond to the start voltage and output a clock signal to the signal conversion module. In addition, the start voltage can also provide power for the crystal oscillator. In this embodiment, the crystal oscillator can be a crystal oscillator that emits a 12MHZ clock.

[0162] In a specific embodiment, the serial bus interface is a universal serial bus interface.

[0163] In this embodiment, the output interfaces of different external electronic devices may require different types of serial bus interface adaptation. Currently, most electronic devices on the market use a universal serial bus for output transmission, so this serial bus interface may be a universal serial bus interface.

[0164] For example, the following will be Figure 12-14 To explain the program burning and debugging of the occultation detector by external electronic equipment:

[0165] Reference Fig.12 , Fig.12 is a schematic diagram of the connection between an occultation detector and an external electronic device provided in an embodiment of the present application, Fig.12 It can be seen that the external electronic device is a computer, the occultation detector has an interface conversion circuit, and four SOC chips, namely the main chip set composed of the main SOC_1 and the main SOC_2, the main chip set is the first SOC chipset mentioned above, and the backup chipset composed of the backup SOC_1 and the backup SOC_2 is the second SOC chipset mentioned above. In addition, Fig.12 There is also Fig.14 The third isolation chip and the fourth isolation chip in.

[0166] The computer and the input end of the interface conversion circuit in the occultation detector are connected in bidirectional communication through a USB line, the main SOC_1 and the main SOC_2 are connected in series, the backup SOC_1 and the backup SOC_2, and the debugging serial ports of the main SOC_1 and the backup SOC_1 are connected to the debugging input serial port 1 on the interface conversion circuit, and the debugging serial ports of the main SOC_2 and the backup SOC_2 are connected to the debugging input serial port 2 on the conversion circuit.

[0167] Refer to the following Fig.13 , Fig.13 It is for Fig.12 A schematic diagram of an interface conversion circuit is provided, from Fig.13 It can be seen that the interface conversion circuit includes: an isolation chip, a signal conversion module, a memory, a crystal oscillator and a power module. The isolation chip is a chip of model 162245, the signal conversion module is a chip of model FT4232, the memory is an electrically erasable programmable memory (EEPROM), and the power module is an LDO power supply. The LDO power supply can convert the 5V voltage output by the computer into a 3.3V voltage.

[0168] The LDO power supply and the signal conversion module are respectively connected to the computer. The LDO power supply is also respectively connected to the isolation chip, the signal conversion module, the memory, and the crystal oscillator. The signal conversion module is also connected to the isolation chip.

[0169] Refer to the following Fig.14 , Fig.14 It is for Fig.12 A schematic diagram of the connection between an interface conversion circuit and a SOC chip is provided. Fig.14 TCK_1 and TCK_2 of the master chipset and the backup chipset are clock interfaces, TCS_1 and TCS_2 are mode interfaces, TDI_1 and TDI_2 are data input interfaces, which are also the first interfaces, TDO_1 and TDO_2 are data output interfaces, which are also the second interfaces, and serial ports 1 and 2 are debugging serial ports. Fig.14The TCK, TMS, and TDI in the interface conversion circuit are the JTAG signal output interfaces of the signal conversion module, TDO is the JTAG signal input interface of the signal conversion module, and serial port 1 and serial port 2 are the debug input serial ports of the signal conversion module.

[0170] TCK, TMS and TDI are respectively corresponding to the output of test clock signal, test mode signal and test data signal, i.e. the program to be burned. TDO is the data output interface of the SOC chip to the interface conversion module for the status information of the response test data information or the output data. Serial port 1 is the debugging serial port for the main SOC_1 or backup SOC_1 to output the debugging result information to the signal conversion module, and serial port 2 is the debugging serial port for the main SOC_2 or backup SOC_2 to output the debugging result information to the signal conversion module.

[0171] from Fig.14 As can be seen, TDO_1 of the main SOC_1 is connected in series with TDI_2 of the main SOC_2.

[0172] The backup chipset uses the same connection method as the main chipset. The interface corresponding to the TDO of the main SOC_2 is routed through the third isolation chip SN7416224, and the interface corresponding to the TDO of the backup SOC_2 is routed through the fourth isolation chip SN74162245 to form one circuit.

[0173] The following will be combined Figure 12-14 The following describes the order of burning and debugging the main SOC chip in the occultation detector using a computer, and then burning and debugging the standby SOC chip:

[0174] First, the computer's USB cable is connected to the serial bus interface of the interface conversion circuit, and the USB signal is output through the serial bus interface of the USB cable interface conversion circuit. The USB signal carries the program to be burned in the SOC chip and the 5V voltage, wherein the 5V voltage is output to the power module, and the program to be burned is output to the signal conversion module.

[0175] At this time, the power module converts the 5V voltage into a 3.3V startup voltage, and outputs it to the first isolation chip, the signal conversion module, the memory and the crystal oscillator respectively.

[0176] The isolation chip is controlled by the startup voltage and presents a low-resistance state, which turns on the communication connection between the signal conversion module and the third isolation chip or the fourth isolation chip. At the same time, the memory outputs a configuration code to the signal conversion module in response to the startup voltage to define the conversion function of the signal conversion module. The crystal oscillator outputs a 12MHZ clock signal to the signal conversion module in response to the startup voltage. Finally, the signal conversion module converts the program to be burned into a JTAG signal that can be recognized by the SOC chip and transmits it to the isolation chip. Since the main SOC chipset is used for burning programs and debugging at this time, the main SOC chip is in a powered-on state, and the third isolation chip connected to the main SOC chip presents a low-resistance state. Therefore, the isolation chip transmits the JTAG signal that can be recognized by the SOC chip to the JTAG ports corresponding to the main SOC_1 and the main SOC_2 connected to the third isolation chip. In the process, the main SOC_1 and the main SOC_2 burn and debug the program to be burned, and then output the debugging result information to the interface conversion circuit through the corresponding debugging serial ports of the main SOC_1 and the main SOC_2. The interface conversion circuit then converts the debugging result information into USB information recognizable by the computer and transmits it to the computer for the debugging personnel to check. If there is no problem, the backup SOC chip is switched on and the main SOC chip is powered off. At this time, the fourth isolation chip responds to the power-on information of the backup SOC chip and presents a low-impedance state, and the third isolation chip presents a high-impedance state. At this time, the isolation chip transmits the JTAG signal recognizable by the SOC chip to the backup SOC_1 and the backup SOC_2 connected to the fourth isolation chip for program burning and testing. The specific process refers to the description of the main SOC_1 and the main SOC_2, which will not be repeated here.

[0177] contrast Figure 1 and Figure 12-Figure 15 , get Table 1, which is a comparison table of optimization projects. From Table 1, we can see that Figure 12-14 The interface conversion circuit provided can convert Figure 1 The number of nodes in the connector is reduced from 36 to 4, and no JTAG programmer or USB-to-serial converter is required. Fig.15 , Fig.15 It is for Fig.12 A simplified schematic diagram of the connection between an occultation detector and external electronic equipment is provided. Fig.15 It can be seen that the data volume of the USB adapter cable is reduced from at least 2 to 1. In addition, when switching to debug SOC, there is no need to switch the download line and the debug line. This reduces the interface resources of the occultation detector, improves the convenience of program burning, and is more conducive to the miniaturization design of the occultation detector.

[0178] Table 1

[0179]

[0180]

[0181] Embodiment 2

[0182] Reference Fig.16 , Fig.16 is a flowchart of the steps of a debugging method provided in an embodiment of the present application, which is applied to the occultation detector described in the first embodiment of the present application, from Fig.16 It can be seen that the method steps include:

[0183] Step S161: obtaining power information of at least one SOC chip in the occultation detector; wherein the power information is used to indicate whether the SOC chip is powered on.

[0184] In this embodiment, when the SOC chip in the occultation detector is programmed and debugged, the SOC chip needs to be in a powered-on state. Therefore, before programming and debugging the SOC chip, it is necessary to first obtain the power supply information of at least one SOC chip in the occultation detector. If one SOC chip is powered on, it indicates that one SOC chip needs to be programmed and debugged. If multiple SOC chips are powered on, it indicates that multiple SOC chips need to be programmed and debugged.

[0185] Step S162: Based on the power information, receiving the program to be burned transmitted by the external electronic device via the serial bus interface through the serial bus interface of the interface conversion circuit.

[0186] In this embodiment, after determining the SOC chip to be downloaded, the external electronic device transmits the program to be burned to the interface conversion circuit through the serial bus interface, so that the SOC chip can be burned and debugged.

[0187] Step S163: and, transmitting the program to be burned to the JTAG interface of the SOC chip through the signal conversion module of the interface conversion circuit.

[0188] In this embodiment, after the interface conversion circuit obtains the program to be burned transmitted by the external electronic device, it converts the program to be burned into a JTAG signal recognizable by the SOC chip, and burns the program to be burned in the JTAG signal into the SOC chip.

[0189] Step S164: and receiving debugging result information output by the debugging serial port of the SOC chip based on the serial bus interface; wherein the debugging result information is the result information of the SOC chip debugging the burned program.

[0190] In this embodiment, after the SOC chip burning program is completed, debugging will be performed based on the program, and then the SOC chip will output the debugging result information to the signal conversion module in the interface conversion circuit. The signal conversion module will convert the debugging result information into information recognizable by external electronic devices, and output the information to the external electronic device through the serial bus interface for display.

[0191] In one embodiment, at least one SOC chip includes a plurality of SOC chips connected in series in sequence; obtaining power supply information of at least one SOC chip in the occultation detector includes:

[0192] In this embodiment, if there are multiple SOC chips that need to be program burned and debugged, and the multiple SOC chips are connected in series in sequence, since each SOC chip may correspond to a different burning program, it is necessary to guide the burning order of each SOC chip so that different programs to be burned can be burned into the corresponding SOC chip. First, the power information of multiple SOC chips is obtained; then based on the power information, the power-on time of each SOC chip can be known, and then the order of programs to be burned in multiple SOC chips is determined. When the signal conversion module of the interface conversion circuit is used to transmit the program to be burned to the JTAG interface of the SOC chip, the communication connection between the external electronic device and the multiple SOC chips can be turned on in sequence based on the burning order of the program to be burned, so as to transmit the program to be burned to the JTAG interface of the multiple SOC chips in sequence.

[0193] In one embodiment, an occultation detector includes a first SOC chipset and a second SOC chipset connected in parallel, and different isolation chips are respectively provided at the front ends of the first SOC chipset and the second SOC chipset, and the first SOC chipset and the second SOC chipset serve as backup for each other; obtaining power information of at least one SOC chip in the occultation detector includes: obtaining power information of the first SOC chipset and the second SOC chipset respectively; determining a target SOC chipset for a program to be burned based on the power information; maintaining a target isolation chip provided at the front end of the target SOC chipset in a low-impedance state based on the target SOC chipset through a power module of an interface conversion circuit; transmitting the program to be burned to a JTAG interface of the SOC chip through a signal conversion module of the interface conversion circuit, including: transmitting the program to be burned to the JTAG interface of the target SOC chipset through the signal conversion module based on the conduction of the isolation chip.

[0194] In the present embodiment, since the first SOC chipset and the second SOC chipset are backup for each other, the first SOC chipset and the second SOC chipset play the same role in the occultation detector. When the first SOC chipset and the second SOC chipset are programmed and debugged, it is generally necessary to program and debug separately, but it is uncertain which chipset is programmed first. Therefore, before programming and debugging, the power supply information of the first SOC chipset and the second SOC chipset is first obtained respectively. The target SOC chipset that needs to be programmed can be known through the power supply information. If the first SOC chipset is powered on, the first SOC chipset is the target chipset. If the second SOC chipset is powered on, the second SOC chipset is the target chipset. After the target chipset is determined, a start-up voltage is output to the corresponding target isolation chip at the front end of the target chipset through the signal conversion module, so that the target isolation chip is in a low-resistance state, and the communication connection between the signal conversion module and the target chipset is turned on, so that the external electronic device transmits the program to be programmed to the JTAG interface of the target SOC chipset through the signal conversion module.

[0195] In one embodiment, based on the conduction of the isolation chip, after transmitting the program to be burned to the JTAG interface of the target SOC chipset through the signal conversion module, the method also includes: obtaining debugging result information output by the debugging serial port of the target SOC chipset, and determining whether the target SOC chipset is burned successfully based on the debugging result information; if so, switching the target isolation chip to a high-impedance state through the power supply module, and other target isolation chips except the target isolation chip to a low-impedance state, and transmitting the program to be burned to the JTAG interface of the SOC chipset corresponding to the other target isolation chips through the signal conversion module.

[0196] In this embodiment, after the target SOC chipset program is completed, it is necessary to obtain the debugging result information output by the debugging serial port of the target SOC chipset, and determine whether the target SOC chipset program is completed through the debugging result information. If the debugging result information shows that the target SOC chipset program is completed and correct, there is no need to burn and debug the target SOC chipset. At this time, it is necessary to switch to other SOC chipsets for program burning and debugging. At this time, the power supply module stops outputting the starting voltage to the target isolation chip. At this time, the target isolation chip is in a high-impedance state, and other target isolation chips are in a low-impedance state. The communication loop between the SOC chipsets corresponding to the other target isolation chips and the signal conversion module is turned on, so that the signal conversion module transmits the program to be burned to the JTAG interface of the SOC chipsets corresponding to the other target isolation chips, and repeats the same action of the target SOC chipset.

[0197] An embodiment of the present application also provides a debugging system for an occultation detector, comprising an external electronic device and the occultation detector described in Embodiment 1 of the present application, wherein the external electronic device, in response to a serial bus interface connected to the interface conversion circuit, transmits a program to be burned to the interface conversion circuit; the interface conversion circuit, in response to the arrival of the program to be burned, transmits the program to be burned to the JTAG interface of the SOC chip in the occultation detector through a signal conversion module in the interface conversion circuit; the occultation detector, in response to the arrival of the program to be burned, burns the program to be burned into the SOC chip.

[0198] In this embodiment, by applying the debugging system of the interface conversion circuit to the process of program burning and debugging of the SOC chip in the occultation detector, the program to be burned can be transmitted to the interface conversion circuit through an external electronic device in response to the serial bus interface connected to the interface conversion circuit; then the interface conversion circuit, in response to the arrival of the program to be burned, transmits the program to be burned to the JTAG interface of the SOC chip in the occultation detector through the signal conversion module in the interface conversion circuit; finally, the occultation detector, in response to the arrival of the program to be burned, burns the program to be burned into the SOC chip

[0199] In one embodiment, the interface conversion circuit also responds to the debugging result information output by the debugging serial port of the SOC chip and transmits it to the external electronic device via the serial bus interface; wherein the debugging result information is the result information of the SOC chip debugging the burned program; the external electronic device also responds to the debugging result information to determine whether to debug the SOC chip.

[0200] In this embodiment, the interface conversion circuit in the debugging system through the interface conversion circuit can also respond to the debugging result information output by the debugging serial port of the SOC chip and transmit it to the external electronic device via the serial bus interface; wherein the debugging result information is the result information of the SOC chip debugging the burned program; the external electronic device also responds to the debugging result information to determine whether to debug the SOC chip. If the debugging result shows that the SOC chip program is burned successfully, the SOC chip does not need to be debugged. If the debugging result shows that the SOC chip program is not burned successfully or the burning is erroneous, the SOC chip needs to be debugged until the SOC chip program is burned successfully.

[0201] In one embodiment, the external electronic device also performs fault detection on the SOC chip corresponding to the number of debugging times exceeding the threshold value in response to the number of debugging times of each SOC chip.

[0202] In this embodiment, in order to improve the debugging efficiency and avoid multiple unsuccessful debugging due to defects of the SOC chip itself, during the debugging process of the SOC chip, if there are multiple debugging of the SOC chip, according to the debugging result information, the SOC chip still needs to be debugged. In order to avoid the failure of a SOC chip, which will delay the debugging process of other SOC chips, the number of debugging times of a SOC chip is limited. When the number of debugging times of the SOC chip exceeds the debugging times threshold, the SOC chip is tested. In this embodiment, the debugging times threshold is not limited, and can be set according to the actual application scenario.

[0203] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0204] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods and systems according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0205] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0206] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0207] The above is a detailed introduction to an occultation detector, debugging method and debugging system provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. An occultation detector, characterized in that: The occultation detector comprises an interface conversion circuit and at least one SOC chip; wherein, The interface conversion circuit includes a serial bus interface, and a power module and a signal conversion module connected to the serial bus interface; wherein the signal conversion module is also connected to the power module and the SOC chip, and the serial bus interface is used to connect to an external electronic device; The power supply module is configured to output a startup voltage to the signal conversion module in response to the external electronic device being connected to the serial bus interface; The signal conversion module is configured to receive the program to be burned transmitted by the external electronic device via the serial bus interface in response to the startup voltage, and transmit the program to be burned to the JTAG interface of the SOC chip, so as to burn the program to be burned into the SOC chip; And, transmitting the debugging result information output by the debugging serial port of the SOC chip to the external electronic device through the serial bus interface; Among them, the debugging result information is the result information of the SOC chip debugging the burned program, and the external electronic device determines whether to debug the SOC chip in response to the debugging result information. If the debugging result shows that the SOC chip program is burned successfully, the SOC chip does not need to be debugged. If the debugging result shows that the SOC chip program is not burned successfully or the burning is erroneous, the SOC chip needs to be debugged until the SOC chip program is burned successfully.

2. The occultation detector according to claim 1, characterized in that: The interface conversion circuit also includes an isolation chip; wherein, The isolation chip is connected in series between the signal conversion module and the SOC chip, and is connected to the power module; The isolation chip is configured to isolate the communication between the signal conversion module and the SOC chip in response to the external electronic device being unplugged from the serial bus interface.

3. The occultation detector according to claim 2, characterized in that: The isolation chip includes a first isolation chip and a second isolation chip; wherein, The first end of the first isolation chip and the first end of the second isolation chip are connected in parallel to one end of the signal conversion module, and the second end of the first isolation chip and the second end of the second isolation chip are connected to different SOC chips respectively.

4. The occultation detector according to claim 3, characterized in that: The SOC chip includes a first SOC chipset and a second SOC chipset; wherein the second SOC chipset is a backup SOC chip of the first SOC chipset; The first SOC chipset is connected to the first isolation chip, and the second SOC chipset is connected to the second isolation chip.

5. The occultation detector according to claim 4, characterized in that: The first SOC chipset includes a plurality of first SOC chips; wherein each first SOC chip is provided with a first interface and a second interface respectively; The first interfaces and the second interfaces corresponding to the plurality of the first SOC chips are connected in series with each other, and among the plurality of the first SOC chips, there is a first interface corresponding to the first SOC chip connected in series with the first isolation chip, and there is another second interface corresponding to the first SOC chip connected in series with the isolation chip; Among them, other interfaces except the first interface and the second interface on each first SOC chip are connected in parallel to the first isolation chip.

6. The occultation detector according to claim 1, characterized in that: The SOC chip includes: a clock interface, a mode interface, a data input interface, a data output interface and a debugging serial port; The signal conversion module includes: a JTAG signal output interface, a JTAG signal input interface and a debug input serial port; wherein, The clock interface, the mode interface, and the data input interface are connected to the JTAG signal output interface, the data output interface is connected to the JTAG signal input interface, and the debugging serial port is connected to the debugging input serial port.

7. The occultation detector according to claim 6, characterized in that: It includes multiple SOC chips; among them, The debugging serial ports corresponding to the plurality of SOC chips are connected to the debugging input serial port of the signal conversion module; The clock interfaces and mode interfaces corresponding to the plurality of SOC chips are respectively connected to the JTAG signal output interface of the signal conversion module; wherein, Among the multiple SOC chips, there is at least one data output interface of a first SOC chip, which is connected in series with the data input interface of at least one second SOC chip, and the data input interface of the first SOC chip is connected to the JTAG signal output interface, and the data output interface of the second SOC chip is connected to the JTAG signal input interface.

8. The occultation detector according to claim 1, characterized in that: The interface conversion circuit also includes a memory; wherein the memory is connected in series between the power module and the signal conversion module; The memory is configured to output a configuration code to the signal conversion module in response to the startup voltage; the configuration code is used to define a function of the signal conversion module.

9. The occultation detector according to claim 1, characterized in that: The interface conversion circuit also includes a crystal oscillator; wherein the crystal oscillator is connected in series between the power module and the signal conversion module; The crystal oscillator is configured to output a clock signal to the signal conversion module in response to the start-up voltage.

10. The occultation detector according to claim 2, characterized in that: The occultation detector further includes: a third isolation chip and a fourth isolation chip, wherein: The first end of the third isolation chip and the first end of the fourth isolation chip are connected in parallel to one end of the isolation chip, and the second end of the third isolation chip and the second end of the fourth isolation chip are connected to different SOC chips respectively; The third isolation chip is configured to present a low impedance state in response to a power-on signal output by a SOC chip connected to the third isolation chip; The fourth isolation chip is configured to present a low impedance state in response to a power-on signal output by a SOC chip connected to the fourth isolation chip.

11. The occultation detector according to claim 3, characterized in that: A first AND gate circuit is provided between the first isolation chip and the power module; wherein the first AND gate circuit is also connected to a first SOC chip connected to the first isolation chip, and is used to receive a first power-on signal output by the first SOC chip; A second AND gate circuit is provided between the second isolation chip and the power module, wherein the second AND gate circuit is also connected to a second SOC chip connected to the second isolation chip, and is used to receive a second power-on signal output by the second SOC chip; Wherein, the first AND gate circuit is configured to control the first isolation chip to be in a low-resistance state in response to the start-up voltage and the first power-on signal; The second AND gate circuit is configured to control the second isolation chip to be in a low-resistance state in response to the start-up voltage and the second power-on signal.

12. The occultation detector according to claim 11, characterized in that: The first isolation chip and the second isolation chip do not present a low resistance state at the same time.

13. The occultation detector according to claim 1, characterized in that: The serial bus interface is a universal serial bus interface.

14. A debugging method, characterized in that: The interface conversion circuit used in the occultation detector according to any one of claims 1 to 13, wherein the debugging method comprises: Acquiring power information of at least one SOC chip in the occultation detector; wherein the power information is used to indicate whether the SOC chip is powered on; Based on the power information, receiving the program to be burned transmitted by the external electronic device via the serial bus interface through the serial bus interface of the interface conversion circuit; And, transmitting the program to be burned to the JTAG interface of the SOC chip through the signal conversion module of the interface conversion circuit; And receiving the debugging result information output by the debugging serial port of the SOC chip based on the serial bus interface; wherein the debugging result information is the result information of the debugging of the burned program by the SOC chip.

15. The debugging method according to claim 14, characterized in that: The at least one SOC chip includes a plurality of SOC chips connected in series in sequence; The obtaining of power supply information of at least one SOC chip in the occultation detector includes: Acquiring power information of the plurality of SOC chips; Based on the power information, determining the order of programs to be burned into the plurality of SOC chips; The signal conversion module of the interface conversion circuit transmits the program to be burned to the JTAG interface of the SOC chip, including: Based on the burning order of the programs to be burned, the communication connection between the external electronic device and the plurality of SOC chips is sequentially conducted, so as to sequentially transmit the programs to be burned to the JTAG interfaces of the plurality of SOC chips.

16. The debugging method according to claim 14, characterized in that: The occultation detector includes a first SOC chipset and a second SOC chipset connected in parallel, and different isolation chips are respectively provided at the front ends of the first SOC chipset and the second SOC chipset, and the first SOC chipset and the second SOC chipset are standby for each other; The obtaining of power supply information of at least one SOC chip in the occultation detector includes: Respectively obtaining power information of the first SOC chipset and the second SOC chipset; Based on the power information, determining a target SOC chipset for the program to be burned; Based on the target SOC chipset, maintaining the target isolation chip provided at the front end of the target SOC chipset in a low impedance state through the power module of the interface conversion circuit; The signal conversion module of the interface conversion circuit transmits the program to be burned to the JTAG interface of the SOC chip, including: Based on the conduction of the isolation chip, the program to be burned is transmitted to the JTAG interface of the target SOC chipset through the signal conversion module.

17. The debugging method according to claim 16, characterized in that: After transmitting the program to be burned to the JTAG interface of the target SOC chipset through the signal conversion module based on the conduction of the isolation chip, the method further includes: Obtaining debugging result information output by the debugging serial port of the target SOC chipset; Based on the debugging result information, determining whether the target SOC chipset is burned successfully; If so, the target isolation chip is switched to a high-impedance state through the power module, and other target isolation chips except the target isolation chip are switched to a low-impedance state, and the program to be burned is transmitted to the JTAG interface of the SOC chipset corresponding to the other target isolation chips through the signal conversion module.

18. A debugging system, characterized in that: The invention comprises an external electronic device and the occultation detector according to any one of claims 1 to 13; wherein: The external electronic device transmits the program to be burned to the interface conversion circuit in the occultation detector in response to the serial bus interface connected to the interface conversion circuit; The interface conversion circuit, in response to the arrival of the program to be burned, transmits the program to be burned to the JTAG interface of the SOC chip in the occultation detector through the signal conversion module in the interface conversion circuit; The occultation detector, in response to the arrival of the program to be burned, burns the program to be burned into the SOC chip.

19. The debugging system according to claim 18, characterized in that: The interface conversion circuit is also responsive to the debugging result information output by the debugging serial port of the SOC chip, and transmits the debugging result information to the external electronic device via the serial bus interface; wherein the debugging result information is the result information of the SOC chip debugging the burned program; The external electronic device also determines whether to debug the SOC chip again in response to the debugging result information.

20. The debugging system according to claim 19, characterized in that: The external electronic device also performs fault detection on the SOC chip corresponding to the number of debugging times exceeding a threshold value in response to the number of debugging times of each SOC chip.

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