Queue scheduling device, method, electronic device and medium

Abstract

The present invention provides a queue scheduling device, method, electronic device, and medium, relating to the field of data storage technology. The device includes: a parsing and processing module and a scheduling module; the parsing and processing module is configured to receive and parse queue data packets from a bus to obtain arbitration information and multiple queue data; send the arbitration information and multiple queue data to the scheduling module; the scheduling module is configured to determine a target arbitration unit from multiple arbitration units based on the arbitration information; call the target arbitration unit and generate a target index based on the arbitration information; determine the target queue data from the multiple queue data based on the target index; convert the target queue data into a target instruction set, and send the target instruction set to the parsing and processing module; the parsing and processing module is further configured to read and write a flash memory chip based on the target instruction set. The present invention improves the queue scheduling speed and scheduling flexibility of a flash memory controller.

Description

Technical Field

[0001] The present invention relates to the field of data storage technology, and in particular to a queue scheduling device, method, electronic equipment and medium. Background Art

[0002] In the prior art, the operation instruction scheduling of the NOT AND gate (NAND) flash memory controller is implemented through software. With the advancement of storage technology and the increase in storage capacity, existing storage controllers can achieve millions of IOPS performance with lower latency. However, the process of using software scheduling may introduce higher latency, thereby reducing the read and write rate of the NAND storage controller accessing the NAND flash memory chip.

[0003] The method of implementing operation instruction scheduling through software can no longer meet the high-speed and low-latency performance requirements of NAND storage controllers. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to overcome the shortcomings of the existing technology and provide a queue scheduling device, method, electronic device and medium, aiming to implement queue scheduling through hardware and improve the queue scheduling performance of NAND flash memory controllers. The present invention provides the following technical solutions:

[0005] In a first aspect, the present invention provides a queue scheduling device, the queue scheduling device comprising: a parsing and processing module and a scheduling module, the scheduling module comprising a plurality of arbitration units;

[0006] The analysis and processing module is respectively connected to the bus, the flash memory chip and the scheduling module in communication;

[0007] The parsing and processing module is configured to receive and parse queue data packets from the bus to obtain arbitration information and a plurality of queue data; and send the arbitration information and the plurality of queue data to the scheduling module;

[0008] The scheduling module is configured to determine a target arbitration unit from the plurality of arbitration units according to the arbitration information; call the target arbitration unit and generate a target index according to the arbitration information; determine target queue data from the plurality of queue data according to the target index; convert the target queue data into a target instruction set, and send the target instruction set to the parsing and processing module;

[0009] The parsing and processing module is further configured to read and write the flash memory chip according to the target instruction set.

[0010] In one embodiment, the scheduling module further includes: a register and a state machine, the state machine being communicatively connected to the register and the plurality of arbitration units respectively; the register being used to receive and save the arbitration information from the analysis and processing module; the state machine being used to obtain the arbitration information from the register, the arbitration information including selection information, a communication identifier corresponding to each queue data, and a priority corresponding to each queue data; and determining the target arbitration unit from the plurality of arbitration units based on the selection information.

[0011] In one embodiment, the state machine is also used to determine whether the priorities corresponding to the queue data are the same if the communication identifiers corresponding to the queue data are the same; if they are the same, calling the target arbitration unit to determine the target communication identifier from the multiple communication identifiers; if they are different, determining the communication identifiers corresponding to the queue data as the target communication identifier in turn according to the priority order corresponding to the queue data; and generating a target index based on the target communication identifier.

[0012] In one embodiment, the state machine is also used to group the communication identifiers to obtain multiple communication identifier sets if the communication identifiers corresponding to the queue data are different, and multiple communication identifiers in the same communication identifier set are the same; according to the communication identifier sequence corresponding to each communication identifier set, each communication identifier set is determined as a target communication identifier set in turn, and the multiple communication identifiers in the target communication identifier set are respectively determined as initial target communication identifiers; for multiple initial target communication identifiers, determine whether the priorities of the corresponding queue data are the same; if they are the same, call the target arbitration unit to determine the target communication identifier from the multiple initial target communication identifiers; if they are different, determine each initial target communication identifier as a target communication identifier in turn according to the priority sequence of the corresponding queue data; and generate a target index based on the target communication identifier.

[0013] In one embodiment, the scheduling module also includes: a queue memory, used to receive and save multiple queue data from the parsing processing module; receive the target index from the state machine, and determine the target queue data from the multiple queue data based on the target index; and send the target queue data to the state machine.

[0014] In one embodiment, the scheduling module further includes: an instruction set generation unit, configured to receive the target queue data from the state machine and convert the target queue data into the target instruction set; and send the target instruction set to the parsing and processing module.

[0015] In one embodiment, the analysis and processing module includes: a bus interface analysis unit and a microprocessor unit;

[0016] The bus interface parsing unit is configured to receive and parse the queue data packet from the bus to obtain the arbitration information and a plurality of queue data, and send the arbitration information to the register and the plurality of queue data to the queue memory;

[0017] The microprocessing unit is used to obtain the target instruction set from the instruction set generation unit, and read and write the flash memory chip according to the target instruction set.

[0018] In a second aspect, the present invention provides a queue scheduling method, which is applied to the queue scheduling device described in the first aspect, and the method includes:

[0019] The parsing processing module receives and parses the queue data packets from the bus to obtain a plurality of queue data and arbitration information; and sends the arbitration information and the plurality of queue data to the scheduling module;

[0020] The scheduling module determines a target arbitration unit from the plurality of arbitration units according to the arbitration information; calls the target arbitration unit and generates a target index according to the arbitration information; determines target queue data from the plurality of queue data according to the target index; converts the target queue data into a target instruction set, and sends the target instruction set to the parsing and processing module;

[0021] The parsing and processing module reads and writes the flash memory chip according to the target instruction set.

[0022] In a third aspect, the present invention provides an electronic device comprising the queue scheduling device described in the first aspect.

[0023] In a fourth aspect, the present invention provides a computer-readable storage medium storing a computer program, wherein the computer program is executed by a processor to implement the queue scheduling method described in the second aspect.

[0024] The present invention provides a queue scheduling device, method, electronic device, and medium. The device includes: a parsing and processing module and a scheduling module, wherein the scheduling module includes multiple arbitration units; the parsing and processing module is respectively connected to a bus, a flash memory chip, and the scheduling module; the parsing and processing module is configured to receive queue data packets from the bus and parse them to obtain arbitration information and multiple queue data; the arbitration information and multiple queue data are sent to the scheduling module; the scheduling module is configured to determine a target arbitration unit from the multiple arbitration units based on the arbitration information; call the target arbitration unit and generate a target index based on the arbitration information; determine the target queue data from the multiple queue data based on the target index; convert the target queue data into a target instruction set and send the target instruction set to the parsing and processing module; the parsing and processing module is further configured to read and write the flash memory chip according to the target instruction set. The present invention implements queue scheduling through hardware, thereby improving queue scheduling performance. In addition, the queue scheduling device provided by the present invention stores multiple queue scheduling algorithms, allowing different scheduling algorithms to be selected according to needs, thereby improving queue scheduling flexibility.

[0025] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0027] Figure 1 A schematic structural diagram of a queue scheduling device provided by an embodiment of the present invention is shown;

[0028] Figure 2 A schematic diagram showing arbitration information provided by an embodiment of the present invention is shown;

[0029] Figure 3 Another structural diagram of the queue scheduling device provided by an embodiment of the present invention is shown;

[0030] Figure 4 A schematic diagram of a process of multi-queue data arbitration provided by an embodiment of the present invention is shown;

[0031] Figure 5 A schematic diagram of a storage structure of multi-queue data provided by an embodiment of the present invention is shown;

[0032] Figure 6A schematic flow chart of a queue scheduling method provided by an embodiment of the present invention is shown.

[0033] Description of main component symbols:

[0034] 100-queue scheduling device; 110-scheduling module; 111-register; 112-queue memory; 113-instruction set generation unit; 114-state machine; 115-first arbitration unit; 116-second arbitration unit; 120-analysis processing module; 121-bus interface analysis unit; 122-microprocessor unit; 200-bus; 300-flash memory chip. DETAILED DESCRIPTION

[0035] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0036] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs. The terms used in the template description herein are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0038] Example 1

[0039] The embodiment of the present invention provides a queue scheduling device. For details, see Figure 1 , the queue scheduling device 100 includes: a scheduling module 110 and a parsing and processing module 120, the scheduling module 110 includes a plurality of arbitration units;

[0040] The analysis and processing module 120 is respectively connected to the bus 200, the flash memory chip 300 and the scheduling module 110;

[0041] The parsing and processing module 120 is configured to receive and parse queue data packets from the bus 200 to obtain arbitration information and a plurality of queue data; and send the arbitration information and the plurality of queue data to the scheduling module 110;

[0042] The scheduling module 110 is configured to determine a target arbitration unit from the plurality of arbitration units based on the arbitration information; call the target arbitration unit and generate a target index based on the arbitration information; determine target queue data from the plurality of queue data based on the target index; convert the target queue data into a target instruction set, and send the target instruction set to the parsing and processing module 120;

[0043] The parsing and processing module 120 is further configured to read and write the flash memory chip 300 according to the target instruction set.

[0044] In this embodiment, the bus 200 is an Advanced Microcontroller Bus Architecture (AMBA), and the parsing processing module 120 receives and parses the bus address and queue data packets from the AMBA bus to obtain arbitration information and multiple queue data, wherein the arbitration information includes selection information, a communication identifier corresponding to each queue data, and a priority corresponding to each queue data. For example, see Figure 2 , Figure 2 Com_id represents the communication identifier corresponding to each queue data, and Pority represents the priority corresponding to each queue data.

[0045] It should be noted that the communication ID is a unique identifier for queue data; priority refers to the order in which queue data is processed within multiple queues. It is understood that data with a lower communication ID number will be processed first, while data with a higher communication ID number will be processed later. Similarly, queue data with a higher priority will be processed first, while queue data with a lower priority will be processed later. Specific data processing logic and scheduling strategies can be implemented based on the communication ID and priority.

[0046] Furthermore, the scheduling module 110 includes multiple different arbitration units, each corresponding to a different scheduling algorithm. Specifically, the multiple arbitration units include a first arbitration unit 115 and a second arbitration unit 116, wherein the first arbitration unit 115 stores a round-robin arbitration algorithm (RoudRobin), and the second arbitration unit 116 stores a weighted round-robin arbitration algorithm (Weight RoundRobin). The scheduling module 110 can determine whether to call the first arbitration unit 115 or the second arbitration unit 116 based on the selection information in the arbitration information, and determine the target index based on the communication identifier and priority of each queue. It should be noted that an index is a data structure used to quickly search and access data. In this embodiment, target queue data can be indexed from multiple queue data based on the target index, and finally the target queue data is converted into an instruction set that can be executed by the parsing and processing module 120, namely, a target instruction set.

[0047] In one embodiment, the scheduling module 110 further includes: a register 111 and a state machine 114, wherein the state machine 114 is respectively communicatively connected to the register 111 and the plurality of arbitration units; the register 111 is configured to receive and store the arbitration information from the parsing and processing module 120; the state machine 114 is configured to obtain the arbitration information from the register 111, wherein the arbitration information includes selection information, a communication identifier corresponding to each queue data, and a priority corresponding to each queue data; and the target arbitration unit is determined from the plurality of arbitration units based on the selection information.

[0048] In this embodiment, see Figure 3 The register 111 is in communication with the state machine 114 and the bus interface parsing unit 121 in the parsing processing module 120, and is used to receive arbitration information from the bus 200 and forward it to the state machine 114. The state machine 114 selects and calls different arbitration units according to the selection information.

[0049] Furthermore, the multiple arbitration units include a first arbitration unit 115 and a second arbitration unit 116. When the selection information is round-robin arbitration, the state machine 114 determines the first arbitration unit 115 as the target arbitration unit. When the selection information is weighted round-robin arbitration, the state machine 114 determines the second arbitration unit 116 as the target arbitration unit.

[0050] In one embodiment, see Figure 4 The state machine 114 is also used to determine whether the priorities corresponding to the queue data are the same if the communication identifiers corresponding to the queue data are the same; if they are the same, call the target arbitration unit to determine the target communication identifier from the multiple communication identifiers; if they are different, determine the communication identifiers corresponding to the queue data as the target communication identifier in turn according to the priority order corresponding to the queue data; and generate a target index based on the target communication identifier.

[0051] In this embodiment, the state machine 114 first determines the order of calling each queue data according to the communication identifier corresponding to each queue data. If the communication identifiers corresponding to each queue data are the same, the order of calling each queue data is further determined according to the priority corresponding to each queue data. If the priorities corresponding to each queue data are the same, the target arbitration unit is called to arbitrate the queue data currently required to be called according to the communication identifier and priority corresponding to each queue data, and generate a target index according to the communication identifier of the queue data.

[0052] When the target arbitration unit is the first arbitration unit 115, it indicates that the arbitration algorithm being called is a round-robin arbitration algorithm. Round-robin arbitration is an algorithm used to schedule data between multiple queues. In round-robin arbitration, each queue data is given an opportunity to execute in a certain order. The cycle starts from the beginning. After the current queue is selected, the priority of the last selected queue is reduced to the lowest at the start of the next round. In round-robin arbitration, each queue data is given an equal opportunity to execute, thereby achieving fair scheduling. When the target arbitration unit is the second arbitration unit 116, it indicates that the arbitration algorithm being called is a weighted round-robin arbitration algorithm. Weighted round-robin arbitration determines the order in which queue data are processed based on the weight of each queue data. For example, if the weight of queue data a is 2 and the weight of queue data b is 1, this means that during queue scheduling, queue data a will be selected twice and queue data b will be selected once. Therefore, queue data a will be processed first, and the communication identifier corresponding to queue data a will be determined as the target communication identifier.

[0053] It should be noted that the arbitration information also includes the weights corresponding to the data in each queue. Please refer to Figure 2 , Figure 2 RoundRobinWeighnt indicates the weight corresponding to each queue data.

[0054] In one embodiment, see again Figure 4 The state machine 114 is also used to, if the communication identifiers corresponding to the queue data are different, group the communication identifiers to obtain multiple communication identifier sets, and multiple communication identifiers in the same communication identifier set are the same; according to the communication identifier sequence corresponding to each communication identifier set, determine each communication identifier set as a target communication identifier set in turn, and determine the multiple communication identifiers in the target communication identifier set as initial target communication identifiers respectively; for multiple initial target communication identifiers, determine whether the priorities of the corresponding queue data are the same; if they are the same, call the target arbitration unit to determine the target communication identifier from the multiple initial target communication identifiers; if they are different, determine each initial target communication identifier as a target communication identifier in turn according to the priority sequence of the corresponding queue data; and generate a target index according to the target communication identifier.

[0055] In this embodiment, if the communication identifiers corresponding to the queue data are different, the same communication identifiers are grouped together to obtain multiple communication identifier sets. Since the multiple communication identifiers in the same communication identifier set are the same, it can be understood that the identification sequence number of the communication identifier set is the same as the identification sequence numbers of the multiple communication identifiers in the communication identifier set. Since data with smaller communication identifier sequence numbers will be processed in a limited manner, the multiple communication identifier sets are sequentially determined as the target communication identifier set in ascending order of their respective identification numbers. Further, it is determined whether the queue data corresponding to each initial target communication identifier in the target communication identifier set have the same priority. If they are the same, the target arbitration unit is called to arbitrate the queue data currently to be called, and a target index is generated based on the communication identifier of the queue data. If they are different, the corresponding target indexes are generated in order of priority, and the queue data is called.

[0056] In one embodiment, the scheduling module 110 also includes: a queue memory 112, which is used to receive and save multiple queue data from the parsing and processing module 120; receive the target index from the state machine 114, and determine the target queue data from the multiple queue data based on the target index; and send the target queue data to the state machine 114.

[0057] In this embodiment, please refer to Figure 3 The queue memory 112 is respectively connected to the state machine 114 and the bus interface parsing unit 121 in the parsing processing module 120 for communication, and dispatches target queue data from multiple queue data according to the target index and then sends it to the state machine 114.

[0058] The queue memory 112 stores multiple queue data. For details, see Figure 5 , Figure 5 In the figure, Queue RAM represents the queue memory 112 , and Queue0 to QueueN represent a plurality of queue data stored in the queue memory 112 .

[0059] In one embodiment, the scheduling module 110 further includes: an instruction set generation unit 113 for receiving the target queue data from the state machine 114 and converting the target queue data into the target instruction set; and sending the target instruction set to the parsing processing module 120.

[0060] In this embodiment, please refer to Figure 3The instruction set generation unit 113 is respectively communicated with the state machine 114 and the micro-processing unit 122 in the parsing and processing module 120. It should be noted that the micro-processing unit 122 is a custom micro-processing unit. Therefore, the target queue data needs to be processed by the instruction set generation unit 113 into an instruction set that can be executed by the custom micro-processing unit, that is, the target instruction set, and then sent to the micro-processing unit 122.

[0061] In one embodiment, the analysis and processing module 120 includes: a bus interface analysis unit 121 and a micro-processing unit 122;

[0062] The bus interface parsing unit 121 is configured to receive and parse the queue data packet from the bus 200 to obtain the arbitration information and a plurality of queue data, and to send the arbitration information to the register 111 and the plurality of queue data to the queue memory 112;

[0063] The micro-processing unit 122 is configured to obtain the target instruction set from the instruction set generating unit 113 and read and write the flash memory chip 300 according to the target instruction set.

[0064] In this embodiment, please refer to Figure 3 The microprocessor unit 122 is respectively connected to the instruction set generation unit 113, the state machine 114, the flash memory chip 300 and the bus 200 for communication. The microprocessor unit 122 reads and writes the flash memory chip 300 according to the received target instruction set, and feeds back the completion status to the state machine 114 after the instruction set is executed.

[0065] The queue scheduling device provided by an embodiment of the present invention includes: a parsing and processing module and a scheduling module, wherein the scheduling module includes multiple arbitration units; the parsing and processing module is respectively connected to a bus, a flash memory chip, and the scheduling module; the parsing and processing module is used to receive queue data packets from the bus and parse them to obtain arbitration information and multiple queue data; the arbitration information and multiple queue data are sent to the scheduling module; the scheduling module is used to determine a target arbitration unit from the multiple arbitration units based on the arbitration information; call the target arbitration unit and generate a target index based on the arbitration information; determine the target queue data from the multiple queue data based on the target index; convert the target queue data into a target instruction set and send the target instruction set to the parsing and processing module; the parsing and processing module is further used to read and write the flash memory chip according to the target instruction set. The present invention implements queue scheduling through hardware, thereby improving queue scheduling speed. In addition, the queue scheduling device provided by the present invention stores multiple queue scheduling algorithms, and different scheduling algorithms can be selected according to needs, which also improves the flexibility of queue scheduling.

[0066] Example 2

[0067] In addition, the present invention also provides a queue scheduling method, which is applied to the queue scheduling device described in Example 1. For details, see Figure 6 , the method comprising:

[0068] In step S610 , the parsing processing module receives and parses a queue data packet from the bus to obtain a plurality of queue data and arbitration information.

[0069] Step S620: Send the arbitration information and the plurality of queue data to a scheduling module.

[0070] Step S630: The scheduling module determines a target arbitration unit from the plurality of arbitration units according to the arbitration information.

[0071] Step S640: calling the target arbitration unit and generating a target index according to the arbitration information.

[0072] Step S650: determining target queue data from the plurality of queue data according to the target index.

[0073] Step S660: convert the target queue data into a target instruction set, and send the target instruction set to the parsing processing module.

[0074] Step S670: the parsing processing module reads and writes the flash memory chip according to the target instruction set.

[0075] The queue scheduling method provided by an embodiment of the present invention receives and parses queue data packets from a bus through a parsing processing module to obtain multiple queue data and arbitration information; sends the arbitration information and the multiple queue data to a scheduling module; the scheduling module determines a target arbitration unit from the multiple arbitration units based on the arbitration information; calls the target arbitration unit and generates a target index based on the arbitration information; determines the target queue data from the multiple queue data based on the target index; converts the target queue data into a target instruction set and sends the target instruction set to the parsing processing module; the parsing processing module reads and writes the flash memory chip based on the target instruction set, thereby implementing hardware execution queue scheduling and improving queue scheduling speed. In addition, the present invention improves the flexibility of queue scheduling by storing multiple different queue scheduling algorithms and selecting different scheduling algorithms according to needs.

[0076] The queue scheduling method provided in the embodiment of the present invention is applied to the queue scheduling device described in Example 1, and will not be described again here to avoid repetition.

[0077] Example 3

[0078] In addition, an embodiment of the present invention provides an electronic device, including the queue scheduling device described in Example 1.

[0079] Specifically, it includes a parsing and processing module and a scheduling module, and the scheduling module includes multiple arbitration units; the parsing and processing module is respectively communicated with the bus, the flash memory chip and the scheduling module; the parsing and processing module is used to receive queue data packets from the bus and parse them to obtain arbitration information and multiple queue data; send the arbitration information and multiple queue data to the scheduling module; the scheduling module is used to determine the target arbitration unit from the multiple arbitration units according to the arbitration information; call the target arbitration unit and generate a target index according to the arbitration information; determine the target queue data from the multiple queue data according to the target index; convert the target queue data into a target instruction set, and send the target instruction set to the parsing and processing module; the parsing and processing module is also used to read and write the flash memory chip according to the target instruction set.

[0080] The electronic device provided by the embodiment of the present invention includes the queue scheduling device described in Example 1, which will not be described again here to avoid repetition.

[0081] Example 4

[0082] In addition, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the queue scheduling method provided in Example 2 is implemented.

[0083] In this embodiment, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0084] The computer-readable storage medium provided in this embodiment can implement the queue scheduling method provided in Example 2, and will not be described again here to avoid repetition.

[0085] In all examples shown and described herein, any specific values ​​should be interpreted as merely exemplary and not limiting, and thus other examples of the exemplary embodiments may have different values.

[0086] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not require further definition or explanation in subsequent drawings.

[0087] The above-described embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that variations and modifications are possible without departing from the scope of the present invention, and such variations and modifications are fully within the scope of protection of the present invention.

Claims

1. A queue scheduling device, characterized in that: The queue scheduling device includes: a parsing and processing module and a scheduling module, wherein the scheduling module includes a plurality of arbitration units; The analysis and processing module is respectively connected to the bus, the flash memory chip and the scheduling module in communication; The parsing and processing module is configured to receive and parse queue data packets from the bus to obtain arbitration information and a plurality of queue data; and send the arbitration information and the plurality of queue data to the scheduling module; The scheduling module is configured to determine a target arbitration unit from the plurality of arbitration units according to the arbitration information; call the target arbitration unit and generate a target index according to the arbitration information; determine target queue data from the plurality of queue data according to the target index; convert the target queue data into a target instruction set, and send the target instruction set to the parsing and processing module; The parsing and processing module is further configured to read and write the flash memory chip according to the target instruction set; The scheduling module further includes: a register and a state machine, wherein the state machine is communicatively connected to the register and the plurality of arbitration units respectively; The register is configured to receive and store the arbitration information from the analysis and processing module; The state machine is configured to obtain the arbitration information from the register, where the arbitration information includes selection information, a communication identifier corresponding to each queue data, and a priority corresponding to each queue data; determining the target arbitration unit from the plurality of arbitration units according to the selection information; The state machine is further configured to determine whether the priorities corresponding to the queue data are the same if the communication identifiers corresponding to the queue data are the same; If they are the same, calling the target arbitration unit to determine the target communication identifier from the multiple communication identifiers; If they are different, the communication identifiers corresponding to the queue data are determined as target communication identifiers in turn according to the priority order corresponding to the queue data; A target index is generated according to the target communication identifier, and the target index is used to search for and access the target queue data.

2. The queue scheduling device according to claim 1, characterized in that: The state machine is further configured to group the communication identifiers to obtain multiple communication identifier sets if the communication identifiers corresponding to the queue data are different, and multiple communication identifiers in the same communication identifier set are the same; According to the communication identification sequence corresponding to each communication identification set, each communication identification set is sequentially determined as a target communication identification set, and the plurality of communication identifications in the target communication identification set are respectively determined as initial target communication identifications; For a plurality of the initial target communication identifiers, determining whether the priorities of the corresponding queue data are the same; If they are the same, calling the target arbitration unit to determine the target communication identifier from the multiple initial target communication identifiers; If they are different, then determining each of the initial target communication identifiers as the target communication identifier in sequence according to the priority order of the corresponding queue data; A target index is generated according to the target communication identifier.

3. The queue scheduling device according to claim 1 or 2, characterized in that: The scheduling module also includes: The queue memory is used to receive and save the multiple queue data from the parsing processing module; receive the target index from the state machine, and determine the target queue data from the multiple queue data according to the target index; and send the target queue data to the state machine.

4. The queue scheduling device according to claim 3, characterized in that: The scheduling module further includes: an instruction set generating unit, configured to receive the target queue data from the state machine and convert the target queue data into the target instruction set; and send the target instruction set to the parsing processing module.

5. The queue scheduling device according to claim 4, characterized in that: The analysis and processing module includes: a bus interface analysis unit and a microprocessor unit; The bus interface parsing unit is configured to receive and parse the queue data packet from the bus to obtain the arbitration information and the plurality of queue data, and to send the arbitration information to the register and the plurality of queue data to the queue memory; The microprocessing unit is used to obtain the target instruction set from the instruction set generation unit, and read and write the flash memory chip according to the target instruction set.

6. A queue scheduling method, characterized in that: The queue scheduling device according to any one of claims 1 to 5, wherein the method comprises: The parsing processing module receives and parses the queue data packets from the bus to obtain a plurality of queue data and arbitration information; and sends the arbitration information and the plurality of queue data to the scheduling module; The scheduling module determines a target arbitration unit from the plurality of arbitration units according to the arbitration information; calls the target arbitration unit and generates a target index according to the arbitration information; determines target queue data from the plurality of queue data according to the target index; converts the target queue data into a target instruction set, and sends the target instruction set to the parsing and processing module; The parsing processing module reads and writes the flash memory chip according to the target instruction set; Determining a target arbitration unit from the plurality of arbitration units according to the arbitration information includes: a register receiving and storing the arbitration information from the parsing and processing module; a state machine acquiring the arbitration information from the register, the arbitration information including selection information, a communication identifier corresponding to each queue data, and a priority corresponding to each queue data; and determining the target arbitration unit from the plurality of arbitration units according to the selection information; If the communication identifiers corresponding to the queue data are the same, the state machine determines whether the priorities corresponding to the queue data are the same; if they are the same, the target arbitration unit is called to determine the target communication identifier from the multiple communication identifiers; if they are different, the communication identifiers corresponding to the queue data are determined as the target communication identifier in turn according to the priority order corresponding to the queue data; a target index is generated according to the target communication identifier, and the target index is used to search and access the target queue data.

7. An electronic device, characterized in that: The invention comprises the queue scheduling device according to any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the queue scheduling method according to claim 6 is implemented.

Images