Method for determining bit error rate of optical module, computing device and readable storage medium

Abstract

The present disclosure relates to a method for determining the bit error rate of an optical module during data transmission, applied to an optical module based on high-speed serial computer expansion bus technology, comprising: initializing the high-speed serial computer expansion bus port of the computing processing unit and detecting the hardware connection state; in the case of completing initialization and normal connection state, resetting the error counter associated with the optical module; sending a control instruction by the central processor to control the computing processing unit or sending a predetermined data packet by the central processor and correspondingly acquiring the error count by the central processor or the computing processing unit; and calculating the bit error rate based on the error count and the predetermined data packet. The method accurately determines the error count of the error counter by means of the high-speed serial computer expansion bus technology data transmission interface, so as to accurately calculate the bit error rate based on the error count and the predetermined data packet, and realize accurate analysis of the transmission performance of the corresponding optical module.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of server, in particular to performance evaluation of optical modules, and more particularly to a method for determining bit error rate of an optical module during data transmission, a computing device for determining bit error rate of an optical module during data transmission, and a computer readable storage medium for implementing the above method for determining bit error rate of an optical module during data transmission. BACKGROUND

[0002] With the development of Internet technology, big data technology and artificial intelligence technology, a large amount of data needs to be transmitted over the network. At this time, the data volume in the data center as the infrastructure will also have an explosive growth demand. In addition, with the improvement of the transmission rate of the fifth and sixth generation high-speed serial computer expansion bus (PCIe) technology, the rate of the signal required for transmission becomes higher and higher, and the loss on the printed circuit board (PCB) or copper wire becomes larger and larger. In the future, optical modules based on PCIe technology will be widely used, and the bit error rate test requirement of the optical module will become a necessary test means for whether the product can be mass-produced. SUMMARY

[0003] In the related art, the test must be performed with the aid of a bit error instrument which is expensive, and at this time the measurement result cannot well reflect the performance in actual application due to the absence of a corresponding standard; in addition, the bit error instrument test is low in efficiency and high in price. The inventors of the present disclosure have innovatively thought of prompting a computing processing unit which is in communication connection with the central processing unit via the high-speed serial computer expansion bus (PCIe) technology to realize the similar function of the bit error instrument with the aid of the central processing unit, so as to realize the evaluation of the transmission performance of the optical module associated with the computing processing unit.

[0004] Specifically, the first aspect of the present disclosure proposes a method for determining bit error rate of an optical module during data transmission, applied to an optical module based on high-speed serial computer expansion bus technology, the method comprising:

[0005] initializing the high-speed serial computer expansion bus port of the computing processing unit and detecting the hardware connection state;

[0006] in the case of completing the initialization and the normal connection state, resetting an error counter associated with the optical module;

[0007] sending a control instruction by the central processing unit to control the computing processing unit or sending a predetermined data packet by the central processing unit and correspondingly acquiring the error count of the error counter by the central processing unit or the computing processing unit; and

[0008] calculating the bit error rate based on the error count and the predetermined data packet.

[0009] In the method for determining the bit error rate of the optical module when transmitting data according to the present disclosure, the control instruction is sent by the central processing unit to control the calculation processing unit or the predetermined data packet is sent by the central processing unit and the error count of the error counter is obtained by the central processing unit or the calculation processing unit accordingly, so that the error count of the error counter can be accurately determined by means of the high-speed serial computer expansion bus technology data transmission interface of the central processing unit or the calculation processing unit, and the bit error rate can be accurately calculated based on the error count and the predetermined data packet, and accurate analysis of the transmission performance of the corresponding optical module can be realized.

[0010] Optionally, in some optional forms according to the present disclosure, the method further comprises: saving the error count in the error counter as a log file. Here, the log file at least includes the error count of the error counter of each link, and can also optionally include one or more parameters associated with the execution of the method for determining the bit error rate of the optical module when transmitting data according to the present disclosure, such as the size of the data packet for each test and the actual running time for each test. Such a log file can be saved in the central processing unit, in the memory associated with the central processing unit, or in the memory associated with the calculation processing unit, for example.

[0011] Optionally, in some optional forms according to the present disclosure, calculating the bit error rate based on the error count and the predetermined data packet comprises: calculating the bit error rate based on the log file and the predetermined data packet. As mentioned earlier, when the error count in the error counter is saved as a log file, the bit error rate can be calculated based on the log file and the predetermined data packet, for example. In this way, the optical module can be evaluated retrospectively after each execution of the method, and the bit error rate when the method for determining the bit error rate of the optical module when transmitting data according to the present disclosure is executed can be traced back at any time point after the execution of the method for determining the bit error rate of the optical module when transmitting data according to the present disclosure, improving the verifiability and checkability of the bit error rate evaluation.

[0012] Optionally, in some optional forms according to the present disclosure, the calculation processing unit is associated with the optical module. Optionally, in some optional forms according to the present disclosure, the graphics calculation unit is configured as any one of a graphics processor, a tensor processor, a neural network processor, a deep learning processor, an acceleration processor, and a general-purpose graphics processor.

[0013] Optionally, in some optional forms according to the present disclosure, initializing the high-speed serial computer expansion bus port of the computing processing unit and detecting the hardware connection status comprises: restarting each computing processing unit and initializing the high-speed serial computer expansion bus port of the computing processing unit. Preferably, in some optional forms according to the present disclosure, the restarting is configured as a hot restart.

[0014] Preferably, in some optional forms according to the present disclosure, before initializing the high-speed serial computer expansion bus port of the computing processing unit and detecting the hardware connection status, the method further comprises: obtaining a predetermined number of execution times of the subsequent steps and a size of the data packet sent at each execution time. Preferably, in some optional forms according to the present disclosure, the method further comprises: comparing a current number of execution times with the predetermined number of execution times; and continuing the execution if the current number of execution times is within the predetermined number of execution times, and terminating the execution and saving a log file if the current number of execution times is greater than the predetermined number of execution times. More preferably, in some optional forms according to the present disclosure, the number of execution times is divided into at least two batches according to a time sequence, and a size of the data packet sent at a later batch execution is greater than a size of the data packet sent at an earlier batch execution. Further preferably, in some optional forms according to the present disclosure, calculating the bit error rate based on the error count and the predetermined data packet comprises: calculating a total bit error rate based on the error count at each execution time and the predetermined data packet. Still further preferably, in some optional forms according to the present disclosure, the method further comprises: terminating the execution of the method if the bit error rate is higher than a predetermined threshold. Preferably, in some optional forms according to the present disclosure, the high-speed serial computer expansion bus technology comprises a sixth generation high-speed serial computer expansion bus technology.

[0015] Optionally, in some optional forms according to the present disclosure, controlling the computing processing unit to send the predetermined data packet further comprises: controlling the computing processing unit to send the predetermined data packet in a host-to-device (H2D) manner. Here, the term host-to-device (Host to Device) is applied in computer science or network technology. Here, "H2D" can refer to a data transmission or communication process from a host computer to other computing devices (such as a GPU) or external devices (such as storage devices, peripheral devices, etc.).

[0016] In addition, a second aspect of the present disclosure proposes a computing device, comprising a memory and a processor, the memory storing computer readable instructions, when the computer readable instructions are executed by the processor, causing the processor to implement the method for determining a bit error rate of a data transmission of an optical module according to the first aspect of the present disclosure.

[0017] Further, the third aspect of the present disclosure proposes a computer readable storage medium having stored thereon computer executable instructions for performing the method for determining the bit error rate of an optical module during data transmission according to the first aspect of the present disclosure.

[0018] In summary, in the method for determining the bit error rate of an optical module during data transmission, the computing device for determining the bit error rate of an optical module during data transmission and the corresponding computer readable storage medium according to the present disclosure, the control instructions are sent by the central processor to control the computing processing unit or the predetermined data packet is sent by the central processor and the error count of the error counter is obtained by the central processor or the computing processing unit accordingly, so that the error count of the error counter can be accurately determined by means of the high-speed serial computer expansion bus technology data transmission interface of the central processor or the computing processing unit, and the bit error rate can be accurately calculated based on the error count and the predetermined data packet, thereby realizing accurate analysis of the transmission performance of the corresponding optical module. BRIEF DESCRIPTION OF DRAWINGS

[0019] The features, advantages, and other aspects of the embodiments of the present disclosure will become more apparent from the following detailed description in conjunction with the accompanying drawings, in which a number of embodiments of the present disclosure are illustrated, by way of example, and not limitation, as follows:

[0020] Figure 1 Fig. 1 shows a schematic diagram of the hardware connection when the method for determining the bit error rate of an optical module during data transmission according to one embodiment of the present disclosure is executed;

[0021] Figure 2A Fig. 2A shows a schematic flowchart of the method 200A for determining the bit error rate of an optical module during data transmission according to the present disclosure;

[0022] Figure 2B Fig. 2B shows a schematic flowchart of the method 200B for determining the bit error rate of an optical module during data transmission according to the present disclosure;

[0023] Figure 2C Fig. 2C shows a schematic flowchart of the method 200C for determining the bit error rate of an optical module during data transmission according to the present disclosure;

[0024] Figure 3 Fig. 3 shows a schematic diagram of the computing device 300 for determining the bit error rate of an optical module during data transmission according to one embodiment of the present disclosure; and

[0025] Figure 4A schematic diagram of a computing device 400 for determining a bit error rate of an optical module when transmitting data is shown, in accordance with another embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] Various example embodiments of the present disclosure are described in detail below with reference to the attached drawing figures. While the example methods, devices described below include software and / or firmware executed on hardware, it should be noted that the examples are merely illustrative and should not be taken as limiting. For example, any or all of the hardware, software, and firmware components could be implemented in hardware, software, or any combination of hardware and software. Thus, while the example methods and devices have been described, it should be apparent that the examples provided are not limiting, and that the methods and devices can be implemented in a variety of ways.

[0027] Furthermore, the flow diagrams and block diagrams in the drawings are intended to illustrate the possible architectures, functions, and operations of methods and systems according to various embodiments of the present disclosure. It will be noted that many of the functions and operations described herein can be implemented as software modules or components. It will also be noted that the functions and operations described herein can be performed by hardware, software, or any combination of hardware and software. It will also be noted that the various functions and operations described herein can be performed by a specially-programmed computer module or component. It will also be noted that the various functions and operations described herein can be performed by a specially-programmed computer module or component.

[0028] The terms "comprise," "comprising," "include," "including," and the like are open-ended terms, i.e., "comprising but not limited to," meaning that other elements can be included. The term "based on" means "based, at least in part, on." The term "one embodiment" is used to indicate "at least one embodiment," the term "another embodiment" is used to indicate "at least one additional embodiment," and so on. In other words, the terms "one embodiment" and "another embodiment" are not used to limit the number of embodiments.

[0029] In the present disclosure, the terms "first," "second," and the like, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another, unless otherwise indicated. In the present disclosure, the meaning of "a," "an," and "the" includes singular and plural references, unless otherwise indicated. The terms "comprising," "comprises" and "comprised of" as used herein are synonymous with "including," "includes" or "containing," "contains" and are inclusive or open-ended and do not exclude additional, unrecited elements or method steps.

[0030] The related art usually provides signal excitation through a bit error rate instrument, directly sends to the optical module, directly tests the electrical eye diagram, the optical eye diagram of the optical module, or calculates the bit error rate by directly sending a signal to the optical module through the bit error rate instrument and then returning to the bit error rate instrument through the optical loopback of the optical module. Such a solution, on the one hand, because the instrument of the bit error rate instrument is expensive, on the other hand, the bit error rate instrument can only test one link at a time, and usually each optical module has eight links, which will make the test efficiency too low. In addition, the specification of the high-speed serial computer expansion bus PCIe does not specially formulate relevant standards for analog optical modules, so the electrical eye diagram test does not know how many dB to calculate the total loss, and the specification of the high-speed serial computer expansion bus PCIe does not specially formulate relevant standards for analog optical modules, resulting in no standard calibration for the instrument. In this way, even if the performance of the bit error rate instrument is good, but in actual system application, there are still many errors, so that the tested optical module that meets the requirements cannot meet the needs of actual application.

[0031] As described before, in the related art, the test must be carried out by means of an expensive bit error rate instrument, and at this time, due to the absence of corresponding standards, the measurement results cannot well reflect the performance in actual application; in addition, the bit error rate instrument is low in test efficiency and high in price. The inventors of the present disclosure innovatively thought of prompting the computing processing unit connected with it through the high-speed serial computer expansion bus PCIe technology by means of the central processing unit to realize the similar function of the bit error rate instrument, so as to realize the evaluation of the transmission performance of the optical module associated with the computing processing unit.

[0032] Generally, the present disclosure proposes a method for determining the bit error rate of an optical module during data transmission, applied to an optical module based on high-speed serial computer expansion bus technology, the method comprising: initializing the high-speed serial computer expansion bus port of the computing processing unit and detecting the hardware connection state; in the case of completing initialization and normal connection state, resetting the error counter associated with the optical module; sending a control instruction by the central processor to control the computing processing unit or sending a predetermined data packet by the central processor and correspondingly acquiring the error count of the error counter by the central processor or the computing processing unit; and calculating the bit error rate based on the error count and the predetermined data packet. In the method for determining the bit error rate of an optical module during data transmission according to the present disclosure, the control instruction is sent by the central processor to control the computing processing unit or the predetermined data packet is sent by the central processor and the error count of the error counter is correspondingly acquired by the central processor or the computing processing unit, so that the error count of the error counter can be accurately determined by means of the high-speed serial computer expansion bus technology data transmission interface of the central processor or the computing processing unit, and the bit error rate can be accurately calculated based on the error count and the predetermined data packet, realizing accurate analysis of the transmission performance of the corresponding optical module.

[0033] The specific steps of the method for determining the bit error rate of an optical module during data transmission according to the present disclosure and the specific details when executed will be described in detail below with reference to the accompanying drawings. Among them, Figure 1 A hardware connection schematic diagram when the method for determining the bit error rate of an optical module during data transmission according to one embodiment of the present disclosure is executed is shown; Figure 2A A schematic flowchart of the method 200A for determining the bit error rate of an optical module during data transmission according to the present disclosure is shown; Figure 2B A schematic flowchart of the method 200B for determining the bit error rate of an optical module during data transmission according to the present disclosure is shown; Figure 2C A schematic flowchart of the method 200C for determining the bit error rate of an optical module during data transmission according to the present disclosure is shown; Figure 3 A schematic diagram of the computing device 300 for determining the bit error rate of an optical module during data transmission according to one embodiment of the present disclosure is shown; and Figure 4 A schematic diagram of the computing device 400 for determining the bit error rate of an optical module during data transmission according to another embodiment of the present disclosure is shown.

[0034] From Figure 1 It can be seen from among them that the method for determining the bit error rate of an optical module during data transmission according to the present disclosure can be run in Figure 1The CPUs shown are located in the same server. As Figure 1 As shown, the CPUs and GPUs can be located in the same server, of course, the CPUs and GPUs can also be located in different servers. Typically, each optical module has eight links, here for simplicity only one link connected by an optical fiber is shown. Of course, each optical fiber can also have multiple lines to connect multiple links between the optical module 1 and the optical module 2. In addition, each server can have, for example, eight or sixteen or more GPU boards. In Figure 1 The illustration of one GPU board in each server is merely exemplary and not limiting. It is merely to make the figure more concise and more targeted to highlight the key point, i.e. a topology connection structure. Furthermore, the left side of the vertical dashed line in Figure 1 The right side of the vertical dashed line in Figure 1 The right side of the vertical dashed line in

[0035] The high-speed serial computer expansion bus port (PCIe port) of the computing processing unit can then be initialized and the hardware connection status (i.e. the connection status of each optical module and the corresponding CPU or GPU) is detected; then the error counter associated with the optical module is reset in the case of successful initialization and normal connection status, so that the number of errors during the subsequent method execution can be accurately known.

[0036] Next, control instructions are sent by the central processor to control the computing processing unit or predetermined data packets are sent by the central processor and the error count of the error counter is obtained by the central processor or the computing processing unit accordingly, for example, instructions can be sent to the GPU through a PCIe bus, so that the computing processing unit such as the GPU sends predetermined data packets and obtains the error count of the error counter. Finally, the bit error rate is calculated based on the error count and the predetermined data packets. Here, the CPU can instruct the GPU to send data to the optical module 2 via the optical module 1, and then the error count is determined by the error counter in the CPU; or the CPU can send data to the optical module 1 via the optical module 2, and then the error count is determined by the error counter in the GPU. Here, the error counter can be located in the central processor CPU or in the computing processing unit such as the GPU, and the error count of the error counter each time is based on the data of the error counter at the receiving end. In general, in the method for determining the bit error rate of the optical module during data transmission according to the present disclosure, control instructions are sent by the central processor to control the computing processing unit or predetermined data packets are sent by the central processor and the error count of the error counter is obtained by the central processor or the computing processing unit accordingly, so that the error count of the error counter can be accurately determined by means of the data transmission interface of the central processor and the computing processing unit, so that the bit error rate can be accurately calculated based on the error count and the predetermined data packets, and the transmission performance of the corresponding optical module can be accurately analyzed.

[0037] The specific method steps of the method 200A for determining the bit error rate of the optical module during data transmission and the method 200B for determining the bit error rate of the optical module during data transmission according to the present disclosure will be described below with reference to the accompanying Figure 2A and the accompanying Figure 2B The specific method steps of the method 200A for determining the bit error rate of the optical module during data transmission and the method 200B for determining the bit error rate of the optical module during data transmission according to the present disclosure will be described below with reference to the accompanying Figure 2AAs can be seen from this, the method 200A for determining the bit error rate of an optical module during data transmission according to this disclosure includes at least the following steps: First, in method step 210, the high-speed serial computer expansion bus port of the computing processing unit is initialized and the hardware connection status is detected; after initialization, in method step 220, if initialization is completed and the connection status is normal, the error counter associated with the optical module is reset; next, in method step 230, the central processing unit sends control instructions to control the computing processing unit or the central processing unit sends predetermined data packets and accordingly the central processing unit or the computing processing unit obtains the error count of the error counter; and finally, in method step 240, the bit error rate is calculated based on the error count and the predetermined data packets, thereby enabling the calculation of the bit error rate to correctly evaluate the transmission performance of the optical module.

[0038] In addition, from Figure 2B It can be seen from this that, compared to Figure 2A The method 200B for determining the bit error rate of an optical module during data transmission, according to this disclosure, includes steps 210 to 240. Specifically, step 200B first initializes the high-speed serial computer expansion bus port of the computing processing unit and detects the hardware connection status in step 210. After initialization, in step 220, if initialization is complete and the connection status is normal, the error counter associated with the optical module is reset. This error counter can be located in the central processing unit (CPU) or a computing processing unit such as a GPU, and the error count is based on the data from the error counter at the receiving end. Next, in step 230, the CPU sends control instructions to control the computing processing unit or sends predetermined data packets, and the CPU or computing processing unit accordingly obtains the error count of the error counter. Finally, in step 240, the bit error rate is calculated based on the error count and the predetermined data packets, thereby enabling the calculation of the bit error rate for accurate evaluation of the optical module's transmission performance.

[0039] In addition, the method 200B for determining the bit error rate of an optical module during data transmission according to this disclosure further includes method step 205, in which a predetermined number of executions of subsequent method steps 210 to 240 of the method 200B for determining the bit error rate of an optical module during data transmission according to this disclosure, and the size of the data packet sent during each execution, are obtained. In summary, the method 200B further includes: obtaining a predetermined number of executions for subsequent steps and the size of the data packet sent during each execution in method step 205. Preferably, in some optional forms according to this disclosure, the method further includes: comparing the current execution count with the predetermined execution count; continuing execution if the current execution count is within the predetermined execution count; and terminating execution and saving a log file if the current execution count is greater than the predetermined execution count. In other words, the execution of subsequent steps can be terminated when the current execution count is greater than a set or obtained execution count, i.e., the current method can be terminated. Subsequent operations are performed when the current execution count is within the predetermined count, i.e., initializing the corresponding port and resetting the corresponding error counter, etc.

[0040] Figure 2C A schematic flowchart of a method 200C for determining the bit error rate of an optical module during data transmission, according to the present disclosure, is shown. From Figure 2C As can be seen, method 200C differs from previous methods 200A and 200B in that it further includes: a method step 206 comparing the current execution count with the predetermined execution count; and continuing to execute subsequent method steps 210C, 220, 230, and 240, as well as a potential method step 250, if the current execution count is within the predetermined execution count; and terminating execution and saving the log file in method step 250 if the current execution count is greater than the predetermined execution count. Of course, if port initialization fails or the hardware connection status is abnormal in method step 210C, it will also enter method step 250, and after calculating the bit error rate, it will increment the current execution count by 1 before proceeding to the next judgment and executing the subsequent method steps accordingly.

[0041] For example, in this field, it is typically required that the bit error rate of an optical module does not exceed 10 in each of 500 tests. -12 If testing directly, at least 10 12The data packets generated are too large, resulting in long execution times and low testing efficiency. To address this problem, the inventors of this disclosure innovatively conceived of increasing the data packet size in batches. For example, during the first 500 executions of the method 200A for determining the bit error rate of an optical module during data transmission according to this disclosure, the data packet size is, for example, only 128MB. If any error occurs, the corresponding optical module is unusable. If no abnormalities are found after these 500 tests, the data packet size is increased to, for example, 250MB. If any error occurs, the corresponding optical module is unusable. If no abnormalities are found after these 500 tests, the data packet size is increased to, for example, 1GB. This process continues until, for example, the data packet size is increased to 10GB. 12 If the bit error rate remains less than 10 after 500 tests, then... -12 This means that the performance of such an optical module can meet the requirements. In summary, the number of executions is divided into at least two batches (each batch, for example, 500 times) according to time sequence, with the data packets sent in the later batch being larger than those sent in the previous batch. More preferably, in some optional forms according to this disclosure, calculating the bit error rate based on the error count and the predetermined data packets includes: calculating the total bit error rate based on the error count and the predetermined data packets at each execution. Even more preferably, in some optional forms according to this disclosure, the method further includes: terminating the execution of the method when the bit error rate exceeds a predetermined threshold. That is, if bit errors occur with small data packets, the bit error rate will inevitably not reach 10. -12 If the requirements are met, there is no need to test with larger data packets. Or, if the number of times the method is executed exceeds the limit, steps 210 to 240 of the method 200B for determining the bit error rate of an optical module during data transmission according to this disclosure will not be executed, and the execution of the method 200B for determining the bit error rate of an optical module during data transmission according to this disclosure will be terminated. This also enables testing according to the PCI-SIG standard, making it more convenient for analyzing and debugging optical module parameter settings.

[0042] After setting the number of executions, the batch of executions, the size of the data packet for each execution or each batch of execution, it is necessary to check whether the current number is less than the set number of executions. If there is still a need to perform the method 200A for determining the bit error rate of the optical module during data transmission according to the present disclosure, it is necessary to restart the GPU board. In general, the initial initialization of the high-speed serial computer expansion bus port of the computing processing unit and the detection of the hardware connection state include: restarting each computing processing unit and initializing the high-speed serial computer expansion bus port of the computing processing unit. Such a restart can be a restart of the entire server or only the above-mentioned computing processing unit. Preferably, in some optional forms according to the present disclosure, the restart is configured as a hot restart.

[0043] After the hardware connection is normal and the restart of each computing processing unit is completed, the error counter can be reset, thereby preparing for subsequent calculation of the bit error rate. At this time, the corresponding GPU is instructed to send a data packet of a predetermined size to another optical module connected thereto through the optical module, and the error count of the error counter of the CPU on the other side is determined to calculate the bit error rate. In the case of test completion, the number of executions of the method 200A for determining the bit error rate of the optical module during data transmission according to the present disclosure exceeds the predetermined number, hardware connection failure, error counter failure to complete the reset, or point-to-point port initialization failure, a log file can be saved. At this time, the method 200A or 200B further includes: saving the error count in the error counter as a log file. Here, the log file includes, for example, at least the error count of the error counter of each link, and can also optionally include, for example, the size of the data packet for each test and the actual running time for each test and various parameters associated with the execution of the method for determining the bit error rate of the optical module during data transmission according to the present disclosure. Such a log file can be saved, for example, in the central processing unit, in the memory associated with the central processing unit, or in the memory associated with the computing processing unit. In addition, optionally, in some optional forms according to the present disclosure, calculating the bit error rate based on the error count and the predetermined data packet includes: calculating the bit error rate based on the log file and the predetermined data packet. As mentioned earlier, when the error count in the error counter is saved as a log file, the bit error rate can be calculated, for example, based on the log file and the predetermined data packet. Thereby, the optical module can be evaluated retrospectively at any time after each method execution, and thereby the bit error rate when the method for determining the bit error rate of the optical module during data transmission according to the present disclosure is executed can be traced back at any time point after the execution of the method for determining the bit error rate of the optical module during data transmission according to the present disclosure, improving the verifiability and checkability of the bit error rate evaluation.

[0044] Optionally, in some optional forms according to the present disclosure, the computing processing unit is associated with the optical module. Optionally, in some optional forms according to the present disclosure, the computing processing unit is configured as any one of a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), a NPU (Neural network Processing Unit), a DPU (Deep learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose computing on Graphics Processing Unit).

[0045] In addition, a second aspect of the present disclosure provides a computing device, comprising a memory and a processor, wherein the memory stores computer readable instructions, and when the computer readable instructions are executed by the processor, the processor implements the method for determining the bit error rate of the optical module during data transmission according to the first aspect of the present disclosure.

[0046] Furthermore, a third aspect of the present disclosure provides a computer readable storage medium having stored thereon computer executable instructions for executing the method for determining the bit error rate of the optical module during data transmission according to the first aspect of the present disclosure.

[0047] In summary, in the method for determining the bit error rate of the optical module during data transmission, the computing device for determining the bit error rate of the optical module during data transmission, and the corresponding computer readable storage medium according to the present disclosure, the control instructions are sent by the central processor to control the computing processing unit or the predetermined data packet is sent by the central processor and the error count of the error counter is obtained by the central processor or the computing processing unit accordingly, so that the error count of the error counter can be accurately determined by means of the data transmission interface of the central processor and the computing processing unit, and the bit error rate can be accurately calculated based on the error count and the predetermined data packet, thereby realizing accurate analysis of the transmission performance of the corresponding optical module.

[0048] The technical solutions described above can be realized by corresponding hardware circuits in addition to being realized in a software manner. In other words, the method for determining the bit error rate of the optical module during data transmission described above can be realized by software stored in a computer-readable storage medium in combination with corresponding hardware components. The computer-readable storage medium has computer-readable program instructions stored thereon for performing various embodiments of the present disclosure. The computer-readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer-readable storage medium can be, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any appropriate combination of the above. More specific examples (non-exhaustive list) of the computer-readable storage medium include a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punched card or a concave-convex structure in a slot, and any appropriate combination of the above. The computer-readable storage medium used herein is not to be interpreted as a transitory signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse through an optical fiber cable), or an electrical signal transmitted through a wire.

[0049] Figure 3 A schematic diagram of a computing device 300 for determining the bit error rate of the optical module during data transmission according to one embodiment of the present disclosure is shown. As can be seen from Figure 3 The computing device 300 for determining the bit error rate of the optical module during data transmission includes a processor (e.g., a central processing unit (CPU)) 310 and a memory 320 coupled to the processor 410. The memory 320 is used to store computer-executable instructions that, when executed, cause the processor 310 to perform the method 200A or the method 200B or the method 200C for determining the bit error rate of the optical module during data transmission in the above embodiments. The processor 310 and the memory 320 are connected to each other through a bus, and an input / output (I / O) interface is also connected to the bus. The computing device 300 for determining the bit error rate of the optical module during data transmission also includes an output unit.

[0050] In addition, the computing device 300 for determining the bit error rate of the optical module during data transmission can also include a plurality of components (e.g., a display, a keyboard, a mouse, a microphone, a speaker, etc.) connected to the I / O interface. Figure 3The computing device 300 for determining the bit error rate of an optical module during data transmission can further include a memory 320 and a processor 310. The memory 320 can be a computer readable storage medium storing computer executable instructions. The processor 310 can be configured to access the memory 320 and implement various embodiments of the method for determining the bit error rate of an optical module during data transmission according to the present disclosure. The computing device 300 for determining the bit error rate of an optical module during data transmission can further include, but not limited to, an input unit, an output unit, a storage unit, and a communication unit. The communication unit allows the computing device 300 for determining the bit error rate of an optical module during data transmission to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0051] At this time, the computer executable instructions stored in the memory 320, when executed, cause the processor 310 to implement the method for determining the bit error rate of an optical module during data transmission according to any one of the various embodiments of the present disclosure. In this way, the method for determining the bit error rate of an optical module during data transmission can be implemented in the form of a computing device for determining the bit error rate of an optical module during data transmission. Figure 2A Alternatively, Figure 2B At this time, the computer executable instructions stored in the memory 320, when executed, cause the processor 310 to implement the method for determining the bit error rate of an optical module during data transmission according to any one of the various embodiments of the present disclosure. In this way, the method for determining the bit error rate of an optical module during data transmission can be implemented in the form of a computing device for determining the bit error rate of an optical module during data transmission.

[0052] In another embodiment, the present disclosure proposes a computer readable storage medium having stored thereon computer executable instructions for implementing the method for determining the bit error rate of an optical module during data transmission in the various embodiments of the present disclosure.

[0053] The present disclosure also proposes a computer program product tangibly stored on a computer readable storage medium and comprising computer executable instructions which, when executed, cause at least one processor to implement the method for determining the bit error rate of an optical module during data transmission in the various embodiments of the present disclosure.

[0054] In general, the various example embodiments of the present disclosure can be implemented in hardware or special-purpose circuits, software, firmware, logic, or any combination thereof. Some aspects can be implemented in hardware, while other aspects can be implemented in firmware or software which can be executed by a controller, microprocessor or other computing device. While various aspects of embodiments of the present disclosure are illustrated or described as block diagrams, flow charts, or using some other pictorial representation, it will be well understood that the blocks, apparatus, systems, techniques or methods described herein can be implemented in, as non-limiting examples, hardware, software, firmware, special-purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.

[0055] Figure 4 A schematic diagram of a computing device 400 for determining the bit error rate of an optical module during data transmission according to another embodiment of the present disclosure is shown. It should be understood that the computing device 400 for determining the bit error rate of an optical module during data transmission can be implemented to implement the method for determining the bit error rate of an optical module during data transmission according to any one of the various embodiments of the present disclosure. Figure 1or the functions of the method 200A or the method 200B or the method 200C in FIG. 2 for determining the bit error rate of the optical module during data transmission. From Figure 4 As can be seen, the computing device 400 for determining the bit error rate of the optical module during data transmission comprises a central processing unit (CPU) 401 (e.g., a processor) that can perform various appropriate actions and processes according to computer program instructions stored in a read-only memory (ROM) 402 or loaded from a storage unit 408 into a random access memory (RAM) 403. Various programs and data required for the operation of the computing device 400 can also be stored in the RAM 403. The CPU 401, the ROM 402, and the RAM 403 are connected to each other through a bus 404. An input / output (I / O) interface 405 is also connected to the bus 404.

[0056] Various components in the computing device 400 for determining the bit error rate of the optical module during data transmission are connected to the I / O interface 405, including an input unit 406, an output unit 407, the storage unit 408 (e.g., a magnetic disk, an optical disk, etc.), and a communication unit 409 (e.g., a network card, a modem, a wireless communication transceiver, etc.). The communication unit 409 allows the computing device 400 for determining the bit error rate of the optical module during data transmission to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0057] The various methods described above, such as the method for determining the bit error rate of the optical module during data transmission, can be performed by the processing unit 401. For example, in some embodiments, the method 200A or the method 200B or the method 200C for determining the bit error rate of the optical module during data transmission can be implemented as a computer software program that is tangibly embodied in a machine-readable medium, such as the storage unit 408. In some embodiments, part or all of the computer program can be loaded and / or installed on the computing device 400 for determining the bit error rate of the optical module during data transmission via the ROM 402 and / or the communication unit 409. When the computer program is loaded into the RAM 403 and executed by the CPU 401, one or more actions or steps in the method 200A or the method 200B or the method 200C described above can be performed, i.e.:

[0058] initializing a high-speed serial computer expansion bus port of the computing processing unit and detecting a hardware connection status;

[0059] resetting an error counter associated with the optical module, in case of successful initialization and normal connection status;

[0060] sending control instructions by the central processing unit to control the computing processing unit or sending predetermined data packets by the central processing unit and obtaining the error count of the error counter by the central processing unit or the computing processing unit accordingly; and

[0061] calculating the bit error rate based on the error count and the predetermined data packets.

[0062] In the method for determining the bit error rate of the optical module when transmitting data according to the present disclosure, sending control instructions by the central processing unit to control the computing processing unit or sending predetermined data packets by the central processing unit and obtaining the error count of the error counter by the central processing unit or the computing processing unit accordingly, so that the error count of the error counter can be accurately determined by means of the data transmission interface of the central processing unit and the computing processing unit, so that the bit error rate can be accurately calculated based on the error count and the predetermined data packets, and accurate analysis of the transmission performance of the corresponding optical module is realized.

[0063] Optionally, in some optional forms according to the present disclosure, when the computer program is loaded into the RAM 403 and executed by the CPU 401, one or more actions or steps in the method 200A or the method 200B or the method 200C described above can also be executed, i.e. saving the error count in the error counter as a log file. Here, the log file at least includes the error count of the error counter of each link, for example, and can also optionally include various parameters associated with the execution of the method for determining the bit error rate of the optical module when transmitting data according to the present disclosure, such as the size of the data packet for each test and the actual running time for each test. Such a log file can be saved in the central processing unit, in the memory associated with the central processing unit, or in the memory associated with the computing processing unit, for example.

[0064] Optionally, in some optional forms according to the present disclosure, calculating the bit error rate based on the error count and the predetermined data packets includes calculating the bit error rate based on the log file and the predetermined data packets. As described above, when the error count in the error counter is saved as a log file, the bit error rate can be calculated based on the log file and the predetermined data packets, for example. Thereby, the optical module can be evaluated retrospectively after each method execution, and thereby the bit error rate when the method for determining the bit error rate of the optical module when transmitting data according to the present disclosure is executed can be traced back at any time point after the execution of the method for determining the bit error rate of the optical module when transmitting data according to the present disclosure, improving the verifiability and checkability of the bit error rate evaluation.

[0065] Optionally, in accordance with some optional forms of the present disclosure, the computing processing units are associated with the optical modules. Optionally, in accordance with some optional forms of the present disclosure, the graphics computing unit is configured as any one of a graphics processor, a tensor processor, a neural network processor, a deep learning processor, an accelerated processor, a general-purpose graphics processor.

[0066] Optionally, in accordance with some optional forms of the present disclosure, initializing the high-speed serial computer expansion bus ports of the computing processing units and detecting hardware connection status comprises: rebooting each computing processing unit and initializing the high-speed serial computer expansion bus ports of the computing processing units. Preferably, in accordance with some optional forms of the present disclosure, the rebooting is configured as a hot reboot.

[0067] Preferably, in accordance with some optional forms of the present disclosure, when the computer program is loaded into the RAM 403 and executed by the CPU 401, one or more actions or steps of the above-described method 200A or method 200B or method 200C can also be performed, i.e. acquiring a predetermined number of execution times of subsequent steps and a size of a data packet sent at each execution. Preferably, in accordance with some optional forms of the present disclosure, the method further comprises: comparing a current number of execution times with the predetermined number of execution times; and continuing execution if the current number of execution times is within the predetermined number of execution times, and terminating execution and saving a log file if the current number of execution times is greater than the predetermined number of execution times. More preferably, in accordance with some optional forms of the present disclosure, the number of execution times is divided into at least two batches in chronological order, and a size of a data packet sent at execution of a later batch is greater than a size of a data packet sent at execution of an earlier batch. Further preferably, in accordance with some optional forms of the present disclosure, calculating the bit error rate based on the error count and the predetermined data packet comprises: calculating a total bit error rate based on the error count at each execution and the predetermined data packet. Still further preferably, in accordance with some optional forms of the present disclosure, when the computer program is loaded into the RAM 403 and executed by the CPU 401, one or more actions or steps of the above-described method 200A or method 200B or method 200C can also be performed, i.e. terminating execution of the method if the bit error rate is higher than a predetermined threshold.

[0068] Preferably, in accordance with some optional forms of the present disclosure, the high-speed serial computer expansion bus technology comprises a sixth-generation high-speed serial computer expansion bus technology.

[0069] In summary, in the method for determining the bit error rate of an optical module during data transmission, the computing device for determining the bit error rate of an optical module during data transmission, and the corresponding computer readable storage medium according to the present disclosure, the control instruction is sent by the central processor to control the computing processing unit or the predetermined data packet is sent by the central processor and the error count of the error counter is obtained by the central processor or the computing processing unit accordingly, so that the error count of the error counter can be accurately determined by means of the high-speed serial computer expansion bus technology data transmission interface of the central processor or the computing processing unit, and the bit error rate can be accurately calculated based on the error count and the predetermined data packet, thereby realizing accurate analysis of the transmission performance of the corresponding optical module.

[0070] Although the various example embodiments of the present disclosure described above can be implemented in hardware or special-purpose circuitry, the above-described computing device for determining the bit error rate of the optical module during data transmission can be implemented in the form of hardware or in the form of software, because in the 1990s, it can be easily determined whether a technical improvement belongs to an improvement in hardware (for example, an improvement in circuit structure such as diodes, transistors, switches, etc.) or an improvement in software (for example, an improvement in method flow). However, with the continuous development of technology, many improvements in method flow today can almost all be implemented by programming the improved method flow into hardware circuitry, in other words, by programming different programs for hardware circuitry to obtain the corresponding hardware circuit structure, that is, the change of hardware circuit structure is realized, so such an improvement in method flow can also be regarded as a direct improvement in hardware circuit structure. Therefore, it cannot be said that an improvement in method flow cannot be implemented by hardware entity modules. For example, a programmable logic device (Programmable Logic Device: PLD) (such as a field programmable gate array (Field Programmable Gate Array: FPGA)) is an integrated circuit whose logic function is determined by the user programming the device. A digital system is "integrated" on a programmable logic device by the designer programming it himself, without having to ask the chip manufacturer to design and manufacture a special integrated circuit chip.Moreover, nowadays instead of making integrated circuit chips by hand, this programming is mostly implemented by using "logic compiler" software, which is similar to the software compiler used when developing programs, and the original code before compilation is also written in a specific programming language, which is called hardware description language (HDL), and there are many kinds of HDLs, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc., and the most commonly used are VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should be aware that only by making slight logical programming of the method flow using the above-mentioned hardware description languages and programming into integrated circuits, the hardware circuit implementing the logical method flow can be easily obtained.

[0071] The computer readable program instructions or computer program product for executing the various embodiments of the present disclosure can also be stored in the cloud, and when needed, the user can access the computer readable program instructions stored in the cloud through mobile Internet, fixed network or other network to implement the technical solutions disclosed according to the various embodiments of the present disclosure.

[0072] The above is only optional embodiments of the present disclosure, and is not used to limit the embodiments of the present disclosure. Those skilled in the art can make various changes and modifications to the embodiments of the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present disclosure shall be included in the protection scope of the embodiments of the present disclosure.

[0073] While embodiments of the disclosure have been described with reference to several particular embodiments, it will be understood that embodiments of the disclosure are not limited to the particular embodiments disclosed. Embodiments of the disclosure are intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the claims will include all such modifications and equivalents.

Claims

1. A method for determining the bit error rate of an optical module during data transmission, applied to an optical module based on high-speed serial computer extended bus technology, characterized in that, The method includes: Initialize the high-speed serial computer expansion bus port of the computing processing unit and detect the hardware connection status; Once initialization is complete and the connection is normal, reset the error counter associated with the optical module; The central processing unit (CPU) sends control commands to control the computing processing unit (CPU), or the CPU sends predetermined data packets and accordingly, the CPU or the CPU obtains the error count of the error counter at the receiving end, wherein the CPU and the CPU are located on the same server or on different servers; and The bit error rate is calculated based on the error count and the predetermined data packets.

2. The method according to claim 1, characterized in that, The method further includes: Save the error count in the error counter as a log file.

3. The method according to claim 2, characterized in that, Calculating the bit error rate based on the error count and the predetermined data packets includes: The bit error rate is calculated based on the log file and the predetermined data packets.

4. The method according to claim 1, characterized in that, The computing processing unit is associated with the optical module.

5. The method according to claim 1, characterized in that, The computing processing unit is configured as any one of a graphics processor, tensor processor, neural network processor, deep learning processor, accelerator processor, or general-purpose graphics processor.

6. The method according to claim 1, characterized in that, Initializing the high-speed serial computer expansion bus port of the computing processing unit and detecting the hardware connection status includes: Restart each computing unit and initialize the high-speed serial computer expansion bus port of the computing unit.

7. The method according to claim 6, characterized in that, The restart is configured as a hot restart.

8. The method according to claim 1, characterized in that, Before initializing the high-speed serial computer expansion bus port of the computing processing unit and detecting the hardware connection status, the following steps are also included: Obtain the predetermined number of executions for subsequent steps and the size of the data packets sent during each execution.

9. The method according to claim 8, characterized in that, The method further includes: Compare the current execution count with the predetermined execution count; and If the current execution count is within the predetermined execution count, continue execution; if the current execution count is greater than the predetermined execution count, terminate execution and save the log file.

10. The method according to claim 8, characterized in that, The number of executions is divided into at least two batches according to the time sequence, and the size of the data packet sent when the later batch is executed is greater than the size of the data packet sent when the previous batch is executed.

11. The method according to any one of claims 8 to 10, characterized in that, Calculating the bit error rate based on the error count and the predetermined data packets includes: The total bit error rate is calculated based on the error count and the predetermined data packets at each execution.

12. The method according to any one of claims 8 to 10, characterized in that, The method further includes: The execution of the method is terminated when the bit error rate exceeds a predetermined threshold.

13. The method according to claim 1, characterized in that, The high-speed serial computer expansion bus technology includes the sixth-generation high-speed serial computer expansion bus technology.

14. The method according to claim 1, characterized in that, Controlling the computing processing unit to send a predetermined data packet further includes: The computing processing unit is controlled to send predetermined data packets in a host-to-device (H2D) manner.

15. A computing device comprising a memory and a processor, the memory storing computer-readable instructions which, when executed by the processor, cause the processor to perform a method according to any one of claims 1 to 14 for determining the bit error rate of an optical module during data transmission.

16. A computer-readable storage medium having computer-executable instructions stored thereon, the computer-executable instructions being used to perform a method for determining the bit error rate of an optical module when transmitting data according to any one of claims 1 to 14.

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