High conduction and low loss IGBT device structure and preparation method thereof

Abstract

The present invention discloses a high-conduction low-loss IGBT device structure and a preparation method thereof, wherein the IGBT device structure comprises an emitter metal layer, a dielectric layer, an N+ source region, a P-type base region, a drift region, a substrate and a collector layer arranged in sequence from top to bottom, and also comprises a trench gate penetrating the N+ source region and the P-type base region from top to bottom and extending into the drift region; wherein an insulating region is arranged between adjacent trench gates in the drift region, and a plurality of N-type doped regions are arranged in the substrate or the collector layer. The high-conduction low-loss IGBT device structure of the present invention and a preparation method thereof can reduce the on-state voltage drop Vcesat of the device, improve the on-state efficiency, reduce the tail current, and reduce the turn-off loss Eoff.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a high-conductance and low-loss IGBT device structure and a preparation method thereof. Background Art

[0002] IGBT (Insulated Gate Bipolar Transistor), insulated gate bipolar transistor, is a composite fully controlled voltage-driven power semiconductor device composed of BJT (bipolar transistor) and MOS (insulated gate field effect transistor), which has the advantages of both MOSFET's high input impedance and GTR's low on-state voltage drop. GTR has low saturation voltage drop and high current density, but high driving current; MOSFET has low driving power and fast switching speed, but high on-state voltage drop and low current density. IGBT combines the advantages of the above two devices, with low driving power and low saturation voltage drop.

[0003] Insulated gate bipolar transistors (IGBTs) are widely used in aerospace, new energy vehicles, industrial control, white appliances and other fields due to their advantages such as low driving power, fast switching speed and low switching loss. Therefore, in electronic circuit applications, high conduction and low loss IGBT devices are crucial.

[0004] However, there is a contradictory relationship between the on-state voltage drop Vce and the turn-off loss Eoff of the IGBT device, so it becomes particularly critical to balance the relationship between the on-state voltage drop Vce and the turn-off loss Eoff of the IGBT device.

[0005] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0006] The object of the present invention is to provide a high-conduction and low-loss IGBT device structure and a preparation method thereof, which can reduce the on-state voltage drop Vcesat of the device, improve the on-state efficiency, reduce the tail current, and reduce the turn-off loss Eoff.

[0007] In order to achieve the above-mentioned object, a specific embodiment of the present invention provides a high-conductance and low-loss IGBT device structure, comprising an emitter metal layer, a dielectric layer, an N+ source region, a P-type base region, a drift region, a substrate and a collector layer arranged in sequence from top to bottom, and also comprising a trench gate penetrating the N+ source region and the P-type base region from top to bottom and extending into the drift region;

[0008] Wherein, an insulating region is arranged between adjacent trench gates in the drift region, and a plurality of N-type doped regions are arranged in the substrate or the collector layer.

[0009] In one or more embodiments of the present invention, the insulating region is disposed on a side of the drift region close to the substrate.

[0010] In one or more embodiments of the present invention, the distance between the insulating regions in the first direction is less than or equal to the distance between adjacent trench gates in the first direction, and the first direction is defined as the arrangement direction of the trench gates.

[0011] In one or more embodiments of the present invention, the number of the N-type doping regions is consistent with the number of the insulating regions, and one N-type doping region is provided corresponding to one insulating region.

[0012] In one or more embodiments of the present invention, a projection of the insulating region in a thickness direction of the device structure coincides with the N-type doping region.

[0013] In one or more embodiments of the present invention, the N-type doped region is formed on a surface of the substrate facing away from the drift region; the N-type doped region is formed by epitaxial growth on the surface of the substrate.

[0014] In one or more embodiments of the present invention, the N-type doped region is formed in the substrate and is located on a side of the substrate away from the drift region; the N-type doped region is formed by ion implantation into the substrate.

[0015] In one or more embodiments of the present invention, a SiO2 layer is formed in the insulating region.

[0016] In one or more embodiments of the present invention, the emitter metal layer partially penetrates the dielectric layer and the N+ source region, and extends into the P-type base region.

[0017] A specific embodiment of the present invention provides a method for preparing a high-conductance and low-loss IGBT device structure, comprising:

[0018] providing a substrate having a first surface and a second surface opposite to each other;

[0019] forming an insulating layer on the first surface of the substrate, and etching the insulating layer to form insulating regions arranged at intervals;

[0020] Forming a drift region on the first surface of the substrate, forming a trench gate, a P-type base region and an N+ source region in the drift region, and forming a dielectric layer and an emitter metal layer on the drift region;

[0021] forming N-type doped regions spaced apart on the second surface of the substrate;

[0022] A collector layer covering the N-type doping region is formed on the second surface of the substrate.

[0023] Compared with the prior art, the high-conduction and low-loss IGBT device structure and preparation method of the present invention, through the setting of the insulating region, blocks the holes (carriers) flowing thereto, reduces the flow of holes from the P-type base region, reduces the on-state voltage drop Vcesat of the device, and improves the on-state efficiency of the IGBT device.

[0024] The high-conduction, low-loss IGBT device structure and preparation method thereof of the present invention provide an N-type doping region on one side of the collector layer to provide an extraction path for holes (carriers) when turned off, thereby reducing tail current and lowering turn-off loss.

[0025] The high-conduction and low-loss IGBT device structure and the preparation method thereof of the present invention balance the relationship between the on-state voltage drop Vce and the off-state loss Eoff, thereby improving the performance of the IGBT device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 A schematic diagram of a high-conductance, low-loss IGBT device structure in one embodiment of the present invention;

[0028] Figure 2 This is a process flow chart of a method for preparing a high-conductance, low-loss IGBT device structure in one embodiment of the present invention;

[0029] Figure 3a-3e This is a process step diagram of a method for preparing a high-conductance, low-loss IGBT device structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0031] As mentioned in the background technology, IGBT (Insulated Gate Bipolar Transistor), an insulated gate bipolar transistor, is a composite fully controlled voltage-driven power semiconductor device composed of BJT (bipolar transistor) and MOS (insulated gate field effect transistor), which has the advantages of both MOSFET's high input impedance and GTR's low on-state voltage drop. GTR has a low saturation voltage drop and a large current density, but a large driving current; MOSFET has a very small driving power and a fast switching speed, but a large on-state voltage drop and a low current density. IGBT combines the advantages of the above two devices, with low driving power and low saturation voltage drop. Insulated gate bipolar transistor (IGBT) is widely used in aerospace, new energy vehicles, industrial control, white appliances and other fields due to its advantages such as low driving power, fast switching speed and low switching loss. Therefore, in electronic circuit applications, high-conductivity, low-loss IGBT devices are crucial.

[0032] However, there is a contradictory relationship between the on-state voltage drop Vce and the turn-off loss Eoff of the IGBT device, so it becomes particularly critical to balance the relationship between the on-state voltage drop Vce and the turn-off loss Eoff of the IGBT device.

[0033] Based on this, the present application provides a high-conduction, low-loss IGBT device structure and a preparation method thereof. By setting an insulating region, holes (carriers) are blocked after flowing to this region, reducing the holes from the P-type base region, reducing the device's on-state voltage drop Vcesat, and improving the on-state efficiency of the IGBT device; by setting an N-type doped region on one side of the collector layer, an extraction path is provided for holes (carriers) when the device is turned off, which can reduce the tail current and reduce the turn-off loss. The present application provides a high-conduction, low-loss IGBT device structure and a preparation method thereof, which can reduce the device's on-state voltage drop Vcesat, improve the conduction efficiency, and reduce the tail current and turn-off loss Eoff.

[0034] like Figure 1 As shown, the high conduction and low loss IGBT device structure in one embodiment of the present invention includes an emitter metal layer 10, a dielectric layer 20, an N+ source region 30, a P-type base region 40, a drift region 50, a substrate 60 and a collector layer 70 arranged in sequence from top to bottom, and also includes a trench gate 80 that penetrates the N+ source region 30 and the P-type base region 40 from top to bottom and extends into the drift region 50. Among them, an insulating region 91 is arranged between adjacent trench gates 80 in the drift region 50. A plurality of N-type doped regions 92 are arranged in the substrate 60 or the collector layer 70.

[0035] In the above technical solution, the setting of the insulating region 91 blocks holes (carriers) flowing there, reduces holes flowing away from the P-type base region 40, inhibits the recombination attenuation of holes and electrons, and equivalently increases the conductor to reduce the on-state voltage drop Vcesat of the device, thereby improving the on-state efficiency of the IGBT device. The setting of the N-type doping region 92 provides an extraction path for holes (carriers) when turning off, which can reduce the tail current and reduce the turn-off loss.

[0036] Specifically, in a preferred embodiment, the insulating region 91 is disposed on the side of the drift region 50 close to the substrate 60. The distance between the insulating regions 91 in the first direction is less than or equal to the distance between adjacent trench gates 80 in the first direction. This design can optimize the voltage drop loss. The first direction is defined as the arrangement direction of the trench gates 80, that is, Figure 1 The insulating region 91 is formed with SiO 2 The layer, for example, can be made of SiO 2 The arrangement of layers forms an insulating region 91 .

[0037] Specifically, in a preferred embodiment, the number of N-type doping regions 92 is consistent with the number of insulating regions 91, and one N-type doping region 92 is provided corresponding to one insulating region 91. More preferably, the projection of the insulating region 91 in the thickness direction of the device structure overlaps with the N-type doping region 92.

[0038] In one embodiment of the present application, the N-type doping region 92 is formed on a surface of the substrate 60 that is away from the drift region 50 . The N-type doping region 92 is formed by epitaxial growth on the surface of the substrate 60 .

[0039] In another embodiment of the present application, the N-type doping region 92 is formed in the substrate 60 and is located on a side of the substrate 60 away from the drift region 50 . The N-type doping region 92 may be formed by performing ion implantation into the substrate 60 .

[0040] In the embodiment of the present application, the N+ source region 30 and the P-type base region 40 are arranged in the drift region 50, and the dielectric layer 20 and the emitter metal layer 10 are arranged on the drift region 50. The emitter metal layer 10 partially penetrates the dielectric layer 20 and the N+ source region 30, and extends into the P-type base region 40. Of course, in other embodiments, the arrangement of the N+ source region 30, the P-type base region 40, the drift region 50, the dielectric layer 20 and the emitter metal layer 10 can also be the arrangement of IGBT devices in other prior arts, because it is not the focus of the present application, and the present application does not limit this.

[0041] refer to Figure 2 As shown, a specific embodiment of the present invention also provides a method for preparing a high-conductance and low-loss IGBT device structure, comprising the following steps:

[0042] S1: providing a substrate having a first surface and a second surface opposite to each other, forming an insulating layer on the first surface of the substrate, and etching the insulating layer to form insulating regions arranged at intervals.

[0043] Exemplary, reference Figure 3a and Figure 3b As shown, a substrate 60 is provided. The substrate 60 is preferably a silicon substrate, and the substrate 60 has a first surface 60a and a second surface 60b arranged opposite to each other. A layer of SiO is grown on the first surface 60a of the substrate 60. 2 The insulating layer 90 is etched through a mask to obtain segmented insulating regions 91 arranged at intervals. The insulating regions 91 retained on the substrate 60 should be located between adjacent polysilicon trench gates 80 to be formed subsequently.

[0044] S2: forming a drift region on the first surface of the substrate, forming a trench gate, a P-type base region and an N+ source region in the drift region, and forming a dielectric layer and an emitter metal layer on the drift region.

[0045] Exemplary, reference Figure 3c and Figure 3d As shown, a Si layer is epitaxially grown on the first surface 60a of the substrate 60 to form a drift region 50. The Si layer should have a certain depth so that some functional regions of the IGBT device can be formed in the drift region 50 in the next process. Then, a trench gate 80, a P-type base region 40 and an N+ source region 30 are formed in the drift region 50 using existing technologies (such as trench etching / filling; P-type base region / N+ source region formation; ILD-dielectric layer deposition / CT etching / metal deposition), and a dielectric layer 20 and an emitter metal layer 10 are formed on the drift region 50. Since the above processes can all adopt existing technologies and are not the innovation points of the present application, the present application will not elaborate on them again.

[0046] S3: forming N-type doped regions spaced apart on the second surface of the substrate.

[0047] Exemplary, reference Figure 3e As shown, the mask used to form the segmented insulating region 91 in step S1 is used as a shield, and segmented N-type doping regions 92 arranged at intervals are formed by epitaxial growth on the second surface 60b of the substrate 60. Since the mask used is the same, the number of segmented N-type doping regions 92 formed is the same as that of the segmented insulating region 91 and they are arranged one-to-one.

[0048] Alternatively, the mask used to form the segmented insulating region 91 in step S1 can be used as a shield, and ion implantation can be performed on the area of ​​the second surface 60b of the substrate 60 that is not shielded by the mask, to form the segmented N-type doping regions 92 arranged at intervals. Similarly, since the same mask is used, the number of segmented N-type doping regions 92 formed is the same as that of the segmented insulating region 91 and they are arranged one-to-one.

[0049] S4: forming a collector layer covering the N-type doped region on the second surface of the substrate.

[0050] Exemplary, reference Figure 1 As shown, collector implantation is performed on the second surface 60 b of the substrate 60 to form a collector layer 70 covering the N-type doping region 92 .

[0051] Compared with the prior art, the high-conduction and low-loss IGBT device structure and preparation method of the present invention, through the setting of the insulating region, blocks the holes (carriers) flowing thereto, reduces the flow of holes from the P-type base region, reduces the on-state voltage drop Vcesat of the device, and improves the on-state efficiency of the IGBT device.

[0052] The high-conduction, low-loss IGBT device structure and preparation method thereof of the present invention provide an N-type doping region on one side of the collector layer to provide an extraction path for holes (carriers) when turned off, thereby reducing tail current and lowering turn-off loss.

[0053] The high-conduction and low-loss IGBT device structure and the preparation method thereof of the present invention balance the relationship between the on-state voltage drop Vce and the off-state loss Eoff, thereby improving the performance of the IGBT device.

[0054] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0055] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A high conduction and low loss IGBT device structure, characterized in that: It includes an emitter metal layer, a dielectric layer, an N+ source region, a P-type base region, a drift region, a substrate and a collector layer arranged in sequence from top to bottom, and also includes a trench gate that penetrates the N+ source region and the P-type base region from top to bottom and extends into the drift region; Wherein, an insulating region is provided between adjacent trench gates in the drift region, and a plurality of N-type doped regions are provided in the substrate or the collector layer; One of the N-type doped regions is arranged corresponding to one of the insulating regions; The projection of the insulating region in the thickness direction of the device structure coincides with the N-type doping region.

2. The high conduction and low loss IGBT device structure according to claim 1, characterized in that: The insulating region is arranged on a side of the drift region close to the substrate.

3. The high conduction and low loss IGBT device structure according to claim 1, characterized in that: The distance between the insulating regions in a first direction is less than or equal to the distance between adjacent trench gates in the first direction, and the first direction is defined as an arrangement direction of the trench gates.

4. The high conduction and low loss IGBT device structure according to claim 1, characterized in that: The number of the N-type doping regions is consistent with the number of the insulating regions.

5. The high conduction and low loss IGBT device structure according to claim 1, characterized in that: The N-type doped region is formed on a surface of the substrate facing away from the drift region; The N-type doped region is formed by epitaxial growth on the surface of the substrate.

6. The high conduction and low loss IGBT device structure according to claim 1, characterized in that: The N-type doped region is formed in the substrate and is located on a side of the substrate away from the drift region; The N-type doping region is formed by implanting ions into the substrate.

7. The high conduction and low loss IGBT device structure according to claim 1, characterized in that: A SiO2 layer is formed in the insulating region.

8. The high conduction and low loss IGBT device structure according to claim 1, characterized in that: The emitter metal layer partially penetrates the dielectric layer and the N+ source region, and extends into the P-type base region.

9. A method for preparing a high-conductance, low-loss IGBT device structure according to any one of claims 1 to 8, characterized in that: include: providing a substrate having a first surface and a second surface opposite to each other; forming an insulating layer on the first surface of the substrate, and etching the insulating layer to form insulating regions arranged at intervals; Forming a drift region on the first surface of the substrate, forming a trench gate, a P-type base region and an N+ source region in the drift region, and forming a dielectric layer and an emitter metal layer on the drift region; forming N-type doped regions spaced apart on the second surface of the substrate; A collector layer covering the N-type doping region is formed on the second surface of the substrate.

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