Instruction processing method, device, equipment and storage medium

Abstract

The present application discloses an instruction processing method, apparatus, device and storage medium, and belongs to the field of computer technology. The method processes instructions based on an address stack, wherein the address stack includes a first sub-stack and a second sub-stack, wherein the target address of the first sub-stack is obtained based on the predicted result of the instruction, and the target address of the second sub-stack is obtained based on the submitted result of the instruction, and comprises: obtaining the predicted result of the operation instruction, wherein the predicted result indicates the next instruction predicted to be executed after the operation instruction; determining the processing operation on the first sub-stack according to the predicted result; performing the processing operation on the target address corresponding to the predicted result in the first sub-stack according to the write pointer of the first sub-stack, wherein the write pointer of the first sub-stack is restricted from rolling back during the execution of the processing operation. The first sub-stack and the second sub-stack are located in the same address stack, and only one stack structure needs to be maintained, with low maintenance overhead. The rollback of the write pointer of the first sub-stack is restricted to ensure the address integrity of the first sub-stack.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to an instruction processing method, apparatus, device, and storage medium. Background Art

[0002] In the field of computer technology, pipeline technology can be used to process multiple instructions to be executed. Pipeline technology includes the instruction fetch stage, the decode stage, and the execution stage. When the first instruction passes through the instruction fetch stage and reaches the decode stage, the second instruction can be fetched, thereby achieving pipeline execution of multiple instructions and improving the processing efficiency of multiple instructions.

[0003] During pipeline processing, the next instruction to be processed must be predicted. For example, if the previously processed instruction is a conditional branch instruction, since conditional branches have two branches, the next instructions corresponding to each branch are different. In this case, the next instruction corresponding to the conditional branch instruction must be predicted before the conditional branch instruction is completed, and the predicted next instruction can be evaluated in advance.

[0004] In some cases, after predicting the next instruction, the target address of the instruction is determined based on the predicted next instruction, and the target addresses are counted using a stack, so that the instruction jump is implemented based on the counted target addresses. Therefore, there is an urgent need for an instruction processing method that can count the target addresses when predicting instructions. Summary of the Invention

[0005] The embodiments of the present application provide an instruction processing method, apparatus, device, and storage medium, which can be used to count target addresses when predicting instructions. The technical solution is as follows:

[0006] In one aspect, an embodiment of the present application provides an instruction processing method for processing an instruction based on an address stack, the address stack including a first sub-stack and a second sub-stack, the target address in the first sub-stack being obtained based on a prediction result of the instruction, and the target address in the second sub-stack being obtained based on a submission result of the instruction, the method comprising:

[0007] Obtaining a prediction result of an operation instruction, the prediction result indicating a next instruction predicted to be executed after the operation instruction;

[0008] determining a processing operation on the first sub-stack according to the prediction result;

[0009] According to the write pointer of the first sub-stack, the processing operation is performed on the target address corresponding to the prediction result in the first sub-stack, and the write pointer of the first sub-stack limits rollback during the execution of the processing operation. The write pointer of the first sub-stack is used to correct the disordered part caused by the execution of the processing operation in the first sub-stack when it is detected that the prediction result is not successfully predicted.

[0010] In a possible implementation, determining a processing operation on the first sub-stack according to the prediction result includes:

[0011] If the prediction result indicates that the next instruction is a call instruction, determining that the processing operation includes the push operation, the push operation is used to push a target address corresponding to the call instruction into the first sub-stack, and the call instruction is used to call any program;

[0012] Alternatively, when the prediction result indicates that the next instruction is a return instruction, it is determined that the processing operation includes a pop operation corresponding to the executed push operation, and the pop operation is used to pop the target address corresponding to the return instruction in the first sub-stack, and the return instruction is used to return after completing the call of any program.

[0013] In a possible implementation, performing the processing operation on the target address corresponding to the prediction result in the first sub-stack according to the write pointer of the first sub-stack includes:

[0014] In a case where the processing operation includes a push operation, pushing a target address corresponding to the prediction result into the first sub-stack according to a write pointer of the first sub-stack, and advancing the write pointer of the first sub-stack when the target address is pushed;

[0015] Alternatively, in a case where the processing operation includes a pop operation corresponding to a push operation that has been executed, the target address corresponding to the prediction result is determined among the target addresses pushed into the first sub-stack based on the write pointer of the first sub-stack, and the determined target address is popped out, and the write pointer of the first sub-stack remains in place when the target address is popped out.

[0016] In a possible implementation, determining, according to the write pointer of the first sub-stack, the target address corresponding to the prediction result from the target addresses pushed into the first sub-stack includes:

[0017] Determining a historical instruction corresponding to the prediction result, wherein the prediction result indicates that any program call ends, and the historical instruction is used to call the any program;

[0018] Determine a write pointer of the historical instruction, where the write pointer is used to push a target address corresponding to the historical instruction into the first sub-stack;

[0019] The target address corresponding to the historical instruction is searched from at least one target address pushed into the first sub-stack according to the write pointer of the historical instruction to obtain the target address corresponding to the prediction result.

[0020] In a possible implementation, searching, according to the write pointer of the historical instruction, for a target address corresponding to the historical instruction from at least one target address pushed into the first sub-stack includes:

[0021] Acquire a link relationship between a write pointer and a first top pointer of the first substack;

[0022] According to the link relationship between the write pointer and the first stack top pointer, searching for the first stack top pointer corresponding to the write pointer of the historical instruction;

[0023] The target address indicated by the first stack top pointer found is determined as the target address corresponding to the historical instruction.

[0024] In a possible implementation, after the determined target address is popped out, the method further includes:

[0025] Roll back the first top pointer of the first sub-stack according to the position of the popped target address.

[0026] In a possible implementation, after pushing the target address corresponding to the prediction result into the first sub-stack according to the write pointer of the first sub-stack, the method further includes:

[0027] A link relationship is established between the write pointer and a first top pointer of the first sub-stack, where the link relationship is used to determine a target address corresponding to the prediction result from the first sub-stack.

[0028] In a possible implementation, after pushing the target address corresponding to the prediction result into the first sub-stack according to the write pointer of the first sub-stack, the method further includes:

[0029] determining a candidate cell in at least one memory cell included in the second sub-stack;

[0030] When the prediction result is submitted, the target address corresponding to the prediction result is stored in the candidate unit.

[0031] In a possible implementation, the method further includes:

[0032] Obtaining an execution result corresponding to the operation instruction, where the execution result indicates a next instruction to be executed after the operation instruction;

[0033] In a case where the execution result and the prediction result are different, it is determined that the prediction result is not successfully predicted, or in a case where the execution result and the prediction result are the same, it is determined that the prediction result is successfully predicted.

[0034] In a possible implementation, the method further includes:

[0035] restoring a write pointer of the first substack according to the out-of-order portion of the first substack;

[0036] The out-of-order portion of the first sub-stack is corrected according to the restored write pointer.

[0037] In another aspect, an instruction processing apparatus is provided, the apparatus being configured to process instructions based on an address stack, the address stack comprising a first sub-stack and a second sub-stack, the target address in the first sub-stack being obtained based on a prediction result of the instruction, and the target address in the second sub-stack being obtained based on a commit result of the instruction, the apparatus comprising:

[0038] an acquisition module, configured to acquire a prediction result of an operation instruction, wherein the prediction result indicates a next instruction predicted to be executed after the operation instruction;

[0039] a determining module, configured to determine a processing operation on the first sub-stack according to the prediction result;

[0040] A processing module is used to perform the processing operation on the target address corresponding to the prediction result in the first sub-stack according to the write pointer of the first sub-stack, the write pointer of the first sub-stack limits rollback during the execution of the processing operation, and the write pointer of the first sub-stack is used to correct the disordered part caused by the execution of the processing operation in the first sub-stack when it is detected that the prediction result is not successfully predicted.

[0041] In one possible implementation, the determination module is used to determine, when the prediction result indicates that the next instruction is a call instruction, that the processing operation includes the push operation, and the push operation is used to push the target address corresponding to the call instruction into the first sub-stack, and the call instruction is used to call any program; or, when the prediction result indicates that the next instruction is a return instruction, determine that the processing operation includes a pop operation corresponding to the executed push operation, and the pop operation is used to pop the target address corresponding to the return instruction from the first sub-stack, and the return instruction is used to return after the call of any program is completed.

[0042] In one possible implementation, the processing module is used to, when the processing operation includes a push operation, push the target address corresponding to the prediction result into the first sub-stack according to the write pointer of the first sub-stack, and the write pointer of the first sub-stack advances when the target address is pushed; or, when the processing operation includes a pop operation corresponding to the executed push operation, determine the target address corresponding to the prediction result in the target addresses pushed into the first sub-stack according to the write pointer of the first sub-stack, pop up the determined target address, and the write pointer of the first sub-stack remains in place when the target address is popped.

[0043] In one possible implementation, the processing module is used to determine the historical instruction corresponding to the prediction result, where the prediction result indicates the end of any program call, and the historical instruction is used to call the any program; determine the write pointer of the historical instruction, where the write pointer is used to push the target address corresponding to the historical instruction into the first sub-stack; and search for the target address corresponding to the historical instruction from at least one target address pushed into the first sub-stack according to the write pointer of the historical instruction to obtain the target address corresponding to the prediction result.

[0044] In one possible implementation, the processing module is used to obtain the link relationship between the write pointer and the first top pointer of the first sub-stack; based on the link relationship between the write pointer and the first top pointer, search for the first top pointer corresponding to the write pointer of the historical instruction; and determine the target address indicated by the found first top pointer as the target address corresponding to the historical instruction.

[0045] In a possible implementation, the processing module is further configured to roll back the first top pointer of the first sub-stack according to the position of the popped target address.

[0046] In a possible implementation, the processing module is further configured to establish a link relationship between the write pointer and a first top pointer of the first sub-stack, and the link relationship is used to determine a target address corresponding to the prediction result from the first sub-stack.

[0047] In a possible implementation, the processing module is further configured to determine a candidate unit in at least one memory unit included in the second sub-stack; and when the prediction result is submitted, store a target address corresponding to the prediction result in the candidate unit.

[0048] In one possible implementation, the acquisition module is further used to obtain the execution result corresponding to the operation instruction, and the execution result indicates the next instruction to be executed after the operation instruction; the determination module is further used to determine that the prediction result is not successfully predicted when the execution result and the prediction result are different, or to determine that the prediction result is successfully predicted when the execution result and the prediction result are the same.

[0049] In a possible implementation, the apparatus further includes: a correction module, configured to restore a write pointer of the first substack according to the out-of-order portion of the first substack; and correct the out-of-order portion of the first substack according to the restored write pointer.

[0050] On the other hand, a computer device is provided, comprising a processor and a memory, wherein the memory stores at least one computer program, and the at least one computer program is loaded and executed by the processor so that the computer device implements any of the above-mentioned instruction processing methods.

[0051] On the other hand, a computer-readable storage medium is provided, in which at least one computer program is stored. The at least one computer program is loaded and executed by a processor to enable a computer to implement any of the above-mentioned instruction processing methods.

[0052] In another aspect, a computer program product or computer program is provided, comprising computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform any of the above-described instruction processing methods.

[0053] The technical solutions provided by the embodiments of the present application bring at least the following beneficial effects:

[0054] The first and second substacks reside in the same address stack, requiring the processor to maintain only one stack structure, resulting in low hardware overhead. Because the write pointer is used to push the target address onto the first substack, by restricting the rollback of the first substack's write pointer, newly pushed target addresses based on the write pointer will not overwrite existing target addresses in the first substack, ensuring the address integrity of the first substack. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0056] Figure 1 This is a schematic diagram of an implementation environment provided by an embodiment of the present application;

[0057] Figure 2 This is a flowchart of an instruction processing method provided by an embodiment of the present application;

[0058] Figure 3 This is a schematic diagram of an instruction processing process provided by an embodiment of the present application;

[0059] Figure 4 is a schematic diagram of an address stack provided in an embodiment of the present application;

[0060] Figure 5 is a schematic diagram of another address stack provided in an embodiment of the present application;

[0061] Figure 6 Schematic diagram of another address stack provided in an embodiment of the present application;

[0062] Figure 7 This is a schematic diagram of the structure of an instruction processing device provided in an embodiment of the present application;

[0063] Figure 8 This is a schematic diagram of the structure of a server provided in an embodiment of the present application;

[0064] Figure 9 It is a structural diagram of an instruction processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0065] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0066] This application embodiment provides a method for processing instructions. Figure 1 , which shows a schematic diagram of an implementation environment for the method provided in an embodiment of the present application. The implementation environment may include: a computing device 11. Computing device 11 is installed and runs a processor, which is used to execute the instruction processing method provided in an embodiment of the present application and calculate the target address based on the predicted result of the operation instruction.

[0067] Optionally, the computing device 11 can be any device with a processor installed, such as a terminal, a server, a switch, a router, etc. For example, the terminal can be any electronic product that can interact with the user through one or more methods such as a keyboard, a touchpad, a touch screen, a remote control, voice interaction or a handwriting device, such as a PC (Personal Computer), a mobile phone, a smart phone, a PDA (Personal Digital Assistant), a wearable device, a PPC (Pocket PC), a tablet computer, a smart car machine, a smart TV, a smart speaker, etc. The server can be a single server or a server cluster consisting of multiple servers. Among them, the processor installed in the computing device 11 can be a CPU (Central Processing Unit) or other types of processors.

[0068] Those skilled in the art should understand that the above-mentioned computing device 11 is only an example, and other existing or future devices that are applicable to this application should also be included in the scope of protection of this application and are included here by reference.

[0069] The embodiment of the present application provides an instruction processing method, which can be applied to the above-mentioned instruction prediction method. Figure 1 In the implementation environment shown, the method can be executed by a processor included in the computing device 11. The flowchart of the method is as follows: Figure 2 As shown, it includes steps 201 to 203.

[0070] In step 201 , a prediction result of an operation instruction is obtained, where the prediction result indicates a next instruction predicted to be executed after the operation instruction.

[0071] For example, an operation instruction refers to the instruction currently being executed. The operation instruction can be any type of instruction, including but not limited to data transfer instructions, calculation instructions, program control instructions, input and output instructions, etc. While executing the operation instruction, the processor also predicts the next instruction that may be executed after the operation instruction.

[0072] For example, after decoding an operation instruction, the type of the operation instruction is determined based on the decoding result, so that the next instruction that may be executed after the operation instruction is predicted based on the type, and the next instruction is processed in advance. For example, the advance processing is to fetch the next instruction from the memory so that after the operation instruction is executed, the next instruction does not need to be fetched from the memory again, and the operation after the instruction fetch can be performed directly on the next instruction. The memory is used to store instructions to be executed by the processor. The memory and the processor can be configured in the same computer device, and a communication connection is established between the memory and the processor.

[0073] Optionally, if the type of the operation instruction indicates that the operation instruction is not a branch instruction, since executing the operation instruction will not result in a branch jump, the processor may predict that the next instruction is the instruction following the operation instruction in the first branch in which the operation instruction is located, thereby obtaining a prediction result for the operation instruction. A branch is used to implement program execution, and a branch includes at least one instruction. After the processor sequentially processes at least one instruction in a branch, execution of the program corresponding to the branch is implemented.

[0074] In one possible implementation, when the type indicates that the operation instruction is a branch instruction, since executing the operation instruction will result in a branch jump, the processor first predicts a second branch that may be jumped to after executing the branch instruction, and predicts the next instruction from the second branch. For example, a branch instruction is an instruction in a computer program that allows the computer program to jump to a different branch of code based on a specific condition during execution.

[0075] Optionally, the branch instruction can be an unconditional branch instruction, which means that after execution, the computer program will definitely jump to a different branch. The unconditional branch instruction can be a Jump instruction, which forces the computer program to jump to a specified code label or another branch of the program. Optionally, the branch instruction can also be a conditional branch instruction, which is used to decide whether to execute the branch based on certain conditions. Certain conditions can be the values ​​in the register or the comparison results. Conditional branch instructions include but are not limited to beq (jump if equal), bne (jump if not equal), etc.

[0076] Since branch instructions may jump to different branches, taking a conditional branch instruction as an example, the branch instruction indicates that when A is less than B, function A is called, and when A is not less than B, function B is called. Therefore, the next instruction executed after the branch instruction may be an instruction in the branch that calls function A, or an instruction in the branch that calls function B. In addition, if the processor waits for the branch instruction to be executed and then jumps based on the execution result of the branch instruction, it will be inefficient because the processor cannot process other instructions before the branch instruction is executed. Therefore, for the branch instruction being processed, the processor can predict the jump situation of the branch instruction before the branch instruction is executed, predict the second branch to be executed after the branch instruction, and use the instruction with the earliest execution order in the second branch as the next instruction to be executed after the branch instruction.

[0077] The present embodiment does not limit the process of predicting the second branch executed after the branch instruction. It can be a process of randomly selecting a branch from the branches that the branch instruction may jump to as the second branch. Continuing with the branch instruction in the above embodiment, which indicates that when A is less than B, function A is called, and when A is not less than B, function B is called, the two branches corresponding to the branch instruction are branch A of function A and branch B of function B. The processor randomly selects branch A as the second branch that the branch instruction may jump to.

[0078] In one possible case, the second branch executed after the branch instruction may also be a default result based on experience or implementation environment settings. Taking the branch instruction indicating whether to jump to branch C as an example, the default branch instruction will execute the jump, and the branch to which the branch instruction may jump is determined to be branch C. Alternatively, the default branch instruction will not execute the jump, and the second branch executed after the branch instruction is determined to be the first branch where the branch instruction is located. Optionally, the processor can also be based on the historical jump results of the branch instruction. For example, the branch instruction has also been executed at a historical moment. The processor obtains the historical jump results and determines the branch with the highest execution frequency in the historical jump results as the second branch that may be executed after the branch instruction.

[0079] Regardless of the method used by the processor to predict the second branch that may be executed after the branch is executed, the processor can use the instruction with the highest execution order on the second branch as the next instruction to be executed after the branch instruction to obtain a prediction result. Taking the example of a branch that may be executed for calling function A, the branch includes at least one instruction executed during the call to function A, and the execution order of the instructions is instruction A, instruction B, and instruction C. Instruction A is the first instruction executed during the call to function A. The processor thus determines that the next instruction to be executed after the branch instruction is instruction A, and the obtained prediction result indicates that the next instruction to be executed after the branch instruction is instruction A.

[0080] Optionally, the prediction result may be any information that can indicate the next instruction, including but not limited to the instruction name, instruction identifier, or instruction fetch address, etc. When the prediction result is the instruction fetch address, the prediction result of the operation instruction may also be referred to as the target address of the predicted operation instruction.

[0081] In step 202, a processing operation on the first sub-stack is determined according to the prediction result.

[0082] In one possible scenario, the next instruction indicated by the prediction result may be an indirect jump instruction. The target address of an indirect jump instruction is read from a register or memory location and cannot be directly obtained from the encoding of the indirect jump instruction. The target address refers to the instruction fetch address of the next instruction executed after the indirect jump instruction is executed, including but not limited to the PC (Program Counter) value.

[0083] For example, indirect jump instructions include the call instruction and the return instruction. The call instruction is used to call any program, jumping the program from the calling program where the call instruction is located to the called program. The return instruction returns after calling any program, returning the called program called by the call instruction to the calling program where the call instruction is located. Because calling a program involves two steps, the call and return instructions are processed in pairs, with the call instruction processed first and the return instruction second.

[0084] In one possible case, the processing order of the call instruction and the return instruction is the first-in-last-out principle, that is, the call instruction is processed first, and the return instruction corresponding to the call instruction is processed later. Next, taking the called programs as program A and program B as examples, the paired processing process of the call instruction and the return instruction is explained. First, the call instruction 1 is processed to call program A. During the process of calling program A, it is found that a value in program A needs to be calculated by program B. The processor processes the call instruction 2 to call program B, calculates the value required by program A by executing at least one instruction of program B, ends the call of program B, and returns to program A based on the return instruction 2 corresponding to the call instruction 2. The calculated value is carried in the return process, and program A continues to run program A according to the returned value. After the program A is finished running, the return instruction 1 corresponding to the call instruction 1 is executed to return to the original program where the call instruction 1 is located.

[0085] Based on the above example, we can conclude that the location returned by the return instruction is the location before the call instruction corresponding to the return instruction jumps, that is, the original branch of the calling program where the call instruction is located. In this case, the adjacent instruction arranged after the call instruction in the original branch is the next instruction to be executed when the return instruction jumps back to the calling program and continues to execute the calling program. Therefore, before the call instruction jumps, the adjacent instructions of the call instruction can be counted so that when the return instruction corresponding to the call instruction is executed, the counted adjacent instructions of the call instruction are determined as the next instructions to be executed.

[0086] In some cases, since each instruction must be fetched from memory based on its instruction fetch address, the processor can count the instruction fetch addresses of adjacent instructions, also known as target addresses, when counting adjacent instructions. This allows the subsequent processor to fetch adjacent instructions directly based on the counted instruction fetch addresses. Furthermore, since the processing order of call and return instructions follows the first-in, last-out principle, which is consistent with the data reading and writing principle of the address stack, it is possible to count the target address in the address stack.

[0087] In one possible implementation, the address stack includes a first sub-stack and a second sub-stack. Both the first sub-stack and the second sub-stack are used to count target addresses. The difference is that the target address in the first sub-stack is obtained based on the prediction result of the instruction, that is, after the predicted next instruction is a call instruction or a return instruction, the operation will be performed on the first sub-stack, and the target address in the second sub-stack is obtained based on the submission result of the instruction, that is, the operation will be performed on the second sub-stack only when the submitted next instruction is a call instruction or a return instruction.

[0088] Figure 3 A schematic diagram of the structure of an address stack provided in an embodiment of the present application is shown. Figure 3 The RAS (Return Address Stack) in the instruction indicates the address stack, the Spec RAS (Speculate RAS) indicates the first sub-stack, and the Commit RAS indicates the second sub-stack. In the case where the first sub-stack is processed based on the prediction result and the second sub-stack is processed based on the commit result, in the embodiment of the present application, the processor processes the first sub-stack based on the prediction result of the operation instruction. For example Figure 3 As shown, after determining the predicted result of the operation instruction through branch prediction, the processing operation can be executed to the Spec RAS based on the predicted result. Optionally, the first sub-stack and the second sub-stack can be set based on experience. For example, the address stack includes 32 memory cells, which in some cases can also be called table entries. The first 16 memory cells can be used as the second sub-stack, and the last 16 memory cells can be used as the first sub-stack. The front and back are used to distinguish the time sequence. The later the memory cell, the earlier the data was popped out.

[0089] In one possible case, the processing operation on the first sub-stack includes a Push operation or a Pop operation, for example Figure 3 The processor may determine whether to perform a push operation or a pop operation on the first sub-stack according to the prediction result, and the determination process includes but is not limited to the following.

[0090] Determination process 1: When the prediction result indicates that the next instruction is a call instruction, determining that the processing operation includes a push operation.

[0091] Among them, the push operation is used to push the target address corresponding to the call instruction into the first sub-stack. The embodiments of the present application do not limit the call instructions that may be executed after the operation instruction. The call instruction can be an instruction for calling a program for the first time, or it can be an instruction for calling a program again after the program has been called. The program that has been called can be a program that has returned. For example, the next instruction is call instruction A, and call instruction B has been executed before call instruction A to call function 1. During the execution of the operation instruction, function 1 has been calculated, and the processor has executed the return instruction B corresponding to call instruction B to return. Optionally, the program that has been called can also be a program that has not returned. For example, in the above embodiment, program A is first called through call instruction 1, and then during the running of program A, it is predicted that program B will be called through call instruction 2.

[0092] Regardless of the call instruction's behavior, executing it will always jump from the calling program to the called program. Therefore, the processor records the target address corresponding to the call instruction to clearly indicate the location of the calling program to return to after the program called by the call instruction completes. The processor pushes the target address corresponding to the call instruction onto the first sub-stack to record the target address. Alternatively, the target address corresponding to the call instruction can be the instruction fetch address of an adjacent instruction to the call instruction.

[0093] Determine process 2: When the prediction result indicates that the next instruction is a return instruction, determine that the processing operation includes a pop operation, and the pop operation is used to pop the target address corresponding to the return instruction from the first sub-stack.

[0094] In one possible case, the prediction result may also indicate that the next instruction is a return instruction. For example, the processor has previously executed a call instruction, and it is predicted that the processor will execute the return instruction corresponding to the call instruction to return the program from the called program to the calling program to which the call instruction jumped before. The processor can pop the target address corresponding to the return instruction from the first sub-stack to clarify the location to which the return instruction is to return. The subsequent processor can fetch the adjacent instructions from the memory based on the target address, and execute the adjacent instructions after the prediction result, thereby returning the program from the called program to the calling program. Optionally, the target address corresponding to the return instruction can be the instruction fetch address of the adjacent instruction of the call instruction corresponding to the return instruction.

[0095] In step 203, according to the write pointer of the first sub-stack, a processing operation is performed on the target address corresponding to the prediction result in the first sub-stack. The write pointer of the first sub-stack limits rollback during the execution of the processing operation. The write pointer of the first sub-stack is used to correct the disordered part caused by the execution of the processing operation in the first sub-stack when it is detected that the prediction result is not successfully predicted.

[0096] For example, a pointer indicates a specific memory cell in the stack, and a write pointer of the first substack indicates a memory cell in the first substack into which a target address is to be pushed. After determining a processing operation for the first substack, the processor may determine the memory cell corresponding to the target address based on the write pointer and perform the processing operation on the determined memory cell. For example, the processor may push the target address into the determined memory cell or pop the target address from the determined memory cell.

[0097] Regarding step 202, the processing operation may be a push operation or a pop operation. Next, the processes of performing different processing operations on the first sub-stack according to the write pointer are respectively described.

[0098] Processing process 1: When the processing operation includes a push operation, the target address corresponding to the prediction result is pushed into the first sub-stack according to the write pointer of the first sub-stack, and the write pointer of the first sub-stack advances when the target address is pushed.

[0099] Exemplarily, the processor determines the memory cell indicated by the write pointer of the first sub-stack and pushes the target address corresponding to the call instruction into the memory cell indicated by the write pointer. Since the memory cell indicated by the write pointer is already occupied by the target address after the target address is pushed into the write pointer, the processor further updates the write pointer to control the write pointer to point to a new unoccupied memory cell. For example, the processor increments the value of the write pointer by 1, thereby updating the memory cell indicated by the write pointer to be above the location where the target address was pushed.

[0100] Figure 4 In an address stack provided in an embodiment of the present application, the Spec stack indicates the first sub-stack, the Commit stack indicates the second sub-stack, and the time arrow on the left indicates that the newly pushed target address is located above. Among them, Wp indicates the write pointer, and Sp indicates the first stack top pointer. Figure 4 In the example, the original top of the Spec stack is located at the fourth row of memory cells. After the target address is pushed into the third row of memory cells, the write pointer advances by one and points to the second row of memory cells.

[0101] In one possible implementation, since the address stack is a linear table, push and pop are performed only at one end, and the end where push and pop are performed can be called the top of the stack. Therefore, after the processor pushes the target address corresponding to the call instruction into the first sub-stack, the pushed target address becomes the new top of the first sub-stack. In some cases, the processor may update the first top pointer indicating the top of the stack after pushing the target address. The update process is, for example, to add 1 to the value of the first top pointer. Optionally, the write pointer of the first sub-stack will also advance. Continue with Figure 4 For example, Figure 4 After the target address is pushed into the third row of memory cells, the new top of the stack is updated to the third row of memory cells.

[0102] In one possible scenario, after pushing the target address into the first sub-stack, the processor also establishes a link relationship between the write pointer and the first top pointer of the first sub-stack. The link relationship between the write pointer and the first top pointer describes the location of the target address written based on the write pointer in the first sub-stack, so that when the target address corresponding to the predicted result is subsequently determined from the first sub-stack, the target address corresponding to the predicted result can be found based on the link relationship. The detailed process of finding the target address based on the link relationship can be found in the relevant content of performing the pop operation in the second processing step below, and will not be repeated here.

[0103] Optionally, after pushing the target address into the first sub-stack based on the prediction result, the processor will also determine a candidate unit in at least one memory unit included in the second sub-stack. The candidate unit is indicated based on the second top pointer of the second sub-stack. The second top pointer can be called commit sp in some cases. By determining the candidate unit, the target address corresponding to the prediction result is pre-allocated in the second sub-stack to write into the location therein. Subsequently, when the prediction result is committed, the target address corresponding to the prediction result is stored in the candidate unit.

[0104] In one possible case, since the first substack and the second substack are located in the same address stack, and an address stack includes a push port and a pop port, for the target address to be pushed into the second substack, the processor adopts an internal target address transfer method to move the target address of the first substack to the candidate unit, for example Figure 3 As shown, the target address pushed in Spec RAS is committed to Commit RAS. Figure 4 For example, Figure 4The Push Commit arrow in the figure reflects the movement of the target address. The first and last arrows point to the candidate cells in the second sub-stack and the storage cell in the first sub-stack corresponding to the target address of the prediction result. By moving the target address from the first sub-stack to the second sub-stack, the target address is counted based on the commit result and the memory cells in the first sub-stack are further freed up.

[0105] Alternatively, the target address of the candidate cell pushed into the second sub-stack may be a target address that has not been pushed into the address stack. For example, the target address is pushed into the candidate cell of the second sub-stack according to the write pointer of the second sub-stack. The process of pushing the target address into the second sub-stack is similar to the process of pushing the address into the first sub-stack, and will not be repeated here.

[0106] Processing process 2: When the processing operation includes a pop operation corresponding to the executed push operation, the target address corresponding to the prediction result is determined in the target address pushed into the first sub-stack according to the write pointer of the first sub-stack, and the determined target address is popped out. The write pointer of the first sub-stack remains in place when the target address is popped out.

[0107] Optionally, for the case where the prediction result is a return instruction indicating the end of any program call, and the processing operation is a pop operation, the processor must first determine the target address corresponding to the prediction result from the target address in the first sub-stack. The determination process is, for example: determining the historical instruction corresponding to the prediction result, the historical instruction is used to call any program; determining the write pointer of the historical instruction, the write pointer is used to push the target address corresponding to the historical instruction into the first sub-stack; searching for the target address corresponding to the historical instruction from at least one target address pushed into the first sub-stack according to the write pointer of the historical instruction, to obtain the target address corresponding to the prediction result.

[0108] In one possible case, the target address corresponding to the return instruction is the same as the target address corresponding to the call instruction, and both are the instruction fetch addresses of the adjacent instructions following the call instruction in the original branch where the call instruction is located. In this case, the processor can first determine the call instruction corresponding to the return instruction, and the call instruction is a historical instruction predicted before the return instruction. Optionally, for the case where the return instruction indicates the end of any program call, the return instruction may be located at the end of the code of any program. In this case, the processor can determine any program corresponding to the return instruction based on the code position of the return instruction, search for the call instruction used to call the any program, and obtain the historical instruction corresponding to the return instruction.

[0109] After determining the historical instruction corresponding to the return instruction, the processor can search the first sub-stack for the target address that was pushed into the first sub-stack during the execution of the historical instruction to jump to the program. Because the processor also pushes the target address corresponding to the historical instruction based on the write pointer of the first sub-stack, after determining the write pointer corresponding to the historical instruction, the processor can search the first sub-stack for the target address corresponding to the historical instruction based on the write pointer.

[0110] In processing process one, the processor will establish a link relationship between the write pointer and the first top stack pointer after pushing the target address. Since the historical instruction is a call instruction, when the processor predicts the historical instruction, the processing process is the same as processing process one. The target address will be pushed according to the write pointer, and a link relationship will be established between the write pointer and the first top stack pointer. In this case, the processor can search for the target address based on the link relationship.

[0111] Exemplarily, the search process includes: obtaining the link relationship between the write pointer and the first top pointer of the first sub-stack; based on the link relationship between the write pointer and the first top pointer, searching for the first top pointer corresponding to the write pointer of the historical instruction; and determining the target address indicated by the first top pointer obtained by the search as the target address corresponding to the historical instruction.

[0112] Optionally, the processor can access a storage unit to obtain a stored link relationship, and the storage unit can be a storage unit inside the processor, or a storage unit provided by other modules that establish a communication connection with the processor. After accessing the storage space to obtain the link relationship between the write pointer and the first top-of-stack pointer, the processor searches for the write pointer of the historical instruction in the link relationship, and after hitting the write pointer, determines the first top-of-stack pointer that establishes a link relationship with the hit write pointer as the first top-of-stack pointer corresponding to the write pointer of the historical instruction. The index used by the processor to retrieve the write pointer can be any identification information that can distinguish write pointers at different times, including but not limited to the time when the write pointer is pushed, the name of the write pointer, or the serial number, etc.

[0113] Referring to the introduction in processing operation one, the first top of stack pointer points to the new top of the first sub-stack after the target address is pushed. The new top of stack, that is, the target address corresponding to the historical instruction, is located in the first sub-stack. Therefore, the processor can determine the historical unit indicated by the first top of stack pointer corresponding to the historical instruction, and determine the target address stored in the historical unit as the target address corresponding to the historical instruction.

[0114] In one possible case, the target address may not exist in the history unit, that is, the history unit is an empty unit. If the history instruction corresponding to the return instruction is a predicted and submitted call instruction, refer to the description of processing operation one. In the process of submitting the call instruction, the target address corresponding to the call instruction will also be moved from the first sub-stack to the second sub-stack. In this case, the target address originally stored in the history unit has been moved to the second sub-stack, and the history unit is empty. Based on the absence of the target address in the history unit, the processor can determine that the history instruction has been submitted to the candidate unit determined in the second sub-stack for the history instruction, and determine the target address in the candidate unit as the target address corresponding to the history instruction.

[0115] After determining the target address corresponding to the historical instruction, the processor can pop out the determined target address. In one possible case, if the target address to be popped out is located in the second sub-stack, the processor will pop out the target address corresponding to the predicted result from the second sub-stack. Since the second sub-stack is a sub-stack maintained according to the actual submission result, the write pointer and the second stack top pointer of the second sub-stack will both be rolled back when popping out. In this case, popping out the target address from the second sub-stack includes reading and deleting the target address. The deletion of the target address is based on the rollback of the write pointer of the second sub-stack. For example, after the target address is popped out, the write pointer in the second sub-stack is rolled back. In this case, the target address subsequently pushed into the second sub-stack will overwrite the previously popped out target address according to the write pointer of the rolled back second sub-stack, thereby achieving the effect of deleting the popped out target address.

[0116] For example, if the target address to be popped is located in the first sub-stack, the processor can read the target address corresponding to the predicted result from the first sub-stack, retaining the target address in the first sub-stack. As described in Process 1, after the predicted call instruction is submitted, the processor will move the target address of the first sub-stack to the second sub-stack, and write the target address through an internal transfer of the address stack. Therefore, the processor retains the target address of the first sub-stack.

[0117] In one possible case, retaining the target address in the first sub-stack can be achieved by limiting the rollback of the write pointer of the first sub-stack, for example, by keeping the write pointer in place. Figure 4 For example, Figure 4 In the example, the target address corresponding to the prediction result is the target address stored in the memory cell marked as the top of the stack. After reading the target address from this memory cell, the processor maintains the write pointer at the position above the top of the stack, that is, the second row of memory cells. The target address of the first sub-stack is subsequently pushed into the memory cell above the top of the stack, that is, the second row of memory cells. This does not overwrite the target address stored in the third row of memory cells, thus preventing the target address from being deleted.

[0118] In one possible implementation, because the processor predicts a return instruction that points to a pop operation, even if the processor does not delete the target address, the processor still updates the top of the first sub-stack. The process of the processor adjusting the first top pointer of the first sub-stack includes but is not limited to: retracting the first top pointer of the first sub-stack based on the position of the popped target address.

[0119] If the target address is located in a history unit, the first stack top pointer can be rolled back to the memory unit below the history stack, for example, the first stack top pointer can be rolled back to the unit next to the history unit where the popped target address is located. Figure 5 A schematic diagram of another address stack structure provided in an embodiment of the present application is shown. Figure 5 The address stack structure and Figure 4 The structure of the address stack is similar to that of Figure 4 The introduction of the address stack will not be repeated here. Figure 5 In the example, after popping the target address in the third row of memory cells, the first stack top pointer is rolled back to the fourth row of memory cells, and, Figure 5 In the example, the write pointer of the first sub-stack remains at the second row of memory cells and does not roll back.

[0120] Since the write pointer will not roll back when the target address is popped out, that is, the new target address pushed in again after the target address is popped out will not overwrite the target address of the first sub-stack, thereby ensuring the information integrity of the first sub-stack. The reason for ensuring information integrity is: if the predicted call instruction is mispredicted, the target address pushed into the first sub-stack based on the prediction error will not overwrite the target address that is actually to be popped out. The target address that is actually to be popped out refers to the target address that is to be pushed into the second sub-stack and popped out in the second sub-stack. If the predicted return instruction is mispredicted, the pop operation performed is a pop operation that should not be performed. Since the processor retains the target address in the first sub-stack during the pop process, the erroneously executed pop operation will not result in a reduction in the target address of the first sub-stack, thereby avoiding deletion of the target address that should be stored.

[0121] In one possible scenario, after executing the processing operation on the first sub-stack, the processor further verifies whether the prediction result is successfully predicted. The prediction process includes, but is not limited to: obtaining an execution result corresponding to the operation instruction, the execution result indicating the next instruction to be executed after the operation instruction; if the execution result and the prediction result are different, determining that the prediction result is not successfully predicted, or if the execution result and the prediction result are the same, determining that the prediction result is successfully predicted.

[0122] Optionally, after executing the operation instruction, the processor may determine the next instruction to be executed based on the execution result of the operation instruction and begin executing it. For example, in step 201, if the operation instruction is a branch instruction, the processor determines based on the execution result that A is not less than B, determines that the function to be called is B, and the next instruction to be executed is the call instruction corresponding to function B.

[0123] After obtaining the execution result, the processor compares the predicted result with the execution result. If the predicted result and the execution result match, the prediction is successful. For example, if the predicted next instruction is also the call instruction corresponding to function B, the prediction result is successful. In this case, because the processor has already pre-processed the next instruction based on the prediction result, such as pre-fetching, the processor can directly decode the next instruction.

[0124] In one possible scenario, if the prediction result and the execution result are inconsistent, it means that the prediction result was not successfully predicted. For example, if the predicted next instruction is the call instruction corresponding to function A, but the next instruction actually executed is the call instruction corresponding to function B, the prediction result is not successfully predicted.

[0125] In the event that the prediction result is not successfully predicted, the processing operation executed based on the prediction result is an erroneous processing operation that should not be executed, and the processor will correct the disordered portion in the first sub-stack caused by the processing operation. Since the instruction that continues to be predicted based on the prediction result that failed to predict is also erroneous, the portion of the target address pushed or popped after the prediction result in the first sub-stack is also erroneous. Therefore, the disordered portion of the first sub-stack includes the target address pushed or popped based on the processing operation and the target address pushed or popped after the processing operation is executed. Optionally, the disordered portion of the first sub-stack is indicated based on the first top-of-stack pointer corresponding to the prediction result. The first top-of-stack pointer corresponding to the prediction result refers to the first top-of-stack pointer updated after the first sub-stack is processed based on the prediction result. If the prediction result is a call instruction, the first top-of-stack pointer corresponding to the prediction result is the first top-of-stack pointer that advances after the target address is pushed. If the prediction result is a return instruction, the first top-of-stack pointer corresponding to the prediction result is the first top-of-stack pointer that rolls back. The disordered portion indicated by the first bottom-of-stack pointer is the memory unit located between the top of the first sub-stack and the first top-of-stack pointer corresponding to the prediction result.

[0126] Exemplarily, the process of the processor correcting the out-of-order portion of the first sub-stack includes: restoring the write pointer of the first sub-stack based on the out-of-order portion of the first sub-stack; and correcting the out-of-order portion of the first sub-stack based on the restored write pointer. The processor determines the first top-of-stack pointer corresponding to the write pointer corresponding to the prediction result based on the link relationship between the write pointer and the first top-of-stack pointer, and restores the write pointer of the first sub-stack based on the determined first top-of-stack pointer. If the prediction result is a call instruction, the out-of-order portion includes a target address incorrectly pushed based on the call instruction, and the processor can restore the write pointer of the first sub-stack to a position before the target address corresponding to the call instruction is pushed. The position before the target address corresponding to the call instruction is determined based on the first top-of-stack pointer corresponding to the write pointer. Figure 6 The first sub-stack after repair is shown. The error repaired is the call instruction that was mispredicted. Figure 4 In the example shown, after the error push, the write pointer points to the second row. The processor restores the write pointer of the first substack to the third row, pointing to the target address of the error push. Subsequent target addresses pushed based on the write pointer overwrite the target address, correcting the out-of-order portion. In one possible scenario, in addition to correcting the write pointer, the processor also corrects the top-of-stack pointer of the first substack.

[0127] In one possible implementation, if the prediction result is a return instruction, the out-of-order portion includes the target address that was erroneously popped based on the return instruction. Since the processor rolls back the first top-of-stack pointer and keeps the write pointer in place during the process of popping the target address from the first sub-stack, the target address is saved in the first sub-stack. Therefore, the target address is not missing from the first sub-stack, and the processor can restore the write pointer of the first sub-stack to above the target address that was erroneously popped. Subsequently, during the process of predicting the instruction, the target address can be pushed back into the first sub-stack based on the restored write pointer, thereby correcting the out-of-order portion of the first sub-stack. In one possible scenario, the processor will also correct the first top-of-stack pointer.

[0128] When correcting the first sub-stack, the processor does not need to adjust the target address stored in the first sub-stack. It only needs to restore the write pointer and the first top pointer in the first sub-stack to correct the out-of-order portion, resulting in a simple and efficient correction process. Furthermore, the processor does not reference the target address in the second sub-stack during the correction process, and does not need to wait for the next instruction indicated by the execution result to complete submission. In other words, the first sub-stack can be corrected by pushing or popping the target address of the next instruction in the second sub-stack. Even if the processor follows the principles of sequential issuance, out-of-order execution, and sequential submission when processing instructions, prediction results found during the execution phase that indicate a prediction failure can be corrected during the execution phase by recording the wp and sp of the first sub-stack and the commit sp and commit bp of the second sub-stack, without waiting for the commit phase. This allows for highly timely corrections. Commit bp indicates the bottom pointer of the second sub-stack.

[0129] Alternatively, the processor may Figure 3 The out-of-order portion of the first sub-stack is corrected using the branch execution unit. Figure 3 The branch execution unit can not only recover (repair) the first sub-stack, but also the second sub-stack. For example, in the above embodiment, if the target address corresponding to the mispredicted return instruction is in the second sub-stack, and the operation of popping the return instruction in the second sub-stack is an erroneous operation, then there will also be an out-of-order portion to be repaired in the second sub-stack. The branch execution unit can repair the second sub-stack based on the submission result and the previously executed call and return instructions.

[0130] In summary, in the instruction processing method provided by the embodiment of the present application, the first sub-stack and the second sub-stack are located in the same address stack, the processor only needs to maintain one stack structure, and the hardware overhead is low. By limiting the rollback of the write pointer of the first sub-stack, the deletion of the target address in the first sub-stack is avoided, and the address integrity of the first sub-stack is guaranteed. In the case where the prediction result is not successfully predicted, the first sub-stack can be corrected by restoring the write pointer. The correction process is simple and the correction efficiency is high. In addition, in the process of correcting the first sub-stack, the target address stored in the second sub-stack is not referenced. Therefore, there is no need to wait until the oldest instruction is submitted. The correction can be performed after the corresponding operation is completed in the second sub-stack, thereby realizing the early out-of-order correction of the first sub-stack and improving the working efficiency of the first sub-stack.

[0131] See also Figure 7 An embodiment of the present application provides an instruction processing device for processing instructions based on an address stack, the address stack including a first sub-stack and a second sub-stack, the target address in the first sub-stack being obtained based on a predicted result of the instruction, and the target address in the second sub-stack being obtained based on a submitted result of the instruction, the device including:

[0132] An acquisition module 701 is configured to acquire a prediction result of an operation instruction, where the prediction result indicates a next instruction predicted to be executed after the operation instruction.

[0133] A determination module 702, configured to determine a processing operation on the first sub-stack according to the prediction result;

[0134] The processing module 703 is used to perform a processing operation on the target address corresponding to the prediction result in the first sub-stack according to the write pointer of the first sub-stack. The write pointer of the first sub-stack limits rollback during the execution of the processing operation. The write pointer of the first sub-stack is used to correct the disordered part caused by the execution of the processing operation in the first sub-stack when it is detected that the prediction result is not successfully predicted.

[0135] In one possible implementation, the determination module 702 is used to determine that the processing operation includes a push operation when the prediction result indicates that the next instruction is a call instruction, and the push operation is used to push the target address corresponding to the call instruction into the first sub-stack, and the call instruction is used to call any program; or, when the prediction result indicates that the next instruction is a return instruction, determine that the processing operation includes a pop operation corresponding to the executed push operation, and the pop operation is used to pop the target address corresponding to the return instruction from the first sub-stack, and the return instruction is used to return after the call of any program is completed.

[0136] In one possible implementation, the processing module 703 is configured to, when the processing operation includes a push operation, push the target address corresponding to the prediction result into the first sub-stack according to the write pointer of the first sub-stack, and advance the write pointer of the first sub-stack when the target address is pushed; or, when the processing operation includes a pop operation corresponding to the executed push operation, determine the target address corresponding to the prediction result from the target addresses pushed into the first sub-stack according to the write pointer of the first sub-stack, pop the determined target address, and keep the write pointer of the first sub-stack in place when the target address is popped.

[0137] In one possible implementation, the processing module 703 is used to determine the historical instructions corresponding to the prediction result, where the prediction result indicates the end of any program call, and the historical instructions are used to call any program; determine the write pointer of the historical instructions, where the write pointer is used to push the target address corresponding to the historical instructions into the first sub-stack; and search for the target address corresponding to the historical instructions from at least one target address pushed into the first sub-stack according to the write pointer of the historical instructions to obtain the target address corresponding to the prediction result.

[0138] In one possible implementation, the processing module 703 is used to obtain the link relationship between the write pointer and the first top pointer of the first sub-stack; based on the link relationship between the write pointer and the first top pointer, search for the first top pointer corresponding to the write pointer of the historical instruction; and determine the target address indicated by the found first top pointer as the target address corresponding to the historical instruction.

[0139] In a possible implementation, the processing module 703 is further configured to roll back the first top pointer of the first sub-stack according to the position of the popped target address.

[0140] In a possible implementation, the processing module 703 is further configured to establish a link relationship between the write pointer and the first top pointer of the first sub-stack, where the link relationship is used to determine a target address corresponding to the prediction result from the first sub-stack.

[0141] In a possible implementation, the processing module 703 is further configured to determine a candidate unit in at least one memory unit included in the second sub-stack; and when the prediction result is submitted, store the target address corresponding to the prediction result in the candidate unit.

[0142] In one possible implementation, the acquisition module 701 is further used to obtain the execution result corresponding to the operation instruction, where the execution result indicates the next instruction to be executed after the operation instruction; the determination module 702 is further used to determine that the prediction result is not successfully predicted when the execution result and the prediction result are different, or to determine that the prediction result is successfully predicted when the execution result and the prediction result are the same.

[0143] In a possible implementation, the apparatus further includes: a correction module configured to restore a write pointer of the first substack according to the out-of-order portion of the first substack; and correct the out-of-order portion of the first substack according to the restored write pointer.

[0144] The first and second substacks reside in the same address stack, requiring the device to maintain only one stack structure, resulting in low hardware overhead. Because the write pointer is used to push the target address into the first substack, limiting the rollback of the first substack's write pointer ensures that the newly pushed target address does not overwrite the existing target address in the first substack, thus maintaining the address integrity of the first substack.

[0145] It should be noted that the apparatus provided in the above embodiments is merely illustrated by the division of the above functional modules when implementing its functions. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments are based on the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0146] Figure 8 This is a structural diagram of a server provided in an embodiment of the present application. The server may have relatively large differences due to different configurations or performances, and may include one or more processors (Central Processing Unit, CPU) 801 and one or more memories 802, wherein at least one computer program is stored in the one or more memories 802, and the at least one computer program is loaded and executed by the one or more processors 801 to enable the server to implement the instruction processing methods provided in the above-mentioned various method embodiments. Of course, the server may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output. The server may also include other components for implementing device functions, which will not be described in detail here.

[0147] Figure 9 This is a schematic diagram of the structure of an instruction processing device provided in an embodiment of the present application. The device may be a terminal, such as a smartphone, tablet computer, player, laptop computer, or desktop computer. A terminal may also be referred to as a user equipment, portable terminal, laptop terminal, desktop terminal, or other similar terminology.

[0148] Typically, the terminal includes: a processor 901 and a memory 902 .

[0149] The processor 901 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 901 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), or PLA (Programmable Logic Array). The processor 901 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 901 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 901 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0150] Memory 902 may include one or more computer-readable storage media, which may be non-transitory. Memory 902 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in memory 902 is used to store at least one instruction, which is executed by processor 901 to enable the terminal to implement the focus detection method for a lithographic apparatus provided in the method embodiment of the present application.

[0151] In some embodiments, the terminal may optionally include a peripheral device interface 903 and at least one peripheral device. The processor 901, memory 902, and peripheral device interface 903 may be connected via a bus or signal lines. Each peripheral device may be connected to the peripheral device interface 903 via a bus, signal lines, or circuit boards. Specifically, the peripheral device may include at least one of a radio frequency circuit 904, a display screen 905, a camera assembly 906, an audio circuit 907, and a power supply 908.

[0152] The peripheral device interface 903 can be used to connect at least one I / O (Input / Output)-related peripheral device to the processor 901 and the memory 902. In some embodiments, the processor 901, the memory 902, and the peripheral device interface 903 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 901, the memory 902, and the peripheral device interface 903 can be implemented on separate chips or circuit boards, which is not limited in this embodiment.

[0153] The RF circuit 904 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The RF circuit 904 communicates with communication networks and other communication devices via electromagnetic signals. The RF circuit 904 converts electrical signals into electromagnetic signals for transmission, or converts received electromagnetic signals into electrical signals. Optionally, the RF circuit 904 includes an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a user identity module card, and the like. The RF circuit 904 can communicate with other terminals via at least one wireless communication protocol. Such wireless communication protocols include, but are not limited to, metropolitan area networks, various generations of mobile communication networks (2G, 3G, 4G, and 5G), wireless local area networks, and / or WiFi (Wireless Fidelity) networks. In some embodiments, the RF circuit 904 may also include circuits related to NFC (Near Field Communication), which is not limited in this application.

[0154] Display screen 905 is used to display a user interface (UI). This UI may include graphics, text, icons, videos, or any combination thereof. When display screen 905 is a touchscreen display, it is also capable of collecting touch signals on or above the surface of display screen 905. These touch signals can be input as control signals to processor 901 for processing. Display screen 905 can also be used to provide virtual buttons and / or a virtual keyboard, also known as soft buttons and / or a soft keyboard. In some embodiments, there can be one display screen 905, located on the front panel of the terminal. In other embodiments, there can be at least two display screens 905, located on different surfaces of the terminal or in a foldable design. In still other embodiments, display screen 905 can be a flexible display, located on a curved or foldable surface of the terminal. Display screen 905 can also be configured as a non-rectangular, irregular shape, also known as a special-shaped screen. Display screen 905 can be made of materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0155] The camera assembly 906 is used to capture images or videos. Optionally, the camera assembly 906 includes a front camera and a rear camera. Typically, the front camera is arranged on the front panel of the terminal, and the rear camera is arranged on the back of the terminal. In some embodiments, there are at least two rear cameras, which are any one of a main camera, a depth of field camera, a wide-angle camera, and a telephoto camera, so as to realize the fusion of the main camera and the depth of field camera to realize the background blur function, the fusion of the main camera and the wide-angle camera to realize panoramic shooting and VR (Virtual Reality) shooting function or other fusion shooting functions. In some embodiments, the camera assembly 906 may also include a flash. The flash can be a monochrome temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm light flash and a cold light flash, which can be used for light compensation at different color temperatures.

[0156] The audio circuit 907 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, and convert the sound waves into electrical signals to be input into the processor 901 for processing, or input into the radio frequency circuit 904 to achieve voice communication. For the purpose of stereo acquisition or noise reduction, there may be multiple microphones, each disposed at different parts of the terminal. The microphone may also be an array microphone or an omnidirectional acquisition microphone. The speaker is used to convert electrical signals from the processor 901 or the radio frequency circuit 904 into sound waves. The speaker may be a traditional thin film speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can not only convert electrical signals into sound waves audible to humans, but also convert electrical signals into sound waves inaudible to humans for purposes such as ranging. In some embodiments, the audio circuit 907 may also include a headphone jack.

[0157] Power supply 908 is used to power various components in the terminal. Power supply 908 can be AC ​​power, DC power, disposable batteries, or rechargeable batteries. When power supply 908 includes a rechargeable battery, the rechargeable battery can support wired charging or wireless charging. The rechargeable battery can also be used to support fast charging technology.

[0158] In some embodiments, the terminal further includes one or more sensors 909 , including but not limited to: an acceleration sensor 910 , a gyroscope sensor 911 , a pressure sensor 912 , an optical sensor 913 , and a proximity sensor 914 .

[0159] The accelerometer 910 can detect the magnitude of acceleration along the three coordinate axes of the coordinate system established by the terminal. For example, the accelerometer 910 can be used to detect the components of gravity acceleration along the three coordinate axes. The processor 901 can control the display screen 905 to display the user interface in a landscape or portrait view based on the gravity acceleration signal collected by the accelerometer 910. The accelerometer 910 can also be used to collect game or user motion data.

[0160] The gyroscope sensor 911 can detect the terminal's body orientation and rotation angle. It can also work with the accelerometer 910 to collect 3D motions of the user on the terminal. Based on the data collected by the gyroscope sensor 911, the processor 901 can implement the following functions: motion sensing (such as changing the UI based on the user's tilt), image stabilization during shooting, game control, and inertial navigation.

[0161] The pressure sensor 912 can be set in the side frame of the terminal and / or the lower layer of the display screen 905. When the pressure sensor 912 is set in the side frame of the terminal, it can detect the user's grip signal of the terminal, and the processor 901 performs left and right hand recognition or shortcut operations based on the grip signal collected by the pressure sensor 912. When the pressure sensor 912 is set in the lower layer of the display screen 905, the processor 901 controls the operable controls on the UI interface based on the user's pressure operation on the display screen 905. Operable controls include at least one of button controls, scroll bar controls, icon controls, and menu controls.

[0162] Optical sensor 913 is used to detect ambient light intensity. In one embodiment, processor 901 can control the display brightness of display screen 905 based on the ambient light intensity detected by optical sensor 913. Specifically, when the ambient light intensity is high, the display brightness of display screen 905 is increased; when the ambient light intensity is low, the display brightness of display screen 905 is decreased. In another embodiment, processor 901 can also dynamically adjust the shooting parameters of camera assembly 906 based on the ambient light intensity detected by optical sensor 913.

[0163] Proximity sensor 914, also known as a distance sensor, is typically located on the front panel of the terminal. Proximity sensor 914 is used to detect the distance between the user and the front of the terminal. In one embodiment, when proximity sensor 914 detects that the distance between the user and the front of the terminal is gradually decreasing, processor 901 controls display screen 905 to switch from the screen-on state to the screen-off state. When proximity sensor 914 detects that the distance between the user and the front of the terminal is gradually increasing, processor 901 controls display screen 905 to switch from the screen-off state to the screen-on state.

[0164] Those skilled in the art will understand that Figure 9 The structure shown in the figure does not constitute a limitation on the instruction processing device, and may include more or fewer components than shown in the figure, or combine certain components, or adopt a different component arrangement.

[0165] In an exemplary embodiment, a computer device is further provided, comprising a processor and a memory, wherein the memory stores at least one computer program. The at least one computer program is loaded and executed by one or more processors to enable the computer device to implement any of the above-mentioned instruction processing methods.

[0166] In an exemplary embodiment, a computer-readable storage medium is further provided, in which at least one computer program is stored. The at least one computer program is loaded and executed by a processor of a computer device to enable the computer to implement any of the above instruction processing methods.

[0167] In one possible implementation, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, and the like.

[0168] In an exemplary embodiment, a computer program product or computer program is also provided, the computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform any of the above-described instruction processing methods.

[0169] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the prediction results involved in this application were obtained with full authorization.

[0170] It should be understood that the term "plurality" used herein refers to two or more. "And / or" describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates an "or" relationship between the associated objects.

[0171] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for processing an instruction, characterized in that: The method is used for processing instructions based on an address stack, the address stack including a first sub-stack and a second sub-stack, the target address in the first sub-stack being obtained based on a prediction result of the instruction, and the target address in the second sub-stack being obtained based on a commit result of the instruction, the method comprising: Obtaining a prediction result of an operation instruction, the prediction result indicating a next instruction predicted to be executed after the operation instruction; determining a processing operation on the first sub-stack according to the prediction result; performing the processing operation on the target address corresponding to the prediction result in the first sub-stack according to the write pointer of the first sub-stack, wherein the write pointer of the first sub-stack is restricted from rolling back during the execution of the processing operation, and the write pointer of the first sub-stack is used to correct an out-of-order portion caused by the execution of the processing operation in the first sub-stack when it is detected that the prediction result is not successfully predicted; When the processing operation includes a push operation, a candidate unit is determined in at least one memory unit included in the second sub-stack; when the prediction result is submitted, the target address corresponding to the prediction result in the first sub-stack is moved to the candidate unit by means of internal target address transfer.

2. The method according to claim 1, characterized in that Determining a processing operation on the first sub-stack according to the prediction result includes: If the prediction result indicates that the next instruction is a call instruction, determining that the processing operation includes the push operation, the push operation is used to push a target address corresponding to the call instruction into the first sub-stack, and the call instruction is used to call any program; Alternatively, when the prediction result indicates that the next instruction is a return instruction, it is determined that the processing operation includes a pop operation corresponding to the executed push operation, and the pop operation is used to pop the target address corresponding to the return instruction in the first sub-stack, and the return instruction is used to return after completing the call of any program.

3. The method according to claim 1, characterized in that The performing the processing operation on the target address corresponding to the prediction result in the first sub-stack according to the write pointer of the first sub-stack includes: In a case where the processing operation includes a push operation, pushing a target address corresponding to the prediction result into the first sub-stack according to a write pointer of the first sub-stack, and advancing the write pointer of the first sub-stack when the target address is pushed; Alternatively, in a case where the processing operation includes a pop operation corresponding to a push operation that has been executed, the target address corresponding to the prediction result is determined among the target addresses pushed into the first sub-stack based on the write pointer of the first sub-stack, and the determined target address is popped out, and the write pointer of the first sub-stack remains in place when the target address is popped out.

4. The method according to claim 3, characterized in that The determining, according to the write pointer of the first sub-stack, a target address corresponding to the prediction result from the target addresses pushed into the first sub-stack includes: Determining a historical instruction corresponding to the prediction result, wherein the prediction result indicates that any program call ends, and the historical instruction is used to call the any program; Determine a write pointer of the historical instruction, where the write pointer is used to push a target address corresponding to the historical instruction into the first sub-stack; The target address corresponding to the historical instruction is searched from at least one target address pushed into the first sub-stack according to the write pointer of the historical instruction to obtain the target address corresponding to the prediction result.

5. The method according to claim 4, characterized in that The step of searching, according to the write pointer of the historical instruction, for a target address corresponding to the historical instruction from at least one target address pushed into the first sub-stack includes: Acquire a link relationship between a write pointer and a first top pointer of the first substack; According to the link relationship between the write pointer and the first stack top pointer, searching for the first stack top pointer corresponding to the write pointer of the historical instruction; The target address indicated by the first stack top pointer found is determined as the target address corresponding to the historical instruction.

6. The method according to any one of claims 3 to 5, characterized in that: After the determined target address is popped out, the method further includes: Roll back the first top pointer of the first sub-stack according to the position of the popped target address.

7. The method according to any one of claims 3 to 5, characterized in that: After pushing the target address corresponding to the prediction result into the first sub-stack according to the write pointer of the first sub-stack, the method further includes: A link relationship is established between the write pointer and a first top pointer of the first sub-stack, where the link relationship is used to determine a target address corresponding to the prediction result from the first sub-stack.

8. The method according to any one of claims 1 to 5, characterized in that: The method further comprises: Obtaining an execution result corresponding to the operation instruction, where the execution result indicates a next instruction to be executed after the operation instruction; In a case where the execution result and the prediction result are different, it is determined that the prediction result is not successfully predicted, or in a case where the execution result and the prediction result are the same, it is determined that the prediction result is successfully predicted.

9. The method according to any one of claims 1 to 5, characterized in that: The method further comprises: restoring a write pointer of the first substack according to the out-of-order portion of the first substack; The out-of-order portion of the first sub-stack is corrected according to the restored write pointer.

10. An instruction processing device, characterized in that: The apparatus is configured to process an instruction based on an address stack, the address stack comprising a first sub-stack and a second sub-stack, a target address in the first sub-stack being obtained based on a prediction result of the instruction, and a target address in the second sub-stack being obtained based on a commit result of the instruction, the apparatus comprising: an acquisition module, configured to acquire a prediction result of an operation instruction, wherein the prediction result indicates a next instruction predicted to be executed after the operation instruction; a determining module, configured to determine a processing operation on the first sub-stack according to the prediction result; a processing module, configured to execute the processing operation on a target address corresponding to the prediction result in the first sub-stack according to a write pointer of the first sub-stack, wherein the write pointer of the first sub-stack is restricted from rolling back during the execution of the processing operation, and the write pointer of the first sub-stack is configured to correct an out-of-order portion caused by the execution of the processing operation in the first sub-stack when it is detected that the prediction result is not successfully predicted; The processing module is further used to determine a candidate unit in at least one memory unit included in the second sub-stack when the processing operation includes a push operation; and to move the target address corresponding to the prediction result in the first sub-stack to the candidate unit by means of internal target address transfer when the prediction result is submitted.

11. A computer device, characterized in that: The computer device includes a processor and a memory, wherein at least one computer program is stored in the memory, and the at least one computer program is loaded and executed by the processor, so that the computer device implements the instruction processing method according to any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores at least one computer program, and the at least one computer program is loaded and executed by a processor to enable a computer to implement the instruction processing method according to any one of claims 1 to 9.

13. A computer program product, characterized in that The computer program product includes a computer program / instruction, and the computer program / instruction is executed by a processor to enable a computer to perform the instruction processing method according to any one of claims 1 to 9.

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