A data processing method and apparatus based on quantum random access memory

Abstract

The application discloses a data processing method and device based on a quantum random access memory (QRAM), and the method comprises the following steps: obtaining a target address and data bits of a preset word length; determining a target path corresponding to the target address by using a preset addressing mode based on the target address; and processing data corresponding to the target address in a parallel mode according to the preset word length of the data bits and the target path, wherein the parallel mode is to read data of the preset word length at a time within a preset time sequence, and the method is used for accelerating the data processing speed, optimizing the time complexity and reducing the execution error rate of the QRAM architecture by proposing a QRAM architecture.

Description

Technical Field

[0001] This invention belongs to the field of quantum computing technology, specifically a data processing method and apparatus based on quantum random access memory. Background Technology

[0002] Quantum Random Access Memory (QRAM) is a storage technology that utilizes the principles of quantum physics. Unlike traditional computer memory, QRAM allows information to be stored in parallel at multiple locations and allows multiple pieces of information to be read simultaneously. This gives QRAM a significant advantage in processing large amounts of data. Theoretically, QRAM has a much higher storage density than traditional memory technologies, and because it can use quantum encryption algorithms, it offers stronger security.

[0003] Although QRAM is a technology with great potential, it is still in the research and development stage and is not currently a mainstream technology in the market. Furthermore, exploring a method to achieve parallel data reading based on QRAM and accelerate data processing speed remains a pressing problem to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide a data processing method and apparatus based on quantum random access memory (QRAM) to overcome the shortcomings of the prior art. It proposes a QRAM architecture to realize a method for parallel data reading based on QRAM, thereby accelerating data processing speed, optimizing time complexity, and reducing the execution error rate of the QRAM architecture.

[0005] One embodiment of this application provides a data processing method based on a quantum random access memory, the method comprising:

[0006] Obtain the target address and the data bits of the preset word length;

[0007] Based on the target address, the target path corresponding to the target address is determined using a preset addressing method;

[0008] Based on the preset word length of the data bits and the target path, the data corresponding to the target address is processed in parallel, wherein the parallel processing method is to read the preset word length of data once within a preset time sequence.

[0009] Optionally, after obtaining the target address and the data bits of the preset word length, the method further includes:

[0010] The target address is read sequentially by an address register, and each bit of the target address read by the address register is transferred using a preset quantum circuit. The preset quantum circuit includes H gate, CNOT gate, controlled Z gate, SWAP gate, and controlled SWAP gate. The transfer operation includes one or more of data copying, data routing, and data exchange.

[0011] Optionally, the quantum random access memory is a binary tree structure, which includes one root node and n-1 subtree nodes. Each layer of the binary tree structure includes one address bit and one data bit, where n is the address length of the target address.

[0012] Optionally, determining the target path corresponding to the target address using a preset addressing method based on the target address includes:

[0013] Starting from the root node, each bit of the n-1 target address read sequentially is transferred to the data bit of the corresponding target layer subtree node through the preset quantum circuit;

[0014] Then, the target address bit read from the data bit of the current target layer subtree node is swapped to the address bit of the current target layer subtree node, until the target path corresponding to the n-bit target address is generated.

[0015] Optionally, the step of transferring each bit of the n-1 target address read sequentially from the root node to the data bit of the corresponding target layer subtree node through the preset quantum circuit includes:

[0016] Starting from n=0, the 0th bit of the target address is transferred to the root node of the binary tree structure;

[0017] Starting from the i-th subtree node, the step of transferring the i-th address of the target address to the data bits of the i-th subtree node of the binary tree structure is performed until every bit of the target address has been transferred, where i is an integer and its value ranges from 1 to n-1.

[0018] Optionally, the step of processing the data corresponding to the target address in parallel according to the preset word length of the data bits and the target path includes:

[0019] Upon receiving the target path, the data corresponding to each address in the target path is obtained according to the data bit parallel reading rule with a preset word length.

[0020] The data corresponding to each bit of the address is transferred to the address bit of the root node in the binary tree structure through the preset quantum circuit to complete the parsing process of the data corresponding to the target path.

[0021] Another embodiment of this application provides a data processing device based on a quantum random access memory, the device comprising:

[0022] The acquisition module is used to obtain the target address and the data bits of a preset word length;

[0023] The determination module is used to determine the target path corresponding to the target address based on the target address and using a preset addressing method;

[0024] The processing module is used to process the data corresponding to the target address in a parallel manner according to the preset word length of the data bits and the target path, wherein the parallel manner is to read the preset word length of data at a time within a preset time sequence.

[0025] Optionally, after obtaining the module, the device further includes:

[0026] The transfer module is used to sequentially read each bit of the target address through the address register, and to perform a transfer operation on each bit of the target address read by the address register using a preset quantum circuit. The preset quantum circuit includes an H gate, a CNOT gate, a controlled Z gate, a SWAP gate, and a controlled SWAP gate. The transfer operation includes one or more of data copying, data routing, and data exchange.

[0027] Optionally, the determining module includes:

[0028] The transfer unit is used to transfer each bit of the n-1 target address read sequentially from the root node to the data bit of the corresponding target layer subtree node through the preset quantum circuit.

[0029] The switching unit is used to swap one bit of the target address read from the data bit of the current target layer subtree node to the address bit of the current target layer subtree node, until the target path corresponding to the n-bit target address is generated.

[0030] Optionally, the transfer unit includes:

[0031] The first transfer subunit is used to transfer the 0th bit of the target address to the root node of the binary tree structure, starting from n=0;

[0032] The second transfer subunit is used to start from the i-th level subtree node and execute the step of transferring the i-th address of the target address to the data bit of the i-th level subtree node of the binary tree structure until every bit of the target address has been transferred, wherein i is an integer and its value ranges from 1 to n-1.

[0033] Optionally, the processing module includes:

[0034] The acquisition unit is used to acquire the data corresponding to each address in the target path according to the data bit parallel reading rule of preset word length when the target path is received;

[0035] The parsing unit is used to transfer the data corresponding to each bit of the address to the address bit of the root node in the binary tree structure through the preset quantum circuit, so as to complete the parsing processing of the data corresponding to the target path.

[0036] Another embodiment of this application provides a storage medium storing a computer program, wherein the computer program is configured to implement the method described in any of the preceding claims when running.

[0037] Another embodiment of this application provides an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to implement the method described in any of the preceding claims.

[0038] Compared with existing technologies, this invention first obtains the target address and data bits of a preset word length. Then, based on the target address, it determines the target path corresponding to the target address using a preset addressing mode. Finally, according to the preset word length of the data bits and the target path, it processes the data corresponding to the target address in a parallel manner. The parallel manner involves reading the preset word length of data once within a preset time sequence. By proposing a QRAM architecture, it realizes a method for parallel data reading based on QRAM, which accelerates data processing speed, optimizes time complexity, and reduces the execution error rate of the QRAM architecture. Attached Figure Description

[0039] Figure 1 This is a system network block diagram corresponding to a data processing method based on quantum random access memory provided in an embodiment of the present invention;

[0040] Figure 2 This is a schematic flowchart of a data processing method based on a quantum random access memory provided in an embodiment of the present invention;

[0041] Figure 3 This is a schematic diagram of a binary tree structure of a quantum random access memory provided in an embodiment of the present invention;

[0042] Figure 4 This is a schematic diagram of a quantum circuit for implementing data copying provided in an embodiment of the present invention;

[0043] Figure 5 This is a schematic diagram of a quantum circuit for implementing address bus input provided by an embodiment of the present invention;

[0044] Figure 6 This is a schematic diagram of a quantum circuit for implementing data bus input provided by an embodiment of the present invention;

[0045] Figure 7 This is a schematic diagram of a quantum circuit for implementing data routing provided in an embodiment of the present invention;

[0046] Figure 8 This is a schematic diagram of a parallel data processing method based on quantum random access memory provided in an embodiment of the present invention;

[0047] Figure 9 This is a schematic diagram of the structure of a data processing device based on a quantum random access memory provided in an embodiment of the present invention. Detailed Implementation

[0048] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0049] The present invention first provides a data processing method based on quantum random access memory, which can be applied to electronic devices, such as computer terminals, specifically ordinary computers, quantum computers, etc.

[0050] The following detailed explanation uses a computer terminal as an example. Figure 1 This is a system network block diagram corresponding to a data processing method based on quantum random access memory provided in an embodiment of the present invention. The system corresponding to the data processing method based on quantum random access memory may include a network 110, a server 120, a wireless device 130, a client 140, a storage unit 150, a classical processing system 160, a quantum processing system 170, and may also include additional memory, classical processor, quantum processor and other devices not shown.

[0051] Network 110 is a medium used to provide communication links between various devices and computers connected together within a system corresponding to the data processing method of quantum random access memory. These include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. The connection method can be wired, wireless communication links, or fiber optic cables.

[0052] Server 120 and client 140 are conventional data processing systems that may contain data and applications or software tools that perform conventional computational processes. Client 140 may be a personal computer or a network computer, so the data may also be provided by server 120. Wireless device 130 may be a smartphone, tablet, laptop, smart wearable device, etc. Storage unit 150 may include database 151, which can be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, and quantum programs.

[0053] The classical processing system 160 (quantum processing system 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 163 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application program 162 (application program 173). The application program 162 (application program 173) may be used to implement a quantum algorithm compiled by the data processing method based on quantum random access memory provided in the embodiments of the present invention.

[0054] Any data or information stored or generated in the classical processing system 160 (quantum processing system 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application executed therein can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0055] It should be noted that a true quantum computer has a hybrid structure, which includes at least... Figure 1 The system consists of two main parts: the classical processing system 160, which is responsible for performing classical calculations and control; and the quantum processing system 170, which is responsible for running quantum programs and thus realizing quantum computing.

[0056] The aforementioned classical processing system 160 and quantum processing system 170 can be integrated into a single device or distributed across two different devices. For example, the first device, including the classical processing system 160, runs a classical computer operating system that provides quantum application development tools and services, as well as the storage and network services required for quantum applications. Users develop quantum applications using the quantum application development tools and services on the second device and send the quantum program to the second device, including the quantum processing system 170, via the network services. The second device runs a quantum computer operating system, which parses the code of the quantum program and compiles it into instructions that can be recognized and executed by the quantum computer control system. The quantum processor 170 then implements the quantum algorithm corresponding to the quantum program based on these instructions.

[0057] In the classic silicon-based processing system 160, the units of the classic processor 161 are CMOS transistors. These computing units are not limited by time or coherence; that is, they are available at any time without time constraints. Furthermore, the number of these computing units in a silicon chip is sufficient; currently, a classic processor contains tens of thousands of computing units. The sufficient number of computing units and the fixed selectable computing logic of the CMOS transistors, such as AND logic, allow for computational efficiency through a combination of numerous CMOS transistors and limited logic functions.

[0058] Unlike the logic units in the classical processing system 160, the basic computational unit of the quantum processor 171 in the quantum processing system 170 is the qubit. The input of a qubit is limited by coherence and coherence time; that is, a qubit is limited by its available usage time and is not always readily available. Making full use of qubits within their available usage time is a key challenge in quantum computing. Furthermore, the number of qubits in a quantum computer is one of the representative indicators of its performance. Each qubit performs computational functions through on-demand configured logic functions. Given the limited number of qubits and the diverse logic functions available in quantum computing, such as Hadamard gates (H gates), Pauli-X gates (X gates), Pauli-Y gates (Y gates), Pauli-Z gates (Z gates), X gates, RY gates, RZ gates, CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc., quantum computing requires combining a limited number of qubits with diverse combinations of logic functions to achieve computational effects.

[0059] Based on these differences, the design of logical functions applied to qubits (including the design of whether qubits are used and the design of the efficiency of each qubit) is crucial to improving the computational performance of quantum computers and requires special design. The aforementioned design considerations for qubits are technical problems that ordinary computing devices do not need to address. Therefore, this invention proposes a data processing method and apparatus based on quantum random access memory (QRAM) to address the shortcomings of existing technologies. It proposes a QRAM architecture to achieve parallel data reading based on QRAM, thereby accelerating data processing speed, optimizing time complexity, and reducing the execution error rate of the QRAM architecture.

[0060] See Figure 2 , Figure 2 A flowchart illustrating a data processing method based on a quantum random access memory, provided as an embodiment of the present invention, may include the following steps:

[0061] S201: Obtain the target address and the data bits of the preset word length.

[0062] Specifically, the target address can be a binary string representing an instruction pointing to a specific memory unit, and the preset word length of data bits can refer to the amount of data stored in a specific memory unit at one time or the length of the data stored in a specific memory unit.

[0063] It should be noted that the architecture of a Quantum Random Access Memory (QRAM) typically consists of the following parts: quantum storage units, quantum control units, quantum error correction units, and transmission interface units. The quantum storage units are the core component of the QRAM, typically using qubits to store information. The quantum control units are responsible for reading and writing to the quantum storage units. The quantum error correction units implement quantum error correction mechanisms to ensure data integrity. The transmission interface units enable data exchange with other computer systems, usually using quantum communication technology. In summary, the QRAM architecture requires efficient quantum control capabilities and a robust quantum error correction mechanism to ensure data integrity and security.

[0064] QRAM can also be understood as a storage system used in quantum computers, a quantum version of RAM (Random Access Memory) in classical computers. QRAM can be used to create quantum superposition states containing information. Unlike RAM, which requires reading data one element at a time, QRAM can read superimposed data at superimposed addresses. For example, it can store d0, d1, d2, ..., d... in address [0, n]. n Using classic RAM, input address i output data d i For QRAM, the following quantum state can be input as the address:

[0065] ∑|i>

[0066] The following target quantum state can be output using QRAM:

[0067] ∑|i>| i >

[0068] This process of inputting an address and outputting data can be called a query or access. Since QRAM plays the role of converting classical data to quantum data in many quantum algorithms (as an intermediate memory for converting classical data into quantum data), and an important condition for quantum speedup of these algorithms is that the time for QRAM to execute a query cannot be too long, this application can reduce the query time through parallel processing.

[0069] The QRAM architecture can be represented as a binary tree structure, which includes a root node of 1 level and n-1 subtree nodes. Each level of the binary tree structure includes an address bit and a data bit, where n is the address length of the target address.

[0070] See Figure 3 , Figure 3 This is a schematic diagram of a binary tree structure for a quantum random access memory provided in an embodiment of the present invention. Figure 3 As shown in the diagram, taking a target address length of 3 as an example, in the QRAM architecture, as indicated by the dashed box, a continuous vertical sequence of A (Address Qubit) and D (Data Qubit) forms a group called a node, which is the basic unit in a binary tree. All nodes constitute a binary tree. In the diagram, (0,0) represents the 0th node at level 0, i.e., the root node; (1,0) represents the 0th node at level 1, i.e., the 0th subtree node at level 1, and so on. Further details are omitted here.

[0071] In one optional implementation, after obtaining the target address and the data bits of a preset word length, the method may further include:

[0072] The target address is read bit by bit sequentially through an address register, and a preset quantum circuit is used to perform a transfer operation on each bit of the target address read from the address register. The preset quantum circuit includes H-gates, CNOT gates, controlled Z-gates, SWAP gates, and controlled SWAP gates. The transfer operation includes one or more of data copying, data routing, and data exchange. The preset quantum circuit's qubits include qubits corresponding to a bus, which includes an address bus and a data bus. The bus functions to input address information and input each data bit of a preset word length.

[0073] Specifically, the overall workflow of the QRAM architecture consists of two main parts: preset addressing and data loading. These two parts can be summarized into the following steps: data copying, address bus input, data bus input, data routing, and data exchange between address bits and data bits.

[0074] For example, see Figure 4 , Figure 4 This is a schematic diagram of a quantum circuit for implementing data copying according to an embodiment of the present invention. The address bits of the nodes in the diagram are a. l，p The data bits are d l，p By using a controlled Z-gate, one bit of data is stored in the corresponding qubit m in the memory pool. 2p In, and if address bit a l，pThe address in the memory is 0, and the corresponding quantum bit m is stored in the memory pool. 2p If address bit a l，p If the address in the memory is 1, then the corresponding memory is stored in the memory pool m. 2p+1 The corresponding qubit.

[0075] It should be noted that data copying, or data replication, is a controlled operation that copies classical data from address bits to data bits. Because the Toffoli gate cannot be used to encode the quantum state |0> during the data input phase... Quantum state |1> is encoded as Therefore, a controlled Z-gate can be used to phase-encode data qubits to complete the data copying operation.

[0076] See Figure 5 , Figure 5 This is a schematic diagram of a quantum circuit for implementing address bus input according to an embodiment of the present invention. Figure A i Let d be the address of the i-th bit. 0，0 This represents the data bits of the root node. The address bus input copies the i-th binary digit of the address bus to the root node, which can be done using a CNOT gate. For example, copying the first bit of the target address to the data bits of the root node, and then subsequently transferring the first bit of the target address to the address bits of the root node, can be done using a SWAP gate or other multiple quantum logic gates to exchange data between the data bits and address bits of a node.

[0077] See Figure 6 , Figure 6 This is a schematic diagram of a quantum circuit for implementing data bus input according to an embodiment of the present invention. Data bus input involves transmitting the i-th binary bit of the data bus to the data bit of the root node. For example, the H gate and SWAP gate shown in the diagram can be used. The H gate enables phase encoding during data copying operations, thereby distinguishing between the |0> state of the data bit and the |0> state of non-data bits; that is, encoding the |0> state into... State, |1> state encoding

[0078] In one alternative implementation, the process of writing the target address is the process of determining the access path in the QRAM. Writing the first bit address differs from writing the other bit addresses, as the first bit address is written to the root node, while the other bit addresses are written to subtree nodes. Specifically, writing the first bit address involves copying it from the bus to the root node, and then copying it to the data bits of the root node. Writing other bit addresses requires downward addressing, routing to the corresponding subtree nodes. Routing can be implemented using controlled SWAP gates. A detailed quantum circuit diagram can be found in [reference needed]. Figure 7, Figure 7 This is a schematic diagram of a quantum circuit for implementing data routing according to an embodiment of the present invention. As shown in the diagram, the layer to which the data is routed is determined by the address of the previous bit. For example, if the address in the p-th address bit of the l-th layer is 0, then the current target bit is routed from the data bit of the p-th node of the l-th layer to the data bit of the 2p-th node of the (l+1)-th layer. If the address in the p-th address bit of the l-th layer is 1, then the current target bit is routed from the data bit of the p-th node of the l-th layer to the data bit of the 2p+1-th node of the (l+1)-th layer.

[0079] S202: Based on the target address, determine the target path corresponding to the target address using a preset addressing method.

[0080] Specifically, determining the target path corresponding to the target address using a preset addressing method based on the target address may include:

[0081] Starting from the root node, through the preset quantum circuit, each bit of the n-1 target address read in sequence is transferred to the data bit of the corresponding target layer subtree node; and the target address bit read from the data bit of the current target layer subtree node is swapped to the address bit of the current target layer subtree node, until the target path corresponding to the n target address is generated.

[0082] Starting from the root node, the process of transferring each bit of the n-1 target address read sequentially to the data bit of the corresponding target layer subtree node via the preset quantum circuit may include:

[0083] Starting from n=0, the 0th bit of the target address is transferred to the root node of the binary tree structure; starting from the i-th level subtree node, the step of transferring the i-th bit of the target address to the data bit of the i-th level subtree node of the binary tree structure is executed until every bit of the target address is transferred, where i is an integer and its value ranges from 1 to n-1.

[0084] S203: Based on the preset word length of the data bits and the target path, process the data corresponding to the target address in a parallel manner, wherein the parallel manner is to read the preset word length of data once within a preset time sequence.

[0085] Specifically, the step of processing the data corresponding to the target address in parallel based on the preset word length of the data bits and the target path may include:

[0086] Step 1: Upon receiving the target path, obtain the data corresponding to each address in the target path according to the data bit parallel reading rule with a preset word length.

[0087] Step 2: Using the preset quantum circuit, transfer the data corresponding to each bit of the address to the address bit of the root node in the binary tree structure to complete the parsing process of the data corresponding to the target path.

[0088] For example, firstly, the target path corresponding to the target address can be obtained and marked or highlighted (Route). Secondly, the data in the corresponding memory pool can be copied according to the target path, that is, the data in the memory pool corresponding to the target path can be copied and obtained. Through the above steps, the addressing operation of the memory pool in a preset manner can be realized, and the corresponding data can be read. This is analogous to the load operation in the classical computer instruction system. A set of classical-control not operations is completed through the classical controller to complete the conversion of classical data to quantum data. Finally, the quantum state preparation of the data in the memory pool corresponding to each address in the target path can be realized.

[0089] Specifically, the parsing process for the data corresponding to the target path can include at least one of the following: writing the data to the target path, storing the data, and reading the data. For example, a parsing operation can be writing a single address bit during the writing process, writing a single data bit during the data storage process, or reading a single data bit during the data reading process. For instance, if the target address length is 4, then the target address writing process can include 4 parsing operations. If the preset word length for the data bits is 3, this can be understood as parsing 3 bits of data at a time within a preset timing sequence.

[0090] For example, for the above Figure 3 The corresponding binary tree structure determines whether to route left or right based on the address of the previous level. For example, if the target address is 010, according to the preset routing rules, 0 routes left and 1 routes right. The address bit in the root node of level 0 is 0. For the second address bit, it is copied from the bus to the data bits of level 0. Because the address bit in level 0 is 0, the second address is routed left, and the first subtree node corresponding to the second address is (1,0). The third address bit is copied from the bus to the data bits of level 0, routed from the data bits of node (0,0) to node (1,0). Because the second address bit is 1, it is routed right to node (2,1), and the third address bit is finally written into the address bits of node (2,1). This process ultimately transfers the data corresponding to each bit of the target address to the address bits of the root node in the binary tree structure.

[0091] It should be noted that this process can be executed in parallel. See also Figure 8 , Figure 8This is a schematic diagram of a parallel data processing method based on quantum random access memory (QRAM) provided by an embodiment of the present invention. The horizontal bands represent QRAM layers, the first black slanted line represents the target address setting stage, the last black slanted line represents the reverse computation stage, and the remaining slanted lines from left to right represent the data acquisition stages in a preset time sequence. D0, D1, and D2 are data bits with a preset word length of 3. First, the target address is obtained. As shown in the diagram, for example, when a bit of the target address has been moved from layer 1 to layer 2, the next address of the target address can be moved to layer 1 in parallel. This ensures that the time required for the entire transfer step does not exceed the time required to move the nth bit of the address to layer n. This can be called the data copying or fetching process. Then, the reverse computation step (Uncomputing) begins. The purpose of the reverse computation is to clear all intermediate results in the data processing process to return to the initial state.

[0092] As can be seen, this invention first obtains the target address and data bits of a preset word length. Then, based on the target address, it determines the target path corresponding to the target address using a preset addressing mode. Finally, according to the preset word length of the data bits and the target path, it processes the data corresponding to the target address in a parallel manner. The parallel manner involves reading the preset word length of data once within a preset time sequence. By proposing a QRAM architecture, it realizes a method for parallel data reading based on QRAM, thereby accelerating data processing speed, optimizing time complexity, and reducing the execution error rate of the QRAM architecture.

[0093] See Figure 9 , Figure 9 This is a schematic diagram of the structure of a data processing device based on a quantum random access memory provided in an embodiment of the present invention. Figure 2 The process shown can include:

[0094] Module 901 is used to obtain the target address and the data bits of a preset word length;

[0095] The determining module 902 is used to determine the target path corresponding to the target address based on the target address and using a preset addressing method;

[0096] The processing module 903 is used to process the data corresponding to the target address in a parallel manner according to the preset word length of the data bits and the target path, wherein the parallel manner is to read the preset word length of data once within a preset time sequence.

[0097] Specifically, after the obtaining module, the device further includes:

[0098] The transfer module is used to sequentially read each bit of the target address through the address register, and to perform a transfer operation on each bit of the target address read by the address register using a preset quantum circuit. The preset quantum circuit includes an H gate, a CNOT gate, a controlled Z gate, a SWAP gate, and a controlled SWAP gate. The transfer operation includes one or more of data copying, data routing, and data exchange.

[0099] Specifically, the determining module includes:

[0100] The transfer unit is used to transfer each bit of the n-1 target address read sequentially from the root node to the data bit of the corresponding target layer subtree node through the preset quantum circuit.

[0101] The switching unit is used to swap one bit of the target address read from the data bit of the current target layer subtree node to the address bit of the current target layer subtree node, until the target path corresponding to the n-bit target address is generated.

[0102] Specifically, the transfer unit includes:

[0103] The first transfer subunit is used to transfer the 0th bit of the target address to the root node of the binary tree structure, starting from n=0;

[0104] The second transfer subunit is used to start from the i-th level subtree node and execute the step of transferring the i-th address of the target address to the data bit of the i-th level subtree node of the binary tree structure until every bit of the target address has been transferred, wherein i is an integer and its value ranges from 1 to n-1.

[0105] Specifically, the processing module includes:

[0106] The acquisition unit is used to acquire the data corresponding to each address in the target path according to the data bit parallel reading rule of preset word length when the target path is received;

[0107] The parsing unit is used to transfer the data corresponding to each bit of the address to the address bit of the root node in the binary tree structure through the preset quantum circuit, so as to complete the parsing processing of the data corresponding to the target path.

[0108] Compared with existing technologies, this invention first obtains the target address and data bits of a preset word length. Then, based on the target address, it determines the target path corresponding to the target address using a preset addressing mode. Finally, according to the preset word length of the data bits and the target path, it processes the data corresponding to the target address in a parallel manner. The parallel manner involves reading the preset word length of data once within a preset time sequence. By proposing a QRAM architecture, it realizes a method for parallel data reading based on QRAM, which accelerates data processing speed, optimizes time complexity, and reduces the execution error rate of the QRAM architecture.

[0109] This invention also provides a storage medium storing a computer program, wherein the computer program is configured to implement the steps in any of the method embodiments described above when running.

[0110] Specifically, in this embodiment, the storage medium can be configured to store a computer program for implementing the following steps:

[0111] S201: Obtain the target address and the data bits of the preset word length;

[0112] S202: Based on the target address, determine the target path corresponding to the target address using a preset addressing method;

[0113] S203: Based on the preset word length of the data bits and the target path, process the data corresponding to the target address in a parallel manner, wherein the parallel manner is to read the preset word length of data once within a preset time sequence.

[0114] Specifically, in this embodiment, the storage medium may include, but is not limited to, USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks, and other media capable of storing computer programs.

[0115] This invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to implement the steps in any of the method embodiments described above.

[0116] Specifically, the aforementioned electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the aforementioned processor, and the input / output device is connected to the aforementioned processor.

[0117] Specifically, in this embodiment, the processor described above can be configured to implement the following steps via a computer program:

[0118] S201: Obtain the target address and the data bits of the preset word length;

[0119] S202: Based on the target address, determine the target path corresponding to the target address using a preset addressing method;

[0120] S203: Based on the preset word length of the data bits and the target path, process the data corresponding to the target address in a parallel manner, wherein the parallel manner is to read the preset word length of data once within a preset time sequence.

[0121] The above description, based on the embodiments shown in the figures, details the structure, features, and effects of the present invention. The above description is only a preferred embodiment of the present invention, but the present invention is not limited to the scope of implementation shown in the figures. Any changes made in accordance with the concept of the present invention, or equivalent embodiments modified to have equivalent changes, that do not exceed the spirit covered by the specification and figures, should be within the protection scope of the present invention.

Claims

1. A data processing method based on quantum random access memory, characterized by, The quantum random memory is a binary tree structure, the binary tree structure includes a 1-layer root node and a layer sub-tree node, wherein each layer of the binary tree structure includes an address bit and a data bit, an address length of a target address; the method comprises: Obtain a target address and a data bit of a preset word length; Starting from the root node, the data will be read sequentially via a pre-defined quantum circuit. Each bit of the target address is sequentially transferred to the data bit of the corresponding target layer subtree node; and the target address bit read from the data bit of the current target layer subtree node is swapped to the address bit of the current target layer subtree node, until the target address is generated. The target path corresponding to the target address; When the target path is received, data corresponding to each bit address in the target path is obtained according to a parallel mode reading rule of the data bit of the preset word length, and the data corresponding to each bit address is respectively transferred to an address bit of a root node in the binary tree structure through the preset quantum circuit, so as to complete the analysis processing of the data corresponding to the target path, wherein the parallel mode is to read data of a preset word length at a time within a preset time sequence.

2. The method of claim 1, wherein, After the target address and the data bit of the preset word length are obtained, the method further includes: Each bit of the target address is read in sequence through an address register, and each bit of the target address read by the address register is subjected to a transfer operation by using a preset quantum circuit, wherein the preset quantum circuit includes an H gate, a CNOT gate, a controlled Z gate, a SWAP gate and a controlled SWAP gate, and the transfer operation includes one or more of data copying, data routing and data exchange.

3. The method of claim 1, wherein, The sequentially read bits are sequentially transferred to the data bits of the corresponding target layer sub-tree nodes from the root node through the preset quantum circuit bit target address is sequentially transferred to the data bits of the corresponding target layer sub-tree nodes, comprising: From starting, the 0th bit address of the target address is transferred to the root node of the binary tree structure; From the Starting from the subtree node, execute the first step of retrieving the target address. The bit address is transferred to the first bit of the binary tree structure. The steps on the data bits of the subtree nodes are repeated until every bit of the target address has been transferred, wherein... The integers are selected from 1 to 1. .

4. A data processing apparatus based on quantum random access memory, characterized by, The quantum random memory is a binary tree structure, the binary tree structure includes a root node of 1 layer and a layer sub-tree node, wherein each layer of the binary tree structure includes an address bit and a data bit, an address length of a target address; the device comprises: An obtaining module is configured to obtain a target address and a data bit of a preset word length; A determining module is configured to sequentially read a target address from the root node through a preset quantum circuit Each bit of the target address is sequentially transferred to a data bit of a corresponding target layer sub-tree node; and one bit of the target address read by the data bit of the current target layer sub-tree node is exchanged to an address bit of the current target layer sub-tree node until a target path corresponding to the target address with 2n bits is generated Each bit of the target address is sequentially transferred to a data bit of a corresponding target layer sub-tree node; and one bit of the target address read by the data bit of the current target layer sub-tree node is exchanged to an address bit of the current target layer sub-tree node until a target path corresponding to the target address with 2n bits is generated A processing module is configured to, when the target path is received, obtain data corresponding to each bit address in the target path according to a parallel mode reading rule of the data bit of the preset word length, and transfer the data corresponding to each bit address to an address bit of a root node in the binary tree structure through the preset quantum circuit, so as to complete the analysis processing of the data corresponding to the target path, wherein the parallel mode is to read data of a preset word length at a time within a preset time sequence.

5. The apparatus of claim 4, wherein, After the obtaining module, the device further includes: A transfer module is configured to read each bit of the target address in sequence through an address register, and to subject each bit of the target address read by the address register to a transfer operation by using a preset quantum circuit, wherein the preset quantum circuit includes an H gate, a CNOT gate, a controlled Z gate, a SWAP gate and a controlled SWAP gate, and the transfer operation includes one or more of data copying, data routing and data exchange.

6. A storage medium, characterized by The storage medium has a computer program stored therein, wherein the computer program is configured to implement the method described in any one of claims 1 to 3 when executed. 7.An electronic device comprising a memory and a processor, the electronic device characterized by, The memory has a computer program stored therein, and the processor is configured to execute the computer program to implement the method described in any one of claims 1 to 3.

Images