Micro LED structure and micro display panel

Abstract

A micro light emitting diode (LED) structure includes a mesa structure. The mesa structure further includes a first semiconductor layer having a first conductivity type, a light emitting layer formed on the first semiconductor layer, a second semiconductor layer formed on the light emitting layer, the second semiconductor layer having a second conductivity type different from the first conductivity type, a sidewall protection layer formed on a sidewall of the mesa structure, and a sidewall reflection layer formed on a surface of the sidewall protection layer. The first semiconductor layer further includes a first type semiconductor region and an ion implantation region formed around the first semiconductor region, the ion implantation region having a higher resistance than the semiconductor region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the field of light emitting diode technology, and more particularly to a micro light emitting diode (LED) structure and a micro display panel including the same. BACKGROUND

[0002] Inorganic micro light emitting diodes (also referred to as “micro-LEDs” or “p-LEDs”) are increasingly important due to their use in various applications including, for example, self-emissive micro-displays, visible light communications, and optogenetics. p-LEDs have better output performance than traditional LEDs due to better strain relaxation, improved light extraction efficiency, uniform current spreading, etc. p-LEDs are characterized by improved thermal effects, improved operation at higher current densities, better response rates, larger operating temperature ranges, higher resolutions, wider color gamut, higher contrast, and lower power consumption, etc. as compared to traditional LEDs.

[0003] p-LEDs include III-V epitaxial layers for forming a plurality of mesas. In certain p-LED designs, a space is needed to be formed between adjacent p-LEDs to avoid the diffusion of carriers in the epitaxial layer from one mesa to an adjacent mesa. The space formed between adjacent p-LEDs can reduce the effective light emitting area and lower the light extraction efficiency. Eliminating the space can increase the effective light emitting area, but this will cause the carriers in the epitaxial layer to laterally diffuse onto adjacent mesas and thus reduce the light emitting efficiency. Moreover, without the space between adjacent mesas, cross-talk between adjacent p-LEDs will occur, which will cause the p-LEDs to be less reliable or less accurate.

[0004] Furthermore, in some p-LED structures, small LED pixels with high current density will be more likely to experience red-shift, lower maximum efficiency, and non-uniform emission, which is typically caused by deteriorated electrical injection during fabrication. Moreover, the peak external quantum efficiency (EQE) and internal quantum efficiency (IQE) of p-LEDs are greatly reduced as the chip size decreases. The reduction in EQE and IQE is caused by non-radiative recombination at the quantum well sidewall that is not properly etched. The reduction in IQE is caused by poor current injection and electron leakage current of the p-LED. Improving the EQE and IQE requires optimizing the quantum well sidewall region to reduce the current density. SUMMARY

[0005] According to the present disclosure, a micro-LED structure is provided. The structure includes a mesa structure. The mesa structure further includes a first semiconductor layer having a first conductivity type, a light emitting layer formed on the first semiconductor layer, and a second semiconductor layer formed on the light emitting layer, the second semiconductor layer having a second conductivity type different from the first conductivity type. A bottom surface area of the first semiconductor layer is made larger than a bottom surface area of the second semiconductor layer, a bottom surface area of the second semiconductor layer is made larger than a top surface area of the second semiconductor layer, and a bottom surface area of the first semiconductor layer is made larger than a top surface area of the first semiconductor layer. The first semiconductor layer further includes a first type semiconductor region and an ion implantation region formed around the first semiconductor region, the ion implantation region having a higher electrical resistance than the semiconductor region.

[0006] Further, according to the present disclosure, a micro-display panel is provided. The micro-display panel includes a micro-LED array. The micro-LED array includes a first micro-LED structure and an integrated circuit (IC) backplane formed under the first micro-LED structure. The first micro-LED structure is electrically coupled to the IC backplane. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a schematic cross-sectional view of a micro-LED structure according to an exemplary embodiment of the present disclosure;

[0008] Figure 2 is a flowchart of a method for fabricating a micro-LED structure as Figure 1 shown in FIG. 1 according to an exemplary embodiment of the present disclosure;

[0009] Figure 3 is a cross-sectional view schematically showing steps of a method for implementing Figure 2 according to an exemplary embodiment of the present disclosure;

[0010] Figure 4 is a cross-sectional view schematically showing steps of a method for implementing Figure 2 according to an exemplary embodiment of the present disclosure;

[0011] Figure 5 is a cross-sectional view schematically showing steps of a method for implementing Figure 2 according to an exemplary embodiment of the present disclosure;

[0012] Figure 6 is a cross-sectional view schematically showing steps of a method for implementing Figure 2 according to an exemplary embodiment of the present disclosure;

[0013] Figure 7is a cross-sectional view schematically illustrating steps of a method for implementing Figure 2 an exemplary embodiment according to the present disclosure;

[0014] Figure 8 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 2 an exemplary embodiment according to the present disclosure;

[0015] Figure 9 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 2 an exemplary embodiment according to the present disclosure;

[0016] Figure 10 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 2 an exemplary embodiment according to the present disclosure;

[0017] Figure 11 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 2 an exemplary embodiment according to the present disclosure;

[0018] Figure 12 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 2 an exemplary embodiment according to the present disclosure;

[0019] Figure 13 is a schematic cross-sectional view of at least a portion of an exemplary microdisplay panel according to an exemplary embodiment of the present disclosure;

[0020] Figure 14 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 an exemplary embodiment according to the present disclosure;

[0021] Figure 15 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 an exemplary embodiment according to the present disclosure;

[0022] Figure 16 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 an exemplary embodiment according to the present disclosure;

[0023] Figure 17 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 an exemplary embodiment according to the present disclosure;

[0024] Figure 18is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure;

[0025] Figure 19 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure;

[0026] Figure 20 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure;

[0027] Figure 21 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure;

[0028] Figure 22 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure;

[0029] Figure 23 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure;

[0030] Figure 24 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure;

[0031] Figure 25 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure;

[0032] Figure 26 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure;

[0033] Figure 27 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure; and

[0034] Figure 28 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] Hereinafter, embodiments consistent with the present disclosure will be described with reference to the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0036] As discussed above, the prior art micro-LEDs can experience problems such as redshift, low maximum efficiency, non-uniform emission, etc. To address these problems, a micro-LED structure is provided in embodiments of the present invention. In accordance with the present invention, the micro-LED structure can be configured to have a top contact, a bottom contact, a top conductive layer, a sidewall protection layer, and a sidewall reflective layer. Figure 1 In some embodiments consistent with the present invention, the micro-LED structure includes a mesa structure 01, a top contact 02, a bottom contact 03, a top conductive layer 04, a sidewall protection layer 104, and a sidewall reflective layer 105. The mesa structure 01 further includes a first type semiconductor layer 101, a light emitting layer 102, and a second type semiconductor layer 103. The light emitting layer 102 is formed on top of the first type semiconductor layer 101. The second type semiconductor layer 103 is on top of the light emitting layer 102. In some embodiments, the first type and the second type refer to different conductive types. For example, the first type is P-type, while the second type is N-type. In another example, the first type is N-type, while the second type is P-type.

[0037] Still referring to Figure 1The bottom surface area of the first semiconductor layer 101 is made larger than the bottom surface area of the second semiconductor layer 103. In some embodiments, the bottom surface area of the second semiconductor layer 103 is made larger than the top surface area of the second semiconductor layer 103. The bottom surface area of the first semiconductor layer 101 is made larger than the top surface area of the first semiconductor layer 101. In some embodiments, the sidewalls of the first semiconductor layer 101, the light emitting layer 102, and the second semiconductor layer 103 are in the same plane in the present embodiment, such that the sidewalls are flat. In some embodiments, the light emitting layer 102 and the second semiconductor layer 103 are not in the same plane and the sidewalls are not flat. In some embodiments, the diameter of the second semiconductor layer 103 is smaller than the diameter of the light emitting layer 102. In some embodiments, the diameter of the first semiconductor layer 101 is smaller than the diameter of the light emitting layer 102. In some embodiments, the material of the first type semiconductor layer 101 includes at least one of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, p-AlGaN, etc. The material of the second type semiconductor layer 103 includes at least one of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-InGaN, n-AlGaN, etc. The light emitting layer 102 is formed of a quantum well layer. The material of the quantum well layer includes at least one of GaAs, InGaN, AlGaN, AlInP, GaInP, AlGaInP, etc. In some further embodiments, the thickness of the first type semiconductor layer 101 is larger than the thickness of the second type semiconductor layer 103, and the thickness of the light emitting layer 102 is smaller than the thickness of the first type semiconductor layer 101. In some embodiments, the thickness of the first type semiconductor layer 101 ranges from 700 nm to 2 μιη, and the thickness of the second type semiconductor layer 103 ranges from 100 nm to 200 nm. In some embodiments, the thickness of the quantum well layer is less than or equal to 30 nm. In some embodiments, the quantum well layer includes no more than three pairs of quantum wells.

[0038] In some embodiments, the first type semiconductor layer 101 includes one or more mirrors 1011. In some embodiments, the mirror 1011 is formed at the bottom surface of the first type semiconductor layer 101. In some embodiments, the mirror 1011 is formed inside the first type semiconductor layer 101. In some embodiments, the material of the mirror 1011 is a mixture of a dielectric material and a metallic material. In some further embodiments, the dielectric material includes SiO2or SiN xwherein “x” is a positive integer. In some embodiments, the metal material includes Au or Ag. In some embodiments, the plurality of mirrors 1011 are formed horizontally one after another in different horizontal planes in the first-type semiconductor layer 1011, thereby dividing the first-type semiconductor layer 101 into a plurality of layers.

[0039] In some embodiments, a top contact 02 is formed at a top surface of the second-type semiconductor layer 103. The conductive type of the top contact 02 is the same as the conductive type of the second-type semiconductor layer 103. For example, if the second type is N-type, the top contact 02 is an N-type contact; or if the second type is P-type, the top contact 02 is a P-type contact. In some embodiments, the top contact 02 is made of a metal or a metal alloy including at least one of AuGe, AuGeNi, etc. The top contact 02 is used to form an ohmic contact between the top conductive layer 04 and the second-type semiconductor layer 103, thereby optimizing the electrical properties of the micro-LED. In some embodiments, the diameter of the top contact 02 ranges from 20 nm to 50 nm, and the thickness of the top contact 02 ranges from 10 nm to 20 nm.

[0040] In some embodiments, the first-type semiconductor layer 101 includes a first-type semiconductor region 1012 and an ion-implanted region 1013. The first-type semiconductor region 1012 is formed directly on the bottom contact 03. The ion-implanted region 1013 is formed around the first-type semiconductor region 1012. In some embodiments, the electrical resistance of the ion-implanted region 1013 is greater than the electrical resistance of the first-type semiconductor region 101. The ion-implanted region 1013 is formed via an additional ion implantation process into the ion-implanted region 1013.

[0041] In some embodiments, the center of the bottom contact 03 is aligned with the center of the first-type semiconductor region 1012 along an axis perpendicular to the bottom surface of the first-type semiconductor region 101. In some further embodiments, the diameter of the ion-implanted region 1013 is greater than or equal to the diameter of the bottom contact 03. The diameter of the first-type semiconductor region 1012 is greater than or equal to the diameter of the bottom contact 03. And the diameter of the ion-implanted region 1013 is greater than the diameter of the first-type semiconductor region 1012. In some embodiments, the diameter of the first-type semiconductor region 1012 is less than or equal to three times the diameter of the bottom contact 03. In some embodiments, the diameter of the ion-implanted region 1013 is greater than twice the diameter of the first-type semiconductor region 1012. In some embodiments, the diameter of the ion-implanted region 1013 ranges from 500 nm to 1250 nm, and the diameter of the bottom contact 03 ranges from 20 nm to 500 nm.

[0042] In some embodiments, the ion implant region 1013 is of the same conductivity type as the first type semiconductor region 1012. In some further embodiments, the ion implant region 1013 includes at least one type of implanted ion. In some embodiments, the implanted ion is selected from one or more of the following ions: hydrogen, nitrogen, fluorine, oxygen, carbon, argon, phosphorus, boron, silicon, sulfur, arsenic, chlorine, and a metal ion. The metal ion is selected from one or more of the following ions: zinc, copper, indium, aluminum, nickel, titanium, magnesium, chromium, gallium, tin, antimony, tellurium, tungsten, tantalum, germanium, molybdenum, and platinum.

[0043] In some further embodiments, the first type semiconductor region 1012 has a thickness that is greater than or equal to the thickness of the ion implant region 1013. In some embodiments, the second type semiconductor region 103 has a thickness in the range of 100 nm to 200 nm, and the first type semiconductor region 1012 has a thickness in the range of 600 nm to 900 nm, and the ion implant region 1013 has a thickness in the range of 500 nm to 800 nm.

[0044] Still referring to Figure 1 In some embodiments, the micro-LED structure further includes a top conductor layer 04 covering a top surface of the second type semiconductor layer 103, and the top contact 02. The top conductor layer 04 is transparent and electrically conductive. In some embodiments, the top conductive layer 04 includes at least one of indium tin oxide (ITO) and fluorine-doped tin oxide (FTO).

[0045] In some embodiments, a bottom contact 03 is formed at a bottom surface of the first type semiconductor layer 101. The conductive type of the bottom contact 03 is the same as the conductive type of the first type semiconductor layer 101. For example, if the first type semiconductor layer 101 is P-type, then the bottom contact 03 is also P-type. Similarly, if the first type semiconductor layer 101 is N-type, then the bottom contact 03 is also N-type. In some embodiments, light is emitted from a top surface of the mesa structure 01. To this end, the diameter of the bottom contact 03 is made larger than the diameter of the top contact 02, and the diameter of the top contact 02 is made as small as possible so that the top contact 02 appears like a point on the top surface of the second type semiconductor layer 103. In some embodiments, the diameter of the bottom contact 03 is equal to or smaller than the diameter of the top contact 02. In some embodiments, the bottom contact 03 is configured to be connected to a bottom electrode, such as a contact pad in an IC backplane. In some embodiments, the diameter of the bottom contact 03 ranges from 20 nm to 1 pm. In some embodiments, the diameter of the bottom contact 03 ranges from 800 nm to 1 pm. In some embodiments, the center of the bottom contact 03 is aligned with the center of the top contact 02 along an axis perpendicular to the upper surface of the first type semiconductor region. In some embodiments, the center of the bottom contact 03, the center of the top contact 02, and the center of the first type semiconductor region are all aligned along an axis perpendicular to the upper surface of the first type semiconductor region. In some embodiments, the material of the bottom contact 03 comprises a transparent conductive material. In some further embodiments, the material of the bottom contact 03 comprises ITO or FTO. In some embodiments, the bottom contact 03 is opaque, and the material of the bottom contact is a conductive metal. In some embodiments, the material of the bottom contact comprises at least one of the following elements: Au, Zn, Be, Cr, Ni, Ti, Ag, and Pt.

[0046] Figure 2 is a flowchart of a method for fabricating a micro-LED structure consistent with embodiments of the present disclosure. Figures 3 to 12 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 2 It is contemplated that the disclosed fabrication method is not limited to the particular micro-LED structure shown in Figures 3 to 12 In some embodiments consistent with Figures 3 to 12 a method of fabricating the aforementioned micro-LED structure is described herein.

[0047] In some embodiments consistent with Figures 4 to 7 In some embodiments consistent with Figure 2 In some embodiments, the ion implantation region 1013 is formed via an ion implantation process. In some embodiments consistent with Figure 3 In some embodiments consistent withFigure 2 The epitaxial structure includes a first-type semiconductor layer 101, a light-emitting layer 102, and a second-type semiconductor layer 103. In some embodiments, the first-type semiconductor layer 101, the light-emitting layer 102, and the second-type semiconductor layer 103 are arranged in an order from top to bottom. In some embodiments, the epitaxial structure can be formed on the substrate 100 by any epitaxial growth process known in the art. In some further embodiments, the first semiconductor layer 101 includes one or more mirrors 1011. The mirror 1011 can be formed at a bottom surface of the first semiconductor layer 101.

[0048] In some embodiments consistent with Figure 4 The mask M is formed on the first-type semiconductor layer 101, thereby defining a preset first-type semiconductor region and a preset ion implantation region in the first-type semiconductor layer 103. More specifically, in some embodiments, in each mesa structure 01, the preset first-type semiconductor region is located underneath the bottom contact 03, as shown by the area between the dashed lines. In some embodiments, the preset ion implantation region surrounds the respective preset first-type semiconductor region, as shown by the area outside the dashed lines. The preset first-type semiconductor region is configured for forming the first-type semiconductor region 1012, and the preset ion implantation region is configured for forming the ion implantation region 103. Figure 4 Figure 4 The mask M is patterned to expose the preset ion implantation region. More specifically, in some embodiments, the mask M is patterned by an etching process. In some embodiments, after the etching process, the mask M above the preset first-type semiconductor region is retained, and the mask M above the preset ion implantation region is removed to expose the preset ion implantation region.

[0049] In some embodiments consistent with Figure 5 The mask M is patterned to expose the preset ion implantation region. More specifically, in some embodiments, the mask M is patterned by an etching process. In some embodiments, after the etching process, the mask M above the preset first-type semiconductor region is retained, and the mask M above the preset ion implantation region is removed to expose the preset ion implantation region.

[0050] In some embodiments consistent with Figure 6 ​In some consistent embodiments, ions are implanted into predetermined ion implantation regions. More specifically, in some embodiments, ions are implanted into a first-type semiconductor layer 101 to form ion implantation regions 1013. In some embodiments, the ion implantation process is performed using conventional ion implantation techniques, wherein the implanted ions include at least one of the following ions: hydrogen, nitrogen, fluorine, oxygen, carbon, argon, phosphorus, boron, silicon, sulfur, arsenic, chlorine, and metal ions. In some further embodiments, the metal ions include at least one of zinc, copper, indium, aluminum, nickel, titanium, magnesium, chromium, gallium, tin, antimony, tellurium, tungsten, tantalum, germanium, molybdenum, and platinum. In some embodiments, the implantation dose ranges from 10E12 to 10E16. In some embodiments, ions are also implanted into mirrors 1011 corresponding to each ion implantation region. In some further embodiments, the ion implantation process is performed prior to the deposition of the bottom contact 03. In some implementations, an ion implantation process is performed after the deposition of the bottom contact 03 to form an ion implantation region, and then the bottom contact 03 is deposited on a predetermined first type semiconductor region when another mask covers the ion implantation region. Figure 7 In some consistent implementations, the mask M is removed via a chemical etching process known in the art.

[0051] In Figure 8 In some consistent implementations, the bottom contact 03 is deposited on the surface of the first type semiconductor layer 101. Figure 2 Step 3 in the process. The bottom contact 03 is deposited using a chemical vapor deposition (CVD) or physical vapor deposition (PVD) process known in the art. In some further embodiments, a first patterned mask is provided to cover the entire surface of the mesa, wherein a portion of the top of the mesa is exposed during the deposition process. After deposition, the first patterned mask is removed by a chemical etching method.

[0052] In Figures 9 to 10 In some consistent implementations, the mesa structure is formed by etching the epitaxial structure. Figure 2 Step 4 in the process. Figure 9 In some consistent embodiments, the epitaxial structure is inverted to form a mesa structure 01, and the substrate 00 is removed from the mesa structure 01 using conventional separation processes known in the art to expose the top of the mesa structure 01. In conjunction with Figure 9 In some consistent implementations, the bottom of the second semiconductor layer 103 is positioned as the top surface of the second type semiconductor layer 103.

[0053] In some further embodiments, the mesa structure 01 is formed by etching the first type semiconductor layer 101, the light emitting layer 102 and the second type semiconductor layer 103 in sequence. The sidewall of the mesa is vertical or inclined with respect to a horizontal plane (e.g., the substrate 00). In some embodiments, the etching process is a dry etching process. In some embodiments, the etching process is a plasma etching process. In some embodiments, the sidewall of the mesa is flat, and the top surface of the mesa is made larger than the bottom surface.

[0054] In some embodiments consistent with Figure 11 , the top contact 02 is deposited on the second type semiconductor layer 103 (step 5) in Figure 2 . In a chemical vapor deposition process or a physical vapor deposition process, the top contact 02 is deposited on the top surface of the second type semiconductor layer 103. In some embodiments consistent with Figure 11 , the area of the top contact 02 is made as small as possible. More specifically, in some embodiments consistent with Figure 11 , the top contact 02 is a dot. In some embodiments consistent with Figure 12 , the top conductive layer 04 is formed on the mesa structure (step 6) in Figure 2 . More specifically, in some embodiments, the top conductive layer 04 is deposited on the second type semiconductor layer 103 as well as on the top and sidewall of the top contact 02, covering the exposed top surface of the second semiconductor layer 103 and the top contact 02. The deposition of the top conductive layer 04 is performed by a chemical vapor deposition method known in the art. In some embodiments consistent with Figure 13 , a micro display panel is provided. The micro display panel includes a micro LED array and an IC backplane 05 formed underneath the micro LED array. The micro LED array includes a plurality of the aforementioned micro LED structures. The micro LED structure is electrically coupled or connected to the IC backplane 05. In some embodiments, the length of the entire micro LED array is no more than 5 cm. The length of the backplane is larger than the length of the micro LED array. In some embodiments, the length of the backplane is no more than 6 cm. The area of the micro LED array is the effective display area. In some embodiments, the micro LED structure further includes a metal bonding structure. More specifically, the metal bonding structure includes a metal bonding layer or a connection hole. For example, as shown in Figure 13 , the metal bonding structure is a metal bonding layer 031, and the metal bonding layer 031 is coupled (e.g., connected or bonded) with the contact pad of the IC backplane 06. In some further embodiments, the top surface of the bottom metal bonding layer 031 is coupled (e.g., connected or bonded) with the bottom contact 03, and the bottom surface of the bottom metal bonding layer 031 is coupled (e.g., connected or bonded) with the contact pad of the IC backplane. In some embodiments, the top conductive layer 04 in the micro display panel covers the entire display panel. Still referring toFigure 13 The micro display panel further comprises a dielectric layer 08. The dielectric layer 08 is formed between adjacent mesa structures 01. The material of the dielectric layer 08 is non-conductive, such that adjacent micro-LEDs are electrically isolated. In some embodiments, the material of the dielectric layer comprises at least one of SiO2, Si3N4, Al2O3, AlN, HfO2, TiO2, and ZrO2.

[0055] In some further embodiments, a reflective structure 07 is formed in the dielectric layer 08 between adjacent mesa structures 01 to avoid cross-talk. In some further embodiments, a reflective structure 07 is formed in the dielectric layer 08 between adjacent mesa structures 01 to avoid cross-talk. The cross-sectional structure of the reflective structure 07 can be an inverted triangle, an inverted rectangle, an inverted trapezoid, or any other inverted shape structure. In some embodiments, an ion implantation region is formed in the second type semiconductor layer 103, and the space between adjacent mesa structures 01 can be formed as small as possible. Figure 14 is a flow chart of a method for manufacturing a micro display panel consistent with the embodiments shown in Figure 13 Figures 15 to 25 is a cross-sectional view schematically showing steps of a method for implementing Figure 14 It is contemplated that the disclosed manufacturing method is not limited to the specific micro-LED structure shown in Figures 15 to 28 In some embodiments consistent with Figures 15 to 28 a method of manufacturing the aforementioned micro display panel is described herein.

[0056] In some embodiments consistent with Figure 15 a substrate 00 having an epitaxial structure is provided (step 1) in Figure 14 More specifically, the epitaxial structure comprises a first type semiconductor layer 101, a light emitting layer 102, and a second type semiconductor layer 103. In some embodiments, the first type semiconductor layer 101, the light emitting layer 102, and the second type semiconductor layer 103 are arranged in an order from top to bottom. In some embodiments, the epitaxial structure can be formed on the substrate 00 by any epitaxial growth process known in the art. In some further embodiments, the first type semiconductor layer 101 comprises one or more mirrors 1011. The mirror 1011 is formed on a surface of the first type semiconductor layer 101.

[0057] In some embodiments consistent with Figures 16 to 19 an ion implantation region 1013 is formed in the second type semiconductor layer 101 via an ion implantation process (step 2) in Figure 14 In some embodiments consistent with Figure 16 ​In some embodiments consistent therewith, a mask M is formed over the first type semiconductor layer 101. More specifically, in some embodiments, a preset first type semiconductor region and a preset ion implant region are defined in the first type semiconductor layer 101. In some embodiments, the preset first type semiconductor region is under the bottom contact 03, and the preset ion implant region is around the preset first type semiconductor region. More specifically, in some embodiments consistent therewith, the preset first type semiconductor region is between the dashed lines, and the preset ion implant region is outside the dashed lines. The preset first type semiconductor region is configured to form the first type semiconductor region 1012, and the preset ion implant region is configured to form the ion implant region 103. In some embodiments consistent therewith, the mask M is patterned to expose the preset ion implant region. More specifically, the mask M is patterned by an etching process known in the art. After the etching process, the mask M over the preset first type semiconductor region is retained, and the mask M over the preset ion implant region is removed to expose the preset ion implant region. In some embodiments consistent therewith, ions are implanted into the preset ion implant region. More specifically, in some embodiments, ions are implanted into the first type semiconductor layer 101 to form the ion implant region 1013. The ion implant process is performed by ion implantation technology. In some embodiments consistent therewith, the implanted ions are selected from one or more of hydrogen, nitrogen, fluorine, oxygen, carbon, argon, phosphorus, boron, silicon, sulfur, arsenic, chlorine, and metal ions. In some embodiments, the metal ions are selected from one or more of zinc, copper, indium, aluminum, nickel, titanium, magnesium, chromium, gallium, tin, antimony, tellurium, tungsten, tantalum, germanium, molybdenum, and platinum. More specifically, in some further embodiments, the implanted dose ranges from 10E12 to 10E16. In some embodiments, ions are also implanted into each respective mirror 1011. Figure 16 In some embodiments consistent therewith, the preset second type semiconductor region is the region between the dashed lines, and the preset ion implant region is the region outside the dashed lines. The preset first type semiconductor region is configured to form the first type semiconductor region 1012, and the preset ion implant region is configured to form the ion implant region 103. In some embodiments consistent therewith, the mask M is patterned to expose the preset ion implant region. More specifically, the mask M is patterned by an etching process known in the art. After the etching process, the mask M over the preset first type semiconductor region is retained, and the mask M over the preset ion implant region is removed to expose the preset ion implant region. In some embodiments consistent therewith, ions are implanted into the preset ion implant region. More specifically, in some embodiments, ions are implanted into the first type semiconductor layer 101 to form the ion implant region 1013. The ion implant process is performed by ion implantation technology. In some embodiments consistent therewith, the implanted ions are selected from one or more of hydrogen, nitrogen, fluorine, oxygen, carbon, argon, phosphorus, boron, silicon, sulfur, arsenic, chlorine, and metal ions. In some embodiments, the metal ions are selected from one or more of zinc, copper, indium, aluminum, nickel, titanium, magnesium, chromium, gallium, tin, antimony, tellurium, tungsten, tantalum, germanium, molybdenum, and platinum. More specifically, in some further embodiments, the implanted dose ranges from 10E12 to 10E16. In some embodiments, ions are also implanted into each respective mirror 1011. Figure 17 In some embodiments consistent therewith, the mask M is patterned to expose the preset ion implant region. More specifically, the mask M is patterned by an etching process known in the art. After the etching process, the mask M over the preset first type semiconductor region is retained, and the mask M over the preset ion implant region is removed to expose the preset ion implant region. In some embodiments consistent therewith, ions are implanted into the preset ion implant region. More specifically, in some embodiments, ions are implanted into the first type semiconductor layer 101 to form the ion implant region 1013. The ion implant process is performed by ion implantation technology. In some embodiments consistent therewith, the implanted ions are selected from one or more of hydrogen, nitrogen, fluorine, oxygen, carbon, argon, phosphorus, boron, silicon, sulfur, arsenic, chlorine, and metal ions. In some embodiments, the metal ions are selected from one or more of zinc, copper, indium, aluminum, nickel, titanium, magnesium, chromium, gallium, tin, antimony, tellurium, tungsten, tantalum, germanium, molybdenum, and platinum. More specifically, in some further embodiments, the implanted dose ranges from 10E12 to 10E16. In some embodiments, ions are also implanted into each respective mirror 1011. Figure 18 In some embodiments consistent therewith, the mask M is patterned to expose the preset ion implant region. More specifically, the mask M is patterned by an etching process known in the art. After the etching process, the mask M over the preset first type semiconductor region is retained, and the mask M over the preset ion implant region is removed to expose the preset ion implant region. In some embodiments consistent therewith, ions are implanted into the preset ion implant region. More specifically, in some embodiments, ions are implanted into the first type semiconductor layer 101 to form the ion implant region 1013. The ion implant process is performed by ion implantation technology. In some embodiments consistent therewith, the implanted ions are selected from one or more of hydrogen, nitrogen, fluorine, oxygen, carbon, argon, phosphorus, boron, silicon, sulfur, arsenic, chlorine, and metal ions. In some embodiments, the metal ions are selected from one or more of zinc, copper, indium, aluminum, nickel, titanium, magnesium, chromium, gallium, tin, antimony, tellurium, tungsten, tantalum, germanium, molybdenum, and platinum. More specifically, in some further embodiments, the implanted dose ranges from 10E12 to 10E16. In some embodiments, ions are also implanted into each respective mirror 1011. Figure 18 In some embodiments consistent therewith, the implanted ions are selected from one or more of hydrogen, nitrogen, fluorine, oxygen, carbon, argon, phosphorus, boron, silicon, sulfur, arsenic, chlorine, and metal ions. In some embodiments, the metal ions are selected from one or more of zinc, copper, indium, aluminum, nickel, titanium, magnesium, chromium, gallium, tin, antimony, tellurium, tungsten, tantalum, germanium, molybdenum, and platinum. More specifically, in some further embodiments, the implanted dose ranges from 10E12 to 10E16. In some embodiments, ions are also implanted into each respective mirror 1011.

[0058] In some embodiments, the ion implant process is performed before the formation of the mesa structure formation. In some embodiments, the ion implant process is performed after the formation of the mesa structure and before the deposition of the bottom contact 03 to form the ion implant region 1013, and then the bottom contact 03 is deposited on the preset first type semiconductor region while another mask covers the ion implant region 1013. In some further embodiments, the ion implant process is performed before the deposition of the bottom contact 03 to form the ion implant region 1013, and then the bottom contact 03 is deposited on the mesa structure 01 while another mask covers the ion implant region 1013. In some embodiments, the ion implant process is performed after the deposition of the bottom contact to form the ion implant region, and then the bottom contact 03 is deposited on the first type semiconductor region while another mask covers the ion implant region.

[0059] In some embodiments consistent with Figure 19 , the mask M is removed from the first type semiconductor layer 101. In some embodiments, the mask M is removed by a chemical etching method known in the art.

[0060] In some embodiments consistent with Figure 4 , the bottom contact 03 and the bottom metal bonding layer 031 are deposited on the surface of the first type semiconductor layer 101 (step 3 in Figure 14 ). The bottom metal bonding layer 031 is deposited by a chemical vapor process or a physical vapor process known in the art. In some further embodiments, a first patterned mask is provided to cover the entire surface of the mesa, with a portion of the mesa top exposed during the deposition process. After deposition, the first patterned mask is removed by a chemical etching method.

[0061] In some embodiments consistent with Figure 21 , a bonding process is performed between the epitaxial structure and the IC backplane 06, and the substrate 00 is removed (step 4 in Figure 14 ). The epitaxial structure is first placed upside down. More specifically, in some embodiments, the bottom of the second semiconductor layer 103 is placed as the top surface of the second type semiconductor layer 103. In some embodiments, the metal bonding layer 031 is bonded with the contact pad of the IC backplane 06 via a metal bonding process. In some embodiments, the substrate 00 can be removed by a conventional separation process known in the art.

[0062] In some embodiments, the substrate 00 is removed prior to the bonding process via a conventional substrate separation process known in the art.

[0063] In some embodiments consistent with Figure 22 , a plurality of mesas are formed by etching the epitaxial structure (step 5 in Figure 14 ). More specifically, the mesas are formed by etching the first type semiconductor layer 101, the light emitting layer 102, and the second type semiconductor layer 103 in sequence. The sidewalls of the mesas are vertical or inclined with respect to the horizontal plane (e.g., the substrate 00). In some embodiments, the etching process is a dry etching process. In some embodiments, the etching process is a plasma etching process.

[0064] In some embodiments consistent with Figures 23 to 24 , a dielectric layer 08 is deposited on the substrate 00 (step 6 in Figure 14 ). More specifically, as shown in Figure 23 , the dielectric layer 08 is deposited on the top and sidewalls of the mesas and on the bottom contact 03, such that the dielectric layer 08 covers the mesas and the bottom contact 03. In some embodiments consistent with Figure 24In some further embodiments, the reflective structure 07 is formed in the dielectric layer 08 between adjacent mesa. In some embodiments, trenches are formed in the dielectric layer 08 between adjacent mesa by etching the dielectric layer 08 with a first protective mask. The first protective mask is formed on the mesa and the dielectric layer 08, exposing the trench region and thus protecting undesirable etched areas. In some embodiments, reflective material is filled into the trenches to form a reflective structure between adjacent mesa. In some embodiments, a second protective mask is formed on the mesa and the dielectric layer 08, exposing the trenches. In some embodiments, after the aforementioned trenches are etched, the protective mask is etched to a certain thickness and a portion of the protective mask is left during the filling of the reflective material to protect undesirable filled areas.

[0065] In Figure 25 In some consistent implementations, a top contact 02 is deposited on the platform structure 01. Figure 14 Step 7). In some further embodiments, the top contact 02 is deposited on the top surface of the second type semiconductor layer 103 via a chemical vapor deposition (CVD) or physical vapor deposition (PVD) process known in the art. In some embodiments, the area of ​​the top contact 03 is configured to be as small as possible. In some embodiments, the area of ​​the top contact 03 is formed as a dot. In some embodiments, a patterned mask is provided to cover the mesa structure 01 by exposing a portion of the surface of the second semiconductor layer 103. In some embodiments, the patterned mask is a patterned photoresist. In some further embodiments, material may be deposited on the surface of the second semiconductor layer 103 to form the top contact 03. Figure 26 Consistent implementation methods ( Figure 14 In step 8), a top conductive layer 04 is formed on the mesa structure 01 and the dielectric layer 08. More specifically, the top conductive layer 04 is deposited on the second type semiconductor layer 103, the top and sidewalls of the top contact 02, and the dielectric layer 08, covering the exposed top surfaces of the second semiconductor layer 103, the top contact 02, and the dielectric layer 08. The deposition of the top conductive layer 04 is performed by a chemical vapor deposition method known to those skilled in the art.

[0066] In Figure 27 In some consistent implementations, the diameter of the bottom contact is smaller than the diameter of the first type of semiconductor region.

[0067] In Figure 28In some embodiments where consistent, the metal bonding layer 031 is a connection hole 05 configured to connect the bottom contact to the IC backplane. In some embodiments, the connection hole 05 is filled with bonding metal. The top side of the connection hole 05 is connected to the bottom contact 03, and the bottom side of the connection hole 05 is connected to the IC backplane 06. In some embodiments, the top conductive layer 04 in the micro display panel is covered the entire display panel. In some embodiments, the bottom of the reflective structure 07 extends down below the bottom of the mesa structure 01.

[0068] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. The specification and examples are intended to be exemplary only and the true scope and spirit of the application is indicated by the following claims.

Claims

1. A micro light emitting diode (LED) structure comprising: a mesa structure comprising: a first semiconductor layer having a first conductivity type; a light emitting layer formed on the first semiconductor layer; a second semiconductor layer formed on the light emitting layer, the second semiconductor layer having a second conductivity type different from the first conductivity type; and a mirror formed on a bottom surface of the first semiconductor layer; wherein a bottom surface area of the first semiconductor layer is greater than each of: a top surface area of the first semiconductor layer, a bottom surface area of the second semiconductor layer, and a top surface area of the second semiconductor layer; and wherein the first semiconductor layer comprises: a semiconductor region; and an ion implant region formed around the semiconductor region, the ion implant region having a higher electrical resistance than the semiconductor region, and wherein the ion implant region is in contact with the mirror, wherein a thickness of the first semiconductor layer is greater than a thickness of the second semiconductor layer, wherein a thickness of the semiconductor region is greater than or equal to a thickness of the ion implant region, a diameter of the semiconductor region is greater than or equal to a diameter of a bottom contact, and a diameter of the ion implant region is greater than a diameter of the semiconductor region, wherein the diameter of the semiconductor region is less than or equal to three times the diameter of the bottom contact; and the diameter of the ion implant region is greater than two times the diameter of the semiconductor region.

2. The micro light emitting diode (LED) structure of claim 1, further comprising: a top contact formed on a top surface of the second semiconductor layer, the top contact having the second conductivity type; and a bottom contact formed on a bottom surface of the first semiconductor layer, the bottom contact having the first conductivity type. a center of the bottom contact, a center of the top contact, and a center of the semiconductor region are aligned along a same axis perpendicular to the bottom surface of the first semiconductor layer, and wherein a diameter of the ion implant region is greater than or equal to a diameter of the bottom contact.

3. The micro light emitting diode (LED) structure of claim 2, wherein, a top conductive layer formed on the second semiconductor layer and the top contact.

4. The micro light emitting diode (LED) structure of claim 2, further comprising: a top conductive layer formed on the second semiconductor layer and the top contact.

5. The micro light emitting diode (LED) structure of claim 2, further comprising: a thickness of the semiconductor region ranges from 600 nm to 900 nm, a thickness of the ion implant region ranges from 500 nm to 800 nm, a diameter of the ion implant region ranges from 500 nm to 1250 nm, and a diameter of the bottom contact ranges from 20 nm to 500 nm.

6. The micro light emitting diode (LED) structure of claim 1, wherein, the sidewall is flat.

7. The micro light emitting diode (LED) structure of claim 1, wherein, the sidewall is not flat.

8. The micro light emitting diode (LED) structure of claim 1, wherein, the ion implant region comprises at least one type of implanted ion.

9. The micro light emitting diode (LED) structure of claim 1, wherein, the implanted ion is selected from one or more of the following ions: hydrogen, nitrogen, fluorine, oxygen, carbon, argon, phosphorus, boron, silicon, sulfur, arsenic, chlorine, and a metal ion.

10. The micro light emitting diode (LED) structure of claim 9, wherein, the metal ion is selected from one or more of zinc, copper, indium, aluminum, nickel, titanium, magnesium, chromium, gallium, tin, antimony, tellurium, tungsten, tantalum, germanium, molybdenum, and platinum.

11. The micro light emitting diode (LED) structure of claim 10, wherein, a thickness of the first semiconductor layer ranges from 700 nm to 2 pm, and a thickness of the second semiconductor layer ranges from 100 nm to 200 nm.

12. The micro light emitting diode (LED) structure of claim 11, wherein, ​ 13. The micro light emitting diode (LED) structure of claim 1, wherein, The light emitting layer has a thickness less than a thickness of the first semiconductor layer.

14. The micro light emitting diode (LED) structure of claim 1, wherein, The light emitting layer is formed by a quantum well layer located between the first semiconductor layer and the second semiconductor layer.

15. The micro light emitting diode (LED) structure of claim 14, wherein, The quantum well layer has a thickness less than or equal to 30 nm.

16. The micro light emitting diode (LED) structure of claim 15, wherein, The quantum well layer includes three or less pairs of quantum wells.

17. The micro light emitting diode (LED) structure of claim 16, further comprising: A second mirror formed inside the first semiconductor layer.

18. A micro display panel comprising: a micro light emitting diode (LED) array comprising: a first micro light emitting diode (LED) structure according to claim 1, the first micro light emitting diode (LED) structure comprising a first mesa structure; and an integrated circuit (IC) backplane formed underneath the first micro light emitting diode (LED) structure, wherein the first micro light emitting diode (LED) structure is electrically coupled to the integrated circuit (IC) backplane.

19. The microdisplay panel of claim 18, wherein, The micro light emitting diode (LED) structure further comprises: a bottom contact, and a bottom metal bonding structure; wherein a top surface of the bottom metal bonding structure is coupled to the bottom contact and a bottom surface of the bottom metal bonding structure is coupled to the integrated circuit (IC) backplane.

20. The micro display panel of claim 19, wherein: the bottom metal bonding structure comprises a connection hole or a metal bonding layer, and the micro display panel further comprises a top conductive layer formed on a top surface of the first mesa structure.

21. The micro display panel of claim 18, further comprising: a second micro light emitting diode (LED) structure according to claim 1, the second micro light emitting diode (LED) structure comprising a second mesa structure; and a dielectric layer, wherein the second mesa structure is located adjacent to the first mesa structure, and wherein the dielectric layer is non-conductive and formed between the first mesa structure and the second mesa structure. A material of the dielectric layer comprises at least one of SiO2, Si3N4, Al2O3, AlN, HfO2, TiO2, and ZrO2.

22. The microdisplay panel of claim 21, wherein, The reflective structure does not contact the first mesa structure and the second mesa structure.

23. The micro display panel of claim 21, further comprising a reflective structure formed in the dielectric layer and between the first mesa structure and the second mesa structure, wherein, The reflective structure comprises:

24. The microdisplay panel of claim 23, wherein, a top surface aligned with top surfaces of the first mesa structure and the second mesa structure; and a bottom surface aligned with bottom surfaces of the first mesa structure and the second mesa structure. The top surfaces of the first mesa structure and the second mesa structure are separated by a distance less than or equal to 200 nm.

25. The microdisplay panel of claim 21, wherein, ​

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