Micro LED structure and micro display panel

Abstract

A micro light emitting diode (LED) structure includes a mesa structure. The mesa structure further includes a first semiconductor layer having a first conductivity type, a light emitting layer formed on the first semiconductor layer, and a second semiconductor layer formed on the light emitting layer, the second semiconductor layer having a second conductivity type different from the first conductivity type. A top surface area of the second semiconductor layer is greater than each of a bottom surface area of the first semiconductor layer, a top surface area of the first semiconductor layer, and a bottom surface area of the second semiconductor layer. The second semiconductor layer further includes a semiconductor region and an ion implantation region formed around the semiconductor region, the ion implantation region having a higher electrical resistance than the semiconductor region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the field of light emitting diode technology, and more particularly to a micro light emitting diode (LED) structure and a micro display panel including the same. BACKGROUND

[0002] Inorganic micro light emitting diodes (also referred to as “micro-LEDs” or “p-LEDs”) are increasingly important due to their use in various applications including, for example, self-emissive micro-displays, visible light communications, and optogenetics. p-LEDs have better output performance than traditional LEDs due to better strain relaxation, improved light extraction efficiency, uniform current spreading, etc. p-LEDs are characterized by improved thermal effects, improved operation at higher current densities, better response rates, larger operating temperature ranges, higher resolutions, wider color gamut, higher contrast, and lower power consumption, etc. as compared to traditional LEDs.

[0003] p-LEDs include III-V epitaxial layers for forming a plurality of mesas. In certain p-LED designs, a space is needed to be formed between adjacent p-LEDs to avoid the diffusion of carriers in the epitaxial layer from one mesa to an adjacent mesa. The space formed between adjacent p-LEDs can reduce the effective light emitting area and lower the light extraction efficiency. Eliminating the space can increase the effective light emitting area, but this will cause the carriers in the epitaxial layer to laterally diffuse onto adjacent mesas and thus reduce the light emitting efficiency. Moreover, without the space between adjacent mesas, cross-talk between adjacent p-LEDs will occur, which will cause the p-LEDs to be less reliable or less accurate.

[0004] Furthermore, in some p-LED structures, small LED pixels with high current density will be more likely to experience red-shift, lower maximum efficiency, and non-uniform emission, which is typically caused by deteriorated electrical injection during fabrication. Moreover, the peak external quantum efficiency (EQE) and internal quantum efficiency (IQE) of p-LEDs are greatly reduced as the chip size decreases. The reduction in EQE and IQE is caused by non-radiative recombination at the quantum well sidewall that is not properly etched. The reduction in IQE is caused by poor current injection and electron leakage current of the p-LED. Improving the EQE and IQE requires optimizing the quantum well sidewall region to reduce the current density. SUMMARY

[0005] According to the present disclosure, a micro LED structure is provided. The structure includes a mesa structure. The mesa structure further includes a first semiconductor layer having a first conductivity type, a light emitting layer formed on the first semiconductor layer, a second semiconductor layer formed on the light emitting layer, a sidewall protection layer formed on a sidewall of the mesa structure, and a sidewall reflection layer formed on a surface of the sidewall protection layer, the second semiconductor layer having a second conductivity type different from the first conductivity type. A top surface area of the second semiconductor layer is greater than each of a bottom surface area of the first semiconductor layer, a top surface area of the first semiconductor layer, and a bottom surface area of the second semiconductor layer. The second semiconductor layer further includes a semiconductor region and an ion implantation region formed around the semiconductor region, the ion implantation region having a higher electrical resistance than the semiconductor region.

[0006] Further, according to the present disclosure, a micro display panel is provided. The micro display panel includes a micro LED array. The micro LED array includes a first micro LED structure and an integrated circuit (IC) backplane formed under the first micro LED structure. The first micro LED structure is electrically connected to the IC backplane. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a schematic cross-sectional view of a micro LED structure according to an exemplary embodiment of the present disclosure;

[0008] Figure 2 is a flowchart of a method for manufacturing a micro LED structure as Figure 1 shown in FIG. 1 according to an exemplary embodiment of the present disclosure;

[0009] Figure 3 is a cross-sectional view schematically showing steps of a method for implementing Figure 2 according to an exemplary embodiment of the present disclosure;

[0010] Figure 4 is a cross-sectional view schematically showing steps of a method for implementing Figure 2 according to an exemplary embodiment of the present disclosure;

[0011] Figure 5 is a cross-sectional view schematically showing steps of a method for implementing Figure 2 according to an exemplary embodiment of the present disclosure;

[0012] Figure 6 is a cross-sectional view schematically showing steps of a method for implementing Figure 2 according to an exemplary embodiment of the present disclosure;

[0013] Figure 7 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 2 according to an example embodiment of the present disclosure;

[0014] Figure 8 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 2 according to an example embodiment of the present disclosure;

[0015] Figure 9 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 2 according to an example embodiment of the present disclosure;

[0016] Figure 10 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 2 according to an example embodiment of the present disclosure;

[0017] Figure 11 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 2 according to an example embodiment of the present disclosure;

[0018] Figure 12 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 2 according to an example embodiment of the present disclosure;

[0019] Figure 13 is a schematic cross-sectional view of at least a portion of an example micro display panel according to an example embodiment of the present disclosure;

[0020] Figure 14 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure;

[0021] Figure 15 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure;

[0022] Figure 16 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure;

[0023] Figure 17 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure;

[0024] Figure 18is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure;

[0025] Figure 19 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure;

[0026] Figure 20 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure;

[0027] Figure 21 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure;

[0028] Figure 22 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure;

[0029] Figure 23 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure;

[0030] Figure 24 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure;

[0031] Figure 25 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure;

[0032] Figure 26 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure;

[0033] Figure 27 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure; and

[0034] Figure 28 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 13 according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] Hereinafter, embodiments consistent with the present disclosure will be described with reference to the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0036] As discussed above, the prior art micro-LEDs can experience problems such as red-shift, low maximum efficiency, non-uniform emission, etc. To address these problems, a micro-LED structure is provided in embodiments of the present invention. In embodiments consistent with the present invention, the micro-LED structure includes a mesa structure 01, a top contact 02, a bottom contact 03, and a top conductive layer 04. The mesa structure 01 further includes a first type semiconductor layer 101, a light emitting layer 102, and a second type semiconductor layer 103. The light emitting layer 102 is formed on top of the first type semiconductor layer 101. The second type semiconductor layer 103 is on top of the light emitting layer 102. In some embodiments, the first type and the second type refer to different conductive types. For example, the first type is P-type, while the second type is N-type. In another example, the first type is N-type, while the second type is P-type. Figure 1

[0037] Figure 1 The top surface area of the second semiconductor layer 103 is made larger than the top surface area of the first semiconductor layer 102. In some embodiments, the top surface area of the second semiconductor layer 103 is made larger than the bottom surface area of the second semiconductor layer 102. The top surface area of the first semiconductor layer 103 is made larger than the bottom surface area of the first semiconductor layer 101. In some embodiments, the sidewalls of the first semiconductor layer 101, the light emitting layer 102, and the second semiconductor layer 103 are in the same plane in the present embodiment, such that the sidewalls are flat. In some embodiments, the light emitting layer 102 and the second semiconductor layer 103 are not in the same plane and the sidewalls are not flat. In some embodiments, the diameter of the second semiconductor layer 103 is smaller than the diameter of the light emitting layer 102. In some embodiments, the diameter of the first semiconductor layer 101 is smaller than the diameter of the light emitting layer 102.

[0038] ​​In some embodiments, the material of the first type semiconductor layer 101 includes at least one of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, p-AlGaN, etc. The material of the second type semiconductor layer 103 includes at least one of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-InGaN, n-AlGaN, etc. The light emitting layer 102 is formed by a quantum well layer. The material of the quantum well layer includes at least one of GaAs, InGaN, AlGaN, AlInP, GaInP, AlGaInP, etc. In some further embodiments, the thickness of the first type semiconductor layer 101 is greater than the thickness of the second type semiconductor layer 103, and the thickness of the light emitting layer 102 is less than the thickness of the first type semiconductor layer 101. In some embodiments, the thickness of the first type semiconductor layer 101 ranges from 700 nm to 2 pm, and the thickness of the second type semiconductor layer 103 ranges from 100 nm to 200 nm. In some embodiments, the thickness of the quantum well layer is less than or equal to 30 nm. In some embodiments, the quantum well layer includes no more than three pairs of quantum wells.

[0039] In some embodiments, the first type semiconductor layer 101 includes one or more mirrors 1011. In some embodiments, the mirror 1011 is formed at the bottom surface of the first type semiconductor layer 101. In some embodiments, the mirror 1011 is formed inside the first type semiconductor layer 101. In some embodiments, the material of the mirror 1011 is a mixture of a dielectric material and a metal material. In some further embodiments, the dielectric material includes SiO2or SiN x wherein "x" is a positive integer. In some embodiments, the metal material includes Au or Ag. In some embodiments, the plurality of mirrors 1011 is formed in the first type semiconductor layer 101 one after another in different horizontal planes, horizontally, thereby dividing the first type semiconductor layer 101 into a plurality of layers.

[0040] In some embodiments, the top contact 02 is formed at the top surface of the second type semiconductor layer 103. The conduction type of the top contact 02 is the same as the conduction type of the second type semiconductor layer 103. For example, if the second type is N-type, the top contact 02 is an N-type contact; or if the second type is P-type, the top contact 02 is a P-type contact. In some embodiments, the top contact 02 is made of a metal or a metal alloy including at least one of AuGe, AuGeNi, etc. The top contact 02 is used to form an ohmic contact between the top conductive layer 04 and the second type semiconductor layer 103, thereby optimizing the electrical properties of the micro-LED. In some embodiments, the diameter of the top contact 02 ranges from 20 nm to 50 nm, and the thickness of the top contact 02 ranges from 10 nm to 20 nm.

[0041] In some embodiments, the second-type semiconductor layer 103 includes a second-type semiconductor region 1031 and an ion-implanted region 1032. The second-type semiconductor region 1031 is formed directly underneath the top contact 02. The ion-implanted region 1032 is formed around the second-type semiconductor region 1031. In some embodiments, the electrical resistance of the ion-implanted region 1032 is greater than the electrical resistance of the second-type semiconductor region 1031. The ion-implanted region 1032 is formed via an additional ion implantation process into the ion-implanted region 1032. In some embodiments, the center of the top contact 02, the center of the bottom contact 03, and the center of the second-type semiconductor region 1031 are aligned along an axis that is perpendicular to the upper surface of the second-type semiconductor region 1031. In some further embodiments, the diameter of the ion-implanted region 1032 is greater than or equal to the diameter of the top contact 02. And the diameter of the second-type semiconductor region 1031 is greater than or equal to the diameter of the top contact 02. In some embodiments, the diameter of the second-type semiconductor region 1031 is less than or equal to three times the diameter of the top contact 02. In some embodiments, the conductivity type of the ion-implanted region 1032 is the same as the conductivity type of the second-type semiconductor region 1031. In some further embodiments, the ion-implanted region 1032 includes at least one type of implanted ion. In some embodiments, the implanted ion is selected from one or more of the following ions: hydrogen, nitrogen, fluorine, oxygen, carbon, argon, phosphorus, boron, silicon, sulfur, arsenic, chlorine, and a metal ion. The metal ion is selected from one or more of the following ions: zinc, copper, indium, aluminum, nickel, titanium, magnesium, chromium, gallium, tin, antimony, tellurium, tungsten, tantalum, germanium, molybdenum, and platinum. In some further embodiments, the diameter of the ion-implanted region 1032 is greater than the diameter of the second-type semiconductor region 1031. In some embodiments, the diameter of the ion-implanted region 1032 is greater than two times the diameter of the second-type semiconductor region 1031. Here, the diameter of the ion-implanted region 1032 ranges from 100 nm to 1200 nm; and the diameter of the top contact 02 ranges from 20 nm to 50 nm. The thickness of the second-type semiconductor region 1031 is greater than or equal to the thickness of the ion-implanted region 1032. In some embodiments, the thickness of the second-type semiconductor region 1031 ranges from 100 nm to 200 nm, and the thickness of the ion-implanted region 1032 ranges from 100 nm to 150 nm.

[0042] Still referring to Figure 1 In some embodiments, the micro-LED structure further includes a top conductor layer 04 that covers the top surface of the second-type semiconductor layer 103, and the top contact 02. The top conductor layer 04 is transparent and electrically conductive. In some embodiments, the top conductor layer 04 includes at least one of indium tin oxide (ITO) and fluorine-doped tin oxide (FTO).

[0043] In some embodiments, a bottom contact 03 is formed at a bottom surface of the first type semiconductor layer 101. The conductive type of the bottom contact 03 is the same as the conductive type of the first type semiconductor layer 101. For example, if the first type semiconductor layer 101 is P-type, then the bottom contact 03 is also P-type. Similarly, if the first type semiconductor layer 101 is N-type, then the bottom contact 03 is also N-type. In some embodiments, light is emitted from a top surface of the mesa structure 01. To this end, the diameter of the bottom contact 03 is made larger than the diameter of the top contact 02, and the diameter of the top contact 02 is made as small as possible so that the top contact 02 appears like a point on the top surface of the second type semiconductor layer 103. In some embodiments, the diameter of the bottom contact 03 is equal to or smaller than the diameter of the top contact 02. In some embodiments, the bottom contact 03 is configured to be connected to a bottom electrode, such as a contact pad in an IC backplane. In some embodiments, the diameter of the bottom contact 03 ranges from 20 nm to 1 pm. In some embodiments, the diameter of the bottom contact 03 ranges from 800 nm to 1 pm. In some embodiments, the center of the bottom contact 03 is aligned with the center of the top contact 02 along an axis perpendicular to the upper surface of the second type semiconductor region 1031. In some embodiments, the center of the bottom contact 03, the center of the top contact 02, and the center of the second type semiconductor region 1031 are all aligned along an axis perpendicular to the upper surface of the second type semiconductor region 1031. In some embodiments, the material of the bottom contact 03 comprises a transparent conductive material. In some further embodiments, the material of the bottom contact 03 comprises ITO or FTO. In some embodiments, the bottom contact 03 is opaque, and the material of the bottom contact is a conductive metal. In some embodiments, the material of the bottom contact comprises at least one of the following elements: Au, Zn, Be, Cr, Ni, Ti, Ag, and Pt.

[0044] Figure 2 is a flowchart of a method for fabricating a micro-LED structure consistent with embodiments of the present disclosure. Figures 3 to 12 is a cross-sectional view schematically illustrating steps of a method for implementing Figure 2 It is contemplated that the disclosed fabrication method is not limited to the particular micro-LED structure shown in Figures 3 to 12 In some embodiments consistent with Figures 3 to 12 a method of fabricating the aforementioned micro-LED structure is described herein.

[0045] In some embodiments consistent with Figure 3 an epitaxial structure ( Figure 2Step 1 in the process. The epitaxial structure includes a first type semiconductor layer 101, a light-emitting layer 102, and a second type semiconductor layer 103. In some embodiments, the first type semiconductor layer 101, the light-emitting layer 102, and the second type semiconductor layer 103 are arranged in a top-to-bottom order. In some embodiments, the epitaxial structure can be formed on the substrate 00 using any epitaxial growth process known in the art. In some further embodiments, the first semiconductor layer 101 includes one or more mirrors 1011. The mirrors 1011 may be formed at the bottom surface of the first semiconductor layer 101.

[0046] In Figure 4 In some consistent implementations, the mesa is formed by etching the epitaxial structure. Figure 2 (Step 2 in the process). A mesa is formed by sequentially etching a first type semiconductor layer 101, a light-emitting layer 102, and a second type semiconductor layer 103. In some embodiments, the sidewalls of the mesa are vertical or inclined relative to a horizontal plane (e.g., substrate 00). In some embodiments, the etching process includes a dry etching process. In some embodiments, the etching process includes a plasma etching process. In some embodiments, the sidewalls of the mesa are flat, and the top surface of the mesa is larger than the bottom surface.

[0047] In Figure 5 In some consistent implementations, the bottom contact 03 is deposited on the surface of the first type semiconductor layer 101. Figure 2 Step 3 in the process. The bottom contact 03 is deposited using a chemical vapor deposition (CVD) or physical vapor deposition (PVD) process known in the art. In some further embodiments, a first patterned mask is provided to cover the entire surface of the mesa, wherein a portion of the top of the mesa is exposed during the deposition process. After deposition, the first patterned mask is removed by a chemical etching method.

[0048] In Figures 6 to 10 In some consistent embodiments, the top contact 02 is deposited on the second type semiconductor layer 103 to form an ion implantation region 1032. Figure 2 Step 4 in the process. Figure 6 In some consistent implementations, the mesa is inverted to form the mesa structure 01 before the top contact 02 is deposited, and the substrate 00 is removed from the mesa structure 01 by a separation process to expose the top of the mesa structure 01. Figure 6 In some consistent embodiments, the bottom of the second semiconductor layer 103 is positioned as the top surface of the second type of semiconductor layer 103. In conjunction with... Figure 7 In some consistent embodiments, during chemical vapor deposition or physical vapor deposition processes, the top contact 02 is deposited on the top surface of the second type semiconductor layer 103. Figure 7In some consistent implementations, the area of ​​the top contact 02 is made as small as possible. More specifically, in conjunction with Figure 7 In some further implementations, the top contact 02 is a point.

[0049] In Figures 8 to 11 In some consistent implementations, the ion implantation region 1032 is formed via an ion implantation process. In conjunction with... Figure 8 In some consistent embodiments, a mask M is formed on the second type semiconductor layer 103. More specifically, in some embodiments, a predetermined second type semiconductor region and a predetermined ion implantation region are defined in the second type semiconductor layer 103. In some embodiments, the predetermined second type semiconductor region is below the top contact 02, and the predetermined ion implantation region surrounds the predetermined second type semiconductor region. More specifically, in conjunction with... Figure 7 In some consistent implementations, the predetermined second type semiconductor region is the region between the dashed lines, and the predetermined ion implantation region is the region outside the dashed lines. The predetermined second type semiconductor region is configured to form second type semiconductor region 1031, and the predetermined ion implantation region is configured to form ion implantation region 1032.

[0050] In Figure 9 In some consistent embodiments, the mask M is patterned to expose a predetermined ion implantation region. More specifically, the mask M is patterned using an etching process known in the art. After the etching process, the mask M over the predetermined second-type semiconductor region is retained, and the mask M over the predetermined ion implantation region is removed to expose the predetermined ion implantation region.

[0051] In Figure 10 In some consistent embodiments, ions are implanted into a predetermined ion implantation region. More specifically, in some embodiments, ions are implanted into a second type of semiconductor layer 103 to form an ion implantation region 1032. The ion implantation process is performed using ion implantation technology. Figure 10 In some consistent embodiments, the implanted ion is selected from one or more of hydrogen, nitrogen, fluorine, oxygen, carbon, argon, phosphorus, boron, silicon, sulfur, arsenic, chlorine, and metal ions. In some embodiments, the metal ion is selected from one or more of zinc, copper, indium, aluminum, nickel, titanium, magnesium, chromium, gallium, tin, antimony, tellurium, tungsten, tantalum, germanium, molybdenum, and platinum. More specifically, in some further embodiments, the implantation dose ranges from 10E12 to 10E16.

[0052] In some embodiments, the ion implantation process is performed after deposition of the top contact 02. In some embodiments, the ion implantation process is performed before deposition of the top contact 02 to form the ion implantation region 1032, and then the top contact 02 is deposited on the preset second type semiconductor region when another mask covers the ion implantation region 1032.

[0053] In some embodiments consistent with Figure 11 , the mask M is removed from the mesa structure. In some embodiments, the mask M is removed by a chemical etching method known in the art.

[0054] In some embodiments consistent with Figure 12 , the top conductive layer 04 is formed on the mesa structure (step 5) in Figure 2 . More specifically, in some embodiments, the top conductive layer 04 is deposited on the second type semiconductor layer 103 as well as on the top and sidewalls of the top contact 02, covering the exposed top surface of the second semiconductor layer 103 and the top contact 02. The deposition of the top conductive layer 04 is performed by a chemical vapor deposition method known in the art.

[0055] In some embodiments consistent with Figure 13 , a micro display panel is provided. The micro display panel includes a micro LED array and an IC backplane 05 formed underneath the micro LED array. The micro LED array includes a plurality of the aforementioned micro LED structures. The micro LED structure is electrically coupled or connected to the IC backplane 05. In some embodiments, the length of the entire micro LED array is no more than 5 cm. The length of the backplane is greater than the length of the micro LED array. In some embodiments, the length of the backplane is no more than 6 cm. The area of the micro LED array is the effective display area.

[0056] In some embodiments, the micro LED structure further includes a metal bonding structure. More specifically, the metal bonding structure includes a metal bonding layer or a connection hole. For example, as Figure 13 shown, the metal bonding structure is a connection hole 05, and the connection hole 05 is filled with a bonding metal. The top side of the connection hole 05 is connected with the bottom contact 03, and the bottom side of the connection hole 05 is connected with a contact pad 09 on the surface of the IC backplane 06. In some embodiments, the top conductive layer 04 in the micro display panel covers the entire display panel.

[0057] Still referring to Figure 13The micro display panel further comprises a dielectric layer 08. The dielectric layer 08 is formed between adjacent mesa structures 01. The material of the dielectric layer 08 is non-conductive, such that adjacent micro-LEDs are electrically isolated. In some embodiments, the material of the dielectric layer comprises at least one of SiO2, Si3N4, Al2O3, AlN, HfO2, TiO2, and ZrO2. In some further embodiments, a reflective structure 07 is formed in the dielectric layer 08 between adjacent mesa structures 01 to avoid crosstalk. In some embodiments, the reflective structure 07 does not contact the mesa structure 01. In some embodiments, the top surface of the reflective structure 07 is aligned with the top surface of the mesa structure 01, and the bottom surface of the reflective structure 07 is aligned with the bottom surface of the mesa structure 01. The cross-sectional structure of the reflective structure 07 can be triangular, rectangular, trapezoidal, or any other shaped structure. In some embodiments, an ion implantation region 1032 is formed in the second type semiconductor layer 103, and the space between adjacent mesa structures 01 can be formed as small as possible. In some embodiments, the bottom of the reflective structure 07 extends downward, below the bottom of the mesa structure 01.

[0058] Figure 14 is a flow chart of a method for manufacturing a micro display panel consistent with the embodiments shown in Figure 13 Figures 15 to 28 is a cross-sectional view schematically showing steps of a method for implementing Figure 14 . In Figures 15 to 28 , the mirror 1011 (shown in Figure 13 ) is not shown, only for the purpose of better illustrating the manufacturing method. This omission should not limit or affect the scope of the present disclosure. It is contemplated that the disclosed manufacturing method is not limited to the specific micro-LED structure shown in Figures 15 to 28 . In some embodiments consistent with Figures 15 to 28 , a method of manufacturing the aforementioned micro display panel is described herein.

[0059] In some embodiments consistent with Figure 15 , a substrate 00 (step 01 in Figure 14 ) having an epitaxial structure is provided. More specifically, the epitaxial structure comprises a first type semiconductor layer 101, a light emitting layer 102, and a second type semiconductor layer 103. In some embodiments, the first type semiconductor layer 101, the light emitting layer 102, and the second type semiconductor layer 103 are arranged in an order from top to bottom. In some embodiments, the epitaxial structure can be formed on the substrate 00 by any epitaxial growth process known in the art. In some further embodiments, the first type semiconductor layer 101 comprises one or more mirrors 1011. The mirror 1011 is formed on a surface of the first type semiconductor layer 101.

[0060] In some embodiments consistent with​Figure 16 In some embodiments consistent with the present disclosure, the plurality of mesas is formed by etching the epitaxial structure (step 02 in FIG. 1). More specifically, the mesas are formed by sequentially etching the first-type semiconductor layer 101, the light-emitting layer 102, and the second-type semiconductor layer 103. The sidewalls of the mesas are vertical or inclined with respect to a horizontal plane (e.g., the substrate 00). In some embodiments, the etching process is a dry etching process. In some embodiments, the etching process is a plasma etching process. Figure 14 In some embodiments consistent with the present disclosure, the bottom contact 03 is deposited on the surface of the mesas (step 03 in FIG. 1). More specifically, the bottom contact 03 is deposited by a chemical vapor deposition process or a conventional physical vapor deposition process. In some further embodiments, a first patterned mask is provided to cover the entire surface of the mesas, wherein a portion of the top of the mesas is exposed during the deposition process. In some embodiments, after the deposition process, the first patterned mask is removed by a chemical etching method, thereby forming the bottom contact on the first semiconductor layer 101.

[0061] Figure 17 In some embodiments consistent with the present disclosure, the dielectric layer 08 is deposited on the substrate 00 (step 04 in FIG. 1). More specifically, the dielectric layer 08 is deposited on the top and sidewalls of the mesas and on the bottom contact 03, such that the dielectric layer 08 covers the mesas and the bottom contact 08. Figure 14 In some embodiments consistent with the present disclosure, the connection hole 05 is formed in the dielectric layer 08 (step 05 in FIG. 1). More specifically, the connection hole 05 is formed in the dielectric layer 08 by etching the dielectric layer 08 with a second protective mask. The second protective mask is formed on the mesas and the dielectric layer 08, leaving the connection hole 05 exposed, thereby protecting the unwanted etching area.

[0062] Figure 18 In some further embodiments consistent with the present disclosure, the reflective structure 07 is formed in the dielectric layer 08 between adjacent mesas. In some embodiments, the reflective structure 07 is formed by etching the dielectric layer 08 between adjacent mesas with a first protective mask. The first protective mask is formed on the mesas and the dielectric layer 08, leaving the trench area exposed, thereby protecting the unwanted etching area. In some embodiments, a reflective material is filled into the trench to form the reflective structure between adjacent mesas. In some embodiments, a second protective mask is formed on the mesas and the dielectric layer 08, leaving the trench exposed. In some embodiments, after the aforementioned trench is etched, the protective mask is etched to a certain thickness and leaves part of the protective mask during the filling process of the reflective material to protect the unwanted filling area. In some further embodiments, the sidewalls of the reflective structure 07 are parallel to the adjacent sidewalls of the mesas. In some embodiments, the reflective structure 07 is formed after the connection hole 05 is formed. Figure 14 In some embodiments consistent with the present disclosure, the dielectric layer 08 is deposited on the substrate 00 (step 04 in FIG. 1). More specifically, the dielectric layer 08 is deposited on the top and sidewalls of the mesas and on the bottom contact 03, such that the dielectric layer 08 covers the mesas and the bottom contact 08.

[0063] Figure 18 In some further embodiments consistent with the present disclosure, the reflective structure 07 is formed in the dielectric layer 08 between adjacent mesas. In some embodiments, the reflective structure 07 is formed by etching the dielectric layer 08 between adjacent mesas with a first protective mask. The first protective mask is formed on the mesas and the dielectric layer 08, leaving the trench area exposed, thereby protecting the unwanted etching area. In some embodiments, a reflective material is filled into the trench to form the reflective structure between adjacent mesas. In some embodiments, a second protective mask is formed on the mesas and the dielectric layer 08, leaving the trench exposed. In some embodiments, after the aforementioned trench is etched, the protective mask is etched to a certain thickness and leaves part of the protective mask during the filling process of the reflective material to protect the unwanted filling area. In some further embodiments, the sidewalls of the reflective structure 07 are parallel to the adjacent sidewalls of the mesas. In some embodiments, the reflective structure 07 is formed after the connection hole 05 is formed.

[0064] In some embodiments consistent with the present disclosure, the dielectric layer 08 is deposited on the substrate 00 (step 04 in FIG. 1). More specifically, the dielectric layer 08 is deposited on the top and sidewalls of the mesas and on the bottom contact 03, such that the dielectric layer 08 covers the mesas and the bottom contact 08. Figures 19 to 21 Figure 14 In some embodiments consistent with the present disclosure, the connection hole 05 is formed in the dielectric layer 08 (step 05 in FIG. 1). More specifically, the connection hole 05 is formed in the dielectric layer 08 by etching the dielectric layer 08 with a second protective mask. The second protective mask is formed on the mesas and the dielectric layer 08, leaving the connection hole 05 exposed, thereby protecting the unwanted etching area.​​​​Figure 19 In some embodiments consistent with the present disclosure, holes 051 are first formed in the dielectric layer 08 to expose the bottom contacts 03 by etching the dielectric layer 08 on each bottom contact 03. In some embodiments, one bottom contact 03 is connected to one hole 051. In some embodiments consistent with the present disclosure, the holes 051 are filled with a bonding metal 05' to form the connection holes 05. More specifically, the bonding metal 05' is also deposited on the top surface of the dielectric layer 08. In some embodiments consistent with the present disclosure, the bonding metal 05' is deposited on the top surface of the dielectric layer 08 by a chemical vapor deposition process or a physical vapor deposition process. Figure 20 In some embodiments consistent with the present disclosure, the top portion of the bonding metal 05' is polished to expose the top of the dielectric layer 08 and form the connection holes 05 by a planarization process. In some embodiments, the planarization process includes a chemical mechanical polishing process. In some embodiments, the top portion of the bonding metal 05' is above the dielectric layer 08. Figure 21 In some embodiments consistent with the present disclosure, the top portion of the bonding metal 05' is polished to expose the top of the dielectric layer 08 and form the connection holes 05 by a planarization process. In some embodiments, the planarization process includes a chemical mechanical polishing process. In some embodiments, the top portion of the bonding metal 05' is above the dielectric layer 08.

[0065] In some embodiments consistent with the present disclosure, a bonding process is performed between the mesa structure 01 and the IC backplane 06, thereby removing the substrate 00 Figure 22 In some embodiments consistent with the present disclosure, the top contacts 02 are deposited on the mesa structure 01, forming ion implantation regions 1032 Figure 14 In some embodiments consistent with the present disclosure, the top contacts 02 are deposited on the mesa structure 01, forming ion implantation regions 1032 In some embodiments consistent with the present disclosure, the top contacts 02 are deposited on the mesa structure 01, forming ion implantation regions 1032

[0066] In some embodiments consistent with the present disclosure, the top contacts 02 are deposited on the mesa structure 01, forming ion implantation regions 1032 Figures 23 to 25 In some embodiments consistent with the present disclosure, the top contacts 02 are deposited on the mesa structure 01, forming ion implantation regions 1032 Figure 14 In some embodiments consistent with the present disclosure, the top contacts 02 are deposited on the mesa structure 01, forming ion implantation regions 1032 Figure 23 In some embodiments consistent with the present disclosure, the top contacts 02 are deposited on the mesa structure 01, forming ion implantation regions 1032 Figure 22 In some embodiments consistent with the present disclosure, the top contacts 02 are deposited on the mesa structure 01, forming ion implantation regions 1032

[0067] In some embodiments consistent with the present disclosure, ion implantation regions 1032 are formed via an ion implantation process. More specifically, the ion implantation process is further described below.

[0068] In some embodiments consistent with the present disclosure, a mask M is formed on the second type semiconductor layer 103, thereby defining a predetermined second type semiconductor region and a predetermined ion implantation region in the second type semiconductor layer 103. More specifically, in some embodiments, in each mesa structure 01, the predetermined second type semiconductor region is located under the top contact, as shown by the region between the dashed lines. In some embodiments, the predetermined ion implantation region surrounds the respective predetermined second type semiconductor region, as shown by the region outside the dashed lines. The predetermined second type semiconductor region is provided for forming the second type semiconductor region 1031, and the predetermined ion implantation region is provided for forming the ion implantation region 1032. Figure 24 Figure 24 In some embodiments consistent with the present disclosure, a mask M is formed on the second type semiconductor layer 103, thereby defining a predetermined second type semiconductor region and a predetermined ion implantation region in the second type semiconductor layer 103. More specifically, in some embodiments, in each mesa structure 01, the predetermined second type semiconductor region is located under the top contact, as shown by the region between the dashed lines. In some embodiments, the predetermined ion implantation region surrounds the respective predetermined second type semiconductor region, as shown by the region outside the dashed lines. The predetermined second type semiconductor region is provided for forming the second type semiconductor region 1031, and the predetermined ion implantation region is provided for forming the ion implantation region 1032. Figure 24

[0069] In some embodiments consistent with the present disclosure, a mask M is formed on the second type semiconductor layer 103, thereby defining a predetermined second type semiconductor region and a predetermined ion implantation region in the second type semiconductor layer 103. More specifically, in some embodiments, in each mesa structure 01, the predetermined second type semiconductor region is located under the top contact, as shown by the region between the dashed lines. In some embodiments, the predetermined ion implantation region surrounds the respective predetermined second type semiconductor region, as shown by the region outside the dashed lines. The predetermined second type semiconductor region is provided for forming the second type semiconductor region 1031, and the predetermined ion implantation region is provided for forming the ion implantation region 1032. Figure 25 In some embodiments consistent with the present disclosure, a mask M is formed on the second type semiconductor layer 103, thereby defining a predetermined second type semiconductor region and a predetermined ion implantation region in the second type semiconductor layer 103. More specifically, in some embodiments, in each mesa structure 01, the predetermined second type semiconductor region is located under the top contact, as shown by the region between the dashed lines. In some embodiments, the predetermined ion implantation region surrounds the respective predetermined second type semiconductor region, as shown by the region outside the dashed lines. The predetermined second type semiconductor region is provided for forming the second type semiconductor region 1031, and the predetermined ion implantation region is provided for forming the ion implantation region 1032.

[0070] Figure 26 In some embodiments consistent with the present disclosure, a mask M is formed on the second type semiconductor layer 103, thereby defining a predetermined second type semiconductor region and a predetermined ion implantation region in the second type semiconductor layer 103. More specifically, in some embodiments, in each mesa structure 01, the predetermined second type semiconductor region is located under the top contact, as shown by the region between the dashed lines. In some embodiments, the predetermined ion implantation region surrounds the respective predetermined second type semiconductor region, as shown by the region outside the dashed lines. The predetermined second type semiconductor region is provided for forming the second type semiconductor region 1031, and the predetermined ion implantation region is provided for forming the ion implantation region 1032.

[0071] In some embodiments consistent with the present disclosure, a mask M is formed on the second type semiconductor layer 103, thereby defining a predetermined second type semiconductor region and a predetermined ion implantation region in the second type semiconductor layer 103. More specifically, in some embodiments, in each mesa structure 01, the predetermined second type semiconductor region is located under the top contact, as shown by the region between the dashed lines. In some embodiments, the predetermined ion implantation region surrounds the respective predetermined second type semiconductor region, as shown by the region outside the dashed lines. The predetermined second type semiconductor region is provided for forming the second type semiconductor region 1031, and the predetermined ion implantation region is provided for forming the ion implantation region 1032. Figure 27 ​​​In some embodiments consistent with the present disclosure, the mask M is removed via a chemical etching process known in the art. In some embodiments, the ion implantation process is performed after deposition of the top contact 02. In some embodiments, the ion implantation process is first performed to form the ion implanted region 1032 prior to deposition of the top contact 02, and then the top contact 02 is deposited on the second type semiconductor region 1031 when another mask covers the ion implanted region 1032.

[0072] In some embodiments consistent with the present disclosure, the top conductive layer 04 is formed on the mesa structure 01 and the dielectric layer 08 (step 08 in FIG. 1). Figure 28 In some embodiments consistent with the present disclosure, the top conductive layer 04 is formed on the mesa structure 01 and the dielectric layer 08 (step 08 in FIG. 1). Figure 14 More specifically, the top conductive layer 04 is deposited on the second type semiconductor layer 103, the top and sidewalls of the top contact 02, and the dielectric layer 08, covering the exposed top surfaces of the second semiconductor layer 103, the top contact 02, and the dielectric layer 08. The deposition of the top conductive layer 04 is performed by a chemical vapor deposition method known to those skilled in the art.

[0073] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. The specification and examples are intended to be exemplary only and the true scope and spirit of the application is indicated by the following claims.

Claims

1. A miniature light-emitting diode (LED) structure, comprising: Mesa structure and top conductive layer, wherein the mesa structure includes: A first semiconductor layer having a first conductivity type; A light-emitting layer formed on the first semiconductor layer; and A second semiconductor layer is formed on the light-emitting layer, the second semiconductor layer having a second conductivity type different from the first conductivity type; Wherein, the top surface region of the second semiconductor layer is larger than each of the following: the bottom surface region of the first semiconductor layer, the top surface region of the first semiconductor layer, and the bottom surface region of the second semiconductor layer; and The second semiconductor layer includes: Semiconductor region; and An ion-implanted region is formed around the semiconductor region, the resistance of the ion-implanted region being higher than the resistance of the semiconductor region, and The top conductive layer is formed on the ion implantation region and the semiconductor region and is in contact with the ion implantation region. Wherein, the thickness of the first semiconductor layer is greater than the thickness of the second semiconductor layer. Wherein, the thickness of the semiconductor region is greater than or equal to the thickness of the ion-implanted region, the diameter of the semiconductor region is greater than or equal to the diameter of the top contact, and the diameter of the ion-implanted region is greater than the diameter of the semiconductor region. Wherein, the diameter of the semiconductor region is less than or equal to three times the diameter of the top contact; and the diameter of the ion implantation region is greater than twice that of the semiconductor region.

2. The micro light-emitting diode (LED) structure according to claim 1, further comprising: A top contact formed on the top surface of the second semiconductor layer, the top contact having the second conductivity type; as well as A bottom contact is formed on the bottom surface of the first semiconductor layer, the bottom contact having the first conductivity type.

3. The micro light-emitting diode (LED) structure according to claim 2, wherein, The centers of the bottom contact, the top contact, and the semiconductor region are aligned along the same axis perpendicular to the top surface of the second semiconductor layer, wherein the diameter of the ion implantation region is greater than or equal to the diameter of the top contact.

4. The micro light-emitting diode (LED) structure according to claim 2, further comprising: A top conductive layer is formed on the second semiconductor layer and the top contact.

5. The micro light-emitting diode (LED) structure according to claim 1, wherein, The tabletop structure includes flat or uneven sidewalls.

6. The micro light-emitting diode (LED) structure according to claim 1, wherein, The ion implantation region includes at least one type of implanted ion.

7. The micro light-emitting diode (LED) structure according to claim 6, wherein, The implanted ions are selected from one or more of the following ions: hydrogen, nitrogen, fluorine, oxygen, carbon, argon, phosphorus, boron, silicon, sulfur, arsenic, chlorine and metal ions.

8. The micro light-emitting diode (LED) structure according to claim 7, wherein, The metal ion is selected from one or more of zinc, copper, indium, aluminum, nickel, titanium, magnesium, chromium, gallium, tin, antimony, tellurium, tungsten, tantalum, germanium, molybdenum, and platinum.

9. The micro light-emitting diode (LED) structure according to claim 1, wherein, The thickness of the first semiconductor layer ranges from 700 nm to 2 μm, and the thickness of the second semiconductor layer ranges from 100 nm to 200 nm.

10. The micro light-emitting diode (LED) structure according to claim 1, wherein, The thickness of the semiconductor region ranges from 100 nm to 200 nm. The thickness of the ion implantation region ranges from 100 nm to 150 nm. The diameter of the ion implantation region ranges from 100 nm to 1200 nm, and The diameter of the top contact ranges from 20 nm to 50 nm.

11. The micro light-emitting diode (LED) structure according to claim 1, wherein, The thickness of the light-emitting layer is less than the thickness of the first semiconductor layer.

12. The micro light-emitting diode (LED) structure according to claim 1, wherein, The light-emitting layer is formed by a quantum well layer located between the first semiconductor layer and the second semiconductor layer.

13. The micro light-emitting diode (LED) structure according to claim 12, wherein, The thickness of the quantum well layer is less than or equal to 30 nm.

14. The micro light-emitting diode (LED) structure according to claim 12, wherein, The quantum well layer comprises three or fewer pairs of quantum wells.

15. The micro light-emitting diode (LED) structure according to claim 1, further comprising: A first reflector is formed on the bottom surface of the first semiconductor layer.

16. The micro light-emitting diode (LED) structure according to claim 15, further comprising: The second reflector is formed inside the first semiconductor layer.

17. A miniature display panel, comprising: A miniature light-emitting diode (LED) array, comprising: A first micro-light-emitting diode (LED) structure, the first micro-light-emitting diode (LED) structure being the micro-light-emitting diode (LED) structure according to claim 1, the first micro-light-emitting diode (LED) structure including a first mesa structure; and The integrated circuit (IC) backplane formed beneath the first micro-LED structure. The first micro LED structure is electrically connected to the backplane of the integrated circuit (IC).

18. The microdisplay panel according to claim 17, wherein, The first miniature light-emitting diode (LED) structure further includes: Connection hole The first side of the connection hole is connected to the bottom contact, and the second side of the connection hole is connected to the backplane of the integrated circuit (IC).

19. The microdisplay panel according to claim 17, wherein: The second miniature light-emitting diode (LED) structure is... According to claim 1, the second micro-LED structure includes a second mesa structure; and dielectric layer, The second platform structure is located adjacent to the first platform structure, and The dielectric layer is non-conductive and is formed between the first mesa structure and the second mesa structure.

20. The microdisplay panel according to claim 19, wherein, The dielectric layer is made of at least one of SiO2, Si3N4, Al2O3, AlN, HfO2, TiO2, and ZrO2.

21. The microdisplay panel of claim 19, further comprising a reflective structure formed in the dielectric layer and between the first mesa structure and the second mesa structure, wherein, The reflective structure does not contact the first platform structure or the second platform structure.

22. The micro display panel according to claim 21, wherein, The reflective structure has: A top surface aligned with the top surfaces of the first and second platform structures; as well as A bottom surface aligned with the bottom surfaces of the first and second countertop structures.

23. The micro display panel according to claim 19, wherein, The top surfaces of the first and second mezzanine structures are separated by a distance of less than or equal to 200 nm.

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