A method and circuit for high frame rate format conversion of high-resolution image data

Abstract

This invention discloses a high frame rate format conversion method for high-resolution image data, comprising: S101 acquiring two completely independent RAMs as image data buffers, each serving as a buffer. S102 connecting the two RAMs to ping-pong logic respectively. S103 inputting the image data into the group format conversion logic and generating control signals, address signals, and data signals for writing to the RAMs in the image data buffers. S104 generating control signals and address signals for reading the RAMs according to the driving timing requirements, and transmitting them to the ping-pong logic. S105 switching the read and write operation functions of the two RAMs using the ping-pong logic. S106 sending the switched image data to the data sequential reading logic, completing the grouping and rearrangement of the image data, ensuring synchronous high frame rate driving of multiple grouped image data. A high frame rate format conversion circuit for high-resolution image data is also disclosed, used for grouping and rearranging high-resolution image data.

Description

Technical Field

[0001] This invention relates to the field of image data format conversion technology, and in particular to a method and circuit for high frame rate format conversion of high-resolution image data. Background Technology

[0002] High-resolution image display devices are characterized by large data volumes. To ensure their high frame rate display capability, such as a frame rate of 200fps or higher, an effective driving method for display devices is to group the high-resolution display device into multiple low-resolution sub-image arrays and drive the sub-array images at a synchronous high frame rate, so that the display device can display high-resolution images at a high frame rate.

[0003] For example, a certain MEMS display chip has a resolution of 1024×1024 pixels. The chip integrates a display driver circuit, employing a grouped synchronous driving method to ensure a display frame rate of 200fps or higher. Inside this display chip, all pixels are grouped into 8 sub-image arrays, each with a resolution of 256 (width) × 512 (height). Figure 5 As shown. Therefore, when this MEMS display chip is working, it provides 8 data input channels to the outside, each data channel corresponding to a sub-array image. At the same time, due to the design of the driving circuit, the input data of each sub-array image cannot be arranged in a row-by-row scanning order from left to right and top to bottom. Instead, there is a specific order requirement. That is, the 256 columns of the sub-array image data are divided into 16 groups, and every 16 consecutive columns form a group. The data sent to the MEMS display chip must be arranged in a row-by-row group, that is: row 1 column 1 (group 1), row 1 column 17 (group 2), row 1 column 33 (group 3), ..., row 1 column 241 (group 16), row 1 column 2 (group 1), row 1 column 18 (group 2), ..., row 256 column 240 (group 15), row 256 column 256 (group 16).

[0004] Therefore, when driving high frame rates for this type of display device, it is necessary to both group and rearrange the image data, and also ensure the synchronous high frame rate driving of multiple grouped image data. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a method for converting high-resolution image data to a high frame rate format.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solution:

[0007] A method for high frame rate format conversion of high-resolution image data includes:

[0008] S101 acquires two completely independent RAMs as image data caches, and uses them as buffers respectively. The address bus, data bus, and control signals of each RAM are respectively connected to the corresponding RAM control logic.

[0009] S102 connects the two RAMs to the ping-pong logic respectively.

[0010] S103 inputs image data into the block format conversion logic and generates control signals, address signals, and data signals to be written to the RAM of the image data buffer. The block format conversion logic is used to convert the format of sequential image data in the input standard image format.

[0011] The S104 data sequential read logic generates control signals and address signals for reading RAM according to the drive timing requirements and transmits them to the ping-pong logic.

[0012] The S105 ping-pong logic control switches the read and write operations of the two RAMs, converting the RAM to be written into a read block and the RAM to be read into a write block.

[0013] The S106 ping-pong logic sends the image data of the RAM that has been switched to the read block to the data sequence read logic.

[0014] The S107 sequential read logic sends image data to the drive circuit interface of the display device.

[0015] Compared with the prior art, the present invention has the following advantages:

[0016] Two independent RAMs are used as image data buffers. These two RAMs operate in a ping-pong logic mode. At any given time, one RAM acts as a buffer for receiving data, storing the received image data, while the other RAM acts as an output data buffer, providing image data to the image display device. When writing data to the receiving RAM, the format of the externally input image data is converted, transforming the standard left-to-right, top-to-bottom sequential format data into a specific grouped data format to meet specific order requirements. When outputting data to the display device, the output is sequentially read from the RAM buffer. This process completes the grouping and rearrangement of image data, ensuring synchronous high-frame-rate driving of multiple grouped image data.

[0017] More preferably, S103 inputs image data into the packet format conversion logic and generates control signals, address signals, and data signals to be written to the RAM of the image data buffer, including:

[0018] S201 determines the number of asynchronous FIFOs to be used and the data depth of each FIFO by multiplication, and assigns a number to each FIFO.

[0019] S202 receives sequential image data and counts it, determines the row and column coordinates in the sequential image data, and writes the row and column coordinates into the corresponding FIFO for buffering, thus obtaining the buffered data.

[0020] S203 When the amount of cached data in the FIFO reaches its full capacity, the FIFO is started to read the cached data sequentially, and the cached data is counted and numbered for each row. The full capacity refers to the number of sub-images contained in each row of image data.

[0021] S204 generates RAM address signals and write control signals based on the read FIFO number and the count value of the read line.

[0022] S205 transmits the data signals read from the FIFO, the address signals from the RAM, and the write control signals to the ping-pong logic.

[0023] By adopting the above technical solution, and considering the specific order requirements of the input image data grouping structure, a multi-channel asynchronous FIFO parallel buffer storage structure is used to ensure fast and reliable temporary storage of input data.

[0024] More preferably, S201 determines the number of asynchronous FIFOs and the data depth of each FIFO using a product method, and numbers each FIFO, including:

[0025] S301 divides each sub-image in the image data into groups to obtain the number of groups.

[0026] S302 sets each column in the group quantity as 1 data channel to determine the number of data channels in the group quantity, thus obtaining the number of data channels.

[0027] S302 multiplies the number of packets by the number of data channels to obtain the number of asynchronous FIFOs used.

[0028] S304 determines that the data depth of the FIFO is at least twice the number of groups.

[0029] S305 assigns a number to each FIFO.

[0030] Using the above technical solution, the number of asynchronous FIFOs, data depth, and numbering are determined by the number of data channels and groups of the input image data, thereby converting the image data into formats and outputting them in sequence.

[0031] More preferably, the grouping format conversion logic is used to convert the sequential image data of the input standard image format, employing a two-layer FIFO method, including:

[0032] The first layer of S401 uses a multi-channel FIFO grouping method to divide sequential image data into multiple buffers and write them into their respective FIFOs to obtain multiple channels of image data.

[0033] The second layer of S402 uses a single FIFO to extract multiple image data from the first-layer multi-channel FIFO and write it into the second-layer FIFO.

[0034] Using the above technical solution, at the output end of the second-layer FIFO, the address signal and control signal required for writing to RAM are generated at the same time as reading the image data, so that the image data after group conversion can be accurately written into the corresponding RAM.

[0035] Further optimization involves using asynchronous FIFO grouping for the multi-channel FIFOs, where the input and output data widths of the FIFOs satisfy a preset ratio, which is the ratio of the input data width to the output data width.

[0036] By adopting the above technical solution, the ratio of the input and output data widths of the asynchronous FIFO is utilized to reassemble the data according to the required input data format. This allows the system to handle the needs of different image data format conversions simply by changing the ratio of the input and output data widths of the asynchronous FIFO and the logic of writing to the FIFO, thus providing high flexibility and real-time performance.

[0037] Further optimization involves the S105 ping-pong logic control switching the read / write operation functions of the two RAMs, converting the RAM to be written into a read block and the read RAM into a write block, including:

[0038] When the S601 packet format conversion logic generates a write control signal and sends it to the ping-pong logic, the ping-pong logic internally generates an imgwriting valid signal to indicate that a RAM write operation is in progress.

[0039] When the S602 sequential data reading generates a read control signal input to the ping-pong logic, the ping-pong logic internally generates an imgreading valid signal to indicate that a RAM write operation is in progress.

[0040] The S603 initiates the ping-pong logic. If both the write valid signal and the read valid signal are invalid, it generates mutually exclusive write select and read select signals to control the exchange of input control signals between the two RAMs.

[0041] By adopting the above technical solution, when writing data to one RAM, data is only read from another RAM, thereby ensuring that the input image data can be format converted and read / write controlled in sequence.

[0042] A high frame rate format conversion circuit for high-resolution image data is also disclosed, used for grouping and rearranging high-resolution image data, including: ping-pong logic, RAM A, and RAM B, wherein the ping-pong logic is connected to RAM A and RAM B respectively through RAM control logic. It also includes:

[0043] The group format conversion logic, connected to the ping-pong logic data, is used to convert the input sequential image data in the standard image format and generate RAM write control signals and address signals.

[0044] The data sequential read logic, connected to the ping-pong logic data, is used to generate control signals and address signals for reading RAM and transmit them to the ping-pong logic.

[0045] By adopting the above technical solution, while performing input data grouping format conversion, the real-time performance and reliability of image data format conversion and image data driving output are ensured. The data sequential reading logic generates control signals and address signals for reading RAM according to the driving timing requirements of the backend display device. The address signal is in sequential mode and is sent to the ping-pong logic. The ping-pong logic controls the switching of the read / write operations between the two RAMs. The ping-pong logic sends the image data read from the RAM to the sequential reading logic, which then sends it to the driving circuit interface of the display device. The grouping format conversion, ping-pong logic, and data sequential reading in the above circuit can be implemented in a single FPGA chip.

[0046] Further optimizations include the following grouping format conversion logic:

[0047] Write the selection logic and connect it to the data source, which is a data source that outputs standard format image data.

[0048] The first-level FIFO is a multi-path format conversion logic connected to the write selection logic. It is used to divide sequential image data into multiple buffers and write them into their respective FIFOs according to the image data format conversion requirements, thus obtaining multiple image data.

[0049] Multiplexer, connected to the first-level FIFO data.

[0050] The second-layer FIFO is a single format conversion logic, which is connected to the multiplexer and the data sequential reading logic respectively. The multiplexer is used to read out multiple image data and send them to the second-layer FIFO. The second-layer FIFO is used to generate write control signals and address signals.

[0051] The above technical solution employs a multi-channel asynchronous FIFO parallel buffer storage structure, which ensures fast and reliable temporary storage of input data and meets the characteristics of the input image data grouping structure.

[0052] Further optimization involves using FIFO read selection logic for sequential data reading.

[0053] By adopting the above technical solution, it is ensured that the converted image data is written or read out in a sequential manner, thus guaranteeing that the image data meets the specific sequential read / write requirements.

[0054] Further optimization includes: address signal generation logic, connected to the second-layer FIFO data, used to generate write address signals.

[0055] Using the above technical solution, the grouped image data and the generated write address signal are used together to generate RAM control logic signals, providing a sequence basis for the ping-pong logic to perform switching arbitration. Attached Figure Description

[0056] Figure 1 This is a schematic diagram of the circuit module connection in Example 2.

[0057] Figure 2 This is a schematic diagram of the method process in Example 1.

[0058] Figure 3 A schematic diagram illustrating the address generation rules for writing data to DDR3 SDRAM.

[0059] Figure 4 This is a schematic diagram of DDR3 SDRAM read / write control using ping-pong logic switching.

[0060] Figure 5 This is a schematic diagram of the sub-image array inside a MEMS display chip. Detailed Implementation

[0061] The following is in conjunction with the appendix Figures 1-5 The present invention will be described in further detail below.

[0062] Example 1

[0063] A method for high frame rate format conversion of high-resolution image data, such as Figure 1 As shown, it includes:

[0064] S101 acquires two completely independent RAMs as image data caches, and uses them as buffers respectively. The address bus, data bus, and control signals of each RAM are respectively connected to the corresponding RAM control logic.

[0065] S102 connects the two RAMs to the ping-pong logic respectively.

[0066] S103 inputs image data into the block format conversion logic and generates control signals, address signals, and data signals to be written to the RAM of the image data buffer. The block format conversion logic is used to convert the format of sequential image data in the input standard image format.

[0067] The S104 data sequential read logic generates control signals and address signals for reading RAM according to the drive timing requirements and transmits them to the ping-pong logic.

[0068] The S105 ping-pong logic control switches the read and write operations of the two RAMs, converting the RAM to be written into a read block and the RAM to be read into a write block.

[0069] The S106 ping-pong logic sends the image data of the RAM that has been switched to the read block to the data sequence read logic.

[0070] The S107 sequential read logic sends image data to the drive circuit interface of the display device.

[0071] Two independent RAMs are used as image data buffers. These two RAMs operate in a ping-pong logic mode. At any given time, one RAM acts as a buffer for receiving data, storing the received image data, while the other RAM acts as an output data buffer, providing image data to the image display device. When writing data to the receiving RAM, the format of the externally input image data is converted, transforming the standard left-to-right, top-to-bottom sequential format data into a specific grouped data format to meet specific order requirements. When outputting data to the display device, the output is sequentially read from the RAM buffer. This process completes the grouping and rearrangement of image data, ensuring synchronous high-frame-rate driving of multiple grouped image data.

[0072] Specifically, in this embodiment, S103 inputs image data into the packet format conversion logic and generates control signals, address signals, and data signals to be written to the RAM of the image data buffer, including:

[0073] S201 determines the number of asynchronous FIFOs to be used and the data depth of each FIFO by multiplication, and assigns a number to each FIFO.

[0074] S202 receives sequential image data and counts it, determines the row and column coordinates in the sequential image data, and writes the row and column coordinates into the corresponding FIFO for buffering, thus obtaining the buffered data.

[0075] S203 When the amount of cached data in the FIFO reaches its full capacity, the FIFO is started to read the cached data sequentially, and the cached data is counted and numbered for each row. The full capacity refers to the number of sub-images contained in each row of image data.

[0076] S204 generates RAM address signals and write control signals based on the read FIFO number and the count value of the read line.

[0077] S205 transmits the data signals read from the FIFO, the address signals from the RAM, and the write control signals to the ping-pong logic.

[0078] To address the specific order requirements of the input image data grouping structure, a multi-channel asynchronous FIFO parallel buffer storage structure is adopted, which ensures fast and reliable temporary storage of input data.

[0079] Specifically, in this embodiment, S201 determines the number of asynchronous FIFOs and the data depth of each FIFO using a product method, and assigns a number to each FIFO, including:

[0080] S301 divides each sub-image in the image data into groups to obtain the number of groups.

[0081] S302 sets each column in the group quantity as 1 data channel to determine the number of data channels in the group quantity, thus obtaining the number of data channels.

[0082] S302 multiplies the number of packets by the number of data channels to obtain the number of asynchronous FIFOs used.

[0083] S304 determines that the data depth of the FIFO is at least twice the number of groups.

[0084] S305 assigns a number to each FIFO.

[0085] The number of asynchronous FIFOs, data depth, and numbering are determined by the number of data channels and groups for the input image data, and the image data is then converted and output sequentially.

[0086] Specifically, in this embodiment, the grouping format conversion logic is used to convert the input sequential image data in standard image format, employing a two-layer FIFO method, including:

[0087] The first layer of S401 uses a multi-channel FIFO grouping method to divide sequential image data into multiple buffers and write them into their respective FIFOs to obtain multiple channels of image data.

[0088] The second layer of S402 uses a single FIFO to extract multiple image data from the first-layer multi-channel FIFO and write it into the second-layer FIFO.

[0089] At the output of the second-level FIFO, while reading image data, address signals and control signals required for writing to RAM are generated, so that the image data after group conversion can be accurately written into the corresponding RAM.

[0090] Specifically, in this embodiment, the multi-channel FIFO grouping is an asynchronous FIFO, and the input and output data widths of the FIFO satisfy a preset ratio, which is the ratio of the input data width to the output data width.

[0091] By utilizing the ratio of the input and output data widths of the asynchronous FIFO, the data can be reassembled according to the required input data format. This allows for the handling of different image data format conversion needs simply by changing the ratio of the input and output data widths of the asynchronous FIFO and the logic of writing to the FIFO, demonstrating high flexibility and real-time performance.

[0092] Specifically, in this embodiment, the S105 ping-pong logic controls the switching of read and write operations between the two RAMs, converting the RAM to be written into a read block and the read RAM into a write block, including:

[0093] When the S601 packet format conversion logic generates a write control signal and sends it to the ping-pong logic, the ping-pong logic internally generates an imgwriting valid signal to indicate that a RAM write operation is in progress.

[0094] When the S602 sequential data reading generates a read control signal input to the ping-pong logic, the ping-pong logic internally generates an imgreading valid signal to indicate that a RAM write operation is in progress.

[0095] The S603 initiates the ping-pong logic. If both the write valid signal and the read valid signal are invalid, it generates mutually exclusive write select and read select signals to control the exchange of input control signals between the two RAMs.

[0096] When writing data to one RAM, data is only read from another RAM, thus ensuring that the input image data can be formatted and read / write controlled in sequence.

[0097] Example 2

[0098] A high frame rate format conversion circuit for high-resolution image data is also disclosed, used for grouping and rearranging high-resolution image data, such as... Figure 1 As shown, it includes: ping-pong logic, RAM A, and RAM B. The ping-pong logic is connected to RAM A and RAM B respectively via RAM control logic. It also includes:

[0099] The group format conversion logic, connected to the ping-pong logic data, is used to convert the input sequential image data in the standard image format and generate RAM write control signals and address signals.

[0100] The data sequential read logic, connected to the ping-pong logic data, is used to generate control signals and address signals for reading RAM and transmit them to the ping-pong logic.

[0101] While performing input data grouping format conversion, the real-time performance and reliability of image data format conversion and image data driving output are ensured. The sequential data reading logic generates control signals and address signals for reading RAM based on the driving timing requirements of the backend display device. The address signal is in sequential mode and is sent to the ping-pong logic. The ping-pong logic controls the switching of read / write operations between the two RAMs. The ping-pong logic sends the image data read from the RAM to the sequential reading logic, which then sends it to the display device's driving circuit interface. The grouping format conversion, ping-pong logic, and sequential data reading in the above circuit can all be implemented within a single FPGA chip.

[0102] Specifically, the grouping format conversion logic in this embodiment includes:

[0103] Write the selection logic and connect it to the data source, which is a data source that outputs standard format image data.

[0104] The first-level FIFO is a multi-path format conversion logic connected to the write selection logic. It is used to divide sequential image data into multiple buffers and write them into their respective FIFOs according to the image data format conversion requirements, thus obtaining multiple image data.

[0105] Multiplexer, connected to the first-level FIFO data.

[0106] The second-layer FIFO is a single format conversion logic, which is connected to the multiplexer and the data sequential reading logic respectively. The multiplexer is used to read out multiple image data and send them to the second-layer FIFO. The second-layer FIFO is used to generate write control signals and address signals.

[0107] The multi-channel asynchronous FIFO parallel buffer storage structure is adopted, which not only ensures fast and reliable temporary storage of input data, but also meets the characteristics of the input image data grouping structure.

[0108] Specifically, in this embodiment, the data sequential reading logic uses FIFO read selection logic to ensure that the converted image data is written or read out in a sequential manner, thus ensuring that the image data meets the specific sequential read and write requirements.

[0109] Specifically, this embodiment also includes: address signal generation logic, which is connected to the second-layer FIFO data and is used to generate write address signals. The grouped image data and the generated write address signals are used together to generate RAM control logic signals, providing a sequence basis for the ping-pong logic to perform switching arbitration.

[0110] Please refer to Examples 1 and 2. Figure 1 , Figure 2 , Figure 3 , Figure 4 as well as Figure 5 Taking a 1024×1024 element MEMS display chip as an example, the process of the above conversion method and conversion circuit is described in detail below:

[0111] The circuit uses two independent DDR3 SDRAMs and one FPGA. The FPGA internally includes packet format conversion logic, ping-pong logic, data sequential read logic, and two sets of independent DDR3 SDRAM control logic. The ping-pong logic is connected to the packet format conversion logic and the data sequential read logic, and also to the two DDR3 SDRAM control logics. The two DDR3 SDRAM control logics are independently connected to the two DDR3 SDRAM control logics respectively; the ping-pong logic is connected to the external image data input interface circuit; and the data sequential read circuit is connected to the image data output interface circuit.

[0112] The group format conversion logic performs format conversion on sequential image data in the input standard image format. The core method uses a two-layer FIFO, as shown in the figure. The first layer uses a multi-channel FIFO grouping method, dividing the sequential image data into multiple buffers according to the image data format conversion requirements and writing them into their respective FIFOs to obtain multiple image data. The second layer uses a single FIFO method to retrieve the buffered multiple image data from the first-layer multi-channel FIFO according to the data sorting requirements after format conversion and write them into the second-layer FIFO. At the output of the second-layer FIFO, address signals and control signals required for writing to DDR3 SDRAM are generated simultaneously when reading image data, so that the multiple image data can be accurately written into the corresponding DDR3 SDRAM. The two FIFO layers are connected by a multiplexer.

[0113] The 1024×1024 element MEMS display device is divided into eight sub-image arrays of 256 (width) × 512 (height), such as Figure 5 As shown, each pixel has a grayscale resolution of 16 bits. In the sub-image array, 16 consecutive columns form a group, for a total of 16 groups. Each column within a group represents one data channel, resulting in a total of 16 data channels. Therefore, the number of asynchronous FIFOs in the first-level FIFO layer is 16 × 16 = 256. Since one row of image data contains four sub-array image data, the minimum storage depth of the FIFO is 8 data points.

[0114] To match the control of DDR3 SDRAM, the first-level FIFO uses an asynchronous FIFO, ensuring a 1:4 ratio between the input and output data widths (16 bits for input, 64 bits for output). The data grouping and writing logic for the first-level FIFO is implemented within the FIFO write selection logic. The principle is that image data of 1024 pixels per line is written to the corresponding FIFO in groups of 256 pixels each. Figure 2 As shown, the image data in columns 1, 257, 513, and 769 of each row are sequentially written to FIFO No. 1; the image data in columns 2, 258, 514, and 770 are sequentially written to FIFO No. 2; and so on, with columns 256, 512, 768, and 1024 sequentially written to FIFO No. 256. When any FIFO in the first-level multiplexed FIFOs holds four data points, the FIFO multiplexer will send a control signal to read out all four data points at once, each 64 bits wide, and write them to the second-level FIFO at the back end. This ensures that the multiple data output from the first-level multiplexed FIFOs is correctly written to a single FIFO in the second level.

[0115] The second-level FIFO uses a synchronous FIFO. When the number of data entries is not empty, the DDR3 SDRAM address signal generation logic uses a 20-bit image data count counter to generate the DDR3 SDRAM write address signal. The high 10 bits of the image data count counter correspond to the row address row_addr[9:0] of the image data, and the low 10 bits correspond to the column address col_addr[9:0]. The actual address generation rules for writing data to the DDR3 SDRAM are as follows: Figure 3 As shown, the lowest 3 bits of the address (bits [2:0]) remain 0, bit [3] is the highest bit of the row address (row_addr [9]), bits [12:4] are the lowest 9 bits of the row address (row_addr [8:0]), and bits [19:13] are the highest 7 bits of the column address (row_addr [9:3]). The DDR3 SDRAM address signal generation logic generates the DDR3 address signal and also generates the read control signal for the second-level FIFO. It reads data from the FIFO, and then uses the read packet image data and the generated DDR3 address signal together to generate the DDR3 SDRAM control logic signal, which is then fed into the ping-pong logic.

[0116] The sequential read logic, under the frame rate control of the 1024×1024 MEMS display device, initiates the generation of DDR3 SDRAM read data logic signals. The address signal is generated using a sequential counter. Then, the DDR3 SDRAM read control and address signals are output to the ping-pong logic. Finally, the DDR3 SDRAM data output by the ping-pong logic is sent to the data input interface of the display device at the back end.

[0117] The control logic for DDR3 SDRAM can be directly implemented using the dedicated IP core built into the FPGA.

[0118] The ping-pong logic is the arbitration logic for the read / write control and address / data channels of two DDR3 SDRAM chips, and its structure is shown in the diagram below. The core of the ping-pong logic consists of the following two lines:

[0119] The ping-pong switching of read / write control between the two DDR3 SDRAMs only occurs after the DDR3 SDRAM write control signal is generated, thus ensuring that the sequential data read logic can always read the latest updated, formatted image data from the DDR3 SDRAM.

[0120] The ping-pong switching of DDR3 SDRAM read / write control should occur when there is no read / write control on either of the two DDR3 SDRAMs, such as... Figure 4 As shown, when the DDR3 SDRAM write control signal generated by the packet format conversion logic is sent to the ping-pong logic, the ping-pong logic will generate an `imgwriting` valid signal to indicate that a DDR3 SDRAM write operation is in progress. When the DDR3 SDRAM read control signal generated by the data sequential read logic is sent to the ping-pong logic, the ping-pong logic will generate an `imgreading` valid signal to indicate that a DDR3 SDRAM write operation is in progress. After a frame of image data is written to the DDR3 SDRAM, the ping-pong logic is started to perform arbitration judgment. If both the `imgwriting` and `imgreading` signals are invalid at this time, mutually exclusive `write select` and `read select` signals are generated to control the exchange of input control signals between the two DDR3 SDRAMs, thereby ensuring that when data is written to DDR3 SDRAM A, data is only read from DDR3 SDRAM B, or vice versa.

[0121] In summary, based on the two embodiments above, we can conclude that the present invention has the following advantages:

[0122] First, two independent RAMs are used for ping-pong logic operations, allowing simultaneous image data format conversion and image data drive output, ensuring the real-time performance and reliability of both. Second, considering the characteristics of the input image data grouping structure, a multi-channel asynchronous FIFO parallel buffer storage structure is adopted. This ensures fast and reliable temporary storage of input data and utilizes the proportional relationship between the asynchronous FIFO input and output data widths to reassemble the data according to the required input data format. This allows for handling different image data format conversion needs simply by changing the asynchronous FIFO input / output data width ratio and the FIFO writing logic, providing high flexibility and real-time performance. Third, the format-converted image data is read out sequentially and output to the display device, reducing the design complexity of the display device driver circuit on the chip.

[0123] This specific embodiment is merely an explanation of the invention and is not intended to limit the invention. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but as long as they are within the scope of protection of this invention, they are protected by patent law.

Claims

1. A method for converting high-frame-rate image data to a high-resolution image format, characterized in that, include: S101 acquires two completely independent RAMs as image data caches, and uses them as buffers respectively. The address bus, data bus and control signal of each RAM are respectively connected to the corresponding RAM control logic. S102 connects the two RAMs to ping-pong logic respectively; S103 inputs image data into the group format conversion logic and generates control signals, address signals, and data signals to be written into the RAM of the image data buffer; the group format conversion logic is used to convert the input sequential image data of the standard image format; S103 inputs image data into the packet format conversion logic and generates control signals, address signals, and data signals to be written into the RAM of the image data buffer, including: S201 determines the number of asynchronous FIFOs and the data depth of each FIFO using a product method, and assigns a number to each FIFO; S202 receives sequential image data and counts it, determines the row and column coordinates in the sequential image data image, and writes the row and column coordinates into the corresponding FIFO for buffering to obtain buffered data; S203 When the number of cached data in the FIFO reaches the full limit, the FIFO is started to read the cached data sequentially, and the cached data is counted and numbered for each row; wherein, the full limit is the number of all sub-images contained in each row of image data; S204 generates the address signal and write control signal of the RAM based on the number of the FIFO read and the count value of the read line; S205 transmits the data signal read from the FIFO, the address signal of the RAM, and the write control signal to the ping-pong logic; The S104 data sequential read logic generates control signals and address signals for reading RAM according to the drive timing requirements, and transmits them to the ping-pong logic; The ping-pong logic control in S105 switches the read and write operation functions of the two RAMs, converting the RAM to be written into a read block and the RAM to be read into a write block; The ping-pong logic in S106 sends the image data of the RAM, which has been switched to a read block, to the data sequential read logic; The sequential reading logic described in S107 sends the image data to the drive circuit interface of the display device.

2. The high frame rate format conversion method for high-resolution image data according to claim 1, characterized in that, S201 determines the number of asynchronous FIFOs and the data depth of each FIFO using a product method, and assigns a number to each FIFO, including: S301 divides each sub-image in the image data into groups to obtain the number of groups; S302 sets each column in the number of groups as 1 data channel to determine the number of data channels in the number of groups, and obtains the number of data channels; S302 multiplies the number of packets by the number of data channels to obtain the number of asynchronous FIFOs used; S304 determines that the data depth of the FIFO is at least twice the number of packets; S305 assigns a number to each FIFO.

3. The high frame rate format conversion method for high-resolution image data according to claim 1, characterized in that, The grouping format conversion logic is used to convert the input sequential image data in a standard image format, employing a two-layer FIFO method, including: The first layer of S401 uses a multi-channel FIFO grouping method to divide sequential image data into multiple buffers and write them into their respective FIFOs to obtain multi-channel image data; The second layer of S402 uses a single FIFO method to extract the multi-channel image data from the first-layer multi-channel FIFO and write it into the second-layer FIFO.

4. The high frame rate format conversion method for high-resolution image data according to claim 3, characterized in that, The multi-channel FIFO grouping is an asynchronous FIFO, and the input and output data widths of the FIFO satisfy a preset ratio, which is the ratio of the input data width to the output data width.

5. The high frame rate format conversion method for high-resolution image data according to claim 3, characterized in that, The ping-pong logic control in step S105 switches the read / write operation functions of the two RAMs, converting the RAM to be written into a read block and the RAM to be read into a write block, including: When the packet format conversion logic generates a write control signal and sends it to the ping-pong logic, the ping-pong logic generates an imgwriting valid signal to indicate that a RAM write operation is in progress. S602 When the sequential reading of data generates a read control signal that is input to the ping-pong logic, the ping-pong logic generates an imgreading valid signal to indicate that a RAM write operation is in progress. S603 initiates the ping-pong logic. If both the write valid signal and the read valid signal are invalid, it generates mutually exclusive write select and read select signals to control the exchange of input control signals between the two RAMs.

6. A high frame rate format conversion circuit for high-resolution image data, used for grouping and rearranging high-resolution image data, characterized in that, include: Ping-pong logic, RAM A, and RAM B, wherein the ping-pong logic is connected to RAM A and RAM B respectively via RAM control logic; and also includes: The group format conversion logic, connected to the ping-pong logic data, is used to convert the input sequential image data of the standard image format and generate RAM write control signals and address signals. The grouping format conversion logic includes: Write selection logic and connect it to the data source, which is a data source that outputs standard format image data; The first-level FIFO is a multi-path format conversion logic, which is data-connected to the write selection logic. It is used to divide sequential image data into multiple buffers and write them into their respective FIFOs according to the image data format conversion requirements to obtain multiple image data. A multiplexer for data transfer, connected to the first-layer FIFO data; The second-layer FIFO is a single format conversion logic, which is connected to the multiplexer and the data sequential reading logic respectively. The multiplexer is used to read out the multiple image data and send it to the second-layer FIFO. The second-layer FIFO is used to generate write control signals and address signals. The data sequential read logic, connected to the ping-pong logic data, is used to generate control signals and address signals for reading RAM and transmit them to the ping-pong logic.

7. The high frame rate format conversion circuit for high-resolution image data according to claim 6, characterized in that, The data sequential reading logic uses FIFO read selection logic.

8. The high frame rate format conversion circuit for high-resolution image data according to claim 6, characterized in that, Also includes: The address signal generation logic is connected to the second-layer FIFO data and is used to generate write address signals.

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