Data encoding, decoding method, device and communication system

Abstract

The present application discloses data transmission, encoding method, decoding method, device, equipment and storage medium. The data encoding method comprises: a first circuit receives a first data stream transmitted by a second circuit through an Ethernet interface, the first data stream is obtained by encoding the original data using an RS code; the first circuit performs FEC encoding on the first data stream again to obtain a second data stream. The present application provides a cascade encoding method, which makes the gain higher, simplifies the conversion process of the FEC code type, reduces the time delay and device power consumption consumed when converting the FEC code type, and increases the distance and speed at which data can be transmitted.

Description

[0001] This application is a divisional application. The application number of the original application is 201980096406.5, and the original application date is July 15, 2019. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to data transmission, encoding, decoding methods, devices, equipment and storage media. Background Art

[0003] Forward error correction (FEC) codes can provide error correction protection for data in transmission, thereby increasing the data transmission rate and transmission distance in the channel. In the process of data transmission using FEC codes, the sending device can use a specific FEC code type to encode the original data and then send the encoded data to the receiving device. The receiving device can use the same FEC code type to decode the received data to obtain the original data.

[0004] In some scenarios, the FEC code type may need to be converted during data transmission. For example, in order to adapt to high-speed and / or long-distance data transmission, when the original FEC code type used by the original data transmission interface cannot meet the data transmission requirements, the FEC code type needs to be converted so that the original FEC code type is replaced with a higher-gain FEC code type. However, the FEC code type conversion process often increases the delay of the data transmission process and the power consumption of the data transmission equipment, thereby affecting the data transmission efficiency.

[0005] In addition, as the Ethernet interface is widely used in the world for data transmission, with the rapid increase in speed, FEC plays an increasingly important role in Ethernet. With the continuous increase in speed and transmission distance, the requirements for FEC are also getting higher and higher. Summary of the invention

[0006] The embodiments of the present application provide a data transmission, encoding, decoding method, device, equipment and storage medium to solve the problems in the related art. The technical solution is as follows:

[0007] In the first aspect, the embodiment of the present application provides a data transmission method, including: a first chip receives a first data stream sent by a second chip; the first data stream is a data stream encoded by a first forward error correction FEC code type; the first chip encodes the first data stream at least once to obtain a second data stream; wherein the second data stream is a cascaded FEC code stream encoded by at least the first FEC code type and the second FEC code type; the first chip sends the second data stream to a third chip. It can be seen that for the first data stream encoded by the first FEC code type sent by the second chip to the first chip, the first chip does not need to first decode the first data stream by using the first FEC code type and then re-encode the original data into a higher gain FEC code type, but can use at least the second FEC code type to encode at least once on the basis of the first data stream, so as to obtain a second data stream cascaded by at least the first FEC code type and the second FEC code type to achieve a higher gain. Therefore, the conversion process of the FEC code type is simplified, the time delay and device power consumption consumed when the FEC code type is converted are reduced, and the data transmission efficiency is improved.

[0008] In combination with any implementation of the first aspect, in a first possible implementation of the first aspect, the first FEC code type is specifically: RS code, BCH code, Staircase code, LDPC code, Turbo code or TPC. It can be seen that the first chip can support encoding to obtain a cascaded FEC code based on multiple different first FEC code types.

[0009] In combination with any implementation of the first aspect, in a second possible implementation of the first aspect, the second FEC code type is specifically: BCH code, RS code, Staircase code, LDPC code, Turbo code or TPC. It can be seen that the first chip can support encoding a cascade FEC code based on the first FEC code type according to a plurality of different second FEC code types.

[0010] In combination with any implementation of the first aspect, in a third possible implementation of the first aspect, the first chip encodes the first data stream at least once more to form a second data stream, including: the first chip distributes the first data stream into n third data streams; wherein data of the same codeword block in the first data stream is distributed to different third data streams; the first chip encodes the multiple third data streams at least once more to form the second data stream. It can be seen that data in the same codeword block in the first data stream can be encoded into multiple different codeword blocks in the second data stream, so that the cascaded FEC code has a stronger error correction capability.

[0011] In combination with the third implementation of the first aspect, in a fourth possible implementation of the first aspect, the k codeword blocks identified from the first data stream are distributed to n third data streams, and the data belonging to the k codeword blocks in each of the third data streams is encoded into a codeword block in the second data stream; wherein the total amount of data contained in the k codeword blocks in the first data stream is equal to the amount of effective load data contained in the n codeword blocks in the second data stream. It can be seen that since the effective load in the n second codeword blocks is the total data in the k codeword blocks, the n second codeword blocks can be directly decoded into the original data according to the second FEC code type and the first FEC code type, which facilitates the decoding operation of the first FEC code type and the second FEC code type on the same chip.

[0012] In combination with the third implementation of the first aspect, in a fifth possible implementation of the first aspect, the data in the first data stream is distributed according to FEC symbol blocks, and the data of the same FEC symbol block in the first data stream is encoded in the same codeword block in the second data stream. It can be seen that the first chip can distribute and process the first data stream with the symbol block as the granularity.

[0013] In combination with the third implementation of the first aspect, in a sixth possible implementation of the first aspect, the data in the first data stream is distributed according to a bit stream, and the data in the third data stream is encoded according to a bit stream. It can be seen that the first chip can distribute and process the first data stream with bits as the granularity.

[0014] In combination with any implementation of the first aspect, in a seventh possible implementation of the first aspect, the first chip and the second chip are located in a first data transmission device, the third chip is located in a second data transmission device, the first chip is an electrical chip, the second chip is a device using an Ethernet interface, and the third chip is an electrical chip. It can be seen that the first data transmission device can encode the first data stream of the first FEC code type output by the device using the Ethernet interface into a second data stream cascaded by at least the first FEC code type and the second FEC code type through the electrical chip and then send it to the second data transmission device, thereby realizing data transmission between the first data transmission device and the second data transmission device through cascaded FEC codes.

[0015] In combination with any possible implementation manner of the first aspect, in an eighth possible implementation manner of the first aspect, the first data stream is transmitted between the second chip and the first chip through a physical path with interference. It can be seen that for the first data stream that generates bit errors when transmitted in the physical path with interference, the first chip can directly encode the first data stream at least once to form a cascaded second data stream without decoding and correcting the first data stream.

[0016] In the second aspect, the embodiment of the present application provides a data transmission method, including: a first chip receives a second data stream sent by a second chip; the second data stream is a cascaded FEC code stream encoded by at least a first FEC code type and a second FEC code type; the first chip decodes the second data stream at least once to form a first data stream; the first data stream is a data stream encoded by the first FEC code type; the first chip sends the first data stream to a third chip. It can be seen that for the second data stream sent by the second chip to the first chip, which is at least a cascade of the first FEC code type and the second FEC code type, the first chip can use other FEC code types except the first FEC code type to decode the second data stream, form a first data stream encoded by the first FEC code type and send it to the third chip, without having to decode the second data stream into original data and then re-encode it into a data stream of the first FEC code type to send to the third chip. Therefore, the conversion process of the FEC code type is simplified, the delay and device power consumption consumed when the FEC code type is converted are reduced, and the data transmission efficiency is improved.

[0017] In combination with any possible implementation manner of the second aspect, in a first possible implementation manner of the second aspect, the first FEC code type is specifically: RS code, BCH code, Staircase code, LDPC code, Turbo code or TPC.

[0018] In combination with any possible implementation of the second aspect, in a second possible implementation of the second aspect, the second FEC code type is specifically: BCH code, RS code, Staircase code, LDPC code, Turbo code or TPC. It can be seen that the first chip can support decoding of multiple different second FEC code types.

[0019] In combination with any possible implementation of the second aspect, in a third possible implementation of the second aspect, the first data stream is used to be decoded by the third chip according to the first FEC code type. It can be seen that the first chip can support cascaded FEC code decoding and output a plurality of different first FEC code types.

[0020] In combination with any possible implementation of the second aspect, in a fourth possible implementation of the second aspect, the second chip is located in the first data transmission device, the first chip and the third chip are located in the second data transmission device, the first chip is an electrical chip, the second chip is a chip, and the third chip is a device using an Ethernet interface. It can be seen that for the second data stream formed by at least the cascade of the first FEC code type and the second FEC code type sent by the first data transmission device to the second data transmission device, the first data transmission device can decode the second data stream into the first data stream of the first FEC code type by using the second FEC code type through the electrical chip and then send it to the device using the Ethernet interface, thereby realizing data transmission between the first data transmission device and the second data transmission device through the cascaded FEC code.

[0021] In combination with any possible implementation of the second aspect, in a fifth possible implementation of the second aspect, the first data stream is transmitted between the first chip and the third chip through a physical medium. It can be seen that the first chip can decode the second data stream into a first data stream encoded with the first FEC code type by using other FEC code types except the first FEC code type without decoding the second data stream into the original data, so that the first data stream is transmitted to the third chip through the physical medium with interference, and then the third chip decodes the first data stream to obtain the original data. The physical medium can be, for example, an optical fiber, an optical waveguide, a circuit, air, etc.

[0022] In a third aspect, an embodiment of the present application provides a data transmission device applied to a first chip, comprising a receiver, an encoder and a transmitter. Wherein: the receiver is used to receive a first data stream sent by a second chip; the first data stream is a data stream encoded using a first forward error correction FEC code type; the encoder is used to encode the first data stream at least once to obtain a second data stream; wherein the second data stream is a cascaded FEC code stream encoded using at least the first FEC code type and the second FEC code type; the transmitter is used to send the second data stream to a third chip.

[0023] In combination with any implementation of the third aspect, in a first possible implementation of the third aspect, the first FEC code type is specifically: RS code, BCH code, Staircase code, LDPC code, Turbo code or TPC.

[0024] In combination with any implementation of the third aspect, in a second possible implementation of the third aspect, the second FEC code type is specifically: BCH code, RS code, Staircase code, LDPC code, Turbo code or TPC.

[0025] In combination with any implementation of the third aspect, in a third possible implementation of the third aspect, the encoder is specifically used to: distribute the first data stream into n third data streams; wherein data of the same codeword block in the first data stream is distributed to different third data streams; and encode the multiple third data streams at least once respectively to form the second data stream.

[0026] In combination with the third implementation manner of the third aspect, in a fourth possible implementation manner of the third aspect, the k codeword blocks identified from the first data stream are distributed to n third data streams, and the data belonging to the k codeword blocks in each of the third data streams is encoded into a codeword block in the second data stream;

[0027] The total amount of data contained in the k codeword blocks in the first data stream is equal to the amount of effective load data contained in the n codeword blocks in the second data stream.

[0028] In combination with the third implementation method of the third aspect, in a fifth possible implementation method of the third aspect, the data in the first data stream is distributed according to FEC symbol blocks, and the data of the same FEC symbol block in the first data stream is encoded in the same codeword block in the second data stream.

[0029] In combination with the third implementation manner of the third aspect, in a sixth possible implementation manner of the third aspect, the data in the first data stream is distributed according to a bit stream, and the data in the third data stream is encoded according to a bit stream.

[0030] In combination with any implementation of the third aspect, in a seventh possible implementation of the third aspect, the first chip and the second chip are located in a first data transmission device, the third chip is located in a second data transmission device, the first chip is an electrical chip, the second chip is a device using an Ethernet interface, and the third chip is an electrical chip.

[0031] In combination with any possible implementation manner of the third aspect, in an eighth possible implementation manner of the third aspect, the first data stream is transmitted between the second chip and the first chip through a physical medium. It can be seen that for a first data stream that generates bit errors when transmitted in a physical medium with interference, the first chip can directly encode the first data stream at least once to form a cascaded second data stream without decoding and correcting the first data stream.

[0032] It can be understood that the data transmission device provided in the third aspect corresponds to the data transmission method provided in the first aspect. Therefore, the technical effects of various possible implementation methods of the data transmission device provided in the second aspect can refer to the introduction of the data transmission method provided in the first aspect.

[0033] In a fourth aspect, an embodiment of the present application provides a data transmission device applied to a first chip, comprising a receiver, a decoder, and a transmitter. Wherein: the receiver is used to receive a second data stream sent by a second chip; the second data stream is a cascaded FEC code stream encoded by at least a first FEC code type and a second FEC code type; the decoder is used to decode the second data stream at least once to form a first data stream; the first data stream is a data stream encoded by the first FEC code type; the transmitter is used to send the first data stream to a third chip.

[0034] In combination with any possible implementation manner of the fourth aspect, in a first possible implementation manner of the fourth aspect, the first FEC code type is specifically: RS code, BCH code, Staircase code, LDPC code, Turbo code or TPC.

[0035] In combination with any possible implementation of the fourth aspect, in a second possible implementation of the fourth aspect, the second FEC code type is specifically: BCH code, RS code, Staircase code, LDPC code, Turbo code or TPC.

[0036] In combination with any possible implementation manner of the fourth aspect, in a third possible implementation manner of the fourth aspect, the first data stream is used to be decoded by the third chip according to the first FEC code type.

[0037] In combination with any possible implementation of the fourth aspect, in a fourth possible implementation of the fourth aspect, the second chip is located in a first data transmission device, the first chip and the third chip are located in a second data transmission device, the first chip is an electrical chip, the second chip is a chip, and the third chip is a device using an Ethernet interface.

[0038] In combination with any possible implementation of the fourth aspect, in a fifth possible implementation of the fourth aspect, the first data stream is transmitted between the first chip and the third chip through a physical medium. It can be seen that the first chip can decode the second data stream into a first data stream encoded with the first FEC code type by using other FEC code types except the first FEC code type without decoding the second data stream into original data, so that the first data stream is transmitted to the third chip through the physical medium with interference, and then the third chip decodes the first data stream to obtain the original data.

[0039] It can be understood that the data transmission device provided in the fourth aspect corresponds to the data transmission method provided in the second aspect. Therefore, the technical effects of various possible implementation methods of the data transmission device provided in the fourth aspect can refer to the introduction of the data transmission method provided in the second aspect.

[0040] In a fifth aspect, an embodiment of the present application further provides a communication method, which includes: the data transmission method described in any one of the implementations of the first aspect, and the data transmission method described in any one of the implementations of the second aspect.

[0041] In a sixth aspect, an embodiment of the present application further provides a communication system, comprising: a data transmission device as described in any one of the implementations of the third aspect, and a data transmission device as described in any one of the implementations of the fourth aspect.

[0042] In a seventh aspect, an embodiment of the present application further provides a network device, which includes the data transmission device described in any one of the implementation methods of the third aspect.

[0043] In an eighth aspect, an embodiment of the present application further provides a network device, which includes the data transmission device described in any one of the implementation methods of the fourth aspect.

[0044] In the ninth aspect, an embodiment of the present application further provides a computer program product, which, when executed on a computer, enables the computer to execute the data transmission method described in any one of the implementations of the first aspect or the data transmission method described in any one of the implementations of the second aspect.

[0045] In the tenth aspect, an embodiment of the present application further provides a computer-readable storage medium, which stores instructions, and when the computer-readable storage medium is executed on a computer or a processor, the computer or the processor executes the data transmission method described in any possible implementation of the first aspect or the data transmission method described in any possible implementation of the second aspect.

[0046] In an eleventh aspect, a data encoding method is provided, the method comprising: a first circuit receives a first data stream transmitted by a second circuit through an Ethernet interface, the first data stream being obtained by encoding original data using an RS code; the first circuit performs BCH encoding on the first data stream to obtain a second data stream. Two-level encoding is achieved by RS and BCH, so that the gain is higher, thereby increasing the distance and speed at which data can be transmitted.

[0047] In combination with the eleventh aspect, in a first possible implementation of the eleventh aspect, the first circuit receives a first data stream transmitted by the second circuit through an Ethernet interface, including: the first circuit receives the first data stream transmitted by the second circuit through an Ethernet interface from multiple physical paths; the first circuit includes one or more BCH encoders, and the first circuit performs BCH encoding on the first data stream to obtain a second data stream, including: when the number of BCH encoders included in the first circuit is consistent with the number of the physical paths, one BCH encoder is connected to one physical path, and the first circuit performs BCH encoding on the first data stream transmitted by the corresponding physical path through the one or more BCH encoders to obtain the second data stream. When the number of BCH encoders is consistent with the number of physical paths, the two can correspond one to one, so that multiple BCH encoders can encode in parallel to improve the encoding speed.

[0048] In combination with the eleventh aspect, in a second possible implementation of the eleventh aspect, the first circuit receives a first data stream transmitted by the second circuit through an Ethernet interface, including: the first circuit receives the first data stream transmitted by the second circuit through an Ethernet interface from multiple physical paths; the first circuit includes one or more BCH encoders, the first circuit also includes a scheduler, the first circuit performs BCH encoding on the first data stream to obtain a second data stream, including: when the number of BCH encoders included in the first circuit is inconsistent with the number of the physical paths, the first circuit schedules the corresponding BCH encoder through the scheduler to perform BCH encoding on the first data stream to obtain the second data stream. Regardless of whether the number of BCH encoders is less than the number of physical paths, or the number of BCH encoders is more than the number of physical paths, the BCH encoder can be scheduled by the scheduler to connect the BCH encoder with the corresponding physical path, thereby achieving BCH encoding of the first data stream transmitted by the physical path.

[0049] In combination with any possible implementation of the eleventh aspect, in a third possible implementation of the eleventh aspect, the BCH encoding of the first data stream includes: filling the data in the first data stream into the corresponding BCH codeword, and the continuous reference number of symbols included in each BCH codeword comes from different RS codewords.

[0050] In combination with the third possible implementation of the eleventh aspect, in the fourth possible implementation of the eleventh aspect, after the data in the first data stream is interleaved according to the reference number of RS code words to obtain symbol stream data, it is output to multiple virtual paths, and then bit multiplexed according to the number of physical paths, and transmitted to the first circuit by multiple physical paths; because the time when the first data streams on multiple physical paths arrive at the first circuit may be different, before filling the data in the first data stream into the corresponding BCH code word, it also includes: the first circuit demultiplexes the first data stream to restore the data of each virtual path; aligns the data of each virtual path to obtain aligned data; and fills the data in the first data stream into the corresponding BCH code word, including: filling the aligned data into the corresponding BCH code word. By aligning the data of each virtual path before BCH encoding, and then filling the aligned data into the corresponding BCH code word, the accuracy of BCH encoding is improved.

[0051] In combination with the third or fourth possible implementation of the eleventh aspect, in a fifth possible implementation of the eleventh aspect, the first data stream includes a first number of RS codewords, each RS codeword includes a first target number of symbols, the data in the first data stream is interleaved according to the first number of RS codewords, each BCH encoder corresponds to a second number of BCH codewords, each BCH codeword includes a second target number of symbols, the second target number is determined according to the first target number, and the second number is determined according to the first number; filling the data in the first data stream into the corresponding BCH codeword includes: filling the first half of the data of each row of the first data stream into the first third number of BCH codewords of the second number of BCH codewords in sequence, and filling the second half of the data of each row of the first data stream into the last third number of BCH codewords of the second number of BCH codewords in sequence, the third number is half of the second number, and the consecutive first number of symbols included in each BCH codeword come from different RS codewords.

[0052] In combination with the fifth possible implementation of the eleventh aspect, in the sixth possible implementation of the eleventh aspect, the first target number is 544, the first number is 2, the second number is 32, and the second target number is 360; filling the data in the first data stream into the corresponding BCH codeword includes: filling the first half of the data of each row of the first data stream into the first 16 BCH codewords of the 32 BCH codewords in sequence, and filling the second half of the data of each row of the first data stream into the last 16 BCH codewords of the 32 BCH codewords in sequence, and the two consecutive symbols included in each BCH codeword come from different RS codewords.

[0053] In combination with the third or fourth possible implementation manner of the eleventh aspect, in the seventh possible implementation manner of the eleventh aspect, the first data stream includes a first number of RS code words, each RS code word includes a first target number of symbols, the data in the first data stream is interleaved according to the first number of RS code words, the symbols at the beginning or end of each column of data in the first data stream are sequentially swapped, each BCH encoder corresponds to a second number of BCH code words, each BCH code word includes a second target number of symbols, the second target number is determined according to the first target number, and the second number is determined according to the first number; filling the data in the first data stream into the corresponding BCH code word includes: filling each column of data of the first data stream into the second number of BCH code words in sequence, and the consecutive first number of symbols included in each BCH code word come from different RS code words.

[0054] In combination with the seventh possible implementation method of the eleventh aspect, in the eighth possible implementation method of the eleventh aspect, the first target number is 544, the first number is 2, the second number is 32, and the second target number is 360; filling the data in the first data stream into the corresponding BCH code word includes: filling each column of data of the first data stream into 32 BCH code words in sequence, and the consecutive 2 symbols included in each BCH code word come from different RS code words.

[0055] In combination with the third or fourth possible implementation manner of the eleventh aspect, in a ninth possible implementation manner of the eleventh aspect, the first data stream includes a first number of RS code words, each RS code word includes a first target number of symbols, the data in the first data stream is interleaved according to the first number of RS code words, each BCH encoder corresponds to a second number of BCH code words, each BCH code word includes a second target number of symbols, the second target number is determined according to the first target number, and the second number is determined according to the first number; filling the data in the first data stream into the corresponding BCH code word includes: deinterleaving the data in the first data stream to obtain the original RS code word; interleaving the original RS code word according to a fourth number of RS code words to obtain interleaved data, the fourth number being greater than the first number; filling each row of data of the interleaved data into the second number of BCH code words in sequence, and the fourth number of consecutive symbols included in each BCH code word come from different RS code words.

[0056] Among them, in the fifth to ninth possible implementations of the eleventh aspect, the first target number can be determined based on the RS code type. For example, for RS (544, 514), the first target number is 544, and each RS code word includes 544 symbols. The second target number can be determined based on the first target number. For RS (544, 514), BCH (360, 340) can be used, and the second target number is 360. For another example, for RS (528, 514), the first target number is 528, and each RS code word includes 528 symbols. In addition, the method provided in the embodiment of the present application is to use RS and BCH two-level encoding, and the embodiment of the present application does not limit which RS code type and which BCH code type are used. In addition, the above-mentioned first target number of symbols and the second target number of symbols can be 10-bit (bit) symbols, 1bit symbols or symbols of other lengths, and the embodiment of the present application does not limit the length of the symbol.

[0057] In combination with any possible implementation of the eleventh aspect, in the tenth possible implementation of the eleventh aspect, after the first circuit performs BCH encoding on the first data stream to obtain the second data stream, it also includes: transmitting the second data stream to the third circuit through a medium using multiple physical paths, or transmitting the second data stream to the third circuit through the medium using one physical path in a time division multiplexing manner.

[0058] In the twelfth aspect, a data decoding method is provided, the method comprising: a third circuit receives a second data stream transmitted by the first circuit, the second data stream being encoded using an RS code and a BCH code; the second data stream is decoded using the BCH code to obtain a first data stream; and the first data stream is decoded using the RS code to obtain original data.

[0059] Since the first circuit uses two-level coding of RS and BCH, the gain is increased, so that the data can be transmitted farther and faster. After being transmitted to the third circuit, the third circuit decodes according to the corresponding RS code and BCH code, so that the data can be successfully decoded.

[0060] In combination with the twelfth aspect, in a first possible implementation of the twelfth aspect, the third circuit receives the second data stream transmitted by the first circuit, including: receiving the second data stream transmitted by the first circuit using multiple physical paths through a medium, or receiving the second data stream transmitted by the first circuit using one physical path in a time division multiplexing manner through the medium. The first circuit can flexibly apply one or more physical paths to transmit the second data stream, and the third circuit can receive the second data stream in the same manner as the first circuit sends the second data stream.

[0061] In combination with the first possible implementation manner of the twelfth aspect, in the second possible implementation manner of the twelfth aspect, before the using the BCH code to decode the second data stream to obtain the first data stream, it also includes: when the second data stream transmitted by the first circuit in a time division multiplexing manner using a physical path is received through the medium, the second data stream is demultiplexed; the using the BCH code to decode the second data stream to obtain the first data stream includes: using the BCH code to decode the demultiplexed data stream to obtain the first data stream.

[0062] In combination with the second possible implementation of the twelfth aspect, in a third possible implementation of the twelfth aspect, before the second data stream after demultiplexing is decoded using the BCH code, it also includes: aligning the second data stream after demultiplexing; the second data stream after demultiplexing is decoded using the BCH code to obtain the first data stream, including: decoding the aligned second data stream using the BCH code to obtain the first data stream. The accuracy of the BCH decoding is ensured by aligning the second data stream after demultiplexing before BCH decoding, and then decoding the aligned second data stream using the BCH code.

[0063] In the thirteenth aspect, a data encoding device is provided, which includes: a receiving module for receiving a first data stream transmitted by a second circuit through an Ethernet interface, wherein the first data stream is obtained by encoding original data using an RS code; and an encoding module for performing BCH encoding on the first data stream to obtain a second data stream.

[0064] In combination with the thirteenth aspect, in a first possible implementation manner of the thirteenth aspect, the receiving module is used to receive a first data stream transmitted by the second circuit through an Ethernet interface from multiple physical paths; the device includes one or more BCH encoders, and the encoding module is used to connect one BCH encoder to one physical path when the number of BCH encoders included is consistent with the number of physical paths, and perform BCH encoding on the first data stream transmitted by the corresponding physical path through the one or more BCH encoders to obtain a second data stream.

[0065] In combination with the thirteenth aspect, in a second possible implementation manner of the thirteenth aspect, the receiving module is used to receive a first data stream transmitted by the second circuit through an Ethernet interface from multiple physical paths; the device includes one or more BCH encoders and a scheduler, and the encoding module is used to perform BCH encoding on the first data stream by scheduling the corresponding BCH encoder through the scheduler when the number of BCH encoders included in the first circuit is inconsistent with the number of physical paths to obtain a second data stream.

[0066] In combination with any possible implementation of the thirteenth aspect, in a third possible implementation of the thirteenth aspect, the encoding module is used to fill the data in the first data stream into the corresponding BCH codeword, and the continuous reference number of symbols included in each BCH codeword comes from different RS codewords.

[0067] In combination with the third possible implementation method of the thirteenth aspect, in a fourth possible implementation method of the thirteenth aspect, after the data in the first data stream is interleaved according to the reference number of RS code words to obtain symbol stream data, it is output to multiple virtual paths, and then bit multiplexed according to the number of physical paths, and transmitted to the device by multiple physical paths; the device also includes: a demultiplexing module, used to demultiplex the first data stream and recover the data of each virtual path; an alignment module, used to align the data of each virtual path to obtain aligned data; the encoding module, used to fill the aligned data into the corresponding BCH code word.

[0068] In combination with the third or fourth possible implementation of the thirteenth aspect, in a fifth possible implementation of the thirteenth aspect, the first data stream includes a first number of RS codewords, each RS codeword includes a first target number of symbols, the data in the first data stream is interleaved according to the first number of RS codewords, each BCH encoder corresponds to a second number of BCH codewords, each BCH codeword includes a second target number of symbols, the second target number is determined according to the first target number, and the second number is determined according to the first number; the encoding module is used to fill the first half of the data of each row of the first data stream into the first third number of BCH codewords of the second number of BCH codewords in sequence, and fill the second half of the data of each row of the first data stream into the last third number of BCH codewords of the second number of BCH codewords in sequence, the third number is half of the second number, and the consecutive first number of symbols included in each BCH codeword come from different RS codewords.

[0069] In combination with the fifth possible implementation of the thirteenth aspect, in the sixth possible implementation of the thirteenth aspect, the first target number is 544, the first number is 2, the second number is 32, and the second target number is 360; the encoding module is used to fill the first half of the data of each row of the first data stream into the first 16 BCH code words of the 32 BCH code words in sequence, and fill the second half of the data of each row of the first data stream into the last 16 BCH code words of the 32 BCH code words in sequence, and the two consecutive symbols included in each BCH code word come from different RS code words.

[0070] In combination with the third or fourth possible implementation of the thirteenth aspect, in the seventh possible implementation of the thirteenth aspect, the first data stream includes a first number of RS code words, each RS code word includes a first target number of symbols, the data in the first data stream is interleaved according to the first number of RS code words, the symbols at the beginning or end of each column of data in the first data stream are sequentially swapped, each BCH encoder corresponds to a second number of BCH code words, each BCH code word includes a second target number of symbols, the second target number is determined according to the first target number, and the second number is determined according to the first number; the encoding module is used to fill each column of data of the first data stream into the second number of BCH code words in sequence, and the consecutive first number of symbols included in each BCH code word come from different RS code words.

[0071] In combination with the seventh possible implementation method of the thirteenth aspect, in the eighth possible implementation method of the thirteenth aspect, the first target number is 544, the first number is 2, the second number is 32, and the second target number is 360; the encoding module is used to fill each column of data of the first data stream into 32 BCH code words in sequence, and the two consecutive symbols included in each BCH code word come from different RS code words.

[0072] In combination with the third or fourth possible implementation manner of the thirteenth aspect, in the ninth possible implementation manner of the thirteenth aspect, the first data stream includes a first number of RS code words, each RS code word includes a first target number of symbols, the data in the first data stream is interleaved according to the first number of RS code words, each BCH encoder corresponds to a second number of BCH code words, each BCH code word includes a second target number of symbols, the second target number is determined according to the first target number, and the second number is determined according to the first number; the encoding module is used to deinterleave the data in the first data stream to obtain the original RS code words; interleave the original RS code words according to a fourth number of RS code words to obtain interleaved data, the fourth number is greater than the first number; each row of data of the interleaved data is sequentially filled into the second number of BCH code words, and the fourth number of consecutive symbols included in each BCH code word come from different RS code words.

[0073] In combination with any possible implementation of the thirteenth aspect, in the tenth possible implementation of the thirteenth aspect, the device also includes: a transmission module, used to transmit the second data stream to the third circuit through a medium using multiple physical paths, or to transmit the second data stream to the third circuit through the medium using one physical path in a time division multiplexing manner.

[0074] In a fourteenth aspect, a data decoding device is provided, the device comprising: a receiving module for receiving a second data stream transmitted by a first circuit, the second data stream being encoded using an RS code and a BCH code; a first decoding module for decoding the second data stream using the BCH code to obtain a first data stream; and a second decoding module for decoding the first data stream using the RS code to obtain original data.

[0075] In combination with the fourteenth aspect, in a first possible implementation of the fourteenth aspect, the receiving module is used to receive, through a medium, the second data stream transmitted by the first circuit using multiple physical paths, or to receive, through the medium, the second data stream transmitted by the first circuit using one physical path in a time division multiplexing manner.

[0076] In combination with the first possible implementation manner of the fourteenth aspect, in a second possible implementation manner of the fourteenth aspect, the device further includes: a demultiplexing module, for demultiplexing the second data stream when the second data stream transmitted by the first circuit in a time division multiplexing manner using a physical path is received through the medium; and the first decoding module, for decoding the demultiplexed data stream using the BCH code to obtain a first data stream.

[0077] In combination with the second possible implementation method of the fourteenth aspect, in a third possible implementation method of the fourteenth aspect, the device further includes: an alignment module, used to align the second data stream after demultiplexing; and the first decoding module, used to use the BCH code to decode the aligned second data stream to obtain the first data stream.

[0078] In the fifteenth aspect, a data transmission device is provided, the device comprising a memory and a processor; at least one instruction is stored in the memory, and the at least one instruction is loaded and executed by the processor to implement a method in any possible implementation of the eleventh aspect or the twelfth aspect of the present application.

[0079] In a sixteenth aspect, a communication device is provided, the device comprising: a transceiver, a memory, and a processor. The transceiver, the memory, and the processor communicate with each other through an internal connection path, the memory is used to store instructions, the processor is used to execute the instructions stored in the memory to control the transceiver to receive signals and control the transceiver to send signals, and when the processor executes the instructions stored in the memory, the processor executes the method in any possible implementation of the eleventh aspect or the twelfth aspect.

[0080] Optionally, the number of the processors is one or more, and the number of the memories is one or more.

[0081] Optionally, the memory may be integrated with the processor, or the memory may be provided separately from the processor.

[0082] In the specific implementation process, the memory can be a non-transitory memory, such as a read-only memory (ROM), which can be integrated with the processor on the same chip or can be set on different chips respectively. The embodiments of the present application do not limit the type of memory and the setting method of the memory and the processor.

[0083] In the seventeenth aspect, a computer program (product) is provided, wherein the computer program (product) comprises: a computer program code, and when the computer program code is executed by a computer, the computer executes a method in any possible implementation of the above-mentioned eleventh aspect or twelfth aspect.

[0084] In the eighteenth aspect, a readable storage medium is provided, which stores a program or instruction. When the program or instruction runs on a computer, a method in any possible implementation of the above-mentioned eleventh aspect or twelfth aspect is executed.

[0085] In the nineteenth aspect, a chip is provided, comprising a processor, the processor being used to call and execute instructions stored in a memory from the memory, so that a communication device equipped with the chip executes a method in any possible implementation of the above-mentioned eleventh aspect or twelfth aspect.

[0086] In the twentieth aspect, another chip is provided, comprising: an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected via an internal connection path, and the processor is used to execute the code in the memory, and when the code is executed, the processor is used to execute the method in any possible implementation manner of the above-mentioned eleventh aspect or twelfth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0087] Figure 1 A schematic diagram of an example of an application scenario in an embodiment of the present application;

[0088] Figure 2 A flowchart of a data transmission method in an embodiment of the present application;

[0089] Figure 3 A schematic diagram of an example of a data distribution method in an embodiment of the present application;

[0090] Figure 4 A schematic diagram of an example of a data distribution method in an embodiment of the present application;

[0091] Figure 5 A schematic diagram of an example of a data distribution method in an embodiment of the present application;

[0092] Figure 6 A schematic diagram of an example of a data distribution method in an embodiment of the present application;

[0093] Figure 7 This is a schematic diagram of a network structure in an exemplary scenario in an embodiment of the present application;

[0094] Figure 8A flowchart of a data transmission method in an embodiment of the present application;

[0095] Fig. 9 A flowchart of a data transmission method in an embodiment of the present application;

[0096] Fig.10 A schematic diagram of a flow chart of an encoding method in an embodiment of the present application;

[0097] Fig.11 A flowchart of a data transmission method in an embodiment of the present application;

[0098] Fig.12 A flowchart of a data transmission method in an embodiment of the present application;

[0099] Fig.13 This is a structural diagram of a data transmission method in an embodiment of the present application;

[0100] Fig.14 This is a structural diagram of a data transmission method in an embodiment of the present application;

[0101] Fig.15 A schematic diagram of an implementation environment provided for an embodiment of the present application;

[0102] Fig.16 A schematic diagram of an implementation environment provided for an embodiment of the present application;

[0103] Fig.17 A flow chart of a data encoding method provided in an embodiment of the present application;

[0104] Fig.18 A schematic diagram of a data transmission process provided in an embodiment of the present application;

[0105] Fig.19 A schematic diagram of a data transmission process provided in an embodiment of the present application;

[0106] Fig. 20 A schematic diagram of the BCH encoding process provided in an embodiment of the present application;

[0107] Fig.21 A schematic diagram of the BCH encoding process provided in an embodiment of the present application;

[0108] Fig. 22 A schematic diagram of the BCH encoding process provided in an embodiment of the present application;

[0109] Fig.23 A schematic diagram of the BCH encoding process provided in an embodiment of the present application;

[0110] Fig.24 A flow chart of a data decoding method provided in an embodiment of the present application;

[0111] Fig.25 A schematic diagram of a data transmission process provided in an embodiment of the present application;

[0112] Fig.26 A schematic diagram of experimental results of interleaving using 4 codewords provided in an embodiment of the present application;

[0113] Fig. 27 A schematic diagram of the structure of a data encoding device provided in an embodiment of the present application;

[0114] Fig.28 A schematic diagram of the structure of a data encoding device provided in an embodiment of the present application;

[0115] Fig.29 A schematic diagram of the structure of a data encoding device provided in an embodiment of the present application;

[0116] Fig.30 A schematic diagram of the structure of a data decoding device provided in an embodiment of the present application;

[0117] Fig.31 A schematic diagram of the structure of a data decoding device provided in an embodiment of the present application;

[0118] Fig.32 A schematic diagram of the structure of a data decoding device provided in an embodiment of the present application;

[0119] Fig.33 A schematic diagram of the structure of a data transmission device provided in an embodiment of the present application;

[0120] Fig.34 A schematic diagram of the structure of a data transmission device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0121] The terms used in the implementation section of the present application are only used to explain the embodiments of the present application and are not intended to limit the present application.

[0122] In the process of data transmission using FEC code, the sending device can use a specific FEC code type to encode the original data and then send the encoded FEC code to the receiving device. The receiving device can decode the received FEC code according to the same FEC code type to obtain the original data. In this way, even if the transmission channel causes errors in certain positions in the FEC code, the receiving device can obtain the original data before the error by performing reverse calculation based on the check bits in the FEC code during decoding, thereby realizing the error correction function.

[0123] In some scenarios, the data may need to convert the FEC code type during transmission. For example, as an enhanced FEC code type, the cascade FEC code uses one or more basic FEC code types to construct a multi-level FEC code, thereby providing stronger error correction protection for the transmitted data. Therefore, the cascade FEC code can be used to transmit data between devices to deal with the noise introduced when the data is transmitted at a high rate or over a long distance. However, the original FEC code type used by the original data transmission interface of the device is the code type specified by the standard. For example, the original Ethernet interface of many devices only supports Reed-Solomon (RS) code. When the device is used in a data transmission scenario with a higher rate or longer distance than the standard, the FEC code type specified by the standard often cannot meet the requirements. Therefore, the device needs to convert the data to be transmitted from the original FEC code type to an FEC code with higher gain. Usually, when converting the FEC code type, the data encoded with the original FEC code type needs to be decoded into the original data, and then the new FEC code type is used to encode the original data. However, such a conversion process will not only bring additional power consumption to the data transmission equipment, but also increase the delay of the data transmission process.

[0124] In order to solve the above problems, in the embodiment of the present application, when data is transmitted between two chips, since the cascade FEC code is a FEC code type that can provide high gain for high-speed and / or long-distance data transmission and the cascade FEC code is formed by cascading multiple FEC code types, when receiving a first data stream encoded with a first FEC code type, the chip does not need to first decode the first data stream with the first FEC code type and then re-encode the original data into a cascade FEC code, but can use at least the second FEC code type on the basis of the first data stream to perform at least one encoding, thereby obtaining a second data stream cascaded by at least the first FEC code type and the second FEC code type to obtain a higher gain. Therefore, the conversion process of the FEC code type is simplified, the time delay and device power consumption required for the FEC code type conversion are reduced, and the data transmission efficiency is improved.

[0125] For example, the embodiments of the present application can be applied to Figure 1In the scenario shown. The data transmission device 101 is provided with a chip 103 and a chip 105, and the data transmission device 102 is provided with a chip 107 and a chip 109. Assuming that both the chip 103 and the chip 109 support the first FEC code type, but the channel 106 between the data transmission device 101 and the data transmission device 102 needs to use a cascaded FEC code for data transmission, the chip 103 can use the first FEC code type to encode the original data to form a first data stream, and send the first data stream to the chip 105 through the channel 104. After receiving the first data stream, the chip 105 can use at least the second FEC code type to encode the first data stream at least once again, to obtain a second data stream cascaded by at least the first FEC code type and the second FEC code type, and send the second data stream to the chip 107 through the channel 106. After receiving the second data stream, the chip 107 can use at least the second FEC code type to decode the second data stream at least once, obtain the first data stream encoded by the first FEC code type, and send the first data stream to the chip 109 through the channel 108. After receiving the first data stream, the chip 109 can use the first FEC code type to decode the first data stream to obtain the original data. Among them, the first FEC code type can be an FEC code type such as RS code supported by the Ethernet interface, and the second FEC code type can be a code type such as Bose-Chaudhuri-Hocquenghem (English: Bose-Chaudhuri-Hocquenghem, abbreviated as: BCH) code. It should be noted that the channel 104, the channel 106 and the channel 108 can all be physical paths with interference, and the data stream will generate errors when it is transmitted in the channel 104, the channel 106 and the channel 108. That is to say, the first data stream sent by chip 103 to chip 105 will generate bit errors when transmitted in channel 104, the second data stream sent by chip 105 to chip 107 will generate bit errors again when transmitted in channel 106, and the first data stream sent by chip 107 to chip 109 will generate bit errors again when transmitted in channel 108.

[0126] In this application, "physical path" and "physical medium" are often used interchangeably. Those skilled in the art will understand that the "physical path" is the path for data to be transmitted in the "physical medium".

[0127] It can be understood that the above scenario is only an example scenario provided by the embodiment of the present application, and the embodiment of the present application is not limited to this scenario.

[0128] The specific implementation of a data transmission method and device in the embodiment of the present application is described in detail below with reference to the accompanying drawings.

[0129] Figure 2 2 is a flow chart of a data transmission method 200 according to an embodiment of the present application. The method may include, for example:

[0130] 201. Chip 1 receives a first data stream sent by chip 2; the first data stream is a data stream encoded using a first forward error correction FEC code type.

[0131] In specific implementation, chip 2 may encode the original data using the first FEC code type to form a first data stream and send it to chip 1. Therefore, the first data stream received by chip 1 is a data stream that has been encoded using the first FEC code type. In other words, the first data stream is a code stream composed of codeword blocks (English: codeword) of the first FEC code type.

[0132] The first FEC code type may be an RS code, a BCH code, a staircase code, a low-density parity-check (LDPC) code, a turbo code, a turbo product code (TPC), etc. For example, in an exemplary scenario, assuming that chip 2 communicates with chip 1 using an Ethernet interface, the first FEC code type may be an RS code.

[0133] It is understandable that the codeword block of the first FEC code type includes an additional parity code provided for the original data, and the parity code is used to correct errors generated during data transmission. For example, the first FEC code type may be a systematic FEC code (English: systematic FEC), that is, the codeword block of the first FEC code type may include the original data and the parity code provided for the original data.

[0134] Among them, the codeword block of the first FEC code type can be processed based on a finite field. The codeword block can be divided into multiple FEC symbol (English: symbol) blocks, and the processing of the codeword block can be based on the granularity of the FEC symbol block. For example, in an RS code, a 5440-bit codeword block includes 5140 bits of original data and 300 bits of check code. If Galois Field (English: Galois Field, abbreviated as: GF) (210) is used for processing, and every 10 bits of data form an FEC symbol block, then a codeword block includes 544 FEC symbol blocks, that is, 514 FEC symbol blocks of original data and 30 FEC symbol blocks of check code. For example, in another RS ​​code, a 5280-bit codeword block includes 5140 bits of original data and 140 bits of check code. If the GF(210) domain is used for processing, and every 10 bits of data form an FEC symbol block, then a codeword block includes 528 FEC symbol blocks, that is, 514 FEC symbol blocks of original data and 14 FEC symbol blocks of check codes. It can be understood that for consecutive errors (English: consecutive errors) or burst errors (English: burst errors), consecutive multi-bit errors will only be reflected as errors in a small number of FEC symbol blocks. Therefore, when the FEC codeword block is processed at the FEC symbol block granularity, the FEC error correction capability is stronger.

[0135] It can be understood that chip 1 and chip 2 are two different chips, and data can be transmitted between the two through a physical path with interference. Therefore, the first data stream sent by chip 2 to chip 1 will be affected by interference and produce bit errors when transmitted on the physical path. It can be seen that the first data stream received by chip 1 is a data stream that has already produced bit errors.

[0136] 202. The chip 1 encodes the first data stream at least once again to obtain a second data stream; wherein the second data stream is a cascaded FEC code stream encoded by at least the first FEC code type and the second FEC code type.

[0137] In specific implementation, for the first data stream encoded by the first FEC code type, the chip 1 may not use the first FEC code type to decode the first data stream into the original data, but may use the second FEC code type at least once to encode the first data stream, thereby forming a second data stream formed by at least the first FEC code type and the second FEC code type being cascaded. In other words, the second data stream may be a cascaded FEC code stream that cascades the first FEC code type and the second FEC code type, that is, the second data stream is a two-stage cascaded FEC code stream, or the second data stream may also be cascaded with one or more stages of cascaded FEC code streams based on the cascade of the first FEC code type and the second FEC code type, that is, the second data stream is a three-stage or more cascaded FEC code stream. It can be understood that if chip 2 sends a first data stream to chip 1 through a physical path with interference, the first data stream received by chip 1 is a data stream that has already generated bit errors. Therefore, chip 1 directly encodes the first data stream that has already generated bit errors at least once without decoding the first data stream that has already generated bit errors, thereby forming a second data stream with multi-stage FEC cascade.

[0138] The second FEC code type may be a BCH code, an RS code, a Staircase code, an LDPC code, a Turbo code, a TPC code, etc. It is understandable that the second FEC code type may be the same as the first FEC code type, or the second FEC code type may be different from the first FEC code type. For example, both the first FEC code type and the second FEC code type may be RS codes, or the first FEC code type may be RS codes and the second FEC code type may be BCH codes.

[0139] It should be noted that the second data stream is a code stream composed of code blocks of the FEC code type used in the last level of encoding. For example, if the second data stream is a data stream formed by the cascade of the first FEC code type and the second FEC code type, the first level is encoded by the first FEC code type, and the second level is encoded by the second FEC code type, then the second data stream is a code stream composed of code blocks of the second FEC code type. Since the second data stream is obtained by encoding the second FEC code type on the basis of the first data stream, the code block of the second FEC code type contains an additional check code provided for the first data stream. If the second FEC code type is a system code, the code block of the second FEC code type includes the data in the first data stream and the check code provided for the data.

[0140] In some embodiments, in order to make the error correction capability stronger, the data in the same codeword block in the first data stream can be encoded into multiple different codeword blocks in the second data stream, so that even if a small number of codeword blocks in the second data stream cannot be correctly decoded, it will not affect the correct decoding of the codeword blocks in the first data stream. In specific implementations, chip 1 can distribute the first data stream to n different channels to form n third data streams, so that the data of the same codeword block in the first data stream is distributed to multiple different third data streams, where n represents a natural number greater than 1. Then, chip 1 can encode the third data streams on the n channels at least once to form a second data stream. For example, in Figure 3 In the example, the first FEC codeword block is a codeword block in the first data stream, and the data in the codeword block is distributed to the third data stream on n channels. The third data stream on each channel is encoded into a second FEC codeword block to form n second FEC code streams. These n second FEC code streams constitute the second data stream. Among them, the first FEC codeword block represents a codeword block encoded by the first FEC code type, the second FEC codeword block represents a codeword block encoded by the second FEC code type, and the second FEC code stream represents a data stream composed of the second FEC codeword blocks.

[0141] It can be understood that the first data stream can be a data stream on one channel, or can be composed of data streams on multiple channels, that is, the first data stream can be a code stream, or can be composed of multiple code streams.

[0142] If the first data stream is a data stream on a channel, the first data stream is distributed into a third data stream, which is equivalent to a data stream being distributed into multiple data streams. Figure 4 In the example shown, it is assumed that n is a natural number greater than 1, the first data stream is the first FEC code stream on a channel, and after distribution processing, the third data stream on n channels is formed, and the third data stream on each channel is respectively encoded into a second FEC code stream, and these n FEC code streams constitute the second data stream. Among them, the first FEC code stream represents a data stream composed of a first FEC code word block, and the first FEC code word block represents a code word block obtained by encoding with a first FEC code type, and the second FEC code stream represents a data stream composed of a second FEC code word block, and the second FEC code word block represents a code word block obtained by encoding with a second FEC code type.

[0143] If the first data stream is composed of data streams on multiple channels, the distribution from the first data stream to the third data stream is equivalent to the distribution from multiple data streams to multiple data streams, and this distribution can be achieved through distribution strategies such as interleaving technology and / or multiplexing technology. Figure 5 In the example shown, assuming that k, m and n are all natural numbers greater than 1, the first data stream is composed of the first FEC code stream on k channels, and after passing through an interleaver, a fourth data stream on m channels can be formed, and after passing through a multiplexer such as a bit multiplexer or a symbol multiplexer, a third data stream on n channels can be formed, and the third data stream on each channel is then encoded into a second FEC code stream, and these n FEC code streams constitute the second data stream. Among them, the first FEC code stream represents a data stream composed of a first FEC code word block, and the first FEC code word block represents a code word block obtained by encoding with a first FEC code type, and the second FEC code stream represents a data stream composed of a second FEC code word block, and the second FEC code word block represents a code word block obtained by encoding with a second FEC code type.

[0144] It should be noted that a variety of distribution methods can be used to distribute the first data stream into n third data streams.

[0145] As an example, chip 1 can distribute and process the first data stream with bit as the granularity, that is, the data in the first data stream can be distributed to n third data streams according to the bit stream. In specific implementation, chip 1 can obtain one bit of data from the first data stream, and select a channel for the data from n channels according to the distribution strategy, so as to distribute the data to the third data stream on the channel. Correspondingly, chip 1 can also encode and process the third data stream with bit as the granularity, that is, the data in the third data stream can be encoded according to the bit stream.

[0146] As another example, chip 1 can distribute and process the first data stream with FEC symbol blocks as the granularity, that is, the data in the first data stream can be distributed according to the FEC symbol stream. In specific implementation, chip 1 can identify an FEC symbol block from the first data stream, and select a channel for the FEC symbol block from n channels according to the distribution strategy, so as to distribute the FEC symbol block to the third data stream on the channel. Correspondingly, chip 1 can also encode the third data stream with FEC symbol blocks as the granularity. In specific implementation, chip 1 can identify a certain number of FEC symbol blocks from the third data stream and encode them into the same codeword block in the second data stream, so that the data of the same FEC symbol block in the first data stream will be encoded in the same codeword block in the second data stream. Among them, the FEC symbol block can be identified by an alignment marker (English: alignment marker, abbreviated as: AM).

[0147] As another example, chip 1 can distribute and process the first data stream with multiple code blocks as the granularity. In specific implementation, chip 1 can identify multiple code blocks from the first data stream, and distribute the data of the multiple code blocks to the third data stream on n channels according to the distribution strategy. Among them, the distribution strategy can be implemented, for example, by interleaving (English: interleave) technology and / or multiplexing (English: multiplexer) technology. In addition, the first data stream can be a code stream, that is, the multiple code blocks can be identified from a code stream, or the first data stream can be composed of multiple code streams, that is, the k code blocks can be identified from multiple code streams, for example, the first data stream is composed of k code streams, and the multiple code blocks can be k code blocks obtained by identifying a code block from each code stream.

[0148] In order to facilitate decoding of the second data stream into original data on the same chip, chip 1 can use all the data of the k codeword blocks in the first data stream as the payload of the n codeword blocks in the second data stream, so that the k codeword blocks in the first data stream are encoded into n codeword blocks in the second data stream. In specific implementation, chip 1 can identify k codeword blocks from the first data stream, and distribute the data of these k codeword blocks to the third data stream on n channels according to the distribution strategy. The data of these k codeword blocks distributed to each channel can be respectively encoded into a codeword block in the second data stream, thereby encoding n codeword blocks in the second data stream on n channels. For example, in Figure 6 In the example shown, assuming that k, m and n are all natural numbers greater than 1, the k first FEC codeword blocks identified from the first data stream are input into an interleaver, and the data output by the interleaver to m channels is then input into a multiplexer such as a bit multiplexer or a symbol multiplexer, and the multiplexer outputs data on n channels, and the data on each channel is then encoded into a second FEC codeword block, thereby obtaining n second FEC codeword blocks in the second data stream. Among them, the first FEC codeword block represents a codeword block encoded using the first FEC code type, and can be identified from the first data stream through AM. The second FEC codeword block represents a codeword block encoded using the second FEC code type.

[0149] In order to enable the k codeword blocks in the first data stream to be encoded into the n codeword blocks in the second data stream, the total data amount of the k codeword blocks of the first data stream needs to be equal to the payload data amount of the n codeword blocks of the second data stream. For example, assuming that the first data stream is an RS code stream and the second data stream is a BCH code stream, the RS codeword blocks of the first data stream include a 5140-bit payload and a 300-bit check code, and the BCH codeword blocks of the second data stream include a 340-bit payload and a 20-bit check code. It can be seen that the total data amount of the 4 RS codeword blocks is 21760 bits, and the payload data amount of the 64 BCH codeword blocks is also 21760 bits. Therefore, the 4 RS codeword blocks of the first data stream can be encoded into 64 BCH codeword blocks of the second data stream.

[0150] 203 . The chip 1 sends the second data stream to the chip 3 .

[0151] After receiving the second data stream, the chip 3 can decode the second data stream, so that the chip 1 and the chip 3 can use the cascaded FEC code to transmit data.

[0152] As an example, chip 3 can decode all FEC code types including the first FEC code type and the second FEC code type in the second data stream to obtain the original data. As another example, chip 3 can decode the other FEC code types in the second data stream except the first FEC code type to obtain the first data stream and transmit it to chip 4, and chip 4 then decodes the first FEC code type in the first data stream to obtain the original data. It can be understood that chip 1 and chip 3 are two different chips, and data can be transmitted between the two through a physical path with interference. Similarly, chip 3 and chip 4 are two different chips, and data can be transmitted between the two through a physical path. Therefore, when the second data stream sent by chip 1 to chip 3 is transmitted on the physical path, it will be interfered by the physical path and generate bit errors. Chip 3 decodes the second data stream of cascade FEC into a first data stream encoded with the first FEC code type and sends it to chip 4 without decoding and correcting the second data stream that has already generated bit errors into original data. The first data stream sent by chip 3 to chip 4 will be affected by interference again and generate bit errors when transmitted on the physical path, so chip 4 decodes and corrects the first data into original data. It can be seen that the first data stream received by chip 1 is a data stream that has already generated bit errors.

[0153] Among them, for the cascaded FEC codes in the second data stream, the decoding of each level of FEC code type can be achieved by identifying the codeword block of the FEC code type of that level and performing reverse calculation on the identified codeword block. For example, if the second data stream is formed by cascading the first FEC code type and the second FEC code type, when decoding the second data stream, the codeword block of the second FEC code type can be identified from the second data stream by AM or self-synchronization technology, and the codeword block of the second FEC code type is reversely calculated to obtain the first data stream, and then, the codeword block of the first FEC code type can be identified from the first data stream by a fixed mapping relationship between the codeword block of the second FEC code type and the codeword block of the first FEC code type or AM, and the codeword block of the first FEC code type is reversely calculated to obtain the original data.

[0154] In an exemplary scenario, Figure 7 As shown, chip 1 and chip 2 may be two chips located in a first data transmission device, and chip 3 and chip 4 may be two chips located in a second data transmission device. Cascaded FEC codes are required to transmit data between the first data transmission device and the second data transmission device, but chip 2 and chip 4 only support the first FEC code type and do not support cascaded FEC codes. Therefore, chip 1 encodes the data stream output by chip 2 to form a cascaded FEC code stream and sends it to chip 3. The chip decodes the cascaded FEC code stream into a data stream of the first FEC code type and then outputs it to chip 4. In this way, data can be transmitted between chip 1 and chip 3 through cascaded FEC codes, thereby realizing data transmission between the first data transmission device and the second data transmission device through cascaded FEC codes. Among them, chip 1 may be an electrical chip, for example, a relay electrical chip or an electrical chip of an optical module, such as a digital signal processing (English: Digital Signal Processing, referred to as: DSP) chip. Chip 2 may be a chip using an Ethernet interface, such as a physical (English: physical, referred to as: PHY) layer chip. Chip 3 may be an electrical chip, for example, a relay electrical chip or an electrical chip of an optical module, such as a DSP chip. Chip 4 may be a chip using an Ethernet interface, such as a physical (PHY) layer chip.

[0155] It should be noted that the cascaded FEC code provided in this embodiment has achieved a good error correction effect in simulation verification. Figure 7In the exemplary scenario shown, simulation verification is performed, and additive white Gaussian noise (AWGN) is inserted into the channel between chip 2 and chip 1, the channel between chip 1 and chip 3, and the channel between chip 3 and chip 4, thereby forming a simulation environment. In this simulation environment: chip 2 sends a data stream of the first FEC code type to chip 1, chip 1 converts the data stream of the first FEC code type into a cascaded FEC code stream and then sends it to chip 3, and chip 3 converts the cascaded FEC code stream into a data stream of the first FEC code type and then sends it to chip 4. At this time, chip 4 can correctly decode the received data stream of the first FEC code type; chip 2 sends the data stream of the first FEC code type to chip 1, chip 1 directly sends the data stream of the first FEC code type to chip 3, and chip 3 directly sends the data stream of the first FEC code type to chip 4. At this time, chip 4 cannot correctly decode the received data stream of the first FEC code type.

[0156] The simulation verification conducted in the above simulation environment shows that compared with the cascaded FEC code stream formed by chip 1 first decoding the code stream of the first FEC code type and then performing multi-stage encoding, the cascaded FEC code stream formed by chip 1 using the second FEC code type to encode the code stream of the first FEC code type again without decoding the code stream of the first FEC code type can not only save 60 to 100ns of delay, but also achieve a net coding gain (English: netcoding gain, abbreviated: NCG) of more than 9dB.

[0157] In this embodiment, for the first data stream encoded with the first FEC code type sent by chip 2 to chip 1, chip 1 does not need to first decode the first data stream with the first FEC code type and then re-encode the original data into a cascaded FEC code, but can use at least the second FEC code type to encode at least once on the basis of the first data stream, so as to obtain a second data stream cascaded by at least the first FEC code type and the second FEC code type. Therefore, the conversion process of the FEC code type is simplified, the time delay and device power consumption consumed when the FEC code type is converted are reduced, and the data transmission efficiency is improved.

[0158] Figure 8 800 is a flow chart of a data transmission method 800 in an embodiment of the present application. The method may include:

[0159] 801. Chip 3 receives a second data stream sent by chip 1; the second data stream is a concatenated FEC code stream encoded by at least a first FEC code type and a second FEC code type;

[0160] 802. The chip 3 decodes the second data stream at least once to form a first data stream; the first data stream is a data stream encoded by the first FEC code type;

[0161] 803 . The chip 3 sends the first data stream to the chip 4 .

[0162] After receiving the first data stream, the chip 4 may decode the first data stream according to the first FEC code type to obtain original data.

[0163] Among them, the first FEC code type can be RS code, BCH code, staircase code, LDPC code, Turbo code, TPC and other code types, and the second FEC code type can be BCH code, RS code, staircase code, LDPC code, Turbo code, TPC and other code types.

[0164] In an exemplary scenario, the chip 1 may be located in a first data transmission device, the chip 3 and the chip 4 may be located in a second data transmission device, the chip 3 and the chip 1 may be electrical chips, such as relay electrical chips or electrical chips of optical modules, and the chip 4 may be a chip using an Ethernet interface.

[0165] It can be understood that this embodiment corresponds to the decoding process of the second data stream, and Figure 2 The embodiment shown corresponds to the encoding process of the second data stream. Therefore, various specific implementations related to this embodiment, such as the specific implementations of the first data stream, the second data stream, the first FEC code type, the second FEC code type, the chip 1, the chip 3, the chip 4, etc., can all be referred to. Figure 2 The description of the embodiment shown, namely Figure 8 The method of the corresponding embodiment is Figure 2 The scheme of reverse decoding of the encoding introduced in the corresponding embodiment can be understood by those skilled in the art and will not be described in detail in this application.

[0166] In this embodiment, for the second data stream formed by cascading at least the first FEC code type and the second FEC code type sent by chip 1 to chip 3, chip 3 can decode the second data stream using other FEC code types except the first FEC code type to form a first data stream encoded using the first FEC code type and send it to chip 4, without decoding the second data stream into original data and then re-encoding it into a data stream of the first FEC code type and sending it to chip 4. Therefore, the conversion process of the FEC code type is simplified, the time delay and device power consumption consumed during the FEC code type conversion are reduced, and the data transmission efficiency is improved.

[0167] The following introduces an application example of the data transmission method provided by the embodiment of the present application in a specific scenario through an example of a specific scenario. In this specific scenario example, a first data transmission device includes a first PHY layer chip and a first optical module, the first optical module has a first DSP chip, and a second data transmission device includes a second PHY layer chip and a second optical module, the second optical module has a second DSP chip. Cascaded FEC codes are used to transmit data between the first data transmission device and the second data transmission device, and the first PHY layer chip and the second PHY layer chip support RS codes but do not support cascaded FEC codes. In this specific scenario, Fig. 9 As shown, the data transmission method 900 between the first data transmission device and the second data transmission device may include, for example:

[0168] 901. The first PHY chip encodes original data once using the RS code to form an RS code stream.

[0169] 902. The first PHY chip sends an RS code stream to the first DSP chip.

[0170] 903. The first DSP chip uses the BCH code to encode the RS code stream again to form a BCH code stream.

[0171] The BCH code stream is actually a concatenated FEC code stream formed by concatenating an RS code and a BCH code.

[0172] 904. The first DSP chip sends a BCH code stream to the second DSP chip.

[0173] 905. The second DSP chip decodes the BCH code stream once using the BCH code to form an RS code stream.

[0174] 906. The second DSP chip sends the RS code stream to the second PHY chip.

[0175] 907. The second PHY chip decodes the RS code stream again using the RS code to obtain original data.

[0176] In this embodiment, the first DSP chip does not need to first decode the RS code stream using the RS code and then re-encode the original data into a cascaded FEC code stream. Instead, it can use the BCH code to encode once on the basis of the RS code stream to form a cascaded FEC code stream formed by cascading the RS code and the BCH code, so that the cascaded FEC code stream can be used to transmit data between the first DSP chip and the second DSP chip, and the second DSP chip does not need to decode the cascaded FEC code stream into the original data and then re-encode it into the RS code stream. Instead, it can use the BCH code to decode the cascaded FEC code stream once to form an RS code stream, so that the second PHY chip can receive the RS code stream. Therefore, the conversion process of the FEC code type is simplified, the time delay and device power consumption consumed when converting the FEC code type are reduced, and the data transmission efficiency is improved.

[0177] Fig.10 1 is a flow chart of an encoding method 1000 in an embodiment of the present application. The method 1000 is used to encode k code blocks of a first FEC code type using a second FEC code type to form n code blocks of a second FEC code type. Specifically, the method 1000 may include:

[0178] 1001. Identify k first codeword blocks from a first data stream.

[0179] The first data stream is a data stream encoded using a first FEC code type, so the first codeword block in the first data stream is a codeword block of the first FEC code type. The first codeword block can be identified from the first data stream by AM.

[0180] 1002. Distribute the data of the k first codeword blocks to n channels.

[0181] The distribution strategy can be implemented by interleaving and / or multiplexing techniques. For example, k first FEC code blocks can be input into an interleaver, and the data outputted by the interleaver to m channels are then inputted into a multiplexer such as a bit multiplexer or a symbol multiplexer, and the multiplexer outputs data on n channels.

[0182] 1003. On each channel, use a second FEC code type to encode the data divided from the k first code blocks to form a second code block, thereby obtaining n second code blocks in a second data stream on n channels.

[0183] Among them, on each channel, the data from the k first codeword blocks are encoded as a payload into a second codeword block, that is, the payload of the second codeword block is the data distributed from the k first codeword blocks on the channel. Therefore, the total payload of the n second codeword blocks encoded on n channels is the total data of the k first codeword blocks, that is, the total data volume of the k first codeword blocks needs to be equal to the payload data volume of the n second codeword blocks.

[0184] In this embodiment, since the effective load in the n second code blocks is all the data in the k code blocks, these n second code blocks can be directly decoded into original data according to the second FEC code type and the first FEC code type, which facilitates the decoding operation of the first FEC code type and the second FEC code type on the same chip.

[0185] Fig.11 1 is a schematic diagram of a data transmission method 1100 in an embodiment of the present application. The method 1100 includes:

[0186] 1101. A first chip receives a first data stream sent by a second chip; the first data stream is a data stream encoded using a first forward error correction FEC code type;

[0187] 1102. The first chip encodes the first data stream at least once to obtain a second data stream; wherein the second data stream is a cascaded FEC code stream encoded using at least the first FEC code type and the second FEC code type.

[0188] In some possible implementations, the first FEC code type is specifically: RS code, BCH code, Staircase code, LDPC code, Turbo code or turbo product code TPC.

[0189] In some possible implementations, the second FEC code type is specifically: BCH code, RS code, Staircase code, LDPC code, Turbo code or TPC.

[0190] In some possible implementations, the first chip encodes the first data stream at least once to form a second data stream, including:

[0191] The first chip distributes the first data stream into n third data streams; wherein data of the same codeword block in the first data stream is distributed to different third data streams;

[0192] The first chip encodes the plurality of third data streams at least once respectively to form the second data stream.

[0193] In some possible implementations, the k codeword blocks identified from the first data stream are distributed to n third data streams, and data belonging to the k codeword blocks in each of the third data streams is encoded into a codeword block in the second data stream;

[0194] The total amount of data contained in the k codeword blocks in the first data stream is equal to the amount of effective load data contained in the n codeword blocks in the second data stream.

[0195] In some possible implementations, the data in the first data stream is distributed according to FEC symbol blocks, and the data of the same FEC symbol block in the first data stream is encoded in the same codeword block in the second data stream.

[0196] In some possible implementations, the data in the first data stream is distributed according to a bit stream, and the data in the third data stream is encoded according to a bit stream.

[0197] In some possible implementations, the first chip and the second chip are located in the same data transmission device, the first chip is an electrical chip, and the second chip is a chip using an Ethernet interface.

[0198] It can be understood that the first chip is the chip 1 mentioned in the data transmission method 200, the second chip is the chip 2 mentioned in the data transmission method 200, and the third chip is the chip 3 mentioned in the data transmission method. Therefore, various specific embodiments of the first chip, the second chip, and the third chip performing operations in this embodiment can be referred to. Figure 2 The introduction of chip 1, chip 2, and chip 3 in the data transmission method 200 is not repeated in this embodiment.

[0199] In this embodiment, for the first data stream encoded with the first FEC code type sent by chip 2 to chip 1, chip 1 does not need to first decode the first data stream with the first FEC code type and then re-encode the original data into a cascaded FEC code, but can use at least the second FEC code type to encode at least once on the basis of the first data stream, so as to obtain a second data stream cascaded by at least the first FEC code type and the second FEC code type. Therefore, the conversion process of the FEC code type is simplified, the time delay and device power consumption consumed when the FEC code type is converted are reduced, and the data transmission efficiency is improved.

[0200] Fig.12 1 is a schematic diagram of a data transmission method 1200 according to an embodiment of the present application. The method 1200 includes:

[0201] 1201. A first chip receives a second data stream sent by a second chip; the second data stream is a cascaded FEC code stream encoded by at least a first FEC code type and a second FEC code type;

[0202] 1202. The first chip decodes the second data stream at least once to form a first data stream; the first data stream is a data stream encoded using the first FEC code type;

[0203] 1203. The first chip sends the first data stream to a third chip.

[0204] In some possible implementations, the first FEC code type is specifically: RS code, BCH code, Staircase code, LDPC code, Turbo code or TPC.

[0205] In some possible implementations, the second FEC code type is specifically: BCH code, RS code, Staircase code, LDPC code, Turbo code or TPC.

[0206] In some possible implementations, the first data stream is used to be decoded by the third chip according to the first FEC code type.

[0207] In some possible implementations, the second chip is located in a first data transmission device, the first chip and the third chip are located in a second data transmission device, the first chip is an electrical chip, the second chip is an electrical chip, and the third chip is a chip using an Ethernet interface.

[0208] It can be understood that the first chip is the chip 3 mentioned in the data transmission method 200, the second chip is the chip 1 mentioned in the data transmission method 200, and the third chip is the chip 4 mentioned in the data transmission method. Therefore, various specific embodiments of the first chip, the second chip, and the third chip performing operations in this embodiment can be referred to. Figure 2 The introduction of chip 3, chip 1, and chip 4 in the data transmission method 200 is not repeated in this embodiment.

[0209] In this embodiment, for the second data stream formed by the concatenation of at least the first FEC code type and the second FEC code type sent by the second chip to the first chip, the first chip can decode the second data stream using other FEC code types except the first FEC code type to form a first data stream encoded using the first FEC code type and send it to the third chip, without having to decode the second data stream into original data and then re-encode it into a data stream of the first FEC code type and send it to the third chip. Therefore, the conversion process of the FEC code type is simplified, the time delay and device power consumption consumed during the FEC code type conversion are reduced, and the data transmission efficiency is improved.

[0210] Fig.13 1 is a schematic diagram of the structure of a data transmission device 1300 in an embodiment of the present application. The device 1300 is a first chip, including:

[0211] The receiver 1301 is used to receive a first data stream sent by the second chip; the first data stream is a data stream encoded using a first forward error correction FEC code type;

[0212] The encoder 1302 is used to encode the first data stream at least once to obtain a second data stream; wherein the second data stream is a cascaded FEC code stream encoded by at least the first FEC code type and the second FEC code type.

[0213] In some possible implementations, the first FEC code type is specifically: RS code, BCH code, Staircase code, LDPC code, Turbo code or TPC.

[0214] In some possible implementations, the second FEC code type is specifically: BCH code, RS code, Staircase code, LDPC code, Turbo code or TPC.

[0215] In some possible implementations, the encoder 1302 is specifically configured to:

[0216] Distribute the first data stream into n third data streams; wherein data of the same codeword block in the first data stream is distributed to different third data streams;

[0217] The plurality of third data streams are respectively encoded at least once to form the second data stream.

[0218] In some possible implementations, the k codeword blocks identified from the first data stream are distributed to n third data streams, and data belonging to the k codeword blocks in each of the third data streams is encoded into a codeword block in the second data stream;

[0219] The total amount of data contained in the k codeword blocks in the first data stream is equal to the amount of effective load data contained in the n codeword blocks in the second data stream.

[0220] In some possible implementations, the data in the first data stream is distributed according to FEC symbol blocks, and the data of the same FEC symbol block in the first data stream is encoded in the same codeword block in the second data stream.

[0221] In some possible implementations, the data in the first data stream is distributed according to a bit stream, and the data in the third data stream is encoded according to a bit stream.

[0222] In some possible implementations, the first chip and the second chip are located in the same data transmission device, the first chip is an electrical chip, and the second chip is a device using an Ethernet interface.

[0223] Understandably, Fig.13 The device 1300 shown is Figure 2 The chip 1 mentioned in the embodiment shown, therefore, various specific embodiments of the device 1300 in this embodiment can be referred to in Figure 2 The description of the chip 1 in the illustrated embodiment will not be repeated in this embodiment.

[0224] In this embodiment, for the first data stream encoded with the first FEC code type sent by the second chip to the first chip, the first chip does not need to first decode the first data stream with the first FEC code type and then re-encode the original data into a cascaded FEC code, but can use at least the second FEC code type to encode at least once on the basis of the first data stream, so as to obtain a second data stream cascaded by at least the first FEC code type and the second FEC code type. Therefore, the conversion process of the FEC code type is simplified, the time delay and device power consumption consumed when the FEC code type is converted are reduced, and the data transmission efficiency is improved.

[0225] Fig.14 1 is a schematic diagram of the structure of a data transmission device 1400 in an embodiment of the present application. The device 1400 is specifically a first chip, including:

[0226] The receiver 1401 is used to receive a second data stream sent by a second chip; the second data stream is a cascaded FEC code stream encoded by at least a first FEC code type and a second FEC code type;

[0227] Decoder 1402, configured to decode the second data stream at least once to form a first data stream; the first data stream is a data stream encoded using the first FEC code type;

[0228] The transmitter 1403 is configured to send the first data stream to the third chip.

[0229] In some possible implementations, the first FEC code type is specifically: RS code, BCH code, Staircase code, LDPC code, Turbo code or TPC.

[0230] In some possible implementations, the second FEC code type is specifically: BCH code, RS code, Staircase code, LDPC code, Turbo code or TPC.

[0231] In some possible implementations, the first data stream is used to be decoded by the third chip according to the first FEC code type.

[0232] In some possible implementations, the second chip is located in a first data transmission device, the first chip and the third chip are located in a second data transmission device, the first chip is an electrical chip, the second chip is a chip, and the third chip is a device using an Ethernet interface.

[0233] Understandably, Fig.14 The device 1400 shown is Figure 2 The chip 3 mentioned in the embodiment shown, therefore, various specific embodiments of the device 1400 in this embodiment can be referred to in Figure 2 The description of the chip 3 in the illustrated embodiment will not be repeated in this embodiment.

[0234] In this embodiment, for the second data stream formed by cascading at least the first FEC code type and the second FEC code type sent by chip 1 to chip 3, chip 1 can decode the second data stream using other FEC code types except the first FEC code type to form a first data stream encoded using the first FEC code type and send it to chip 3, without decoding the second data stream into original data and then re-encoding it into a data stream of the first FEC code type and sending it to chip 3. Therefore, the conversion process of the FEC code type is simplified, the time delay and device power consumption consumed during the FEC code type conversion are reduced, and the data transmission efficiency is improved.

[0235] In addition, an embodiment of the present application further provides a communication method, which includes: the aforementioned data transmission method 1100 and the aforementioned data transmission method 1200.

[0236] In addition, an embodiment of the present application further provides a communication system, which includes the aforementioned data transmission device 1300 and the aforementioned data transmission device 1400.

[0237] In addition, an embodiment of the present application further provides a network device, which includes the aforementioned data transmission device 1300 or 1400.

[0238] In addition, an embodiment of the present application also provides a data transmission system, including the aforementioned network device.

[0239] In addition, the embodiments of the present application also provide a computer program product including instructions, which, when executed on a computer, enables the computer to execute the data transmission method 1100 or 1200 described in the method embodiment of the embodiments of the present application.

[0240] In addition, an embodiment of the present application also provides a computer-readable storage medium, which stores instructions. When the computer-readable storage medium is executed on a computer or a processor, the computer or the processor executes the data transmission method 1100 or 1200 as described in the method embodiment of the embodiment of the present application.

[0241] During data transmission, the loss and noise of the path limit the rate and distance of data transmission. The emergence of FEC provides error correction protection for the data in transmission, making the transmission capacity of the path gradually approach the Shannon limit, thereby increasing the data transmission rate and transmission distance in the path. This application further improves the gain by cascading multiple levels of FEC codes, thereby increasing the data transmission rate and transmission distance. The Shannon limit is a data rate that can be transmitted in a certain path, which is proved by Shannon's theorem and cannot be exceeded.

[0242] Among them, FEC is an error control method. The principle of FEC is to provide additional check bits (parity code) for the transmitted data through some method. There are many types of FEC, such as Reed-Solomon FEC (RS-FEC), Bose-Chaudhuri-Hocquenghem FEC (BCH FEC), Fire code, turbo code, low density parity check code (LDPC), etc. These FECs can obtain different gains by different code lengths and different overhead ratios.

[0243] In addition, different FECs have different calculation methods. In some FECs, the original data will not be changed, only the check bits are added. This type of FEC is called systematic FEC. For systematic codes, the parity code and the original data are sent to the receiving end in the channel. When the parity code and the original data are transmitted in the channel, errors may occur in some positions of the original data or the parity code. The original data before the error can be obtained by reverse calculation at the receiving end.

[0244] Since FEC can increase the data transmission rate and transmission distance in the channel, it is widely used in data transmission technology. Ethernet interface is the most widely used data transmission interface in the world. As the rate increases rapidly, FEC plays an important role in it. For example, for the 10 Gigabit Ethernet (GbE) interface, FEC was added. At that time, it was a cyclic code (Cyclic code), with a data length of 2080 bits and a check bit of 32 bits, thus forming FC (2112, 2080) FEC coding. This coding can correct common bit errors that occur in backplane transmission. For example, the length of a code block of Firecode is 2080 bits of data and 32 bits of check code. Based on the error correction capability of Firecode, the common bit error that Firecode can correct is a burst error with a maximum length of 11 bits. During the formulation of the 100GbE standard, the industry introduced a stronger FEC code - RS FEC. For example, KR4 FEC and KP4 FEC are both RS-FEC, and their code types are RS(528,514) and RS(544,514) respectively. Both KR4 FEC and KP4 FEC are calculated based on the GF(210) domain. Each symbol contains 10-bit data, and all calculations are in symbols. Each code word of KP4 FEC contains 514 FEC symbols corresponding to the original data information and 30 FEC symbols corresponding to the check bits, that is, 5140 bits of original data information and 300 bits of check bits. Each code word of KR4 FEC contains 514 FEC symbols corresponding to the original data information and 14 FEC symbols corresponding to the check bits, that is, 5140 bits of original data information and 140 bits of check bits. One advantage of using FEC symbols is that they provide strong error correction capabilities for consecutive errors (also called burst errors). For example, consecutive 20-bit errors will not extend to more than 3 symbols, and to the decoder, they appear to be at most 3 error symbols.

[0245] Taking KP4 FEC as an example, its post-correction bit error rate Post-FEC BER = 1×10 -13In the case of FEC, there is about 6.5dB net coding gain (NCG), that is, when the data reaches the bit error rate (BER) level, the required signal-to-noise ratio (SNR) is lower than the SNR required when FEC is not used. For example, the industry generally believes that the required signal-to-noise ratio is about 6.5dB lower than the SNR required when FEC is not used. This greatly increases the distance that the signal can be transmitted.

[0246] However, as the rate continues to increase and the transmission distance continues to increase, the requirements for FEC are also getting higher and higher. But at the same time, stronger FEC often requires more check bits, which makes the bandwidth required for data higher, and the serializer / deserializer rate is limited. Different designs may even have different frequency point requirements, which also limits the choice of FEC. For example, at a transmission rate of 100Gb / s, the industry often uses rates of 103.125G, 106.25G, etc.

[0247] KR4 FEC and KP4 FEC were mentioned above. RS (544, 514) is also used on 400GbE, and in order to deal with burst errors, two code words are interleaved and retransmitted. In this way, burst errors that occur on the link can be distributed to two FEC symbols with a greater probability, and then distributed to two code words, thereby reducing the number of erroneous symbols in each code word. This method can enhance the performance of FEC and successfully correct errors that cannot be corrected by a single code word. The use of interleaving is particularly effective for channels with burst errors. However, when the Ethernet interface is connected to an optical module, the design of the optical module needs to be taken into consideration, so it is often required that the data does not require particularly complex processing on the optical module side.

[0248] In this regard, the embodiment of the present application provides a data encoding method, which can be applied to the current Ethernet interface and the Ethernet interface that may appear in the future. For example, the Ethernet interface used in the present application includes an electrical interface or an optical interface of a rate such as 10GBASE-T, 100GBASE-LR4, 200GBASE-SR4, and also includes an attachment unit interface (AUI) interface, and also includes 100GBASE-CR1, 400GBASE-KR4 and other interfaces. In addition, the method provided in the embodiment of the present application is applicable to both single-segment paths and multi-segment paths. Among them, the difference between a single-segment path and a multi-segment path is whether an active circuit is passed in the middle during the entire data transmission process, or whether all of it is transmitted through a medium. If the data passes through all passive media during the transmission process from the sending end to the receiving end, such as a PCB circuit board and an optical fiber, then this is considered to be a single-segment path. If other circuits, photoelectric conversion devices, etc. are passed between the sending end and the receiving end, then the multi-segment paths are divided into multiple paths with the other circuits, photoelectric conversion devices, etc. as the dividing point. Different paths may have different path characteristics, including burst error behavior, etc.

[0249] See also Fig.15 , the implementation environment of the data encoding method includes a second circuit and a first circuit. The second circuit can be set in a data transmission device 1, and the first circuit can be set in a data transmission device 2. Taking the second circuit as a data sending end and the first circuit as a data receiving end as an example, the second circuit includes a circuit supporting an Ethernet interface, such as a circuit supporting a standard 400GbE interface.

[0250] The second circuit obtains the RS original data received from the media access control (MAC) layer and transmits it to the physical coding sublayer (PCS) by a certain media independent interface (MII). Among them, after the original data is encoded and rate matched by the PCS, it is transcoded with 256B (bit) or 257B, and then the transcoded data is scrambled and aligned with the symbol in turn. Alignment symbol insertion refers to inserting an alignment marker (AM) into the scrambled data, and aligning it through the AM identifier. The AM identifiers between different virtual channels can be different, so that the data on different virtual channels can be distinguished based on AM, and the boundary of the FEC codeword or the boundary of the FEC symbol can be determined by AM alignment during subsequent encoding. After alignment, data distribution is performed before FEC encoding, so that the data is distributed to the corresponding RS encoder. The second circuit includes one or more RS encoders. Taking the 400GbE interface as an example, the RS original data received by the MAC layer of the second circuit is FEC-encoded to obtain two RS (544, 514) code words, such as Fig.15 FEC-CW1 and FEC-CW2 in. After that, the two RS code words are interleaved. On 400GbE, RS (544, 514) is used to deal with burst errors. By using two encoders for encoding and interleaving the results before transmitting, the burst errors that occur on the physical path can be distributed to two FEC symbols and then distributed to two code words, thereby reducing the number of erroneous symbols in each code word. This method can enhance the performance of FEC and successfully correct errors that cannot be corrected by a single codeword. Therefore, the use of interleaving has a significant effect on paths with burst errors. In addition, as a possible implementation method, PCS can use IEEE 802.3 standards, such as IEEE 802.3-2005 and other versions of IEEE 802.3 standards, to perform the above-mentioned encoding, transcoding, and AM insertion functions. In other rates such as 25GbE, 50GbE and 100GbE, the order of encoding, transcoding, scrambling and AM insertion is different, see IEEE 802.3-2018 standard.

[0251] Furthermore, after the two RS codewords are interleaved, the interleaved data is distributed to the virtual lane (called PCS lane in the standard, also called logical channel). Taking 16 virtual lanes as an example, 16×25G, 8×50G or 4×100G output modes are supported. The data is transmitted to the physical medium attachment sublayer (PMA) through the virtual lane, and the PMA performs bit multiplexing (bit-mux), thereby multiplexing the data transmitted on multiple virtual lanes to one or more physical lanes. Fig.15 As shown in the example, the number of virtual channels is m, the number of physical channels is n, and m:n multiplexing (MUX) is implemented in PMA. The size of m and n is not limited in the embodiment of the present application, that is, the number of virtual channels and physical channels is not limited in the embodiment of the present application. The specification of multiplexing in PMA can be determined according to the number of physical channels, so that data can be multiplexed to the physical channels in the form of bit streams. For example, the IEEE 802.3bs standard has defined 400GbE BASE-LR8, which uses 8 parallel optical paths, each supporting 50G rate. The "50G rate" here refers to the rate of transmitting the payload, including the transmission rate of overhead, which is 53.125Gbps; 802.3bs also defines 400GBASE-DR4, which uses 4 parallel optical paths, each supporting 100G rate. The "100G rate" here refers to the rate of transmitting the payload, excluding overhead, such as FEC overhead, etc. The transmission rate including overhead is about 106.25Gbps; and the 802.3cu project uses 4 wavelengths to multiplex into one optical path using WDM, and each wavelength carries 100G rate. In this application, unless otherwise specified, the "transmission rate" mentioned refers to the rate of transmitting the payload.

[0252] After multiplexing the virtual path to the physical path, the second circuit transmits the first data stream to the first circuit through the physical path, that is, transmits the first data stream to the first circuit through the Ethernet interface, and the first data stream is the RS-encoded data. After the first circuit receives the first data stream, it can perform BCH encoding on the first data stream through the BCH encoder to obtain the second data stream. It is then distributed to the physical path, transmitted to the medium through the PMA and the physical media dependent (PMD) layer, and the medium transmits the second data stream to other receiving ends, such as the third circuit. The medium includes but is not limited to optical fiber, backplane or copper cable.

[0253] Fig.15In the implementation environment shown, the virtual path for transmitting data in the second circuit is the first path, and the physical path for transmitting the first data stream between the second circuit and the first circuit is the second path. As a data receiving end, the first circuit may not recognize the boundary of the FEC code word or FEC symbol. After receiving the first data stream, the first circuit uses the first data stream as the original data and performs BCH encoding according to the bit stream. For example, this method can be applied to the situation where there are many random errors in the second path.

[0254] As an optional implementation environment, in the case where the second circuit transmits the first data stream to the first circuit through multiple physical paths, there will be skew in the data between the multiple physical paths. For example, when the first data stream arrives at the first circuit from the second circuit through a circuit board or a cable, the time at which the data sent simultaneously arrives at the first circuit on each physical path is not exactly the same. Therefore, the method provided in the embodiment of the present application realigns the data before performing BCH encoding on the first data stream. In this case, the implementation environment can be as follows Fig.16 As shown. Fig.15 Based on the scheme shown in the figure, in the first circuit, before the BCH encoder processes the first data stream, the data received from multiple physical channels are aligned at the PMA layer. For example, the first data stream consisting of the data received from multiple physical channels is demultiplexed to restore the data of each virtual channel. That is, the data received from n physical channels is converted into m groups of data, and then the m groups of data are aligned. For example, see the above Fig.15 According to the introduction, before the first data stream is transmitted to the first circuit, the data on different virtual channels are distinguished by the AM identifier, so before the first data stream is BCH encoded, the data of each virtual channel can be aligned according to the AM to obtain the aligned data. After that, the aligned first data stream is distributed before FEC encoding and distributed to the corresponding BCH encoder for BCH encoding.

[0255] Whether it is the above Fig.15 The implementation environment shown is still the above Fig.16 In the implementation environment shown, for the data transmission process between the first circuit and the second circuit, the embodiment of the present application provides a data encoding method, which can be applied to the first circuit and the second circuit. Fig.17 , the method includes the following steps:

[0256] Step 1701: The second circuit acquires original data, encodes the original data using RS code, and obtains a first data stream based on the encoded RS code word.

[0257] As mentioned above Fig.15As shown in the implementation environment, the second circuit obtains the original data for RS encoding from the MAC layer. It is transmitted to the PCS by a certain MII. Among them, after the original data is encoded and rate matched at the PCS layer, it is transcoded with 256B (bit) or 257B, and then scrambled and aligned symbols are inserted in sequence after transcoding. After alignment, the data is distributed before FEC encoding, so that the data is distributed to the corresponding RS encoder, and the RS encoder encodes the original data to obtain the RS codeword, so as to obtain the first data based on the encoded RS codeword.

[0258] Step 1702: The second circuit transmits the first data stream to the first circuit through the Ethernet interface.

[0259] As mentioned above Fig.15 As shown in the implementation environment, after the two RS code words are encoded by the RS encoder, the two RS code words are interleaved and the interleaved data is distributed to the virtual path. The data is transmitted to the PMA through the virtual path, and the PMA performs bit multiplexing, thereby realizing multiplexing from the virtual path to one or more physical paths. That is, when the second circuit transmits the first data stream to the first circuit through the Ethernet interface, the first data stream can be transmitted through one or more physical paths.

[0260] Step 1703: The first circuit receives a first data stream transmitted by the second circuit through the Ethernet interface.

[0261] Based on the above-mentioned manner in which the second circuit transmits the first data stream, in a possible implementation manner, the first circuit receives the first data stream transmitted by the second circuit through the Ethernet interface, including: the first circuit receives the first data stream transmitted by the second circuit through the Ethernet interface from multiple physical paths.

[0262] In another possible implementation, the first circuit receives the first data stream transmitted by the second circuit through the Ethernet interface, including: the first circuit receives the first data stream transmitted by the second circuit through the Ethernet interface from multiple physical paths.

[0263] Step 1704: The first circuit performs BCH encoding on the first data stream to obtain a second data stream.

[0264] After the first circuit receives the first data stream, it can perform FEC encoding on the first data stream again, taking BCH encoding as an example this time, to improve the gain by cascade encoding. In one possible implementation, the first circuit includes one or more BCH encoders, and the first circuit receives the first data stream through one or more physical paths. The number of BCH encoders is consistent with the number of physical paths. After the first circuit receives the first data stream, each physical path sends the first data stream transmitted on the physical path to the BCH encoder connected to the physical path, and the BCH encoder performs BCH encoding.

[0265] by Fig.18 Taking the data transmission implementation environment shown as an example, Fig.18 In the example, the second circuit supports 400GbE interface and performs RS encoding on the original data according to RS (544, 514) defined in 802.3bs. The second circuit performs RS encoding through the RS encoder to obtain 2 RS (544, 514) codewords. The data is transmitted to the PMA through 16 virtual channels, and is multiplexed by the PMA in a 16:n specification. The 16 virtual channels are multiplexed to n physical channels, such as circuit-to-module (C2M) or short-distance circuit-to-circuit (C2C-S) connections. The first circuit includes an optical module or a clock and data recovery (CDR). CDR can be a circuit, and the industry also calls CDR a retimer. The first circuit includes BCH encoders that are consistent with the number of physical channels. After each BCH encoder receives the first data stream transmitted by the physical channel connected to it, it encodes the first data stream and obtains the second data stream based on the encoded data. As Fig.18 As shown, after the data is interleaved with 2 RS (544, 514) code words, it is multiplexed by PMA 16:4, and the first data stream is directly output through 4 physical channels. The 4 physical channels can enter 4 BCH encoders respectively and are encoded according to the bit stream in a time division multiplexing manner. After that, the second data stream is transmitted to other circuits, such as the third circuit, through n physical channels. Alternatively, the second data stream is transmitted to other circuits by multiplexing a physical channel in a link multiplexing manner.

[0266] By adding a light FEC, such as a BCH encoder, to the optical module to implement cascade coding, further gain can be obtained through cascading, so that the distance of data transmission can be further increased or the single wavelength rate can be higher. The light FEC, that is, the BCH encoder can adopt the BCH (360, 340) encoding method. Of course, other types of BCH encoders can also be used, and the embodiments of the present application are not limited to this.

[0267] Except for the case where the number of BCH encoders is consistent with the number of physical channels, when the number of BCH encoders included in the first circuit is less than the number of physical channels, the first circuit performs BCH encoding on the first data stream to obtain the second data stream, including: the first circuit performs BCH encoding on the first data stream through one or more BCH encoders in a time division multiplexing manner to obtain the second data stream. Since the number of BCH encoders included in the first circuit is less than the number of physical channels, one or more BCH encoders are multiplexed in a time division multiplexing manner to achieve BCH encoding of all first data streams.

[0268] In a possible implementation, when the number of BCH encoders included in the first circuit is inconsistent with the number of physical channels, the first circuit further includes a scheduler, and the first circuit performs BCH encoding on the first data stream to obtain a second data stream, including: the first circuit schedules the corresponding BCH encoder through the scheduler to perform BCH encoding on the first data stream to obtain the second data stream. Since the number of BCH encoders is greater or less than the number of physical channels, the selection of which BCH encoder to perform encoding among multiple BCH encoders can be implemented through scheduling by the scheduler. In other words, the scheduler is used to connect the physical channel with the corresponding BCH encoder, and the BCH encoder performs BCH encoding on the first data stream. In this case, the first circuit may also include a cache. The first data stream transmitted on the physical channel is first stored in the cache, and then the corresponding BCH encoder is scheduled by the scheduler for BCH encoding.

[0269] by Fig.19 Taking the data transmission implementation environment shown as an example, Fig.19 In the example, the second circuit still supports the 400GbE interface and performs RS encoding on the original data according to RS (544, 514) defined in 802.3bs. The second circuit performs RS encoding through the RS encoder to obtain 2 RS (544, 514) codewords. The data is transmitted to the PMA through 16 virtual channels, and the PMA multiplexes the data in a 16:n specification. The 16 virtual channels are multiplexed to n physical channels, such as C2M or C2C-S connection. The first circuit is an optical module or CDR, including a BCH encoder. The scheduler is used to schedule the BCH encoder to encode the first data stream transmitted by which physical channel, and the second data stream is obtained based on the encoded data. Afterwards, the second data stream is transmitted to other circuits, such as the third circuit, through the scheduling of the scheduler through n physical channels. Alternatively, the second data stream is transmitted to other circuits by multiplexing a physical channel in a link multiplexing manner.

[0270] Furthermore, whether the above Fig.18 or Fig.19In the structure shown, in a possible implementation, BCH encoding is performed on the first data stream, including: filling the data in the first data stream into the corresponding BCH codeword, and the continuous reference number of symbols included in each BCH codeword comes from different RS codewords.

[0271] It should be understood that if the first data stream is transmitted through only one physical path, there is no data skew, so there is no need to identify codeword boundaries or symbol boundaries, and there is no need to change any existing or future Ethernet interface data output mode, and the first data stream can be directly BCH encoded. Fig.18 and Fig.19 In addition to the examples shown, the method provided by the embodiments of the present application can be flexibly expanded to support any number of physical channels. For example, under the 8x50G solution, each physical channel can flow to a BCH encoder, or a smaller number (1, 2, 4, etc.) of BCH encoders can be used for time division multiplexing. For another example, in the 1x100G mode, the first data stream of a physical channel enters a BCH encoder for encoding. Since this method does not change any existing or future Ethernet interface data output mode, it is only placed in the data stream as an enhanced device for secondary encoding, thereby achieving higher gain.

[0272] However, in the case where the first data stream is transmitted through multiple physical paths, since the first data streams transmitted through the multiple physical paths reach the first circuit at different times, an alignment operation is performed before encoding the first data stream. In a possible implementation, after the data in the first data stream is interleaved according to a reference number of RS code words to obtain symbol stream data, it is output to multiple virtual paths, and then bit multiplexed according to the number of physical paths, and transmitted to the first circuit by the multiple physical paths; before the data in the first data stream is filled into the corresponding BCH code word, it also includes: the first circuit demultiplexes the first data stream to recover the data of each virtual path; aligns the data of each virtual path to obtain the aligned data; and fills the data in the first data stream into the corresponding BCH code word, including: filling the aligned data into the corresponding BCH code word.

[0273] Regardless of whether alignment is required, the data in the first data stream is filled into the corresponding BCH codeword, including but not limited to the following three methods:

[0274] Mode 1: Taking the case where the first data stream includes a first number of RS code words, each RS code word includes a first target number of symbols, the data in the first data stream is interleaved according to the first number of RS code words, each BCH encoder corresponds to a second number of BCH code words, each BCH code word includes a second target number of symbols, the second target number is determined according to the first target number, and the second number is determined according to the first number as an example, the data in the first data stream is filled into the corresponding BCH code word, including:

[0275] The first half of each row of the first data stream is sequentially filled into the first third number of BCH codewords of the second number of BCH codewords, and the second half of each row of the first data stream is sequentially filled into the last third number of BCH codewords of the second number of BCH codewords, the third number is half of the second number, and the continuous first number of symbols included in each BCH codeword comes from different RS codewords. The above-mentioned first number can be determined according to the RS code type, or according to the application scenario or experience, and the embodiment of the present application does not limit this.

[0276] For example, taking the first target number as 544, the first number as 2, the second number as 32, and the second target number as 360 as an example, the data in the first data stream is filled into the corresponding BCH codeword, including: filling the first half of the data of each row of the first data stream into the first 16 BCH codewords of the 32 BCH codewords in sequence, and filling the second half of the data of each row of the first data stream into the last 16 BCH codewords of the 32 BCH codewords in sequence, and the two consecutive symbols included in each BCH codeword come from different RS codewords.

[0277] by Fig. 20 Take the BCH encoding process shown as an example, Fig. 20 A schematic diagram of the BCH encoding process of the above method 1 is given in FIG. Fig. 20 As shown, the Ethernet interface of the second circuit has 16 virtual paths, that is, m=16. The first data stream includes 2 RS code words, each RS code word has 544 symbols. For example, A and B represent two RS code words, and the subscripts under A and B represent different symbols in the code word. After the data in the first data stream is interleaved according to the two RS code words, the interleaved data is as follows Fig. 20 The data on these 16 virtual paths are filled into the BCH codewords on the right, such as the first line of data A0B8A in the first data stream. 16 B 24 …A 528 B 536Divide into two parts, the first half is sequentially filled into the first codeword of 32 BCH codewords, that is, BCH-0, and the second half is sequentially filled into the 17th codeword of 32 BCH codewords, that is, BCH-16. Divide the second line of data of the first data stream into two parts, the first half is sequentially filled into the second codeword of 32 BCH codewords, that is, BCH-1, and the second half is sequentially filled into the 18th codeword of 32 BCH codewords, that is, BCH-17. And so on, until all the data in the first data stream is filled into the corresponding BCH codeword. And in this way, the two consecutive symbols included in each BCH codeword come from different RS codewords.

[0278] Method 2: Taking the first data stream including a first number of RS code words, each RS code word including a first target number of symbols, the data in the first data stream is interleaved according to the first number of RS code words, the symbols at the beginning or end of each column of data in the first data stream are sequentially swapped, each BCH encoder corresponds to a second number of BCH code words, each BCH code word includes a second target number of symbols, the second target number is determined according to the first target number, and the second number is determined according to the first number as an example, the data in the first data stream is filled into the corresponding BCH code words, including: filling each column of data of the first data stream into the second number of BCH code words in sequence, and the consecutive first number of symbols included in each BCH code word come from different RS code words.

[0279] For example, taking the first target number as 544, the first number as 2, the second number as 32, and the second target number as 360 as an example, the data in the first data stream is filled into the corresponding BCH codeword, including: filling each column of data of the first data stream into 32 BCH codewords in sequence, and the two consecutive symbols included in each BCH codeword come from different RS codewords.

[0280] by Fig.21 Take the BCH encoding process shown as an example, Fig.21 A schematic diagram of the BCH encoding process of the above method 2 is given in FIG. Fig.21 As shown, the Ethernet interface of the second circuit has 16 virtual paths, that is, m=16. The first data stream includes 2 RS code words, each RS code word has 544 symbols. For example, A and B represent two RS code words, and the subscripts under A and B represent different symbols in the code word. After the data in the first data stream is interleaved according to the two RS code words, the interleaved data is as follows Fig.21 As shown on the left. Fig.21It can be seen that the symbols at the beginning of each column of the first data stream are swapped sequentially starting from the second column, so as to ensure that when each column of data is filled into 32 BCH code words, the two consecutive symbols included in each BCH code word come from different RS code words. For example, A0B0A1B1…A 16 B 16 Fill in BCH-0 in sequence, A 17 B 17 A 18 B 18 …A 33 B 33 Fill in BCH-1 in sequence, and so on, fill the data in the first data stream into the corresponding BCH codeword. Of course, Fig.21 The following description only takes the case where the order of the symbols at the beginning of the second column is permuted as an example. In addition, the order of the symbols at the end of each column can also be permuted.

[0281] It should be noted that the above only uses Mode 1 and Mode 2 to implement that the two consecutive symbols included in each BCH code word come from different RS code words. In addition, other methods can also be used to implement that the two consecutive symbols included in each BCH code word come from different RS code words, that is, no two consecutive symbols come from the same RS code word, and the embodiments of the present application are not limited to this.

[0282] In addition, both the above-mentioned method 1 and method 2 implement BCH encoding after the data in the first data stream is interleaved, and the first circuit does not change the interleaving method. Then, in order to increase the interleaving depth, in the method provided in the embodiment of the present application, the first circuit can also re-interleave the data therein after receiving the first data stream. The BCH encoding method of this method is detailed in the following method 3.

[0283] Method three: the first data stream includes a first number of RS code words, each RS code word includes a first target number of symbols, the data in the first data stream is interleaved according to the first number of RS code words, each BCH encoder corresponds to a second number of BCH code words, each BCH code word includes a second target number of symbols, the second target number is determined according to the first target number, and the second number is determined according to the first number; the data in the first data stream is filled into the corresponding BCH code word, including: deinterleaving the data in the first data stream to obtain the original RS code word; interleaving the original RS code word according to a fourth number of RS code words to obtain interleaved data, the fourth number is greater than the first number; each row of the interleaved data is filled into the second number of BCH code words in sequence, and the fourth number of consecutive symbols included in each BCH code word come from different RS code words.

[0284] Since the data in the first data stream itself has been interleaved, the method provided in the embodiment of the present application first deinterleaves the data in the first data stream after acquiring the first data stream to obtain the original RS codeword. Then re-interleave, use more codewords to interleave during interleaving, thereby increasing the interleaving depth. Then, each row of the re-interleaved data is sequentially filled into the second number of BCH codewords. In this way, the fourth number can be determined according to the RS code type, or according to the application scenario or experience, and the embodiment of the present application does not limit this. Since the depth of re-interleaving is greater than the interleaving depth in the previous first data stream, the fourth number is greater than the first number. In addition, the first circuit can set a cache to interleave after receiving the fourth number of codewords.

[0285] For example, taking the first target number as 544, the first number as 2, the fourth number as 4, and the second target number as 360, the first circuit further deinterleaves the first data stream and recovers the original RS-FEC code words, so that more RS-FEC can be accumulated for stronger interleaving, such as using 4 code words for interleaving. The first circuit performs a certain degree of buffering when receiving the first data stream, and then performs interleaving after receiving the full 4 code words. Fig. 22 and Fig.23 Take the BCH encoding process shown as an example, Fig. 22 and Fig.23 A schematic diagram of a BCH encoding process of the above-mentioned method three is given respectively. Fig. 22 and Fig.23 Two interleaving modes are given as examples, where A, B, C, and D represent symbols from different RS-FEC code words. Fig. 22 and Fig.23 The letters A to D in the figure do not reflect the subscript serial number, but only represent different symbols from different code words. Four RS code words are used for interleaving, so that any four consecutive symbols are from different RS code words.

[0286] It should be noted that, in the above three implementations of filling the data in the first data stream into the corresponding BCH code word, the first target quantity can be determined based on the RS code type. For example, for RS (544, 514), the first target quantity is 544, and each RS code word includes 544 symbols. The second target quantity can be determined based on the first target quantity. For RS (544, 514), BCH (360, 340) can be used, and the second target quantity is 360. For another example, for RS (528, 514), the target quantity is 528, and each RS code word includes 528 symbols. In addition, the method provided in the embodiment of the present application is to use RS and BCH two-stage encoding, and the embodiment of the present application does not limit which RS code type and which BCH code type are used. In other words, for different code types, the first target quantity and the second target quantity can also use other numerical values. In addition, the first target number of symbols and the second target number of symbols may be 10-bit symbols, 1-bit symbols or symbols of other lengths, and the embodiment of the present application does not limit the length of the symbols.

[0287] In addition, no matter which of the above methods is used to fill the data in the first data stream into the corresponding BCH codeword, for the BCH encoding method, the polynomial p(x)=x can be used. 10 +x 3 +x+1. That is, the BCH encoder can be based on the polynomial p(x)=x 10 +x 3 Of course, in addition to the polynomial of P(x) above, there may be other polynomials used in BCH coding, which is not limited in the present application.

[0288] As a possible implementation, after the first circuit performs BCH encoding on the first data stream to obtain the second data stream, it also includes: transmitting the second data stream to the third circuit through a medium using multiple physical paths, or transmitting the second data stream to the third circuit through a medium using one physical path in a time division multiplexing manner. The medium includes but is not limited to optical fiber, backplane or copper cable. For example, taking a 100GbE Ethernet port as an example, it can be sent out in the form of one wavelength carrying a 100G rate and transmitted through optical fiber; or one electrical interface transmits a 100G rate signal and is transmitted through a backplane or copper cable. Alternatively, taking the 800GbE port that may appear in the future as an example, there may be various different solutions such as 8x100G, 4x200G, etc., which can be transmitted on optical fiber, backplane or copper cable.

[0289] See also Fig.24 The embodiment of the present application provides a data decoding method, which can be used in a third circuit, the third circuit is used to apply Fig.17 The second data stream obtained by encoding with the encoding method is decoded. Fig.24 As shown, the method includes the following steps:

[0290] Step 2401: The third circuit receives a second data stream transmitted by the first circuit, where the second data stream is encoded using an RS code and a BCH code.

[0291] In a possible implementation, the third circuit receives the second data stream transmitted by the first circuit, including: receiving the second data stream transmitted by the first circuit using multiple physical paths through a medium, or receiving the second data stream transmitted by the first circuit using one physical path in a time division multiplexing manner through a medium. The medium includes but is not limited to an optical fiber, a backplane, or a copper cable. Fig.17 The encoding method shown performs BCH encoding on the first data stream that has been RS-encoded, so the second data stream is encoded using the RS code and the BCH code.

[0292] Step 2402: The third circuit decodes the second data stream using the BCH code to obtain the first data stream.

[0293] The BCH code used by the third circuit to decode the second data stream is consistent with the code type used by the first circuit to BCH encode the first data stream, thereby ensuring that the third circuit can successfully decode the second data stream to obtain the first data stream.

[0294] Since the first circuit may use one physical path or multiple physical paths to transmit the second data stream in a time division multiplexing manner, in a possible implementation manner, before using the BCH code to decode the second data stream to obtain the first data stream, the method further includes: when receiving the second data stream transmitted by the first circuit in a time division multiplexing manner using one physical path through a medium, demultiplexing the second data stream; decoding the second data stream using the BCH code to obtain the first data stream, including: decoding the demultiplexed data stream using the BCH code to obtain the first data stream.

[0295] In order to avoid skew when the second data stream reaches the third circuit in the manner of transmitting the second data stream through multiple physical paths, in a possible implementation, before decoding the second data stream after demultiplexing using the BCH code, it also includes: aligning the second data stream after demultiplexing; decoding the second data stream after demultiplexing using the BCH code to obtain the first data stream, including: decoding the aligned second data stream using the BCH code to obtain the first data stream. Since the BCH code will not change the AM character, when aligning the second data stream after demultiplexing, the existing AM character in the second data stream can be reused to achieve alignment of the second data stream after demultiplexing.

[0296] Step 2403: The third circuit decodes the first data stream using the RS code to obtain original data.

[0297] The RS code used by the third circuit to decode the first data stream is consistent with the RS code type used when encoding the data in the first data stream, thereby ensuring that the third circuit can successfully decode the first data stream to obtain the original data.

[0298] Based on the above data encoding method and data decoding method, the embodiment of the present application is verified on a field-programmable gate array (FPGA) through modeling. Fig.25 As shown, PRBS31 is used as the original data as an example. PRBS31 is a test data that generates a pseudo-random sequence as the system input. At the encoding end, the original data is encoded with RS (544, 514), and then the result of 4 RS code word interleaving is taken as an example. The first data stream obtained after interleaving is transmitted to the BCH encoder through path 1 through bit multiplexing for BCH encoding to obtain the second data stream. Then, the second data stream is transmitted to the decoding end through path 2. The decoding end first performs BCH decoding on the second data stream to obtain the first data stream. After the first data stream is transmitted through path 3, bit demultiplexing is performed, and then the demultiplexed data is deinterleaved. RS decoding is performed through the RS (544, 514) decoder to obtain the original data.

[0299] Through the above interleaving process, the gain is improved. Fig.26 The comparison diagram shown in the figure shows that compared with the RS-FEC provided by 802.3bs, in the 1E-15 post FEC BER region, the cascade coding scheme provided by the embodiment of the present application can have a 2dB net gain improvement. Whether on the electrical interface or the optical interface, the additional net gain can greatly increase the distance of signal transmission.

[0300] See also Fig. 27, the embodiment of the present application provides a data encoding device, which is used to execute the above data encoding method. Fig. 27 As shown, the device comprises:

[0301] A receiving module 271, configured to receive a first data stream transmitted by the second circuit through an Ethernet interface, wherein the first data stream is obtained by encoding original data using an RS code;

[0302] The encoding module 272 is used to perform BCH encoding on the first data stream to obtain a second data stream.

[0303] In a possible implementation, the receiving module 271 is configured to receive, from a plurality of physical paths, a first data stream transmitted by the second circuit through an Ethernet interface;

[0304] The device includes one or more BCH encoders, and the encoding module 272 is used to connect one BCH encoder to one physical path when the number of the included BCH encoders is consistent with the number of physical paths, and perform BCH encoding on the first data stream transmitted by the corresponding physical path through one or more BCH encoders to obtain a second data stream.

[0305] In a possible implementation, the receiving module 271 is configured to receive, from a plurality of physical paths, a first data stream transmitted by the second circuit through an Ethernet interface;

[0306] The device includes one or more BCH encoders, and also includes a scheduler and an encoding module 272, which is used to schedule the corresponding BCH encoder to perform BCH encoding on the first data stream through the scheduler when the number of BCH encoders included in the first circuit is inconsistent with the number of physical channels to obtain a second data stream.

[0307] In a possible implementation manner, the encoding module 272 is configured to fill the data in the first data stream into the corresponding BCH codeword, and the continuous reference number of symbols included in each BCH codeword comes from different RS codewords.

[0308] In a possible implementation manner, after the data in the first data stream is interleaved according to a reference number of RS code words to obtain symbol stream data, the data is output to multiple virtual paths, bit multiplexed according to the number of physical paths, and transmitted to the data encoding device through the multiple physical paths;

[0309] See also Fig.28 , the data encoding device further comprises:

[0310] A demultiplexing module 273, used for demultiplexing the first data stream and recovering the data of each virtual path;

[0311] An alignment module 274, used for aligning the data of each virtual path to obtain aligned data;

[0312] The encoding module 272 is used to fill the aligned data into the corresponding BCH codeword.

[0313] In a possible implementation, the first data stream includes a first number of RS codewords, each RS codeword includes a first target number of symbols, data in the first data stream is interleaved according to the first number of RS codewords, each BCH encoder corresponds to a second number of BCH codewords, each BCH codeword includes a second target number of symbols, the second target number is determined according to the first target number, and the second number is determined according to the first number;

[0314] The encoding module 272 is used to sequentially fill the first half of the data of each row of the first data stream into the first third number of BCH code words of the second number of BCH code words, and sequentially fill the second half of the data of each row of the first data stream into the last third number of BCH code words of the second number of BCH code words, where the third number is half of the second number, and the continuous first number of symbols included in each BCH code word come from different RS code words.

[0315] In one possible implementation, the first target number is 544, the first number is 2, the second number is 32, and the second target number is 360;

[0316] The encoding module 272 is used to sequentially fill the first half of the data of each row of the first data stream into the first 16 BCH code words of 32 BCH code words, and sequentially fill the second half of the data of each row of the first data stream into the last 16 BCH code words of 32 BCH code words, wherein the two consecutive symbols included in each BCH code word come from different RS code words.

[0317] In a possible implementation, the first data stream includes a first number of RS code words, each RS code word includes a first target number of symbols, data in the first data stream is interleaved according to the first number of RS code words, symbols at the beginning or end of each column of data in the first data stream are sequentially swapped, each BCH encoder corresponds to a second number of BCH code words, each BCH code word includes a second target number of symbols, the second target number is determined according to the first target number, and the second number is determined according to the first number;

[0318] The encoding module 272 is used to sequentially fill each column of data of the first data stream into a second number of BCH code words, wherein the continuous first number of symbols included in each BCH code word comes from different RS code words.

[0319] In one possible implementation, the first target number is 544, the first number is 2, the second number is 32, and the second target number is 360;

[0320] The encoding module 272 is used to fill each column of data of the first data stream into 32 BCH code words in sequence, and the two consecutive symbols included in each BCH code word come from different RS code words.

[0321] In a possible implementation, the first data stream includes a first number of RS codewords, each RS codeword includes a first target number of symbols, data in the first data stream is interleaved according to the first number of RS codewords, each BCH encoder corresponds to a second number of BCH codewords, each BCH codeword includes a second target number of symbols, the second target number is determined according to the first target number, and the second number is determined according to the first number;

[0322] The encoding module 272 is used to deinterleave the data in the first data stream to obtain the original RS codeword; interleave the original RS codeword according to a fourth number of RS codewords to obtain interleaved data, where the fourth number is greater than the first number; and fill each row of the interleaved data into the second number of BCH codewords in sequence, where the fourth number of consecutive symbols included in each BCH codeword come from different RS codewords.

[0323] See also Fig.29 , the data encoding device further comprises:

[0324] The transmission module 275 is used to transmit the second data stream to the third circuit through the medium using multiple physical paths, or to transmit the second data stream to the third circuit through the medium using one physical path in a time division multiplexing manner.

[0325] See also Fig.30 , the embodiment of the present application provides a data decoding device, which is used to perform the above data decoding method. Fig.30 As shown, the device comprises:

[0326] A receiving module 161, configured to receive a second data stream transmitted by the first circuit, where the second data stream is encoded using an RS code and a BCH code;

[0327] A first decoding module 162, configured to decode the second data stream using a BCH code to obtain a first data stream;

[0328] The second decoding module 163 is used to decode the first data stream using the RS code to obtain original data.

[0329] In a possible implementation, the receiving module 161 is configured to receive, through a medium, a second data stream transmitted by the first circuit using multiple physical paths, or to receive, through a medium, a second data stream transmitted by the first circuit using one physical path in a time division multiplexing manner.

[0330] In one possible implementation, see Fig.31 , the data decoding device further comprises:

[0331] A demultiplexing module 164, configured to demultiplex the second data stream when receiving the second data stream transmitted by the first circuit in a time division multiplexing manner using one physical path through the medium;

[0332] The first decoding module 162 is used to decode the demultiplexed data stream using a BCH code to obtain a first data stream.

[0333] In one possible implementation, see Fig.32 , the data decoding device further comprises:

[0334] An alignment module 165, configured to align the second data stream after demultiplexing;

[0335] The first decoding module 162 is used to decode the aligned second data stream using a BCH code to obtain a first data stream.

[0336] It should be understood that the above-mentioned device only uses the division of the above-mentioned functional modules as an example to illustrate when implementing its functions. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0337] It should be noted that the above-mentioned first circuit, second circuit, third circuit, data encoding device and data decoding device can be implemented in one or more chips.

[0338] Based on the same concept, the present application also provides a data transmission device, see Fig.33 The device includes a memory 191 and a processor 192; the memory 191 stores at least one instruction, and the at least one instruction is loaded and executed by the processor 192 to implement any of the above-mentioned data encoding or data decoding methods provided in the embodiments of the present application.

[0339] The present application also provides a data transmission device. Fig.34, the device includes: a transceiver 3401, a memory 3402 and a processor 3403. The transceiver 3401, the memory 3402 and the processor 3403 communicate with each other through an internal connection path, the memory 3402 is used to store instructions, and the processor 3403 is used to execute the instructions stored in the memory to control the transceiver 3401 to receive signals and control the transceiver 3401 to send signals, and when the processor 3403 executes the instructions stored in the memory 3402, the processor 3403 executes any one of the above-mentioned data encoding methods or data decoding methods.

[0340] The present application also provides a data transmission system, which includes the above Figure 27-29 Any of the data encoding devices shown, and the above Figure 30-32 Any data decoding device shown.

[0341] The data encoding device and the data decoding device in the embodiment of the present application can be a personal computer (PC) or a server or a network device. For example, the data encoding device and the data decoding device can be a router, a switch, a server, etc.

[0342] An embodiment of the present application also provides a computer-readable storage medium, in which at least one instruction is stored. The instruction is loaded and executed by a processor to implement any of the above-mentioned data encoding methods or data decoding methods provided in the embodiment of the present application.

[0343] An embodiment of the present application also provides a circuit, including a processor, which is used to call and execute instructions stored in the memory from the memory, so that a communication device equipped with the circuit executes any of the above-mentioned data encoding methods or data decoding methods.

[0344] An embodiment of the present application also provides a circuit, including: an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected via an internal connection path, and the processor is used to execute the code in the memory. When the code is executed, the processor is used to execute any of the above-mentioned data encoding methods or data decoding methods.

[0345] It should be understood that the above processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. It is worth noting that the processor may be a processor supporting the advanced RISC machines (ARM) architecture.

[0346] Further, in an optional embodiment, the above-mentioned processor is one or more, and the memory is one or more. Optionally, the memory can be integrated with the processor, or the memory and the processor are separately arranged. The above-mentioned memory can include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory can also include a non-volatile random access memory. For example, the memory can also store information about the device type.

[0347] The memory may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memory. Among them, the nonvolatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available. For example, static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM) and direct memory bus random access memory (DR RAM).

[0348] The present application provides a computer program. When the computer program is executed by a computer, a processor or a computer can be enabled to execute the corresponding steps and / or processes in the above method embodiments.

[0349] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in this application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integration. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk Solid State Disk), etc.

[0350] The ordinal numbers such as "1", "2", "3", "first", "second", and "third" mentioned in the embodiments of the present application are used to distinguish multiple objects and are not used to limit the order of multiple objects.

[0351] Through the description of the above implementation methods, it can be known that those skilled in the art can clearly understand that all or part of the steps in the above-mentioned embodiment method can be implemented by means of software plus a general hardware platform. Based on such an understanding, the technical solution of the present application can be embodied in the form of a software product, which can be stored in a storage medium, such as a read-only memory (ROM) / RAM, a magnetic disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network communication device such as a router) to execute the methods described in each embodiment of the present application or some parts of the embodiments.

[0352] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can refer to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment. The equipment and system embodiments described above are merely schematic, in which the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative work.

[0353] The above description is only an embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A data encoding method, characterized in that: Executed by a first circuit, the method includes: receiving a first data stream transmitted by the second circuit through an Ethernet interface, wherein the first data stream is obtained by performing FEC encoding on original data using a first forward error correction FEC code, wherein the first FEC code is a Reed-Solomon RS code; Performing FEC encoding on the first data stream again with a second FEC code to obtain a second data stream; The step of performing FEC encoding on the first data stream again with a second FEC code comprises: Fill the data in the first data stream into the second FEC codeword corresponding to the second FEC code, and the continuous number of symbols included in each of the second FEC codewords comes from different Reed-Solomon forward error correction RS-FEC codewords; wherein, After receiving the first data stream, the first circuit does not RS-FEC decode the first data stream before FEC encoding the first data stream again with the second FEC code.

2. The method according to claim 1, characterized in that: The second FEC code is a Bose-Chaudhuri-Hokkewenheim BCH code.

3. The method according to claim 1, characterized in that: The first circuit includes a plurality of FEC encoders for encoding with the second FEC code, and the FEC encoding of the first data stream again with the second FEC code to obtain the second data stream includes: The first data stream is FEC-encoded again with the second FEC code by the multiple FEC encoders to obtain the second data stream.

4. The method according to claim 2, characterized in that: The first circuit includes a plurality of FEC encoders for encoding with the second FEC code, and the FEC encoding of the first data stream again with the second FEC code to obtain the second data stream includes: The first data stream is FEC-encoded again with the second FEC code by the multiple FEC encoders to obtain the second data stream.

5. The method according to claim 1, characterized in that The Ethernet interface is an attachment unit interface AUI.

6. The method according to claim 2, characterized in that The Ethernet interface is an attachment unit interface AUI.

7. The method according to claim 5, characterized in that The attachment unit interface AUI is a chip-to-module C2M interface.

8. The method according to claim 6, characterized in that The attachment unit interface AUI is a chip-to-module C2M interface.

9. The method according to any one of claims 1 to 8, characterized in that: The first circuit is an optical module.

10. The method according to any one of claims 1 to 8, characterized in that: The method further comprises: The second data stream is sent through an 800GbE port, where the 800GbE port is a 4x200GbE port.

11. The method according to claim 9, characterized in that The method further comprises: The second data stream is sent through an 800GbE port, where the 800GbE port is a 4x200GbE port.

12. A data decoding method, characterized in that: Executed by a third circuit, the method includes: Receive a second data stream sent by the first circuit, where the second data stream is obtained by the first circuit performing FEC encoding on the first data stream using a second forward error correction (FEC) code, and the first data stream is obtained by performing FEC encoding on original data using a first FEC code, where the first FEC code is a Reed-Solomon (RS) code, and where the consecutive number of symbols included in each second FEC codeword corresponding to the second FEC code comes from different Reed-Solomon (RS-FEC) codewords; Performing FEC decoding on the second data stream to obtain the first data stream; Perform FEC decoding on the first data stream to obtain the original data; wherein, The performing FEC decoding on the second data stream to obtain the first data stream includes: The second data stream is FEC decoded using the second FEC code but not the first FEC code to obtain the first data stream.

13. The method according to claim 12, characterized in that The second FEC code is a Bose-Chaudhuri-Hokkewenheim BCH code.

14. The method according to claim 12 or 13, characterized in that The first circuit is an optical module.

15. A data encoding device, characterized in that: The device comprises: A receiving module, receiving a first data stream transmitted by the second circuit through an Ethernet interface, wherein the first data stream is obtained by performing FEC encoding on original data using a first forward error correction FEC code, wherein the first FEC code is a Reed-Solomon RS code; An encoding module, configured to perform FEC encoding on the first data stream again using a second FEC code to obtain a second data stream; The step of performing FEC encoding on the first data stream again with a second FEC code includes: Fill the data in the first data stream into the second FEC codeword corresponding to the second FEC code, and the continuous number of symbols included in each of the second FEC codewords comes from different Reed-Solomon forward error correction RS-FEC codewords; wherein, The encoding module is also used for: Before the first data stream is FEC-encoded again with the second FEC code, the first data stream is not RS-FEC-decoded.

16. The data encoding device according to claim 15, characterized in that: The second FEC code is a Bose-Chaudhuri-Hokkewenheim BCH code.

17. The data encoding device according to claim 15, characterized in that: The encoding module includes a plurality of FEC encoders, and the encoding module is used for: The first data stream is FEC-encoded again with the second FEC code by the multiple FEC encoders to obtain the second data stream.

18. The data encoding device according to claim 16, characterized in that: The encoding module includes a plurality of FEC encoders, and the encoding module is used for: The first data stream is FEC-encoded again with the second FEC code by the multiple FEC encoders to obtain the second data stream.

19. The data encoding device according to claim 15, characterized in that: The Ethernet interface is an attachment unit interface AUI.

20. The data encoding device according to claim 16, characterized in that: The Ethernet interface is an attachment unit interface AUI.

21. The data encoding device according to claim 17, characterized in that: The Ethernet interface is an attachment unit interface AUI.

22. The data encoding device according to claim 18, characterized in that: The Ethernet interface is an attachment unit interface AUI.

23. The data encoding device according to any one of claims 19 to 22, characterized in that: The attachment unit interface AUI is a chip-to-module C2M interface.

24. The data encoding device according to any one of claims 15 to 22, characterized in that: The data encoding device also includes: The 800GbE port is used to send the second data stream, and the 800GbE port is a 4x200GbE port.

25. The data encoding device according to any one of claims 15 to 22, characterized in that: The data encoding device is an optical module.

26. The data encoding device according to claim 23, characterized in that: The data encoding device also includes: The 800GbE port is used to send the second data stream, and the 800GbE port is a 4x200GbE port.

27. The data encoding device according to any one of claims 15 to 22, characterized in that: The data encoding device includes an optical module and the second circuit, and the optical module includes the receiving module and the encoding module.

28. The data encoding device according to any one of claims 15 to 22, characterized in that: The data encoding device is a chip.

29. A data decoding device, characterized in that: The device comprises: a receiving module, configured to receive a second data stream transmitted by the first circuit, wherein the second data stream is obtained by the first circuit performing FEC encoding on the first data stream using a second forward error correction (FEC) code, and the first data stream is obtained by performing FEC encoding on original data using a first FEC code, and the first FEC code is a Reed-Solomon (RS) code, wherein a continuous number of symbols included in each second FEC codeword corresponding to the second FEC code comes from different Reed-Solomon (RS-FEC) codewords; A first decoding module, configured to perform FEC decoding on the second data stream to obtain the first data stream; The second decoding module is used to perform FEC decoding on the first data stream to obtain the original data; wherein, The first decoding module is further used for: The second data stream is FEC decoded using the second FEC code but not the first FEC code to obtain the first data stream.

30. The data decoding device according to claim 29, characterized in that: The second FEC code is a Bose-Chaudhuri-Hokkewenheim BCH code.

31. The data decoding device according to claim 29 or 30, characterized in that: The first circuit is an optical module.

32. A communication system, characterized in that: It comprises the data encoding device described in any one of claims 15-28 and the data decoding device described in any one of claims 29-31.

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