Projection display device and control method thereof

Abstract

A projection display device and a control method thereof are provided, which suppresses a display defect in a case where a projection position is shifted. The projection display device includes a liquid crystal panel having a plurality of panel pixels; a light path shifting element which shifts a position of a projection pixel projected from the panel pixels for each unit period included in a first unit period to a fourth unit period in one frame period; and a display control circuit which controls the liquid crystal panel and the light path shifting element, the display control circuit supplying a data signal to the plurality of panel pixels for each unit period, supplying a signal based on pixel data of an image pixel constituting an image image as the data signal to a peripheral panel pixel disposed at a periphery among the plurality of panel pixels in a part of the unit periods in either one of an odd frame period and an even frame period, and supplying a signal having a gradation level of a threshold value or less as the data signal in the unit periods other than the part of the unit periods in the one frame period.

Description

Technical Field

[0001] This invention relates to a projection display device and its control method. Background Technology

[0002] In projection display devices that project image light generated by a liquid crystal panel onto a screen or the like, a technique is known to simulate increasing resolution using a light path shifting element. Specifically, in a projection display device, a frame period is divided into multiple unit periods, and the projection position of a panel pixel in the liquid crystal panel is shifted for each of these multiple unit periods, representing grayscale levels specified by multiple pixel data in the image data (see, for example, Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2020-107984

[0004] However, in the above-mentioned techniques, there is a problem that a portion of the image data is visually confirmed missing depending on the projection position. Summary of the Invention

[0005] To address the aforementioned issues, one aspect of the present invention provides a projection-type display device comprising: a liquid crystal panel having a plurality of panel pixels; an optical path shifting element that shifts the position of a projection pixel projected from the plurality of panel pixels for each unit period of k unit periods from a first unit period to a kth unit period contained in a frame period, wherein k is an integer greater than or equal to 2; and a display control circuit that controls the liquid crystal panel and the optical path shifting element, the display control circuit providing a data signal to the plurality of panel pixels for each unit period, wherein for a portion of a frame period in either the first frame period or the second frame period, a signal based on pixel data of image pixels constituting an image is provided as the data signal to a peripheral panel pixel disposed at the periphery of the plurality of panel pixels, and for unit periods other than the portion of a frame period in either one frame period, a signal with a gray level below a threshold is provided as the data signal to the peripheral panel pixel. Attached Figure Description

[0006] Figure 1 This is a diagram showing the projection-type display device according to the first embodiment.

[0007] Figure 2 This is a block diagram showing the structure of a projection display device.

[0008] Figure 3 This is a three-dimensional diagram showing the structure of a liquid crystal panel in a projection display device.

[0009] Figure 4 This is a cross-sectional view showing the structure of a liquid crystal panel.

[0010] Figure 5 It is a block diagram representing the electrical structure of a liquid crystal panel.

[0011] Figure 6 This is a diagram showing the structure of the pixel circuitry in a liquid crystal panel.

[0012] Figure 7 It is a top view showing the arrangement of the panel pixels in the LCD panel.

[0013] Figure 8 This is a diagram showing the frame duration and unit duration in a projection display device.

[0014] Figure 9 This is a diagram illustrating the operation of the optical path shifting element.

[0015] Figure 10 It is a diagram that shows the relationship between the arrangement of image pixels and the arrangement of panel pixels.

[0016] Figure 11 This is a diagram showing the correspondence between image pixels and panel pixels during each frame in the first embodiment.

[0017] Figure 12 This is a diagram showing the order of the image pixels provided to the panel pixels in the first embodiment and the positions of the image pixels corresponding to the panel pixels.

[0018] Figure 13 This is a diagram showing the relationship between image pixels, panel pixels, and projection position during odd-numbered frames in the first embodiment.

[0019] Figure 14 This is a diagram showing the relationship between image pixels, panel pixels, and projection position during even-numbered frames in the first embodiment.

[0020] Figure 15 This is a diagram showing the data signals provided to the panel pixels during odd-numbered frames in the first embodiment.

[0021] Figure 16 This is a diagram showing the data signals provided to the panel pixels during even-numbered frames in the first embodiment.

[0022] Figure 17 This is a top view showing the arrangement of panel pixels in the liquid crystal panel of the second embodiment.

[0023] Figure 18 This is a diagram showing the data signals provided to the panel pixels during odd-numbered frames in the second embodiment.

[0024] Figure 19 This is a diagram showing the data signals provided to the panel pixels during even-numbered frames in the second embodiment.

[0025] Figure 20 This is a top view showing the arrangement of panel pixels in the liquid crystal panel of the third embodiment.

[0026] Figure 21 This is a diagram showing the order of the image pixels provided to the panel pixels in the third embodiment and the positions of the image pixels corresponding to the panel pixels;

[0027] Figure 22 This is a diagram showing the data signals provided to the panel pixels during odd-numbered frames in the third embodiment.

[0028] Figure 23 This is a diagram showing the data signals provided to the panel pixels during even-numbered frames in the third embodiment.

[0029] Figure 24 It is a top view showing the arrangement of panel pixels in a proportional LCD panel.

[0030] Figure 25 This is a diagram representing the data signals provided to panel pixels during odd-numbered frames in a comparative format.

[0031] Figure 26 This is a diagram representing the data signals provided to panel pixels during even-numbered frames in a comparative format.

[0032] Label Explanation

[0033] 1: Projection type display device; 100R, 100G, 100B: Liquid crystal panel; 110: Pixel circuit; 118: Pixel electrode; 120: Liquid crystal element; 20: Display control circuit; 22: Processing circuit; 230: Optical path shifting element. Detailed Implementation

[0034] Hereinafter, the electro-optical device according to the embodiments will be described with reference to the accompanying drawings. Furthermore, the dimensions and scales of the various parts in the drawings differ appropriately from the actual dimensions and scales. Additionally, the embodiments described below are preferred examples, and therefore various preferred limitations are imposed technically; however, the scope of this disclosure is not limited to these methods unless specifically limited in the following description.

[0035] Figure 1This diagram illustrates the optical structure of the projection display device 1 according to the embodiment. As shown, the projection display device 1 includes liquid crystal panels 100R, 100G, and 100B. Furthermore, a lamp unit 2102, composed of a white light source such as a halogen lamp, is disposed inside the projection display device 1. The projected light emitted from this lamp unit 2102 is separated into three primary colors—red (R), green (G), and blue (B)—by three reflectors 2106 and two dichroic mirrors 2108 disposed inside the lamp unit 2102. Specifically, R light is incident on the liquid crystal panel 100R, G light on the liquid crystal panel 100G, and B light on the liquid crystal panel 100B.

[0036] Furthermore, the optical path of B is longer than that of R and G, so it is necessary to prevent losses in the optical path of B. Therefore, a relay lens system 2121 consisting of an incident lens 2122, a relay lens 2123, and an exit lens 2124 is provided in the optical path of B.

[0037] The liquid crystal panel 100R has multiple pixel circuits. Each pixel circuit contains a liquid crystal element. As described later, the liquid crystal elements of the liquid crystal panel 100R are driven based on a data signal corresponding to R, thereby achieving a transmittance corresponding to the voltage of that data signal. Therefore, in the liquid crystal panel 100R, a transmissive image of R is generated by individually controlling the transmittance of each liquid crystal element. Similarly, in the liquid crystal panel 100G, a transmissive image of G is generated based on a data signal corresponding to G, and in the liquid crystal panel 100B, a transmissive image of B is generated based on a data signal corresponding to B.

[0038] Transmitted images of various colors generated by liquid crystal panels 100R, 100G, and 100B are incident on dichroic prism 2112 from three directions. In dichroic prism 2112, the light from R and B is refracted at 90 degrees, while the light from G travels in a straight line. Therefore, dichroic prism 2112 synthesizes the images of each color. The synthesized image from dichroic prism 2112 is incident on projection lens 2114 via optical path shifting element 230.

[0039] The projection lens 2114 magnifies the composite image after passing through the optical path shifting element 230 and projects it onto the screen Scr.

[0040] The optical path shifting element 230 shifts the composite image emitted from the dichroic prism 2112. Specifically, the optical path shifting element 230 shifts the image projected onto the screen Scr relative to the projection surface in the left-right direction and / or up-down direction.

[0041] Furthermore, the transmitted images of liquid crystal panels 100R and 100B are projected after being reflected by the dichroic prism 2112, while the transmitted image of liquid crystal panel 100G is projected in a straight line. Therefore, the transmitted images of liquid crystal panels 100R and 100B are in a left-right inverted relationship relative to the transmitted image of liquid crystal panel 100G.

[0042] For ease of explanation, when observing the projection surface of the screen Scr from the projection display device 1, let the left-right direction be the X-axis and the up-down direction be the Y-axis. Furthermore, let the right direction along the left-right axis be the X-direction, and the left direction be the opposite direction of the X-direction. Similarly, let the down direction along the up-down direction of the Y-axis be the Y-direction, and the up direction be the opposite direction of the Y-direction. Let the projection direction of the projection display device 1 be the Z-direction.

[0043] Figure 2 This is a block diagram showing the electrical structure of the projection display device 1. As shown, the projection display device 1 includes a display control circuit 20, the aforementioned liquid crystal panels 100R, 100G, and 100B, and an optical path shifting element 230.

[0044] The image data Vid-in is provided synchronously with the synchronization signal Sync from a higher-level device such as a host device (not shown in the diagram). The image data Vid-in specifies the grayscale level of the pixels in the image to be displayed in 8 bits per RGB.

[0045] Furthermore, the pixels of the image specified by the image data Vid-in are denoted as image pixels, the data specifying the grayscale level of the image pixels are denoted as pixel data, and the pixels of the composite image of the liquid crystal panels 100R, 100G, and 100B are denoted as panel pixels. In this embodiment, for convenience, panel pixels are divided into effective panel pixels and electrically separated panel pixels. Electrically separated panel pixels have a transmittance corresponding to the pixel data during a certain period, and a minimum transmittance during other periods, as detailed later. However, for a portion of the effective panel pixels, there are also cases where the transmittance corresponds to the pixel data and cases where the transmittance is at its minimum.

[0046] Furthermore, the position of the panel pixel that is shifted by the optical path shifting element 230 and projected onto the screen Scr is denoted as the projection position.

[0047] In the composite image of liquid crystal panels 100R, 100G, and 100B, the panel pixels are arranged in a matrix both vertically and horizontally. In an embodiment, the arrangement of image pixels, whose grayscale level is specified by image data Vid-in, is, for example, about twice as large in the vertical direction and about twice as large in the horizontal direction compared to the arrangement of panel pixels composited from liquid crystal panels 100R, 100G, or 100B.

[0048] In this embodiment, the color image projected onto the screen Scr is represented by combining the transmissive images of the liquid crystal panels 100R, 100G, and 100B. Therefore, the pixel, the smallest unit of the color image, can be divided into red sub-pixels of the liquid crystal panel 100R, green sub-pixels of the liquid crystal panel 100G, and blue sub-pixels of the liquid crystal panel 100B. However, regarding the sub-pixels in the liquid crystal panels 100R, 100G, and 100B, in cases where a specific color is not required, or where only brightness is a concern, it is not necessary to specifically designate them as sub-pixels. Therefore, in this description, the display unit in the liquid crystal panels 100R, 100G, and 100B is also defined as a panel pixel.

[0049] The synchronization signal Sync includes a vertical synchronization signal indicating the start of vertical scanning of image data Vid-in, a horizontal synchronization signal indicating the start of horizontal scanning, and a timing clock signal indicating the amount of one image pixel in image data Vid-in.

[0050] The display control circuit 20 includes a processing circuit 22 and conversion circuits 23R, 23G and 23B.

[0051] After accumulating image data Vid-in provided from the upper-level device for one or more frames, the processing circuit 22 reads out the pixel data of the image pixel corresponding to the projection position of the optical path shifting element 230 and outputs it according to each RGB component. In addition, the processing circuit 22 sometimes outputs black data that minimizes transmittance to the effective panel pixels and electrically separated panel pixels according to the projection position.

[0052] The R component in the pixel data or black data output from the processing circuit 22 is denoted as Vad_R, the G component as Vad_G, and the B component as Vad_B.

[0053] In the projection display device 1, since the projection position varies according to each unit period after dividing a frame period into 4 parts, there can be 8 projection positions in 8 unit periods of 2 consecutive frames. However, in the embodiment, as described later, the projection position is set to 7 in 8 unit periods.

[0054] In addition, the unit period refers to the period during which the user visually confirms, through the composite image of the LCD panels 100R, 100G and 100B, that the resolution of the image is reduced to 1 / 4 of the resolution of the image specified by the image data Vid-in for one frame period.

[0055] The processing circuit 22 controls the projection position of the optical path shifting element 230 during each unit period. Specifically, the processing circuit 22 controls the shift of the optical path shifting element 230 along the X-axis direction via the control signal P_x, and controls the shift of the optical path shifting element 230 along the Y-axis direction via the control signal P_y.

[0056] Furthermore, details regarding the projection position for each unit period and which image pixel in the image pixels specified by the image data Vid-in corresponds to each projection position will be described later.

[0057] Furthermore, the processing circuit 22 generates a control signal Ctr for controlling the liquid crystal panels 100R, 100G, and 100B according to each unit period.

[0058] Conversion circuit 23R converts the R component data Vad_R into an analog voltage pixel signal, which is then provided to the LCD panel 100R as the data signal Vid_R. Conversion circuit 23G converts the G component data Vad_G into an analog voltage pixel signal, which is then provided to the LCD panel 100G as the data signal Vid_G. Conversion circuit 23B converts the B component data Vad_B into an analog voltage pixel signal, which is then provided to the LCD panel 100B as the data signal Vid_B.

[0059] Next, LCD panels 100R, 100G, and 100B will be described. LCD panels 100R, 100G, and 100B differ only in the color of the incident light, i.e., the wavelength; their construction is identical. Therefore, for LCD panels 100R, 100G, and 100B, the reference numeral will be 100, and they will be described in a general manner without specifying a color.

[0060] Figure 3 This diagram shows the main parts of the LCD panel 100. Figure 4 Therefore Figure 3 A cross-sectional view cut off by the Hh line.

[0061] As shown in these figures, in the liquid crystal panel 100, the element substrate 100a with pixel electrodes 118 and the opposing substrate 100b with common electrodes 108 are bonded together by sealing material 90 in such a way that the electrode forming surfaces are facing each other and a fixed gap is maintained. Liquid crystal 105 is sealed in the gap.

[0062] As the component substrate 100a and the opposing substrate 100b, transparent substrates such as glass and quartz are used respectively. Figure 3As shown, one side of the component substrate 100a extends from the opposing substrate 100b. In this extended area, a plurality of terminals 106 are arranged laterally in the figure. One end of an FPC (Flexible Printed Circuits) substrate (not shown) is connected to the plurality of terminals 106. Furthermore, the other end of this FPC substrate is connected to the display control circuit 20 and is provided with the various signals described above.

[0063] On the surface of the component substrate 100a facing the opposing substrate 100b, a pixel electrode 118 is formed, for example, by patterning a transparent conductive layer such as ITO (Indium Tin Oxide).

[0064] In addition, various elements other than electrodes are provided on the opposing surfaces of the component substrate 100a and the opposing surfaces of the opposing substrate 100b, but these are omitted in the figure.

[0065] Figure 5 This is a block diagram showing the electrical structure of the liquid crystal panel 100. In the liquid crystal panel 100, a scan line driving circuit 130 and a data line driving circuit 140 are provided at the periphery of the display area 10.

[0066] In the display area 10 of the liquid crystal panel 100, pixel circuits 110 are arranged in a matrix. Specifically, in the display area 10, multiple scan lines 12 are arranged extending horizontally, and multiple data lines 14 extend vertically and are electrically isolated from the scan lines 12. Furthermore, the intersections of the pixel circuits 110 with the multiple scan lines 12 and the multiple data lines 14 are arranged in a matrix.

[0067] With the number of scan lines 12 being (m+2) and the number of data lines 14 being (n+2), the pixel circuit 110 is arranged in a matrix of (m+2) rows × (n+2) columns. Both m and n are integers greater than or equal to 2. In the scan lines 12 and pixel circuit 110, to distinguish the rows of the matrix, they are sometimes referred to as rows 1, 2, 3, ..., m, (m+1), and (m+2) from top to bottom in the diagram. Similarly, in the data lines 14 and pixel circuit 110, to distinguish the columns of the matrix, they are sometimes referred to as columns 1, 2, 3, ..., n, (n+1), and (n+2) from left to right in the diagram.

[0068] The scan line driving circuit 130, under the control of the display control circuit 200, selects scan lines 12 one by one in the order of rows 1, 2, 3, ..., m, (m+1), (m+2), and sets the scan signal for the selected scan line 12 to H level. Additionally, the scan line driving circuit 130 sets the scan signal for scan lines 12 other than the selected scan line 12 to L level.

[0069] The data line driving circuit 140 latches the amount of one line of data signal provided by the corresponding color circuit in the processing circuits 220R, 220G or 220B, and outputs it via the data line 14 to the pixel circuit 110 located on the scan line 12 during the period when the scan signal for the scan line 12 is at level H.

[0070] Figure 6 This is a diagram showing the equivalent circuit of a total of four pixel circuits 110, consisting of two rows and two columns, corresponding to the intersections of two adjacent scan lines 12 and two adjacent data lines 14.

[0071] As shown in the figure, the pixel circuit 110 includes a transistor 116 and a liquid crystal element 120. The transistor 116 is, for example, an n-channel thin-film transistor. In the pixel circuit 110, the gate node of the transistor 116 is connected to the scan line 12, while its source node is connected to the data line 14, and its drain node is connected to the pixel electrode 118, which is square in shape when viewed from above.

[0072] A common electrode 108 is provided for all pixels in a manner opposite to the pixel electrode 118. A voltage LCcom is applied to the common electrode 108. Furthermore, liquid crystal 105 is sandwiched between the pixel electrode 118 and the common electrode 108 as described above. Therefore, according to each pixel circuit 110, a liquid crystal element 120 is constructed by sandwiching liquid crystal 105 between the pixel electrode 118 and the common electrode 108.

[0073] Furthermore, the storage capacitor 109 is connected in parallel with the liquid crystal element 120. One end of the storage capacitor 109 is connected to the pixel electrode 118, and the other end is connected to the capacitor line 107. The capacitor line 107 is subjected to a time-constant voltage, such as the same voltage LCcom applied to the common electrode 108. The pixel circuit 110 is arranged in a matrix in the extension direction of the scan line 12 (horizontal) and the extension direction of the data line 14 (vertical), therefore the pixel electrodes 118 included in the pixel circuit 110 are also arranged in both the vertical and horizontal directions.

[0074] In scan line 12 where the scan signal is at level H, the transistor 116 of the pixel circuit 110 corresponding to scan line 12 is turned on. With the transistor 116 turned on, data line 14 and pixel electrode 118 are electrically connected, so the data signal supplied to data line 14 reaches pixel electrode 118 via the turned-on transistor 116. If scan line 12 is at level L, transistor 116 is turned off, but the voltage of the data signal reaching pixel electrode 118 is maintained by the capacitance of liquid crystal element 120 and the storage capacitor 109.

[0075] As is well known, in the liquid crystal element 120, the orientation of the liquid crystal molecules varies according to the electric field generated by the pixel electrode 118 and the common electrode 108. Therefore, the liquid crystal element 120 has a transmittance corresponding to the effective value of the applied voltage.

[0076] Furthermore, the area in the liquid crystal element 120 that functions as a pixel, i.e., the area with transmittance corresponding to the effective value of the voltage, is the area where the pixel electrode 118 overlaps with the common electrode 108 when viewed from above the element substrate 100a and the opposing substrate 100b. The pixel electrode 118 is square when viewed from above, therefore the shape of the pixels in the liquid crystal panel 100 is also square.

[0077] In addition, in the embodiment, the liquid crystal 105 is in VA (Vertical Alignment) mode, which is a normally black mode where the transmittance is lowest when the applied voltage to the liquid crystal element 120 is zero and the transmittance increases as the applied voltage increases.

[0078] In this way, the liquid crystal element 120 functions as a panel pixel of the liquid crystal panel 100. Therefore, the arrangement of the panel pixels is the same as that of the pixel circuit 110. Furthermore, there is no difference in the construction and electrical structure between the effective panel pixels and the electrically separated panel pixels.

[0079] The operation of providing data signals to the pixel electrodes 118 of the liquid crystal element 120 is performed sequentially in a unit period, in the order of rows 1, 2, 3, ..., m, (m+1), (m+2). Thus, in the liquid crystal elements 120 of the pixel circuit 110 arranged in (m+2) rows and (n+2) columns, voltages corresponding to the data signals are maintained, each liquid crystal element 120 becomes a target transmittance, and a transmissive image of the corresponding color is generated through the liquid crystal elements 120 arranged in (m+2) rows and (n+2) columns.

[0080] In this way, the transmission image is generated according to each RGB, and the synthesized RGB color image is projected onto the screen Scr.

[0081] The data Vad_R, Vad_G, and Vad_B output from the processing circuit 22 corresponding to one unit period are pixel data of the image pixels corresponding to that unit period or black data with the lowest gray level. Therefore, at least during that unit period, a composite color image corresponding to the projection position is projected at that projection position.

[0082] Figure 7 It is a top view showing the arrangement of panel pixels, and a magnified view showing the upper left (UL), upper right (UR), lower left (DL), and lower right (DR) ends of the panel pixel arrangement.

[0083] As described above, the pixel circuit 110, i.e., the panel pixels, are arranged in a matrix of (m+2) rows × (n+2) columns. In this arrangement of panel pixels, in the first embodiment, the effective panel pixels Vp are arranged in a matrix of m rows × n columns, excluding the first row, the (m+2)th row, the first column, and the (n+2)th column.

[0084] The electrically separated panel pixel Dp is configured as a frame surrounding the area of ​​the effective panel pixel Vp arranged in m rows × n columns. In other words, the electrically separated panel pixel Dp is arranged in the left column L1, the top row L2, the right column L3, and the bottom row L4 of the panel pixel arrangement in the (m+2) rows × (n+2) columns.

[0085] exist Figure 7 In the figure, boundary 192 is an imaginary line representing the boundary between the effective panel pixel Vp and the electrically separated panel pixel Dp, and outer edge 194 is an imaginary line representing the outer edge of the area where the panel pixels are arranged. Relative to the area where the panel pixels are arranged, a light-shielding part 196 is provided outside the outer edge 194, as shown by the shaded area in the figure, which functions as a separator (border).

[0086] Furthermore, there is no structural difference between the effective panel pixel Vp and the electrically separated panel pixel Dp; the different names are merely for ease of distinction.

[0087] As described above, the arrangement of image pixels in the image data Vid-in is approximately twice as large vertically and twice as large horizontally as the arrangement of panel pixels in the liquid crystal panels 100R, 100G, and 100B (m+2) rows and (n+2) columns, which is 2m rows and 2n columns. In other words, the arrangement of panel pixels is approximately half the size of the arrangement of image pixels both vertically and horizontally.

[0088] Therefore, in the implementation, from the perspective of a frame period, by shifting a panel pixel at a total of 4 locations (2 vertical locations × 2 horizontal locations), it is visually recognized as a panel pixel representing 4 image pixels specified by the image data Vid-in.

[0089] However, in a structure that simply shifts a panel pixel to four positions within one frame to represent an image pixel, display quality can sometimes be degraded. Therefore, in this implementation, the projection position of a panel pixel is shifted per unit period of eight units over two frames to represent the image pixel. Furthermore, the direction of shifting the projection position per unit period in odd-numbered frames is set to be opposite to the direction of shifting the projection position per unit period in even-numbered frames. In other words, the arrangement of the four image pixels represented in odd-numbered frames and the arrangement of the four image pixels represented in even-numbered frames are point-symmetric about a common image pixel.

[0090] Figure 8 This is a diagram used to illustrate the relationship between frames and unit periods in the implementation method. As shown in the diagram, in the implementation method, the 2-frame (2F) period is divided into an earlier odd-numbered frame period and a later even-numbered frame period.

[0091] Odd-numbered frame periods are divided into four unit periods. To easily distinguish these four unit periods, they are assigned the numbers f1-1, f1-2, f1-3, and f1-4 in chronological order. Even-numbered frame periods are also divided into four unit periods. To easily distinguish these four unit periods, they are assigned the numbers f2-1, f2-2, f2-3, and f2-4 in chronological order.

[0092] Furthermore, the number "4" in both odd-numbered and even-numbered frame periods is an example of k being an integer greater than 2. Additionally, odd-numbered frame periods are examples of the first frame period, and even-numbered frame periods are examples of the second frame period. Unit periods f1-1 and f2-1 are examples of the first unit period, unit periods f1-2 and f2-2 are examples of the second unit period, unit periods f1-3 and f2-3 are examples of the third unit period, and unit periods f1-4 and f2-4 are examples of the fourth unit period.

[0093] A frame period refers to the period during which one frame of image data (Vid-in) from the higher-level device is provided. When the frequency of the vertical synchronization signal included in the Sync signal is 60Hz, a frame period is 16.7 milliseconds, which is one cycle. In this case, the length of each unit period is 1 / 4 of the length of a frame period, i.e., 4.17 milliseconds.

[0094] Figure 9 This is a diagram showing an example of the waveforms of the control signals P_x and P_y provided to the optical path shifting element 230.

[0095] The optical path shifting element 230 shifts the image projected onto the screen Scr relative to the projection surface along the X and Y axes. For convenience, this shift amount will be explained in terms of the size of the pixels projected onto the screen Scr, i.e., the size of the panel pixels.

[0096] The control signals P_x and P_y take any one of the three values: +A, 0, and -A during the unit periods f1-1 to f1-4 and f2-1 to f2-4, excluding the back-end period. The levels of the control signals P_x and P_y change during the back-end period. The back-end period is equivalent to the vertical scan retrace period.

[0097] In addition, the level of the control signal P_x or P_y may be fixed for two consecutive unit periods.

[0098] For ease of explanation, the projection position of the period other than the back end period in the unit period f1-1 of the odd frame period, that is, the projection position of the period when the level of control signals P_x and P_y is 0, is set as the reference position.

[0099] If the level of the control signal P_x is +A, the optical path shifting element 230 shifts the projection position from the reference position to half of the panel pixel in the X direction. If the level of the control signal P_x is -A, the projection position shifts from the reference position to half of the panel pixel in the opposite direction of the X direction.

[0100] If the level of the control signal P_y is +A, the optical path shifting element 230 shifts the projection position from the reference position to half of the panel pixel in the Y direction. If the level of the control signal P_y is -A, the projection position shifts from the reference position to half of the panel pixel in the opposite direction in the Y direction.

[0101] Therefore, for example, if the level of the control signal P_x is +A and the level of the control signal P_y is +A, the optical path shifting element 230 shifts the projection position from the reference position by half of the panel pixel in the X and Y directions, respectively.

[0102] In addition, Figure 9 In the diagram, the arrows at the end of each unit period indicate the direction in which the projection position shifts when the levels of control signals P_x and P_y change or remain constant during that end period.

[0103] In addition, the shift of the projection position by the optical path shifting element 230 is sometimes not consistent with the level of the control signals P_x and P_y, but is accompanied by a time delay.

[0104] Next, it will be explained which image pixel of the image data Vid-in is represented by the panel pixels of the liquid crystal panel 100 during odd-numbered frames and even-numbered frames. Furthermore, "representing a certain image pixel" means that the panel pixel becomes a brightness (luminance) equivalent to the grayscale level specified by the pixel data, based on the data signal corresponding to that image pixel.

[0105] Figure 10 The left column of the diagram is a partial image extracted from the image data Vid-in to illustrate the arrangement of image pixels; specifically, it shows the image pixels located at the top left of the image. The right column shows the arrangement of panel pixels corresponding to the arrangement of image pixels in the left column.

[0106] In addition, Figure 10 In the left column, to distinguish the image pixels of the image data Vid-in, for convenience, the first row is labeled A11, B11, A21, B21, A31, and B31 respectively. The same applies to rows 2 through 5, as shown in the figure.

[0107] exist Figure 10 In the right column, for the convenience of distinguishing panel pixels, the first row is assigned p11, p21 and p31, and the second row is assigned p12, p22 and p32 as labels.

[0108] Figure 11 This diagram illustrates the image pixels represented by a panel pixel during odd-numbered frames and even-numbered frames. Furthermore, in the diagram, the thick black frame enclosing four image pixels (2 rows x 2 columns) represents the set of image pixels represented by one panel pixel. The four image pixels represented by one panel pixel differ between odd-numbered and even-numbered frames. Specifically, in the first embodiment, the 2×2 image pixels represented by a certain panel pixel during even-numbered frames are offset by one pixel to the right and one pixel downwards relative to the 2×2 image pixels represented by the same panel pixel during odd-numbered frames.

[0109] Figure 12 The top section focuses specifically on panel pixel p11, showing the order in which image pixels are represented by panel pixel p11 during odd-numbered and even-numbered frame periods. As shown, panel pixel p11 represents image pixels C11, B11, A11, and D11 sequentially during unit periods f1-1 to f1-4 in odd-numbered frame periods, and represents image pixels C11, B12, A22, and D21 sequentially during unit periods f2-1 to f2-4 in even-numbered frame periods. In other words, the order in which panel pixel p11 represents image pixels during odd-numbered frame periods and the order in which panel pixel p11 represents image pixels during even-numbered frame periods are point-symmetric with respect to image pixel C11.

[0110] Figure 12 The lower section is a diagram showing the positions and order of image pixels C11, B11, A11, and D11 represented by panel pixel p11 in unit periods f1-1 to f1-4 during odd-numbered frames, labeled 1 to 4. For example, position 3 in panel pixel p11 indicates that, when viewed over two frame periods, panel pixel p11 is represented in the third unit period f1-3. Figure 12Image pixel A11 at position 3 in the upper column. Furthermore, regarding this reference numeral, parentheses are omitted in the accompanying drawings, but are indicated with parentheses in the description. Similarly, in the unit periods f2-1 to f2-4 during even-numbered frames, the positions and order of image pixels C11, B12, A22, and D21 represented by panel pixel p11 are indicated by 5 to 8.

[0111] Figure 13 and Figure 14 This diagram illustrates which image pixel is represented at which projection position by a panel pixel in the projection-type display device 1 of the embodiment. More specifically, Figure 13 It means Figure 10 In which projection position do the 6 panel pixels appear during the unit period f1-1 to f1-4 in odd-numbered frames? Figure 10 The left column shows the image pixels. Additionally, Figure 14 It is a diagram that shows the projection position of the image pixels in the unit period f2-1 to f2-4 during the even-numbered frame period of the 6 panel pixels.

[0112] For convenience, the projection position in the unit period f1-1 during odd-numbered frames is set as the reference position as described above. For example... Figure 13 As shown, during the unit period f1-1 of the odd-numbered frames, panel pixels p11, p21, p31, p12, p22, and p32 represent the image pixels C11, C21, C31, C12, C22, and C32 with shadows, respectively. That is, among the four image pixels represented by one panel pixel during the odd-numbered frames, the image pixel at position (1) is represented during the unit period f1-1.

[0113] During the latter part of unit period f1-1 (vertical retrace period), the optical path shifting element 230 shifts the projection position from the reference position in unit period f1-1 (shown by the dashed line) by 0.5 pixels in the upward direction (opposite to the Y direction) of the panel pixel. In the next unit period f1-2, panel pixels p11, p21, p31, p12, p22, and p32 represent the shadowed image pixels B11, B21, B31, B12, B22, and B32, respectively. That is, of the four image pixels represented by one panel pixel during odd-numbered frame periods, the image pixel at position (2) is represented in unit period f1-2.

[0114] During the latter part of unit period f1-2, the optical path shifting element 230 shifts the projection position from the projection position in unit period f1-2 (shown by the dashed line) to the left (opposite to the X direction) by 0.5 pixels of the panel pixel. In the next unit period f1-3, panel pixels p11, p21, p31, p12, p22, and p32 represent the shadowed image pixels A11, A21, A31, A12, A22, and A32, respectively. That is, of the four image pixels represented by one panel pixel during odd-numbered frame periods, the image pixel at position (3) is represented in unit period f1-3.

[0115] During the latter part of unit period f1-3, the optical path shifting element 230 shifts the projection position from the projection position in unit period f1-3 (shown by the dashed line) downwards (in the Y direction) by 0.5 pixels of the panel pixel. In the next unit period f1-4, panel pixels p11, p21, p31, p12, p22, and p32 represent the shadowed image pixels D11, D21, D31, D12, D22, and D32, respectively. That is, of the four image pixels represented by one panel pixel during odd-numbered frame periods, the image pixel at position (4) is represented in unit period f1-4.

[0116] During the latter part of unit period f1-4, the optical path shifting element 230 shifts the projection position from the projection position in unit period f1-4 (shown by the dashed line) to the right (X direction) in the figure by an amount of 0.5 pixels of panel pixels and returns it to the reference position. In the initial unit period f2-1 of the even-numbered frame period, panel pixels p11, p21, p31, p12, p22, and p32 represent the image pixels C11, C21, C31, C12, C22, and C32 with shadows, respectively. That is, the image pixel represented by one panel pixel in unit period 1-1 is the same as the image pixel represented by that one panel pixel in unit period 2-1. Furthermore, of the four image pixels represented by one panel pixel in the even-numbered frame period, the image pixel at position (5) is represented in unit period f2-1.

[0117] During the latter part of unit period f2-1, the optical path shifting element 230 shifts the projection position from the reference position in unit period f2-1 (shown by the dashed line) downwards (in the Y direction) by 0.5 pixels of the panel pixel. In the next unit period f2-2, panel pixels p11, p21, p31, p12, p22, and p32 represent the shadowed image pixels B12, B22, B32, B13, B23, and B33, respectively.

[0118] In addition, among the four image pixels represented by one panel pixel during even-numbered frames, the image pixel at position (6) is represented during unit period f2-2.

[0119] During the latter part of unit period f2-2, the optical path shifting element 230 shifts the projection position from the projection position in unit period f2-2 (shown by the dashed line) to the right (X direction) of the panel pixel by 0.5 pixels. Furthermore, in unit period f2-3, panel pixels p11, p21, p31, p12, p22, and p32 represent the shadowed image pixels A22, A32, A42, A23, A33, and A42, respectively. Additionally, of the four image pixels represented by one panel pixel during even-numbered frames, the image pixel at position (7) is represented in unit period f2-3.

[0120] During the latter part of unit period f2-3, the optical path shifting element 230 shifts the projection position from the projection position in unit period f2-3 (shown by the dashed line) to the upper direction (opposite to the Y direction) of the panel pixel by 0.5 pixels. In the next unit period f2-4, panel pixels p11, p21, p31, p12, p22, and p32 represent the shadowed image pixels D21, D31, D41, D22, D32, and D42, respectively. In addition, of the four image pixels represented by one panel pixel during even-numbered frames, the image pixel at position (8) is represented in unit period f2-4.

[0121] During the latter part of the unit period f2-4, the optical path shifting element 230 shifts the projection position from the projection position shown by the dashed line to the left (opposite to the X direction) of the panel pixel by an amount of 0.5 pixels and returns it to the reference position.

[0122] In this embodiment, before describing the electrically separated panel pixel Dp in the panel pixels, a comparative example relative to this embodiment will be described.

[0123] Figure 24 This is a top view showing the arrangement of panel pixels in a comparative example, with a particularly magnified view of the upper left (UL), upper right (UR), lower left (DL), and lower right (DR) portions of the pixel arrangement. As shown in the figure, in the comparative example, there are no electrically separated panel pixels (Dp), only the effective panel pixels (Vp) arranged in a matrix of m rows × n columns. Furthermore, in the comparative example, when viewed from above, a light-shielding portion 196 is arranged outside the arrangement area of ​​the effective panel pixels (Vp).

[0124] During odd-numbered frames, image pixels and panel pixels are in Figure 11 The correspondence is shown in the left column. That is, during odd-numbered frames, one panel pixel is represented by four image pixels surrounded by thick black lines using four unit periods 1-1 to 1-4. Therefore, as... Figure 25As shown in the comparative example, during the odd-numbered frames, all image pixels arranged in 2m rows and 2n columns are represented by panel pixels arranged in m rows and n columns, so no display loss occurs when representing image pixels.

[0125] During even-numbered frames, the four image pixels represented by one panel pixel are shifted downwards by one image pixel and to the right by one image pixel, based on the four image pixels in odd-numbered frames. In the comparative example, when viewed from above, a light-shielding portion 196 is arranged outside the arrangement area of ​​the effective panel pixels Vp, and there are no panel pixels capable of representing image pixels. Therefore, during even-numbered frames, Figure 11 The top row and left column of image pixels shown in the right column are not displayed. Therefore, as... Figure 26 As shown in the comparative example, during even-numbered frames, not all image pixels arranged in 2m rows and 2n columns are represented by panel pixels, resulting in display defects.

[0126] Furthermore, in the comparative example, the effective panel pixels Vp in the rightmost column arranged in m rows × n columns do not have any image pixels to be displayed at positions (7) and (8). Similarly, the effective panel pixels Vp in the bottom row do not have any image pixels to be displayed at positions (6) and (7).

[0127] In this embodiment, in order to prevent the absence of a display like the one shown in the comparison, the electrically separated panel pixels Dp are configured to surround the effective panel pixels Vp, and the image pixels, etc., are displayed as follows during even-numbered frame periods and odd-numbered frame periods.

[0128] Figure 15 and Figure 16 This is a top view showing the correspondence between panel pixels and image pixels in this embodiment, as well as the panel pixel with the lowest transmittance. In these figures, Figure 15 Indicates the period of odd-numbered frames, Figure 16 This indicates the period of even-numbered frames.

[0129] Additionally, in these figures, the boxes represented by thick solid lines are the effective panel pixels Vp, and the boxes represented by thick dashed lines are the electrically separated panel pixels Dp.

[0130] Furthermore, in the effective panel pixels Vp or electrically separated panel pixels Dp, 1 to 4 and Figure 12 Similarly, positions (1) to (4) within unit periods f1-1 to f1-4 are indicated. The shaded portion indicates that the black signal with the lowest transmittance is displayed as black in the corresponding unit period, while the unshaded portion indicates that the image pixel is represented in the corresponding unit period.

[0131] like Figure 15As shown, during odd-numbered frames, the processing circuit 22 controls the effective panel pixel Vp to represent the image pixel, and controls all electrically separated panel pixels Dp to display in black. Furthermore, when the processing circuit 22 controls the panel pixel to display in black, it means outputting black data with a grayscale level equivalent to the lowest value. The display control circuit 20 outputs the analog data signal obtained by converting the black data to that panel pixel.

[0132] For example, the effective panel pixel Vp1 located at the upper left end represents the image pixel C11 at position (1) in unit period f1-1, the image pixel B11 at position (2) in unit period f1-2, the image pixel A11 at position (3) in unit period f1-3, and the image pixel D11 at position (4) in unit period f1-4.

[0133] In addition, for example, in Figure 15 The electrical separator panel pixel Dp1, located at the upper left end, becomes black during the unit period f1-1 to f1-4, as can be seen from the shadows attached to positions (1) to (4), and functions as part of the light-shielding part. Description of other panel pixels is omitted.

[0134] like Figure 16 As shown, during even-numbered frame periods, processing circuit 22 causes the effective panel pixel Vp to display image pixels for the entire even-numbered frame period, or to display image pixels for a portion of the even-numbered frame period, and to remain black for the remaining portion. Furthermore, processing circuit 22 controls the electrically separated panel pixel Dp to display image pixels for a portion of the even-numbered frame period, and to remain black for the remaining portion, or to remain black for the entire even-numbered frame period.

[0135] For example, the effective panel pixel Vp1 located at the upper left end represents the image pixel C11 located at position (5) in unit period f2-1, the image pixel B12 located at position (6) in unit period f2-2, the image pixel A22 located at position (7) in unit period f2-3, and the image pixel D21 located at position (8) in unit period f2-4.

[0136] Furthermore, for example, the effective panel pixel Vp2 located at the lower right end represents the image pixel located at position (5) during unit period f2-1, and becomes black display during unit periods f2-2 to f2-4, as can be seen from the shadow attached at positions (6) to (8).

[0137] Furthermore, for example, the electrical separator panel pixel Dp1 located at the upper left end becomes black in unit periods f2-1, f2-2 and f2-4, as can be known from the shadows attached at positions (5), (6) and (8), and in unit period f2-3 represents the image pixel A11 located at position (7).

[0138] Furthermore, for example, the electrical separator panel pixel Dp2 located at the lower right end, during the unit period f2-1 to f2-4, becomes black as can be seen from the shadows attached at positions (5) to (8), and functions as part of the light-shielding part. Description of other panel pixels is omitted.

[0139] The processing circuit 22 controls the active panel pixel Vp and the electrically separated panel pixel Dp in this way.

[0140] According to this embodiment, in the comparative example, the image pixels missing in the top row and left column during even-numbered frames are also represented by panel pixels, thus suppressing the display loss.

[0141] Next, the second embodiment will be described.

[0142] Figure 17 This is a top view showing the arrangement of panel pixels in the liquid crystal panel 100 of the second embodiment, and is a particularly enlarged view showing the upper left end UL, upper right end UR, lower left end DL, and lower right end DR of the arrangement of panel pixels.

[0143] In the second embodiment, the panel pixels are arranged in a matrix of (m+1) rows × (n+1) columns. Compared with the first embodiment, there is one less row in the row direction and one less column in the column direction.

[0144] Specifically, in the second embodiment, the effective panel pixels Vp are arranged in a matrix with m rows × n columns, excluding the first row and the first column.

[0145] The electrical separator panel pixel Dp surrounds the area of ​​the effective panel pixel Vp arranged in m rows × n columns on two sides, specifically one column on the left L1 and one row on the top L2.

[0146] In other words, in the second embodiment, unlike the first embodiment, no electrically separated panel pixels Dp are provided in the column 1 of right L3 and the row 1 of bottom L4.

[0147] In the second embodiment, the correspondence between image pixels and panel pixels during odd-numbered frames and even-numbered frames is... Figure 11 The first embodiment shown is the same, except that the order of the image pixels represented by the panel pixels during odd-numbered frames and even-numbered frames is the same. Figure 12The first embodiment shown is the same. Furthermore, in the second embodiment, the relationship between image pixels, panel pixels, and projection position during odd-numbered frame periods and even-numbered frame periods is the same as... Figure 13 as well as Figure 14 The first embodiment shown is the same.

[0148] Figure 18 and Figure 19 This is a top view showing the correspondence between panel pixels and image pixels in the second embodiment, as well as the panel pixel with the lowest transmittance. In these figures, Figure 18 Indicates the period of odd-numbered frames, Figure 19 This indicates the period of even-numbered frames.

[0149] Additionally, the boxes indicated by thick solid lines represent effective panel pixels (Vp), and the boxes indicated by thick dashed lines represent electrically separated panel pixels (Dp). Furthermore, the meanings of 1-4 in effective panel pixels (Vp) or electrically separated panel pixels (Dp) and the shading are... Figure 15 and Figure 16 same.

[0150] like Figure 18 As shown, during odd-numbered frames, the processing circuit 22 controls the effective panel pixel Vp to represent the image pixel and controls all electrically separated panel pixels Dp to be displayed in black.

[0151] For example, the effective panel pixel Vp1 located at the upper left end represents the image pixel C11 at position (1) in unit period f1-1, the image pixel B11 at position (2) in unit period f1-2, the image pixel A11 at position (3) in unit period f1-3, and the image pixel D11 at position (4) in unit period f1-4.

[0152] Furthermore, the electrical separator panel pixel Dp1 located at the upper left end is displayed as black during the unit period f1-1 to f1-4, as can be seen from the shadows attached to positions (1) to (4). Description of other panel pixels is omitted.

[0153] like Figure 19 As shown, during even-numbered frame periods, processing circuit 22 causes the effective panel pixel Vp to display image pixels for the entire even-numbered frame period, or to display image pixels for a portion of the even-numbered frame period, and to remain black for the remaining portion. Furthermore, processing circuit 22 causes the electrically separated panel pixel Dp to display image pixels for a portion of the even-numbered frame period, and to remain black for the remaining portion. Unlike the first embodiment, in the second embodiment, the electrically separated panel pixel Dp is not displayed black for the entire even-numbered frame period.

[0154] For example, the effective panel pixel Vp1 represents image pixel C11 at position (5) in unit period f2-1, image pixel B12 at position (6) in unit period f2-2, image pixel A22 at position (7) in unit period f2-3, and image pixel D21 at position (8) in unit period f2-4.

[0155] In addition, the effective panel pixel Vp2 represents the image pixel located at position (5) during unit period f2-1, and becomes black display during unit period f2-2 to f2-4.

[0156] Furthermore, for example, the electrically separated panel pixel Dp1 represents the image pixels C11, B11 and D11 located at positions (5), (6) and (8) during unit periods f2-1, 2-2 and 2-4, and becomes black during unit period f2-3.

[0157] The processing circuit 22 controls the active panel pixel Vp and the electrically separated panel pixel Dp in this way.

[0158] According to the second embodiment, the image pixels in the top row and left column that are missing during even-numbered frames in the comparative example are also represented by panel pixels. Therefore, similar to the first embodiment, the display omissions can be suppressed. Furthermore, according to the second embodiment, compared to the first embodiment, the number of electrically separated panel pixels Dp in the panel pixels can be reduced.

[0159] Next, the third embodiment will be described.

[0160] Figure 20 This is a top view showing the arrangement of panel pixels in the liquid crystal panel 100 of the third embodiment, and is a particularly enlarged view showing the upper left end UL, upper right end UR, lower left end DL and lower right end DR of the arrangement of panel pixels.

[0161] In the third embodiment, the panel pixels are arranged in a matrix of (m+1) rows × (n+1) columns, similar to the second embodiment. Compared to the first embodiment, there is one less row in the row direction and one less column in the column direction. In the third embodiment, the effective panel pixels Vp arranged in a matrix of m rows × n columns are located at the left and top edges. The electrically separated panel pixels Dp are arranged along the two sides of the area surrounding the effective panel pixels Vp arranged in m rows × n columns, specifically in one column on the right (L3) and one row on the bottom (L4).

[0162] In other words, in the third embodiment, the electrical separation panel pixel Dp differs from that in the second embodiment, and is not set in one column on the left L1 and one row on the top L2.

[0163] In the third embodiment, the correspondence between image pixels and panel pixels during odd-numbered frames and even-numbered frames is... Figure 11 The first embodiment shown is different.

[0164] Specifically, such as Figure 21 As shown in the upper section, panel pixel p11 represents C11, B11, A21, and D21 during odd-numbered frames, and C11, B12, A12, and D11 during even-numbered frames. That is, in the third embodiment, the 2×2 image pixels represented by a certain panel pixel during even-numbered frames are offset by one pixel to the left and one pixel downward relative to the 2×2 image pixels represented by the same panel pixel during odd-numbered frames.

[0165] Figure 21 The lower column is a diagram showing the position and order of image pixels C11, B11, A21, and D21 represented by panel pixel p11 in unit periods f1-1 to f1-4 during odd-numbered frames, labeled with numbers 1 to 4.

[0166] For example, position 3 in panel pixel p11 indicates that, when viewed over a period of 2 frames, panel pixel p11 represents the third unit period f1-3. Figure 21 Image pixel A21 at position 3 in the upper column. Furthermore, regarding this reference numeral, parentheses are omitted in the accompanying drawings, but are indicated with parentheses in the description. Similarly, in the unit periods f2-1 to f2-4 during even-numbered frames, the positions and order of image pixels C11, B12, A12, and D11 represented by panel pixel p11 are indicated by 5 to 8.

[0167] Figure 22 as well as Figure 23 This is a top view showing the correspondence between panel pixels and image pixels in the third embodiment, as well as the panel pixel with the lowest transmittance. In these figures, Figure 22 Indicates the period of odd-numbered frames, Figure 23 This indicates the period of even-numbered frames.

[0168] Additionally, the boxes indicated by thick solid lines represent effective panel pixels (Vp), and the boxes indicated by thick dashed lines represent electrically separated panel pixels (Dp). Furthermore, the meanings of 1-4 in effective panel pixels (Vp) or electrically separated panel pixels (Dp) and the shading are... Figure 15 , Figure 16 , Figure 18 and Figure 19 same.

[0169] like Figure 22 As shown, during odd-numbered frames, the processing circuit 22 controls the effective panel pixel Vp to represent the image pixel and controls all electrically separated panel pixels Dp to be displayed in black.

[0170] For example, the effective panel pixel Vp1 located at the upper left end represents the image pixel C11 at position (1) in unit period f1-1, the image pixel B11 at position (2) in unit period f1-2, the image pixel A21 at position (3) in unit period f1-3, and the image pixel D21 at position (4) in unit period f1-4.

[0171] Furthermore, the electrical separator panel pixel Dp1 located at the upper left end becomes black during the unit period f1-1 to f1-4, as can be seen from the shadow attached to positions (1) to (4).

[0172] like Figure 23 As shown, during even-numbered frame periods, the processing circuit 22 causes the effective panel pixel Vp to display image pixels for a portion of the even-numbered frame period and to be displayed as black for the remaining portion, or causes the effective panel pixel Vp to display image pixels for the entire even-numbered frame period.

[0173] Furthermore, in the second embodiment, the processing circuit 22 causes the electrically separated panel pixel Dp to display image pixels during a portion of the even-numbered frame period and to be displayed as black during the remaining period. Unlike the first embodiment, in the third embodiment, the electrically separated panel pixel Dp is not displayed as black for the entire even-numbered frame period, which is the same as in the second embodiment.

[0174] For example, the effective panel pixel Vp1 represents the image pixel C11 at position (5) in unit period f2-1, the image pixel B12 at position (6) in unit period f2-2, and becomes black in unit periods f2-3 and f2-4.

[0175] Additionally, for example, the effective panel pixel Vp3 adjacent to the right of the effective panel pixel Vp1 represents image pixel C21 at position (5) in unit period f2-1, image pixel B22 at position (6) in unit period f2-2, image pixel A22 at position (7) in unit period f2-3, and image pixel D21 at position (4) in unit period f2-4.

[0176] Furthermore, for example, the electrically separated panel pixel Dp1 becomes black during unit periods f2-1, f2-3 and f2-4, and during unit period f2-2 represents the image pixel B11 located at position (6).

[0177] According to the third embodiment, all image pixels are represented by panel pixels, thus suppressing the loss of display quality such as that in a scaled-down display. Furthermore, according to the third embodiment, similar to the second embodiment, the number of electrically separated panel pixels Dp in the panel pixels can be reduced.

[0178] In the first to third embodiments described above (hereinafter referred to as "the embodiments, etc."), various modifications or applications can be made as follows.

[0179] In implementation methods, when panel pixels are set as separator pixels, the grayscale level is set to zero, resulting in a black display with the lowest transmittance. However, it can also be set to a transmittance corresponding to a grayscale level below a threshold (e.g., a decimal value of "10"). That is, when panel pixels are set as separator pixels, they can also be set to a darker state with a transmittance below a certain level, essentially functioning as a separator pixel and part of a light-shielding component.

[0180] Furthermore, in the implementation method, a frame is configured to be divided into 4 unit periods. That is, the number of unit periods k contained in a frame is described as "4" as an example. k is not limited to "4", and can be "2" or more.

[0181] In implementations, the period during which the levels of the control signals P_x and P_y provided to the optical path shifting element 230 change is set to a later period corresponding to the vertical scanning period in unit periods f1-1 to f1-4 and f2-1 to f2-4. However, as described above, the shift of the projection position by the optical path shifting element 230 is sometimes not consistent with the levels of the control signals P_x and P_y, but is accompanied by a time delay. In such cases, for example, the level change of the control signals P_x and P_y can be started by predicting the time delay, so that the image formed by the liquid crystal panel 100 in a unit period is shifted to the projection position corresponding to that unit period.

[0182] Based on the examples above, for instance, master the following methods.

[0183] An example (method 1) of a projection display device includes: a liquid crystal panel having a plurality of panel pixels; an optical path shifting element that shifts the position of a projection pixel projected from the plurality of panel pixels for each unit period of k unit periods from a first unit period to a kth unit period contained in a frame period, wherein k is an integer greater than or equal to 2; and a display control circuit that controls the liquid crystal panel and the optical path shifting element, the display control circuit providing a data signal to the plurality of panel pixels for each unit period, providing a signal based on pixel data of image pixels constituting an image as the data signal to a peripheral panel pixel disposed at the periphery of the plurality of panel pixels for a portion of a frame period of either the first frame period or the second frame period, and providing a signal with a gray level below a threshold as the data signal to the peripheral panel pixel for unit periods other than the portion of a frame period of the first frame period.

[0184] According to method 1, it is possible to suppress the display deficiency where image pixels are not represented by panel pixels.

[0185] In a specific method of Method 1 (Method 2), when the peripheral panel pixel displays the image pixel in one unit period, the display control circuit provides the peripheral panel pixel with a pixel signal based on the pixel data of the image pixel as the data signal in that one unit period. When the peripheral panel pixel does not display the image pixel in other unit periods, the display control circuit provides the peripheral panel pixel with a signal whose gray level is below a threshold as the data signal in those other unit periods.

[0186] According to method 2, when the peripheral panel pixel does not represent an image pixel, the black signal is used as the data signal during the other unit period, and the black signal is provided to the peripheral panel pixel so that it functions as part of the light-shielding part.

[0187] In a specific embodiment of Method 1 (Method 3), the peripheral panel pixels are arranged along the four perimeters of a rectangular area where the plurality of panel pixels are arranged. According to Method 3, display defects can be suppressed.

[0188] In a specific embodiment of Method 1 (Method 4), the peripheral panel pixels are arranged on two adjacent sides of the periphery within a rectangular region where the plurality of panel pixels are arranged. According to Method 4, compared to Method 3, the number of panel pixels relative to the number of image pixels can be reduced.

[0189] In a specific method of Method 1 (Method 5), a panel pixel display shows k image pixels that are displayed during the first unit period to the kth unit period of the first frame and k image pixels that are displayed during the first unit period to the kth unit period of the second frame, arranged point-symmetrically with a common image pixel as the reference. According to Method 5, so-called flicker can be reduced.

[0190] The projection display device of method 1 can be understood as the control method of projection display of method 6. That is, in the control method of projection display of method 6, the projection display device includes: a liquid crystal panel having a plurality of panel pixels; an optical path shifting element that shifts the position of a projection pixel projected from the plurality of panel pixels in each unit period of k unit periods from the first unit period to the kth unit period contained in a frame period, where k is an integer greater than or equal to 2; and a display control circuit that controls the liquid crystal panel and the optical path shifting element. In the control method of the projection display device, the display control circuit provides a data signal to the plurality of panel pixels in each unit period. In a portion of a frame period of either the first frame period or the second frame period, a pixel signal based on pixel data of image pixels constituting an image is provided as the data signal to a peripheral panel pixel disposed at the periphery of the plurality of panel pixels. In unit periods other than the portion of a frame period of the first frame period, a signal with a gray level below a threshold is provided as the data signal to the peripheral panel pixel.

Claims

1. A projection display device, characterized by comprising: The projection display device includes: a liquid crystal panel having a plurality of panel pixels; a light path shifting element that shifts a position of a projection pixel projected from the plurality of panel pixels for each of k unit periods included in a frame period from a first unit period to a kth unit period, where k is an integer of two or more; and a display control circuit that controls the liquid crystal panel and the light path shifting element, the display control circuit supplies a data signal to the plurality of panel pixels for each of the unit periods, in a part of the unit periods in a frame period of either one of a first frame period and a second frame period, a signal based on pixel data of an image pixel constituting an image image is supplied to a peripheral panel pixel disposed at a periphery among the plurality of panel pixels as the data signal, in a unit period other than the part of the unit periods in the frame period of the one side, a signal having a gradation level of a threshold value or less is supplied to the peripheral panel pixel as the data signal.

2. The projection display device according to claim 1, wherein in a case where the peripheral panel pixel exhibits the image pixel in one unit period, the display control circuit supplies a pixel signal based on pixel data of the image pixel to the peripheral panel pixel as the data signal in the one unit period, in a case where the peripheral panel pixel does not exhibit the image pixel in another unit period, the display control circuit supplies the signal having the gradation level of the threshold value or less to the peripheral panel pixel as the data signal in the other unit period.

3. The projection display device according to claim 1, wherein the peripheral panel pixel is disposed at a periphery of four sides in a rectangular region in which the plurality of panel pixels are arranged.

4. The projection display device according to claim 1, wherein the peripheral panel pixel is disposed at two sides adjacent to each other at a periphery in a rectangular region in which the plurality of panel pixels are arranged.

5. The projection display device according to claim 1, wherein one panel pixel displays an image pixel arranged in point symmetry with k image pixels exhibited in a first unit period to a kth unit period of the first frame period and k image pixels exhibited in a first unit period to a kth unit period of the second frame period based on one common image pixel.

6. A control method of a projection display device, the projection display device including: a liquid crystal panel having a plurality of panel pixels; a light path shifting element that shifts a position of a projection pixel projected from the plurality of panel pixels for each of k unit periods included in a frame period from a first unit period to a kth unit period, where k is an integer of two or more; and a display control circuit that controls the liquid crystal panel and the light path shifting element, in the control method of the projection display device, the display control circuit supplies a data signal to the plurality of panel pixels for each of the unit periods, ​ In a part of the unit period in either one of the frame period of the first frame and the frame period of the second frame, a pixel signal based on pixel data of an image pixel constituting an image is supplied as the data signal to the peripheral panel pixels disposed at the periphery among the plurality of panel pixels, In a unit period other than the part of the unit period of the frame period of the one side, a signal having a gradation level lower than a threshold value is supplied as the data signal to the peripheral panel pixels.

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